JP2008288393A - Field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an MOS transistor of high soft error resistance. <P>SOLUTION: A barrier layer 7 comprising an impurity region of the same conductive type as source-drain regions 4 and 5 is provided, just under the source-drain regions 4 and 5 of transistor 10, 20 formation region subject to element separation by an STI2 comprising an embedded insulating film. The barrier layer 7 is so provided at the position shallower than the STI2 so that its periphery contacts to the side surface of the embedded insulating film 2. Since the perimeter and bottom surface of the transistor 10, 20 formation region are surrounded with the STI2 and the barrier layer 7, effects to adjacent elements voltage fluctuation of the transistor 10, 20 formation region on an adjoining element when α ray enters are suppressed. The upper surface of the barrier layer 7 acts as a barrier wall against a positive hole or electron and prohibits transmission of the positive hole or electron generated deeper than the impurity region 7, reducing noises at entering of α ray. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a field effect transistor having excellent soft error resistance, and more particularly to a field effect transistor having a barrier layer that suppresses inflow of carriers generated in a semiconductor substrate into a source / drain region by the passage of α rays.

  Since CMOS has low power consumption, it is widely used in semiconductor devices that are highly integrated and require low power consumption, such as static memory. However, when the memory cell area is reduced and the size of the transistors constituting the CMOS memory cell is reduced, so-called soft errors are increased.

  Soft errors are caused by radiation caused by the semiconductor device material or cosmic rays, for example, alpha rays that pass through the memory cell. As a result, electrons and holes are generated along the traces of the alpha rays in the semiconductor substrate. This is an error that induces a malfunction of the transistor.

  FIG. 9 is a cross-sectional view of a conventional field effect transistor, showing pMOS and nMOS transistors when a soft error occurs. FIG. 10 is a cross-sectional view of a field effect transistor formed in a conventional triple well structure, and shows a pMOS transistor and an nMOS transistor constituting a CMOS circuit.

  Referring to FIG. 9, the conventional MOS transistor has a transistor formation region that is isolated by STI (Shallow Trench Isolation) 2 made of a buried insulating film formed in semiconductor substrate 1. Then, a MOS transistor having a gate electrode 3, a source region 4, and a drain region 5 is formed in the transistor formation region isolated from the element.

  Referring to FIG. 9A, a pMOS transistor among these MOS transistors is formed, for example, in an n well 6 formed in a p-type semiconductor substrate 1. Further, referring to FIG. 9B, the nMOS transistor is formed on the p-type semiconductor substrate 1 and constitutes a CMOS circuit together with the pMOS transistor formed in the n-well 6.

  Referring to FIG. 9, when the semiconductor substrate 1 is irradiated with α rays 11 from the surface, pairs of electrons and holes are generated in the semiconductor substrate 1 along the tracks of the α rays 11. Referring to FIG. 9A, in the pMOS transistor formed in the n-well 6, holes out of the electron-hole pairs generated in the n-well 6 are absorbed into the drain region 5 to which a negative voltage is applied. Then, a pulsed noise current flows to the drain. In the nMOS transistor, referring to FIG. 9B, electrons of the electron-hole pairs generated in the p-type semiconductor substrate 1 are absorbed by the drain 5 to which a positive voltage is applied, A noise current flows through the drain 5.

  In this way, irradiation with α rays generates pulsed noise in the drain 5 and, as a result, induces malfunction of these transistors. In particular, since the pMOS transistor is often designed to be smaller in size than the nMOS transistor, even if the same amount of pulse current is used, the ratio of the drain current to the drain current increases and the resistance to noise is low. Similarly, if the size is small, the resistance to soft errors is low even with an nMOS transistor.

  Referring to FIG. 10, n-well 6 is formed in p-type semiconductor substrate 1, and has a triple well structure in which p-well is provided in n-well 6. A pMOS transistor is provided in n-well 6 and p-well 8 is provided. In a semiconductor device in which a pMOS transistor is formed, holes or electrons flowing into the drain are limited to those generated in the wells 6 and 8. For this reason, although the occurrence of soft errors is somewhat suppressed, it is not sufficient in practice.

  In order to improve such soft error resistance, a field effect transistor has been devised in which a barrier layer made of an n-type impurity layer is provided below the transistor. (For example, refer to Patent Document 1).

  FIG. 11 is a cross-sectional view of a conventional field effect transistor with improved soft error resistance, and shows a field effect transistor in which a barrier layer made of an n-type impurity layer is provided below a transistor formation region.

  Referring to FIG. 11, in a conventional field effect transistor with improved soft error resistance, a pMOS transistor and an nMOS transistor are formed in an element formation region in which the upper surface of p-type semiconductor substrate 1 is isolated by STI2. The pMOS transistor is formed in the n-well 601 and the nMOS transistor is formed in the p-well 801.

  A p-type impurity region 501 and an n-type impurity region 502 serving as source / drain regions are formed on the surface of the formation region of the pMOS transistor and the nMOS transistor, respectively. A barrier layer 701 made of an n-type impurity layer is provided on the bottom surfaces of the n well 601 and the p well 801.

  In this field effect transistor, the barrier layer 701 made of an n-type impurity layer provided on the bottom surfaces of the wells 601 and 801 functions as a barrier for preventing diffusion of electrons and holes generated by α rays. Therefore, electrons and holes generated in the semiconductor substrate below the barrier layer 701 reach the p-type impurity region 501 and the n-type impurity region 502 that are the source / drain regions formed on the surface of the semiconductor substrate 1. Is suppressed, and noise caused by soft errors is reduced. For this reason, soft error tolerance becomes high.

  In an nMOS transistor having this barrier layer, the barrier layer 701 and the p-well 801 of the n-type semiconductor layer are held at a reverse voltage in a normal operation state. Therefore, the junction surface between the barrier layer 701 and the p-well 801, that is, the upper surface of the barrier layer 701 forms an electron barrier. Therefore, only electrons generated between the n-type impurity region 502 that is the source / drain region and the upper surface of the barrier layer 701 flow into the n-type impurity region 502 that is the source / drain region, which causes noise. The electrons generated in (1) do not flow into the n-type impurity region 502, and therefore do not cause noise.

  On the other hand, in the pMOS transistor, the barrier layer 701 and the p well 701 of the n-type semiconductor layer are held at a forward voltage, so that a barrier against holes is not formed. The barrier against holes is formed on the bottom surface of the barrier layer 701 of the n-type semiconductor layer, that is, the junction surface between the p-type semiconductor substrate 1 and the barrier layer 701. Therefore, the holes generated in the barrier layer 701 flow into the upper n-type impurity region 502 and generate noise. As described above, in the pMOS transistor, in addition to the holes generated in the n-well 601, the holes generated in the barrier layer 701 generate noise, so that the soft error resistance is inferior to that of the nMOS transistor. In addition, since the pMOS transistor is often designed to be small, the soft error resistance further deteriorates.

Furthermore, the conventional field effect transistor having this barrier layer is formed such that the upper surface of the barrier layer 701 is positioned deeper than the bottom surface of the STI 2 that is the element isolation band. Electrons or holes generated by α-ray irradiation are absorbed by the drain region (impurity regions 501 and 502), and one pair of carriers remains after that, so that a voltage is generated in the wells 601 and 801. In this conventional field effect transistor in which the barrier layer 701 is formed deeper than STI2, the voltage generated in the wells 601 and 801 may adversely affect the adjacent elements.
JP 2005-259938 A

  As described above, the conventional field effect transistor has a problem that the soft error resistance is low because carriers generated in the well or the semiconductor substrate are absorbed in the source / drain regions to generate a large noise.

  In a conventional field effect transistor in which a barrier layer made of an n-type semiconductor layer is provided on the bottom of the well, the barrier layer is located deeper than the STI, and the well voltage fluctuation generated by the incidence of α rays is adjacent to the field effect transistor. There is a problem of destabilizing the operation.

  Further, in the p-type field effect transistor, even if a barrier layer made of an n-type semiconductor layer is provided, a hole barrier is formed on the bottom surface of the barrier layer, so that holes generated in the barrier layer are also generated in the source / drain regions. To be absorbed. Therefore, there is a problem that large noise is generated and it is difficult to improve the soft error resistance of the p-type field effect transistor.

  The present invention relates to a field effect transistor having excellent soft error resistance, and in particular, to provide a field effect transistor in which the influence of voltage fluctuation of a well caused by the incidence of α-rays on the operation of an adjacent field effect transistor is small. To do.

  Furthermore, it aims at providing the p-type field effect transistor which has the outstanding soft error tolerance in addition to the said objective.

  In order to solve the above-described problem, a field effect transistor having a first configuration according to the present invention includes a source region of a field effect transistor separated by a buried insulating film, for example, STI (Shallow Trench Isolation), and Immediately below the drain region, an impurity region having the same conductivity type as the source region and the drain region is provided, and the impurity region is formed at a position shallower than the bottom of the buried insulating film. In addition, in order to simplify the description, in the following specification, the impurity region is sometimes referred to as a barrier layer.

  In the first configuration, the impurity region (barrier layer) is provided at a position shallower than the bottom of the buried insulating film, for example, so that the periphery of the impurity region is in contact with the wall surface of the buried insulating film. Therefore, the semiconductor region (well or part of the semiconductor substrate) in which the field effect transistor is formed is surrounded by the buried insulating film and the bottom surface by the impurity region. These impurity regions and the buried insulating film function as an insulating isolation band with respect to the semiconductor substrate. For this reason, even if this semiconductor region has a voltage variation due to the incidence of α rays, it has excellent insulation isolation from the semiconductor substrate, and therefore has little influence on the adjacent field effect transistor.

  Note that the impurity region is provided immediately below the source region and the drain region, and may not be provided immediately below the gate electrode, for example. By adopting such a structure, the impurity region and the source / drain region can be easily formed by deep ion implantation and shallow ion implantation using the gate electrode as a mask.

  Further, in the first configuration, the conductivity type of the impurity region is made the same as that of the source region and the drain region. In this configuration, the semiconductor region in which the field effect transistor is formed has a conductivity type opposite to that of the impurity region and the source / drain region. That is, in a p-type field effect transistor, an n-type semiconductor region (for example, an n-well) is sandwiched between an impurity region made of p-type impurities and a source / drain region.

  In a normal use state of the p-type field effect transistor, the interface between the p-type impurity region and the n-type semiconductor region becomes a hole barrier. Accordingly, in the p-type field effect transistor, similarly to the n-type field effect transistor, only carriers generated in the semiconductor region above the upper surface of the impurity region serve as a noise source, and carriers generated in the impurity region serve as a noise source. Don't be. For this reason, the soft error tolerance of a p-type field effect transistor can be improved.

  In the first configuration, the impurity region can be provided on the entire bottom surface of the field effect transistor formation region. In this structure, the semiconductor region in which the field effect transistor is formed is completely separated from the semiconductor substrate by the buried insulating film and the impurity region. Therefore, the influence on the adjacent field effect transistor is smaller.

  The field effect transistor of the second configuration of the present invention connects the impurity region of the field effect transistor of the first configuration described above to a high power supply potential or a low power supply potential. More specifically, the p-type impurity region is connected to a low power supply potential, and the n-type impurity region is connected to a high power supply potential.

  In this configuration, a voltage in the reverse voltage direction is applied between the impurity region and the semiconductor region where the field effect transistor is formed. For this reason, the barrier formed on the upper surface of the impurity region is increased, and the effect of suppressing the soft error is increased.

  Some of the electron-hole pairs generated by α rays also flow into the impurity region, and holes are accumulated in the p-type impurity region and electrons are accumulated in the n-type impurity region. As a result, the p-type impurity region is charged to a positive potential, and the n-type impurity region is charged to a negative potential. This charging lowers the barrier of the junction between the impurity region and the semiconductor region where the field effect transistor is formed. For this reason, when a large amount of electron-hole pairs are generated by high energy α-rays, the potential of the impurity region is displaced in the direction of lowering the barrier (ie, changes in the forward voltage direction), and the upper surface of the impurity region. The blocking effect of electrons or holes in is reduced. Furthermore, since electrons or holes are easily emitted from the impurity region, the soft error resistance is deteriorated.

  In the second configuration, by connecting an external power source to the impurity region, electrons or holes accumulated in the impurity region are quickly eliminated. For this reason, the barrier against electrons and holes on the upper surface of the impurity region can always be kept high. Further, by applying a reverse voltage to the impurity region, electrons or holes near the impurity region are absorbed by the impurity region. For this reason, few electrons or holes flow into the drain region when α rays are incident, and the soft error resistance of the field effect transistor is improved.

  According to the present invention, since the field effect transistor formation region is separated by the buried insulating film and the impurity region, the influence of the voltage generated in the well due to the incidence of α rays on the adjacent field effect transistor is effectively suppressed. be able to. Moreover, it is possible to provide a field effect transistor having excellent soft error resistance, including a p-type field effect transistor.

  The first embodiment of the present invention relates to a pMOS transistor and an nMOS transistor (p-type field effect transistor and n-type field effect transistor) which are formed in a double well structure and have a barrier layer immediately below a source region and a drain region.

  FIG. 1 is a cross-sectional view of a field effect transistor according to a first embodiment of the present invention, showing pMOS and nMOS transistors formed in a double well. 1A shows a cross section of the pMOS transistor 10, and FIG. 1B shows a cross section of the nMOS transistor 20. FIG. 1 (c) shows a circuit diagram of a CMOS inverter circuit constituted by these pMOS and nMOS transistors.

Referring to FIG. 1, in the first embodiment, an STI 2 made of a buried insulating film surrounding an element formation region (field effect transistor formation region) is formed on the upper surface of a semiconductor substrate 1 made of p-type silicon. Each element formation region is element-isolated. The STI 2 is formed, for example, by filling a trench formed in the surface of the semiconductor substrate 1 with an insulating material such as SiN or SiO ₂ .

  Referring to FIG. 1A, the pMOS transistor is formed in an n-well formed on the surface of the semiconductor substrate 1. The n-well is formed so as to completely include the region surrounded by STI2. A gate electrode 3 is provided on the semiconductor substrate 1 via a gate insulating film 3 a, and a source region 4 and a drain region 5 made of p-type impurity regions are provided on the surface of the semiconductor substrate 1 on both sides of the gate electrode 3.

  A barrier layer 7 made of a p-type impurity region having a planar pattern similar to that of the source region 4 and the drain region 5 is provided immediately below the source region 4 and the drain region 5, respectively. The barrier layer 7 having such a planar pattern can be easily formed by ion implantation using the same mask as the formation of the source / drain regions 4 and 5.

  The barrier layer 7 is provided apart from the depletion layer extending from the source and drain regions 4 and 5 during normal operation. On the other hand, since the number of holes flowing into the drain region 5 when α rays are incident increases, it is desirable to dispose them near the source / drain regions 4 and 5 unless they contact the depletion layer. At this time, the depth of the barrier layer 7 is determined so that the upper surface of the barrier layer 7 is located shallower than the depth of the STI 2. In this structure, since the periphery of the barrier layer 7 can be brought into contact with the side wall surface of the STI 2, the influence of the voltage fluctuation generated in the n-well 6 region on the barrier layer 7 on the adjacent field effect transistor is suppressed. be able to.

  Further, the barrier layer 7 is provided in the n-well, that is, at a position sufficiently away from the bottom surface of the n-well 7. In this structure, since the thick n-well 7 is interposed between the p-type semiconductor substrate 1 and the p-type barrier layer 7, the gain of the parasitic bipolar transistor formed between the p-type semiconductor substrate 1 and the p-type barrier layer 7 is small. Even if the potential of the barrier layer 7 fluctuates at the time of incidence, the occurrence of latch-up is suppressed.

  Referring to FIG. 1B, the nMOS transistor 20 is formed in a region surrounded by the STI 2 formed on the surface of the p-type semiconductor substrate 1. A gate electrode 3 is provided on this region via a gate insulating film 3a, and a source region 4 and a drain region 5 made of n-type impurity regions are provided on the surface of the semiconductor substrate 1 on both sides of the gate electrode 3.

  A barrier layer 7 made of an n-type impurity layer having a planar pattern similar to that of the source region 4 and the drain region 5 is provided immediately below the source region 4 and the drain region 5, respectively. The barrier layer 7 is provided so as not to contact the depletion layer extending from the source and drain regions 4 and 5. Further, as long as the pMOS transistor 10 is disposed, it is disposed near the source / drain regions 4 and 5 as long as it is not in contact with the depletion layer, and the upper surface of the barrier layer 7 is disposed shallower than the STI.

  The method for manufacturing the field effect transistor according to the first embodiment of the present invention will be described below.

  FIG. 2 is a cross-sectional view of a manufacturing process according to the first embodiment of the present invention, showing a cross section of the pMOS transistor 10 and the nMOS transistor 21 constituting the CMOS circuit.

Referring to FIG. 2, in the manufacture of the field effect transistor according to the first embodiment of the present invention, first, a trench 2a having a depth of 0.15 μm surrounding the transistor formation region is formed on the upper surface of a semiconductor substrate 1 made of p-type silicon. To do. Next, an SiO ₂ film 2b filling the trench 2a is deposited on the semiconductor substrate 1, the SiO ₂ film 2b deposited on the upper surface of the semiconductor substrate 1 is removed by CMP (chemical mechanical polishing), and the inside is formed by the SiO ₂ film 2b. An embedded STI 2 is formed. The inside of the trench 2a can be filled with another insulator, for example, a two-layer or multilayer film made of SiO ₂ / SiN, or an insulating film such as polysilicon.

  Next, an n-type impurity, for example, P or As is ion-implanted into the pMOS transistor 10 formation region surrounded by the STI 2 where the pMOS transistor 10 is to be formed, thereby forming the n-well 6. Next, the gate electrode 3 is formed on the pMOS transistor 10 formation region via the gate insulating film 3a. The above process is the same as the process for forming a pMOS transistor formed in an n-well in a normal semiconductor device having a double well structure.

Next, referring to FIG. 2B, using a resist mask (not shown) for exposing the pMOS transistor 10 formation region and the gate electrode 3 as a mask, a p-type impurity, for example, B is applied to the pMOS transistor 10 formation region as an acceleration voltage. 4-6 keV, a dose of 1-5 × 10 ¹⁵ cm ⁻² , or As is ion-implanted at an acceleration voltage of 25-30 keV, a dose of 1-5 × 10 ¹⁵ cm ⁻² , a deep position of the n-well 6, for example a barrier layer 7 made of p-type impurity layer distributed at a concentration of 1 × 10 ²⁰ cm ^-3 in the depth range of 0.08μm~0.13μm from the surface. The barrier layer 7 is provided so as to divide the entire n-well 6 vertically except for the region directly below the gate electrode 3, and the outer periphery thereof is in contact with the side surface of the STI 2.

Next, referring to FIG. 2C, a p-type impurity, for example, B is ion-implanted at a low acceleration voltage using the resist mask (not shown) that exposes the pMOS transistor 10 formation region and the gate electrode 3 as a mask. Then, a source region 4 and a drain region 5 made of a p-type impurity region having a surface concentration of 2 × 10 ²⁰ cm ⁻³ are formed on both sides of the gate electrode 3. Thereby, the pMOS transistor 10 is manufactured.

  Next, referring to FIG. 2D, n-type impurities such as P or As are accelerated at a high speed using the resist mask (not shown) that exposes the formation region of the nMOS transistor 20 surrounded by the STI 2 and the gate electrode 3 as a mask. Ions are implanted by voltage to form a barrier layer 7 made of n-type impurities at a deep position in the nMOS transistor 20 formation region. The thickness and depth of the barrier layer 7 can be the same as those of the barrier layer 7 formed in the pMOS transistor 10 formation region. The outer periphery of the barrier layer 7 is preferably formed so as to be in contact with the side surface of the STI 2.

  Next, referring to FIG. 2E, an n-type impurity such as P or As is ion-implanted at a low acceleration voltage using the resist mask (not shown) that exposes the nMOS transistor 20 formation region and the gate electrode 3 as a mask. Then, the source region 4 and the drain region 5 are formed on both sides of the gate electrode 3. Thereby, the nMOS transistor 20 is manufactured.

  After the above steps, a semiconductor device having a double well structure including the pMOS transistor 10 and the nMOS transistor 20 is manufactured through steps such as circuit wiring.

  FIG. 3 is an impurity concentration distribution diagram of the field effect transistor, and shows an impurity concentration distribution in a direction perpendicular to the surface of the semiconductor substrate 1 through the source region 4 or the drain region 5. Note that a SIMS (secondary ion mass spectrometry) apparatus was used to measure the impurity concentration. 7A shows the impurity concentration distribution of the conventional field effect transistor (pMOS transistor) shown in FIG. 9, and FIG. 7B shows the impurity concentration distribution of the pMOS transistor 10 of the first embodiment of the present invention. .

Referring to FIG. 3B, the p-type impurity concentration of the pMOS transistor 10 according to the first embodiment of the present invention is 20 × 10 ¹⁹ cm ⁻³ on the surface of the semiconductor substrate (near depth of 0 μm), and becomes deeper. It decreases rapidly and becomes almost non-doped at a depth of 0.05. The high concentration region on the surface of the semiconductor substrate corresponds to the source region 4 or the drain region 5. Further, a high concentration region of 1 × 10 ²⁰ cm ⁻³ is formed in a depth range of 0.08 μm to 0.13 μm. This high concentration region corresponds to the barrier layer 7.

  As described above, electron / hole pairs are generated along the tracks of α rays incident on the semiconductor substrate 1. Holes generated between the source / drain regions 4 and 5 and the barrier layer 7 are absorbed by the source / drain regions 4 and 5 to generate noise. On the other hand, holes generated in the barrier layer 7 and below the barrier layer remain in the barrier layer 7 because the upper surface of the barrier layer 7 becomes a barrier against the holes, and do not become a noise generation source.

  Referring to FIG. 3A, in the conventional pMOS transistor, only a high concentration impurity region formed on the surface of the semiconductor substrate corresponding to the source region and the drain region is observed, and a deeper region has a high impurity concentration. There is no area.

  In the structure without the barrier layer 7, all the holes generated in the semiconductor substrate 1 (in the n-well in the first embodiment) are absorbed into the source / drain regions, and a large noise is generated.

  FIG. 4 is a comparison diagram of soft error characteristics according to the first embodiment of the present invention, which simulates the time course of drain current when α rays are incident on the pMOS transistor of the first embodiment. In the figure, curve a represents the drain current of the conventional pMOS transistor, and curve b in the figure represents the drain current of the pMOS transistor 10 of the first embodiment of the present invention.

Referring to curve (a) in FIG. 4, in the conventional pMOS transistor, the drain current rapidly increases to a peak value of 7 × 10 ⁻⁴ A slightly after incidence of α rays, and then gradually decreases. On the other hand, in the pMOS transistor 10 according to the first embodiment of the present invention having the barrier layer 7, the peak value of the drain current remains at about 4 × 10 ⁻⁴ A with reference to the curve b in FIG. . Thus, it is clear that the pMOS transistor of the present invention has an excellent soft error resistance because the increase in drain current generated upon incidence of α rays is as small as 60% of the conventional pMOS transistor.

  The same measurement was performed for the nMOS transistor 20 of the first embodiment of the present invention. As a result of comparison between the conventional nMOS transistor having the same concentration distribution as the impurity concentration shown in FIG. 3 and the nMOS transistor 20 of the first embodiment, the change of the drain current at the time of α-ray incidence is almost the same. As described above, the pMOS transistor and the nMOS transistor 20 according to the first embodiment of the present invention have substantially the same soft error resistance, and the deterioration of the soft error resistance in the conventional pMOS transistor is eliminated.

  In the first embodiment, the barrier layer 7 is not formed immediately below the gate electrode 3 but forms a slit-shaped opening. Through this opening, the upper and lower regions of the barrier layer 7 are electrically connected. For this reason, the potential fluctuation generated in the region on the barrier layer 7 (region in which the transistor is formed) upon incidence of α rays is caused by the region below the barrier layer 7 (below the n-well 6 and the semiconductor substrate 1 or the semiconductor substrate 1). ) Causes potential fluctuations in adjacent transistor formation regions. However, in a short channel length transistor, the area of the opening of the barrier layer that opens directly below the gate electrode 3 is sufficiently smaller than the width of the source / drain regions 4 and 5, so that the upper and lower regions pass through the openings. The electrical resistance of the connecting path is large, and the potential fluctuation can be sufficiently suppressed in practical use.

  In the second embodiment of the present invention, a pMOS transistor 11 and an nMOS transistor 21 (p-type field effect transistor and n-type field effect transistor) formed in a double well structure and having a barrier layer provided on the entire horizontal cross section of the transistor formation region. )

  FIG. 5 is a cross-sectional view of a field effect transistor according to the second embodiment of the present invention, showing pMOS and nMOS transistors formed in a double well. 1A shows a cross section of the pMOS transistor 10, and FIG. 1B shows a cross section of the nMOS transistor 20.

  The pMOS and nMOS transistors 11 and 21 of the second embodiment have the same structure as the pMOS and nMOS transistors 10 and 20 of the first embodiment described above, except for the planar shape of the barrier layer 7.

  With reference to FIG. 5, in the second embodiment, the barrier layer 7 is provided over the entire horizontal cross section of the formation region of the pMOS transistor 11 and the formation region of the nMOS transistor 21. Therefore, the formation region of the pMOS transistor 11 is completely surrounded by the STI 2 and the bottom surface thereof is completely surrounded by the barrier layer 7 to be isolated. In addition, the formation region of the nMOS transistor 21 is also completely surrounded by the STI 2 and the barrier layer 7 to isolate the element.

  In the second embodiment, since the transistor formation region is completely surrounded by the STI 2 and the barrier layer 7 and the elements are separated, even if the potential fluctuation in the transistor formation region occurs due to the incidence of α rays, the adjacent transistor formation region The impact on is small.

  A method for manufacturing the field effect transistor according to the second embodiment will be described below.

  FIG. 6 is a cross-sectional view showing a manufacturing process according to the second embodiment of the present invention, and shows a cross section of the pMOS transistor 10 and the nMOS transistor 21 constituting the CMOS circuit.

Referring to FIG. 6A, first, a trench 2a surrounding each formation region of the pMOS transistor 10 and the nMOS transistor 21 is formed on the surface of the semiconductor substrate 1 made of p-type silicon. Next, an SiO ₂ film 2b filling the trench 2a is deposited, and an SiO ₂ film deposited on the upper surface of the semiconductor substrate 1 by CMP is formed to form an STI 2 composed of the trench 2a filled with the SiO ₂ film 2b.

  Next, referring to FIG. 6B, an n-type impurity, for example, P or As is ion-implanted using a first mask (not shown) having an opening that exposes the formation region of the pMOS transistor 11, and n Well 6 is formed. The steps up to here are the same as the manufacturing steps of the first embodiment.

  Next, referring to FIG. 6C, a p-type impurity, for example, B is accelerated at a high speed using the first mask (not shown) used for ion implantation of the n-type impurity for forming the n-well 6. A barrier layer 7 made of a p-type impurity layer is formed deep in the n-well 6 by ion implantation with a voltage. The barrier layer 7 is provided so as to extend over the entire horizontal section of the formation region of the pMOS transistor 11 surrounded by the STI 2. The barrier layer 7 is provided at a position shallower than the bottom of the STI 2, and the periphery of the barrier layer 7 is formed so as to be in contact with the side surface of the STI 2.

  Next, referring to FIG. 6C, the mask (not shown) used for ion implantation of the n-type impurity is removed, and an opening for exposing the formation region of the nMOS transistor 11 is formed on the semiconductor substrate 1. A second mask (not shown) is formed. Then, using this second mask (not shown), an n-type impurity such as P or As is ion-implanted at a high acceleration voltage, and a barrier layer 7 made of an n-type impurity layer is formed deep from the surface of the semiconductor substrate 1. Form. The barrier layer 7 is also formed over the entire formation region of the nMOS transistor 21 so that the periphery is in contact with the side surface of the STI 2. By this step, a pMOS transistor 11 formation region and an nMOS transistor 21 formation region made of an n-type semiconductor and a p-type semiconductor, the periphery of which is surrounded by STI2 and the bottom surface of which is surrounded by the barrier layer 7, are formed.

  Next, referring to FIG. 6D, gate electrodes 3 are formed on the pMOS transistor 11 formation region and the nMOS transistor 21 formation region via the gate insulating film 3a, respectively.

  Next, referring to FIG. 6 (e), p-type impurities are ion-implanted at a low acceleration voltage using the mask (not shown) for exposing the pMOS transistor 11 formation region and the gate electrode 3 as a mask. A source region 4 and a drain region 5 of the pMOS transistor 11 made of a p-type impurity region are formed on both sides. Thereby, the pMOS transistor 11 was manufactured.

  Next, the mask (not shown) that exposes the pMOS transistor 11 formation region is removed, and a mask (not shown) that exposes the nMOS transistor 21 formation region is formed. Using a mask (not shown) for forming the nMOS transistor 21 formation region and the gate electrode 3 as a mask, n-type impurities are ion-implanted at a low acceleration voltage, and the nMOS transistor 21 is formed of n-type impurity regions on both sides of the gate electrode 3. Source region 4 and drain region 5 are formed. Thereby, the pMOS transistor 21 was manufactured.

  Through the above steps, a semiconductor device having the pMOS transistor 11 and the nMOS transistor 21 constituting the CMOS circuit in the double well is manufactured.

  The third embodiment of the present invention relates to a semiconductor device having a triple well structure.

  FIG. 7 is a cross-sectional view of a field effect transistor according to the third embodiment of the present invention, showing a pMOS transistor and an nMOS transistor formed in a triple well.

  Referring to FIG. 7A, in the first example of the third embodiment, an n well 16 and a p well 17 are formed on the surface of the p-type semiconductor substrate 1. The n-well 16 is provided over the formation region of the pMOS transistor 12 and the formation region of the nMOS transistor 22. The p-well 17 is provided in the formation region of the nMOS transistor 22 in the n-well 16. These n-well 16 and p-well 17 form a triple well structure formed on the surface of the p-type semiconductor substrate 1. Note that the pMOS transistor 12 formation region and the nMOS transistor 22 formation region are each surrounded by STI2 and element-isolated.

  A pMOS transistor 12 having p-type source / drain regions 4 and 5 and a p-type barrier layer 7 provided immediately below is formed in the pMOS transistor 12 formation region including the n-well 16. An nMOS transistor 22 having n-type source / drain regions 4 and 5 and an n-type barrier layer 7 provided immediately below is formed in the nMOS transistor 22 formation region formed of the p-well 17. The pMOS transistor 12 and the nMOS transistor 22 according to the first example have the same structure as that of the pMOS transistor 10 and the nMOS transistor 20 of the first embodiment except for the difference in well structure, and the same soft error. Tolerant.

  The second example of the third embodiment of the present invention relates to a semiconductor device in which a field effect transistor having the structure of the second embodiment is formed in a triple well structure.

  Referring to FIG. 7B, in the second example of the third embodiment, an n well 16 and a p well 17 similar to those in the first example are formed on the surface of the p-type semiconductor substrate 1. . Then, the pMOS transistor 13 and the nMOS transistor 23 having the same structure as the pMOS transistor 11 and the nMOS transistor 21 of the second embodiment are formed in the n well 16 and the p well 17, respectively. The second embodiment is different from the first embodiment in that the barrier layer 7 is formed over the entire horizontal cross section of the transistor formation region.

  The third example of the third embodiment of the present invention is a modification of the p-well 17 structure of the second example.

  Referring to FIG. 7C, in the third embodiment, a structure in which the p well 17 in which the nMOS transistor 23 of the second embodiment is formed is replaced with an n well in the lower part of the barrier layer 7 is formed. Have That is, the nMOS transistor 24 of the third embodiment differs from that of the second embodiment in that the n-type barrier layer 7 is not formed on the lower surface of the p-well 17 where the nMOS transistor 24 is formed and is directly in contact with the n-well 16. Is different.

  Even in this structure, since a barrier against holes is formed at the interface between the p-well 17 and the n-well 16 in contact with the bottom surface, the same high soft error resistance as in the second embodiment is obtained. Note that a layer (7) similar to the barrier layer 7 in which n-type impurities are ion-implanted at a high concentration may be formed in the vicinity of the n-well 16 in contact with the bottom surface of the p-well 17 to increase the barrier against holes.

  The fourth embodiment of the present invention relates to a field effect transistor in which a barrier layer is connected to a low power supply potential or a high power supply potential.

  FIG. 8 is an explanatory diagram of a field effect transistor structure according to the fourth embodiment of the present invention. 8A shows a cross section of the field effect transistor, and FIG. 8B shows a plan view.

  Referring to FIG. 8A, in the fourth embodiment, the barrier layer 7 of the pMOS transistor 10 of the first embodiment is connected to the low power supply potential Vcc through the lead line 9c. On the other hand, the barrier layer 7 of the nMOS transistor 20 of the first embodiment is connected to the high power supply potential Vdd via the lead line 9d. By doing so, a reverse bias voltage is applied to the barrier layer 7 and the semiconductor region constituting the transistor formation region on the barrier layer 7, so that the barrier against holes or electrons becomes large and noise at the time of α-ray incidence. Is reduced.

  Further, holes generated by the incidence of α rays are integrated in the barrier layer 7 constituting the pMOS transistor 10 of the first embodiment, and the voltage of the barrier layer 7 varies. This voltage fluctuation reduces the barrier against holes on the upper surface of the barrier layer 7 and increases noise, thereby lowering the soft error withstand voltage. Similar voltage fluctuations in the barrier layer 7 also occur in the nMOS transistor 20 of the first embodiment.

  In the field effect transistor of the fourth embodiment, since the barrier layer 7 of the pMOS transistor 10 in which holes are integrated is connected to the low power supply potential Vcc, the holes flow into the low power supply potential Vcc and disappear. For this reason, even if a large amount of electron / hole pairs are generated by the incidence of α rays, the potential fluctuation of the barrier layer 7 can be reduced.

  The nMOS transistor 20 in which electrons are integrated is similarly described by replacing holes with electrons and replacing a low potential with a high potential. Therefore, the field effect transistors 10 and 20 of the fourth embodiment have high soft error resistance.

  Referring to FIG. 8B, STIs that respectively surround the pMOS transistor 10 formation region and the nMOS transistor 10 formation region are formed on the surface of the semiconductor substrate 1. A gate electrode 3 is provided across each formation region. Source / drain regions 4 and 5 are formed along the gate electrode 3, and a barrier layer 7 is provided immediately below the source / drain regions 4 and 5 so as to overlap the source / drain regions 4 and 5.

  At this time, the source / drain regions 4 and 5 are formed to be shorter than the gate electrode 3, and a transistor formation region where the source / drain regions 4 and 5 are not formed appears on one end side of the gate electrode 3. Deploy. Then, connection lines 9c and 9d connected to the barrier layer 7 are formed in the transistor formation region where the source / drain regions 4 and 5 are not formed.

  The connection lines 9c and 9d are each made of a high-concentration impurity region having the same conductivity type as that of the barrier layer 7, and can connect the barrier layer 7 and the external power supply potential with a low resistance. The source / drain regions 4 and 5 exposed on the surface of the semiconductor substrate 1 are connected to circuit wirings through contact holes 4a and 5a, respectively, in the same manner as in a normal CMOS circuit.

The present specification described above discloses the invention described in the following supplementary notes.
(Supplementary note 1) In a field effect transistor in which elements are separated by a buried insulating film formed on a semiconductor substrate,
An impurity region having the same conductivity type as the source region and the drain region is provided under the source region and the drain region of the transistor,
The field effect transistor, wherein the impurity region is formed at a position shallower than a bottom of the buried insulating film.
(Supplementary note 2) The field effect transistor according to supplementary note 1, wherein an outer periphery of the impurity region is provided in contact with a side surface of the buried insulating film.
(Supplementary note 3) The field effect transistor according to Supplementary note 1 or 2, wherein the impurity region is provided on the entire surface of the region isolated by the buried insulating film.
(Supplementary note 4) Any one of Supplementary notes 1 to 3, wherein the source region, the drain region, and the impurity region are p-type conductivity and are provided in an n-well or an n-type semiconductor substrate. Field effect transistor.
(Supplementary note 5) The field effect transistor according to supplementary note 4, wherein the impurity region is connected to a low power supply potential.
(Appendix 6) When the impurity region is p-type, the impurity region is connected to a low power supply potential.
5. The field effect transistor according to any one of appendices 1 to 4, wherein when the impurity region is n-type, the impurity region is connected to a high power supply potential.
(Supplementary note 7) In a field effect transistor in which elements are separated by a buried insulating film formed on a semiconductor substrate,
The transistor is formed in an n-well;
An impurity region made of a p-type impurity region is provided immediately below a source region and a drain region made of a p-type impurity region constituting the transistor,
The field effect transistor according to claim 1, wherein the impurity region is formed at a position shallower than a bottom of the buried insulating film in the n-well.
(Supplementary note 8) The field effect transistor according to supplementary note 7, wherein the impurity region including the p-type impurity region provided in the n-well is provided apart from a bottom surface of the n-well.
(Supplementary note 9) The field effect transistor according to supplementary note 4, wherein the impurity region is connected to a low power supply potential.

  By applying the present invention to a semiconductor device having CMOS static memory cells, a semiconductor device with few malfunctions due to soft errors can be provided.

First Embodiment Field Effect Transistor Cross Section First embodiment of the present invention manufacturing process sectional view Impurity concentration distribution map of field effect transistor Comparison diagram of soft error characteristics according to the first embodiment of the present invention Second Embodiment Field Effect Transistor Cross Section View of the Present Invention Sectional view of manufacturing process of second embodiment of the present invention Third Embodiment Field Effect Transistor Cross Section View of the Present Invention Fourth embodiment of the present invention Field effect transistor structure explanatory diagram Cross section of a conventional field effect transistor Sectional view of a field effect transistor formed in a conventional triple well structure Cross-sectional view of a conventional field effect transistor with improved soft error resistance

Explanation of symbols

1 Semiconductor substrate 2 STI (embedded insulating film)
2a trench 2b SiO ₂ film 3 gate electrode 3a gate insulating film 4 source region 4a 5a contact hole 5 drain region 6, 601 n-well 7 barrier layer (impurity region)
8, 801 p-well 9c, 9d leader lines 10, 11, 12 pMOS transistor 16 n-well 17 p-well 20, 21, 22 nMOS transistor 501 p-type impurity region 502 n-type impurity region 701 barrier layer Vcc low power supply potential Vdd high power supply potential

Claims (5)

In a field effect transistor separated by a buried insulating film formed on a semiconductor substrate,
An impurity region having the same conductivity type as the source region and the drain region is provided under the source region and the drain region of the transistor,
The field effect transistor, wherein the impurity region is formed at a position shallower than a bottom of the buried insulating film.   2. The field effect transistor according to claim 1, wherein an outer periphery of the impurity region is provided in contact with a side surface of the buried insulating film.   3. The field effect transistor according to claim 1, wherein the impurity region is provided on the entire surface of the region isolated by the buried insulating film.   4. The field effect transistor according to claim 1, wherein the source region, the drain region, and the impurity region are p-type conductivity and are provided in an n-well or an n-type semiconductor substrate. When the impurity region is p-type, the impurity region is connected to a low power supply potential;
5. The field effect transistor according to claim 1, wherein when the impurity region is n-type, the impurity region is connected to a high power supply potential.

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