CN102646680B

CN102646680B - Semiconductor device and manufacture method thereof

Info

Publication number: CN102646680B
Application number: CN201210036105.3A
Authority: CN
Inventors: 竹内雅彦
Original assignee: Renesas Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 2011-02-22
Filing date: 2012-02-15
Publication date: 2016-11-30
Anticipated expiration: 2032-02-15

Abstract

The present invention provides a kind of semiconductor device and manufacture method thereof.The present invention can prevent the contact plunger sandwiching the docking section between gate electrode to be short-circuited via the cavity formed in the dielectric film of described docking section.On the side wall (SW) that docking section between gate electrode (G2) and (G5) is relative, form liner insulating film (6) and interlayer dielectric (7).Between side wall (SW), make liner insulating film (6) contact formed respectively on the sidewall of side wall (SW), and then make to close between side wall (SW), thus prevent the inside at interlayer dielectric (7) with liner insulating film (6) from producing cavity.

Description

Semiconductor device and manufacture method thereof

Technical field

The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly relate to one and be applicable to manufacture there is docking section It is spaced the effective technology of the semiconductor element of narrower gate electrode.

Background technology

Along with the propelling of the granular of semiconductor device, such as reduction of gate abutting direction (grid width direction, i.e. with Constitute SRAM [Static Random Access Memory: static RAM) the bearing of trend of grid parallel Direction]) design time, there is the side that patterns of gate electrode to constituting SRAM by double exposure and twice etching Method.The method is to have added to realize the granular of semiconductor device to cut off the skill that the mask of grid end is processed Art, is used for having along the unidirectional MIS (Metal being arranged with gate electrode that is multiple and that extend in the direction discontinuously Insulator Semiconductor: metal-insulator semiconductor (MIS)) (Field Effect Transistor: the field effect of type FET Transistor) etc..In present patent application, add mask to process the docking section between gate electrode pattern aforementioned Technology be referred to as end-grain cutting (end cut).By using end-grain cutting, it is arranged in string making multiple gate patterns along bearing of trend Time, it is possible to reduce the interval of the docking section between each gate electrode accurately to form gate electrode.

Patent documentation 1 (Japanese Unexamined Patent Publication 2009-252825 publication) is recorded and has been formed at narrower gate electrode Between interlayer dielectric in prevent cavity (void), thus prevent the region clipped between described gate electrode and configure Conductive material because of cavity the phenomenon that is switched on.Wherein describe the subregion reduced between adjacent gate electrode in length and breadth The method of ratio.It addition, technology described in patent documentation 1 is not about relative to each other and close right between the end of gate electrode Meet portion.

Patent documentation 1: Japanese Unexamined Patent Publication 2009-252825 publication

Summary of the invention

In the semiconductor device of the gate electrode that there is use end-grain cutting and formed, in the grid length direction of gate electrode Between upper adjacent gate electrode, the interval between gate electrode is wider than the interval between the gate electrode of above-mentioned docking section, therefore exists There is no problem for the imbedibility of the interlayer dielectric formed between gate electrode.But, achieving the semiconductor device of granular, In such as semiconductor device below 32nm node, on the bearing of trend of gate electrode, (docking between adjacent gate electrode Portion) the imbedibility of interlayer dielectric there may exist problem.

If carrying out end-grain cutting, then at gate electrode in the manufacturing process of the semiconductor device such as 32nm node or 28nm node Bearing of trend between adjacent gate electrode the distance of (docking section) be up to 30～about 50nm.This have narrower When forming interlayer dielectric on multiple gate electrodes at interval, owing at docking section, distance between gate patterns is narrower, therefore Imbedibility is deteriorated, it is possible to form cavity (space) in interlayer dielectric.Subsequently, if being formed with cavity to sandwich The mode of docking section forms contact hole on interlayer dielectric, and imbeds the conductive materials such as W (tungsten) in each contact hole to be formed Contact plunger, then conductive material also can be filled in described cavity, causes two contact plungers via the conduction in described cavity Material causes short circuit (short), thus causes yield penalty or cause the problem of reliability decrease of semiconductor device.

It is an object of the invention to improve the yield rate in manufacturing process, or improve the reliability of semiconductor device.

The purpose of the present invention is particular in that prevent between contact plunger because the phenomenon of short circuit occurs in the cavity between gate electrode.

Purpose and new feature beyond the described content of the present invention and described content are said at description and the accompanying drawing of this specification Write exactly in bright.

It is briefly described as follows about representative embodiment in embodiment disclosed in present patent application Summary.

The semiconductor device of a currently preferred embodiment is for having: multiple gate electrodes, the plurality of grid electricity Pole upwardly extends the 1st side along Semiconductor substrate first type surface, and is formed at described quasiconductor along described 1st direction arrangement On substrate；1st dielectric film, described 1st dielectric film is formed between the plurality of gate electrode adjacent on described 1st direction； 2nd dielectric film, the side of described 2nd dielectric film the plurality of gate electrode on 2nd direction orthogonal with described 1st direction Face, and it is formed at the upper surface of the described Semiconductor substrate exposed from described gate electrode；And multiple contact plunger, described many Individual contact plunger is arranged in the both sides of described 1st dielectric film, and is connected in described Semiconductor substrate, and, described 1st insulation Film and described 2nd dielectric film constitute the 3rd dielectric film, and described 3rd dielectric film is to cover described Semiconductor substrate and the plurality of grid The mode of pole electrode is formed, and the extreme lower position of described 1st dielectric film upper surface is than the extreme lower position of described 2nd dielectric film upper surface High.

And, in the preferred embodiment of the present invention, the manufacture method of semiconductor device includes following operation: operation (a), The most on a semiconductor substrate, form the operation of multiple gate electrode across gate insulating film, the plurality of gate electrode along 1st side of described Semiconductor substrate first type surface upwardly extends, and along described 1st direction arrangement；Operation (b), i.e. the plurality of The operation of regions and source/drain is formed on the first type surface of the Semiconductor substrate of gate electrode both sides；Operation (c), i.e. described many The operation of side wall is formed on the sidewall of individual gate electrode；Operation (d), i.e. after described operation (b) and described operation (c), In described Semiconductor substrate, from institute in the way of covering the plurality of gate electrode, described regions and source/drain and described side wall State semiconductor-substrate side and sequentially form the 2nd dielectric film and the operation of the 3rd dielectric film；And operation (e), i.e. in described 1st direction The both sides in the region between upper adjacent the plurality of gate electrode, form through described 2nd dielectric film and described 3rd dielectric film Multiple through holes after, formed in the respective inner side of the plurality of through hole and be connected to the contact of described regions and source/drain The operation of connector；Further, adjacent on the described 1st direction described 2nd dielectric film upper surface between the plurality of gate electrode Extreme lower position, than on 2nd direction orthogonal with described 1st direction, be formed at from the plurality of gate electrode and described side The lowest order of the described 2nd dielectric film upper surface on the upper surface of the described Semiconductor substrate that wall exposes sets high.

Be briefly described as follows about in disclosed invention in present patent application according to representative embodiment The effect obtained.

The present invention can improve the yield rate of semiconductor device manufacturing process, it is also possible to improves the reliability of semiconductor device.

The present invention can occur the phenomenon of short circuit between contact plunger because of the cavity between gate electrode.

Accompanying drawing explanation

Shown in Fig. 1 is the plane figure of semiconductor device in embodiments of the present invention 1.

Shown in Fig. 2 is the profile cut open along the line A-A of Fig. 1.

Shown in Fig. 3 is the profile cut open along the line B-B of Fig. 1.

Shown in Fig. 4 is the profile cut open along the line C-C of Fig. 1.

Shown in Fig. 5 (a) is the equivalent circuit diagram of the SRAM of embodiment 1.Shown in Fig. 5 (b) is in embodiment 1 half The profile of conductor device.

Shown in Fig. 6 (a) is for the profile of semiconductor device manufacturing process in embodiment 1 is described.Fig. 6 (b) institute Show is for the profile of semiconductor device manufacturing process in embodiment 1 is described.

Shown in Fig. 7 (a) is the profile of the semiconductor device manufacturing process of then Fig. 6 (a).Shown in Fig. 7 (b) is to connect The profile of the semiconductor device manufacturing process of Fig. 6 (b).

Shown in Fig. 8 is the plane figure of the semiconductor device manufacturing process of then Fig. 7 (a) and Fig. 7 (b).

Shown in Fig. 9 (a) is the profile of the semiconductor device manufacturing process of then Fig. 7 (a).Shown in Fig. 9 (b) is to connect The profile of the semiconductor device manufacturing process of Fig. 7 (b).

Shown in Figure 10 is the plane figure of the semiconductor device manufacturing process of then Fig. 9 (a) and Fig. 9 (b).

Shown in Figure 11 (a) is the profile of the semiconductor device manufacturing process of then Fig. 9 (a).Shown in Figure 11 (b) it is Then the profile of the semiconductor device manufacturing process of Fig. 9 (b).

Shown in Figure 12 (a) is the profile of the semiconductor device manufacturing process of then Figure 11 (a).Shown in Figure 12 (b) It it is the profile of the semiconductor device manufacturing process of then Figure 11 (b).

Shown in Figure 13 (a) is the profile of the semiconductor device manufacturing process of then Figure 12 (a).Shown in Figure 13 (b) It it is the profile of the semiconductor device manufacturing process of then Figure 12 (b).

Shown in Figure 14 (a) is the profile of the semiconductor device manufacturing process of then Figure 13 (a).Shown in Figure 14 (b) It it is the profile of the semiconductor device manufacturing process of then Figure 13 (b).

Shown in Figure 15 (a) is the profile of the semiconductor device manufacturing process of then Figure 14 (a).Shown in Figure 15 (b) It it is the profile of the semiconductor device manufacturing process of then Figure 14 (b).

Shown in Figure 16 (a) is the profile of the semiconductor device manufacturing process of then Figure 15 (a).Shown in Figure 16 (b) It it is the profile of the semiconductor device manufacturing process of then Figure 15 (b).

Shown in Figure 17 (a) is the profile of the semiconductor device manufacturing process of then Figure 16 (a).Shown in Figure 17 (b) It it is the profile of the semiconductor device manufacturing process of then Figure 16 (b).

Shown in Figure 18 (a) is the profile of the 1st variation in embodiment 1.Shown in Figure 18 (b) is embodiment 1 In the profile of the 1st variation.

Shown in Figure 19 is the profile of the 2nd variation in embodiment 1.

Shown in Figure 20 is the profile of the 3rd variation in embodiment 1.

Shown in Figure 21 is the profile of the 3rd variation in embodiment 1.

Shown in Figure 22 is the profile of semiconductor device in embodiments of the present invention 2.

Shown in Figure 23 is the profile of semiconductor device in embodiments of the present invention 2.

Shown in Figure 24 is the plane figure of the semiconductor device of comparative example.

Shown in Figure 25 is the profile of the semiconductor device of comparative example.

Symbol description

1 Semiconductor substrate

2 element isolation regions

2a groove

3 gate insulating films

4 silicon oxide films

4a offset spacers

5 silicon nitride films

6 liner insulating films

6a liner insulating film

7 interlayer dielectrics

7a contact hole

8 stop dielectric film

9 interlayer dielectrics

9a wiring groove

BL1 bit line

BL2 bit line

D15 drain region

D26 drain region

D3 drain region

D4 drain region

E1 first node

E2 second node

G1～G6 gate electrode

GL, GM, GN gate electrode

M1 metal line

MG metal gate layers

MGa metal level

NS silicide layer

NW N-shaped trap

P1 contact plunger

P2 contact plunger

PE p-type semiconductor regions

PG polysilicon layer

PGa polysilicon layer

PL contact plunger

PS diffusion layer

PW p-type trap

Q1～Q6MI SFET

S1～S6 source region

SD regions and source/drain

SP space

SW side wall

Vdd power supply potential line

Vss arranges equipotential line

WL wordline

Detailed description of the invention

Embodiments of the present invention are described in detail below according to accompanying drawing.In order to illustrate in all figures of embodiment, principle On to have same function component use same symbol, dispense the explanation of repetition.It addition, except needing special instruction In addition, it is not repeated having on same or same Some principles.

(embodiment 1)

The semiconductor device of present embodiment is described with reference to Fig. 1～Fig. 5 (a).Shown in Fig. 1 is to have by being formed at half The plane figure of the semiconductor device of the SRAM that the multiple MISFET on conductor substrate are constituted.Shown in Fig. 2 is to have composition The profile of the gate electrode of the MISFET formed on semiconductor substrate 1, between the gate electrode on the line A-A of display Fig. 1 The section of docking section (gate terminal counterpart).Shown in Fig. 3 is the profile cut open along the line B-B of Fig. 1, display grid electricity The docking section of interpolar and the contact plunger being formed on gate electrode.Shown in Fig. 4 is the section cut open along the line C-C of Fig. 1 Figure, shows the gate electrode of MISFET of the SRAM shown in pie graph 1, regions and source/drain and is formed at these area top The section of contact plunger.The line A-A of Fig. 1 and line B-B are the bearing of trend i.e. lines in grid width direction along gate electrode, Line C-C is orthogonal with line A-A and line B-B and the line in grid length direction along gate electrode.Shown in Fig. 5 (a) is Fig. 1 institute The equivalent circuit diagram of the SRAM shown.

SRAM uses the sequential circuits such as trigger (flip flop) to store data, is that the supply of one once unregulated power is deposited The volatile memory that storage content will disappear.SRAM Yu DRAM (Dynamic Random Access Memory: dynamic random Access memorizer) different, owing to employing flip-flop circuit in storage part, therefore need not update operation, be that one can Reduce the storage circuit of the power consumption stored under hold mode.As the structure of memory element, SRAM can be divided into by four crystalline substances High load resistance type device that body pipe and two high-resistance components are constituted and the CMOS being made up of six transistors (Complementary MOS: complementary metal oxide semiconductors (CMOS)) type device.Present embodiment is entered as a example by CMOS-type SRAM Row explanation, CMOS-type SRAM becomes current main flow device owing to leakage current is the least and reliability is high when keeping data.

In FIG, in order to make drawing be easily understood, it is shown that by the source/drain being formed at Semiconductor substrate upper surface Region and form multiple MISFET that gate electrode on a semiconductor substrate constitutes, be formed in each regions and source/drain and Contact plunger on gate electrode and be formed at the element isolation region of Semiconductor substrate upper surface, but other cloth are not shown Line or interlayer dielectric etc..The region that dotted line in Fig. 1 surrounds includes six MISFETQ1～Q6 constituting a SRAM, half Multiple SRAM, described SRAM it is formed with using the structure surrounded by aforementioned imaginary line as a unit on conductor substrate.

Constitute the gate electrode the 1st direction extension each along Semiconductor substrate first type surface of MISFETQ1～Q6.Constitute The gate electrode G1 of MISFETQ1 and MISFETQ3 and the gate electrode G3 constituting MISFETQ6 is formed along the 1st direction arrangement, structure The gate electrode G2 becoming MISFETQ2 and MISFETQ4 and the gate electrode G4 constituting MI SFETQ5 is formed along the 1st direction arrangement. That is, the extended line that gate electrode G1 extends forms gate electrode G3, the extended line that gate electrode G2 extends is formed grid Pole electrode G4.

The relative end of gate electrode G1 and G 3 is close to each other, in present patent application, as it has been described above, will along with One direction extend between arrangement and adjacent gate electrode relative to end between region (gate terminal counterpart) be referred to as grid electricity The docking section of pole.Similarly, the relative end of gate electrode G2 and G4 is close to each other, also has between gate electrode G2 and G4 There is docking section.The interval for example, 40nm of docking section between each gate electrode on 1st direction in present embodiment.

Gate electrode G1～G4 is formed in the electrode on same layer, gate electrode G2 and gate electrode G4 along electric with grid Orthogonal and along Semiconductor substrate first type surface the direction, direction that is the 2nd of the bearing of trend of pole G1 is arranged.And, gate electrode G3 and gate electrode G2 adjacent formation on the 2nd direction.It addition, the grid width direction that the 1st direction is gate electrode G1～G4, 2nd direction is the grid length direction of gate electrode G1～G4.In the side in the 2nd direction of gate electrode G1, there is gate electrode The docking section of G2, G4, has the docking section of gate electrode G1, G3 in the side in the 2nd direction of gate electrode G2.

It addition, in the way of sandwiching gate electrode G2, form gate electrode G5 in the opposition side of gate electrode G4.Grid electricity Pole G5 has docking section between gate electrode G2, constitutes MISFET contained in other SRAM.And, at gate electrode G1 The side in the 2nd direction and the orientation of non-grid electrode G2, G4 form gate electrode G6, gate electrode G6 and constitute in other SRAM Contained MISFET.

MISFETQ1, MISFETQ3 have gate electrode G1, and MISFETQ2, MISFETQ4 have gate electrode G2, MISFETQ5 has gate electrode G4, and MISFETQ6 has gate electrode G3.District between gate electrode G1 and gate electrode G2 P-type semiconductor region i.e. source region S3 it is formed with on the first type surface of the Semiconductor substrate in territory, and, in source region, S3 is contrary On the first type surface of the Semiconductor substrate of side, in the way of clipping gate electrode G1, form p-type semiconductor region i.e. drain region D3, MISFETQ3 is constituted by source region S3, drain region D3 and gate electrode G1.And, at gate electrode G1 and gate electrode G2 Between region Semiconductor substrate first type surface on be formed with p-type semiconductor region i.e. source region S4, and, in source region On the first type surface of the Semiconductor substrate of S4 opposition side, in the way of clipping gate electrode G2, form p-type semiconductor region i.e. drain Region D4, and constituted MISFETQ4 by source region S4, drain region D4 and gate electrode G2.That is, MISFETQ3, MISFETQ4 For p-channel type field-effect transistor.

It is formed with n-type semiconductor on the first type surface of the Semiconductor substrate in region between gate electrode G1 and gate electrode G4 Region i.e. drain region D15, and, on the first type surface of the Semiconductor substrate of D15 opposition side, drain region, to clip grid electricity The mode of pole G1 forms n-type semiconductor region i.e. source region S1, by drain region D15, source region S1 and gate electrode G1 Constitute MISFETQ1.Further, on the first type surface of the Semiconductor substrate of D15 opposition side, drain region, to clip gate electrode G4 Mode form n-type semiconductor region i.e. source region S5, drain region D15, source region S5 and gate electrode G4 are constituted MISFETQ5。

Similarly, between gate electrode G2 and gate electrode G3, it is formed with n on the first type surface of the Semiconductor substrate in region Type semiconductor regions i.e. drain region D26, and, on the first type surface of the Semiconductor substrate of D26 opposition side, drain region, with folder The mode gate electrode G2 forms n-type semiconductor region i.e. source region S2, by drain region D26, source region S2 and grid Pole electrode G2 constitutes MISFETQ2.Additionally, on the first type surface of the Semiconductor substrate of D26 opposition side, drain region, to clip grid The mode of pole electrode G3 forms n-type semiconductor region i.e. source region S6, by drain region D26, source region S6 and grid electricity Pole G3 constitutes MISFETQ6.

That is, MISFETQ1, MISFETQ2, MISFETQ5 and MISFETQ6 is n-channel type field-effect transistor.And, MISFETQ1 and MISFETQ5 common drain region D15, MISFETQ2 and MISFETQ6 common drain region D26.

On the 1st direction, source region S3 is arranged between source region S4 and drain region D15.At gate electrode G2 With on the top of the end of the gate electrode G2 near the docking section of gate electrode G4 and source region S3, it is formed continuously relatively The contact plunger P2 of the column vertically extended in the first type surface of Semiconductor substrate, contact plunger P2 are electrically connected in grid Electrode G2 and source region S3, therefore gate electrode G2 and source region S3 electrically connects (refer to Fig. 4).Similarly, close Contact plunger P1, gate electrode have been formed continuously it on the top of the end of the gate electrode G1 of gate electrode G3 and source region S4 G1 and source region S4 is electrically connected by contact plunger P1.

And, at source region S1, S2, S5, S6, drain region D15, D3, D26, D4, gate electrode G 3 and G4 each Top be respectively formed with contact plunger PL.The contact plunger PL on the S1 of source region and on the S2 of the source region cloth by upper strata Line (not shown) electrically connects, and supplies same current potential to source region S1 and source region S2.Contact on the D15 of drain region Connector PL and contact plunger P2 is electrically connected by the wiring (not shown) on upper strata, similarly, and the contact on the D26 of drain region Connector PL and contact plunger P1 is electrically connected by the wiring (not shown) on upper strata.

The figure of gate electrode G1～G4 shown in Fig. 1 is not partly to be led being formed at by single exposure and once etching Film on body substrate is processed and is formed, but by expose at least twice and twice etching and formed.This is in order to high-precision The processing method that degree ground carries out trickle processing to the docking section of gate electrode and uses, processes grid electricity by double patterning Pole, i.e. the 1st direction along gate electrode form the patterning of sidewall and form the patterning of sidewall along the 2nd direction, thus The interval of docking section between the gate electrode in the 1st direction can be reduced further.In present embodiment, form grid as previously mentioned Repeatedly pattern during electrode.In present patent application, by described repeatedly patterning in be processed to form the right of gate electrode Patterning operation when meeting portion is referred to as end-grain cutting.

Such as, in present embodiment, when forming gate electrode G1～G4, first, in order to form the grid electricity in the 1st direction The docking section of interpolar, after the sidewall formed along the 2nd direction of each gate electrode is patterned (end-grain cutting), then to edge Each gate electrode the 1st direction formed sidewall pattern so that along the 2nd direction arrangement gate electrode between The first type surface of Semiconductor substrate exposes.But, the order of patterning when carrying out end-grain cutting is not limited to this, it is also possible to above-mentioned phase Instead, as after the sidewall formed along the 1st direction of gate electrode is patterned, then to along the of each gate electrode The sidewall that 2 directions are formed carries out patterning (end-grain cutting).

It follows that use Fig. 5 (a) that the structure of above-mentioned SRAM is described.As shown in the equivalent circuit diagram of Fig. 5 (a), this enforcement In mode, SRAM has six MISFETQ1～MISFETQ6, the source electrode (source area shown in Fig. 1 of MISFETQ5, MISFETQ6 Territory S5, S6) it is connected to bit line BL1 and BL2, the gate electrode (gate electrode shown in Fig. 1 of MISFETQ5, MISFETQ6 G3, G4) it is connected to wordline WL.

The drain electrode (the drain region D15 shown in Fig. 1) of MISFETQ5 is connected to the drain electrode of MISFETQ1 via first node E1 The source electrode (the source region S3 shown in Fig. 1) of (the drain region D15 shown in Fig. 1), MISFETQ3, MISFETQ2 and MISFETQ4 Grid (the gate electrode G2 shown in Fig. 1).Similarly, the drain electrode (the drain region D26 shown in Fig. 1) of MISFETQ6 is via 2 node E2 are connected to the drain electrode (the drain region D26 shown in Fig. 1) of MISFETQ2, the source electrode (source shown in Fig. 1 of MISFETQ4 Territory, polar region S4), the grid (the gate electrode G1 shown in Fig. 1) of MISFETQ1 and MISFETQ3.

The drain electrode (drain region D3, the D4 shown in Fig. 1) of MISFETQ3, MISFETQ4 is all connected to power supply potential line Vdd, The source electrode (source region S1, the S2 shown in Fig. 1) of MISFETQ1, MISFETQ2 is all connected to arrange equipotential line Vss. MISFETQ5, MISFETQ6 are the field-effect transistor of transmission, MISFETQ1, MISFETQ2 and MISFETQ3, MISFETQ4 be respectively n-channel transistor npn npn is combined with p-channel transistor npn npn CMIS (Complementary MIS: Complimentary mis body quasiconductor) inverter.Herein, in order to carry out the write/read of data, constitute by MISFETQ1, The flip-flop circuit that CMIS with MISFETQ3 of MISFETQ2, the CMIS of MISFETQ4 are connected in the way of cross-lapping.

The method of operating of SRAM is described below.In the write activity of SRAM, improve the electricity of wordline WL shown in Fig. 5 (a) Press and the grid of MISFETQ5, MISFETQ6 is set to conducting state, improve the voltage of bit line BL1, and reduce the electricity of bit line BL2 Pressure, thus store data " 1 " in first node E1 on the left of flip-flop circuit, in second node E2 on the right side of flip-flop circuit Storage data " 0 ".If on the contrary, reduce the voltage of bit line BL1, improving the voltage of bit line BL2, then deposit in first node E1 Storage data " 0 ", stores data " 1 " in second node E2.Now, even if the voltage of wordline WL is dropped to 0V, if the electricity of device Source is still connected, then the data " 1 ", " 0 " that write still can continue storage.

When the reading operation of data, improve the voltage of wordline WL and be set to lead by the grid of MISFETQ5, MISFETQ6 Logical state, now, according to the state (first node E1 and " 1 " of second node E2, the combination of " 0 ") of storage, at bit line BL1 and Produce potential difference between BL2, therefore amplify by detection amplifier and detect this potential difference.

As in figure 2 it is shown, such as first type surface in the Semiconductor substrate 1 being made up of monocrystal silicon is formed and has imported n-type impurity The p-type trap PW of (such as B (boron)) and element isolation region 2, across being made up of silicon oxide film on the first type surface of Semiconductor substrate 1 Gate insulating film 3 and be respectively formed with gate electrode G2 and G5.P-type trap PW be respectively formed at gate electrode G2, G5 just under Side, on the first type surface of the Semiconductor substrate 1 immediately below the docking section between the end that gate electrode G2 and G5 is relative, such as, is formed There is the element isolation region 2 being made up of silicon oxide film.Gate electrode G2, G5 respectively include starting layer successively from Semiconductor substrate 1 side Metal gate layers MG being made up of TiN (titanium nitride) film etc. being stacked on gate insulating film 3 and polysilicon layer PG, at polysilicon layer The silicide layer NS comprising nickel (Ni) etc. such as it is formed on PG.

On the respective sidewall of gate electrode G2, G5, being formed with the side wall SW with stepped construction, described stepped construction is The region starting from Semiconductor substrate 1 side to be sequentially laminated with between silicon oxide film 4 and silicon nitride film 5, and gate electrode G2, G5 is Most of region of docking section is side wall SW.Offset spacers 4a being made up of silicon oxide film is between gate electrode G2, G5 each Sidewall and side wall SW between.

Being formed on the sidewall of gate electrode G2, G5, side wall SW does not connects side wall SW autoregistration (self-aligning) The upper surface of the sidewall and side wall SW that touch gate electrode has continuous print curved surface.Therefore, the side wall SW of the sidewall of gate electrode G2 And the distance between the side wall SW of the sidewall of gate electrode G5, uprises along with the height of the first type surface from Semiconductor substrate 1 and makes Interval becomes big, between each side wall SW, is formed in the way of covering the Semiconductor substrate first type surface comprising gate electrode G2, G5 Liner insulating film 6.That is, be formed between liner insulating film 6 and the respective sidewall of gate electrode G2, G5 side wall SW and skew every Absciss layer 4a.

The dielectric film that liner insulating film 6 is e.g. made up of SiN (silicon nitride) film, is embedded with the contact shown in Fig. 1 being formed During the contact hole of connector P1, P2 and PL etc., there is the effect of etching barrier film.Liner insulating film 6 is formed at the 1st as shown in Figure 2 Between gate electrode adjacent on direction, and as shown in Figure 4, the side of each gate electrode on the 2nd direction, it is also formed in The upper surface of the Semiconductor substrate 1 that the side wall SW formed on each gate electrode and sidewall exposes.Now, gate electrode G2, G5 The height that the extreme lower position of liner insulating film 6 upper surface on top, docking section is positioned at than gate electrode G2, the upper surface of G5 is higher Region.And, on liner insulating film 6, it is sequentially formed with interlayer dielectric 7 from the main surface side of Semiconductor substrate 1, stops Dielectric film 8, interlayer dielectric 9.Interlayer dielectric 7,9 is such as made up of silicon oxide film, stops that dielectric film 8 is such as by silicon nitride film Constitute.When forming, in interlayer dielectric 9, the wiring groove being embedded with metal line, stop that dielectric film 8 has the work of etching barrier film With.

As it is shown on figure 3, the section comprising gate electrode G1, G3 has the structure similar to Fig. 2.But, at gate electrode The surface of G1, G3 is respectively formed with contact plunger P1, PL, the first type surface of the Semiconductor substrate 1 immediately below contact plunger P1 On be formed with element isolation region 2.Gate electrode G1, G3 of being made up of metal gate layers MG and polysilicon layer PG are via at polycrystalline On silicon layer PG formed silicide layer NS and electrically connect with contact plunger P1, PL respectively.Contact plunger P1, PL respectively be formed at Each metal line M1 electrical connection on top.

By silicide layer NS is interposed between gate electrode and regions and source/drain and contact plunger, it is possible to decrease grid The contact resistance of pole electrode and regions and source/drain and contact plunger.Silicide layer NS is the conversion zone of metal and silicon, such as may be used Use nickel silicide, cobalt silicide, Platinum Silicide or Titanium silicide etc. as the material of silicide layer NS.

Contact plunger P1, PL are across intercepting the connection member that electrically conductive film (not shown) is formed, and intercept electrically conductive film It is formed at inwall and the bottom of contact hole 7a.Contact plunger P1, PL are such as made up of tungsten etc., in the obstruct that sidewall and bottom are formed Electrically conductive film is such as made up of titanium nitride etc..

Metal line M1 is the wiring to the MISFET supply regulation current potential constituting SRAM, is inlayed by well-known metal Embedding technology and formed.The obstruct electrically conductive film that metal line M1 is formed by inwall and the bottom at wiring groove 9a with across described obstruct Electrically conductive film and the metal film that is filled in wiring groove 9a is constituted.Described obstruct electrically conductive film is such as by Ta (tantalum) and TaN (tantalum nitride) Stacked film constitute, described metal film is the film being mainly made up of Cu (copper).Described obstruct electrically conductive film is to prevent described gold Belong in the metallic element in film is diffused into interlayer dielectric 9 and wait and arrange.It addition, as the material of obstruct electrically conductive film, except tantalum In addition, it is also possible to use titanium (Ti), ruthenium (Ru), manganese (Mn) or the compound etc. of these elements.

Now, identical with the structure shown in Fig. 2, the docking section of gate electrode G1, G3 and with the phase of gate electrode G1, G3 To sidewall on be respectively formed with side wall SW, configure in the way of major part contacts between described side wall SW.Therefore, at grid The most interelectrode docking section, the space of embedment liner insulating film 6 is less, liner insulating film 6 upper surface directly over docking section Extreme lower position is positioned at the higher region of the upper surface than gate electrode G1, G3, thus without the liner insulating film 6 on docking section Upper surface formed bigger concavo-convex, thus become the most smooth shape.

As shown in Figure 4, on the section along the 2nd direction on the line C-C of Fig. 1, it is shown that constitute the grid of MISFETQ3 Electrode G1, source region S3 and the section of drain region D3.On the first type surface of Semiconductor substrate 1, it is formed with element isolation zone Territory 2 and imported the n-type semiconductor region i.e. N-shaped trap NW of p-type impurity (such as P (phosphorus)).On semiconductor substrate 1, across grid Pole dielectric film 3 is formed with gate electrode G2, G1 and G6, on the sidewall of each gate electrode both sides, across offset spacers 4a shape Become to have side wall SW.On the first type surface of the Semiconductor substrate 1 of gate electrode G1 both sides, to clip the n immediately below gate electrode G1 The mode of type trap NW is formed with source region S3 and drain region D3.

Source region S3 and drain region D3 has: to have imported the n-type impurity (such as B (boron)) of high concentration and to have engaged deep Spend deeper semiconductor regions i.e. diffusion layer PS；And imported the concentration n-type impurity lower than diffusion layer PS (such as B (boron)) and The semiconductor regions i.e. p-type semiconductor regions PE that depth of engagement is more shallow than diffusion layer PS.P-type semiconductor regions PE is formed at side wall On the N-shaped trap NW of SW bottom, diffusion layer PS is formed self-aligned at gate electrode G1, G2, G6 and the N-shaped trap exposed from side wall SW The upper surface of NW.Respectively gate electrode G2 and the sidewall of gate electrode G2 a side wall SW be formed immediately below with element every From region 2, the first type surface of Semiconductor substrate 1 is formed without N-shaped trap NW.

It is formed with silicide layer NS at diffusion layer PS, the respective upper surface of gate electrode G1, G2 and G6, constitutes drain region Be formed with contact plunger PL across silicide layer NS on the diffusion layer PS of territory D3, constitute source region S3 diffusion layer PS on and It is formed with contact plunger P2 across silicide layer NS on gate electrode G2.Contact plunger P2 from the upper surface of gate electrode G2 to structure Become the upper surface of the diffusion layer PS of source region S3, be continuously formed and be integrated, and, to cover gate electrode G2 i.e. near grid The mode of the sidewall of electrode G1 side, pole and formed.

Identical with the structure shown in Fig. 3, contact plunger P2, PL shown in Fig. 4 are formed at and run through liner insulating film 6 and interlayer In the contact hole 7a of dielectric film, described liner insulating film 6 and interlayer dielectric are sequentially formed at has gate electrode G1, G2 and side On the first type surface of the Semiconductor substrate 1 of wall SW.Be sequentially formed with on the respective top of contact plunger P2, PL stop dielectric film 8 and Interlayer dielectric 9, is formed with a plurality of metal line M1, leakage in the wiring groove 9a running through interlayer dielectric 9 and stop dielectric film 8 Territory, polar region D3 electrically connects with metal line M1 across silicide layer NS and contact plunger PL.And, gate electrode G2 and The source region S3 of MISFETQ3 electrically connects via silicide layer NS and contact plunger P2.

Gate electrode G1, G2 shown in Fig. 4 are identical with the gate electrode shown in Fig. 2, Fig. 3, by metal gate layers MG and shape The polysilicon layer PG on MG top is become to constitute.With being a difference in that of Fig. 2, Fig. 3, between the most not shown gate electrode Docking section, and the interval of gate electrode G1, G2 adjacent on the 2nd direction arranges bigger than the docking section shown in Fig. 2, Fig. 3.This It is to form regions and source/drain and contact plunger between gate electrode.Therefore, and between the gate electrode in the 1st direction Docking section is different, and between gate electrode adjacent on the 2nd direction, the interval between side wall SW is wider than docking section, liner insulating film 6 Without being widely formed on the first type surface of Semiconductor substrate across gate electrode or side wall SW.Now, shown in Fig. 2 On 1 direction the height of the minimum upper surface of the liner insulating film 6 of docking section between adjacent gate electrodes be positioned at than shown in Fig. 4 The higher region of height of the minimum upper surface of liner insulating film 6 between adjacent gate electrodes on 2nd direction.

It follows that the effect of the semiconductor device of present embodiment is illustrated.SRAM as shown in Figure 1, along the 1st Direction is arranged in the semiconductor device of multiple gate electrode, along with the granular of device, the docking section between gate electrode Narrow intervals with 30～about 50nm is formed, and the imbedibility of the dielectric film that therefore there is the docking section between gate electrode is deteriorated Problem.The dielectric film of the docking section for example, liner insulating film 6 shown in Fig. 2 and Fig. 3 in present embodiment.Figure at gate electrode In the docking section that interval between shape is narrower, it is difficult to liner insulating film 6 is closely imbedded the deeper groove between gate electrode In, therefore it is easily generated cavity (space) in the liner film of docking section.

In order to producing the structure in above-mentioned cavity, particularly the structure easily producing cavity being illustrated, in fig. 24 Show the gate electrode of the plane figure of comparative example, i.e. semiconductor device and the plane figure of regions and source/drain.? In Figure 24, it is shown that be formed in Semiconductor substrate (not shown) and in the 1st direction along Semiconductor substrate first type surface Multiple gate electrode GN of upper extension, formed in the way of clipping gate electrode GN on the 2nd direction orthogonal with the 1st direction In two regions and source/drain SD of Semiconductor substrate first type surface and be respectively formed at the contact in each regions and source/drain SD Connector PL.Identical with the semiconductor device of the present embodiment shown in Fig. 1, gate electrode GN is along respective bearing of trend that is 1 direction has been arranged multiple, and between the relative end of adjacent gate electrode GN, (docking section) is spaced apart about 40nm Narrow intervals.In present embodiment, use end-grain cutting when forming the docking section of gate electrode.

In fig. 24, regions and source/drain SD is by along in the way of the 1st side upwardly extending gate electrode GN, along the 1st Direction extends and is formed.Gate electrode GN is formed, with this in the way of the disconnection of midway discontinuously by the figure extended along the 1st direction Relatively, even if regions and source/drain SD also will not disconnect near the docking section that gate electrode GN interrupts, but shown in Figure 24 Region in, be formed continuously along the docking section between multiple gate electrode GN and described gate electrode GN.

That is, regions and source/drain SD is formed in the way of clipping the docking section of gate electrode GN on the 2nd direction and partly leads On the first type surface of body substrate.And, in each regions and source/drain SD, in the way of clipping docking section, it is formed with contact plunger In PL, this enforcement and mode, the contact plunger PL of contact plunger PL, docking section and the opposite side of side joins along the 2nd direction arrangement Put.That is, between the contact plunger PL in each regions and source/drain SD configured in the way of clipping gate electrode GN, have Do not form the region of gate electrode GN.Though not shown in figure, but on the first type surface of described Semiconductor substrate, with cover source electrode/ Drain region SD, the mode of gate electrode GN are formed with dielectric film.Described dielectric film is also formed in the district between contact plunger PL At the territory i.e. docking section of gate electrode, the through described dielectric film of contact plunger PL and be connected to regions and source/drain SD.

Shown in Figure 25 is the profile of the semiconductor device of another comparative example, for including along Semiconductor substrate 1 master meter Between two gate electrode GM that the 1st direction in face extends relative to end between region, along the profile in the 1st direction. The gate electrode GM of the semiconductor device of the comparative example shown in Figure 25 uses end-grain cutting, and carries out pattern by twice etching work procedure Change, the distance for example, 40nm between gate electrode GM adjacent on the 1st direction.

Identical with the semiconductor device of the present embodiment shown in Fig. 2, the gate electrode GM shown in Figure 25 and GM sidewall Side wall SW has stepped construction.And, identical with the plane figure shown in Figure 24, between the gate electrode GM shown in Figure 25 The side of docking section, is formed with contact plunger (figure in the way of clipping docking section on the 2nd direction orthogonal with the 1st direction Not shown in).It addition, the dielectric film shown in Figure 24 is corresponding to the liner insulating film 6a shown in Figure 25.

As shown in figure 25, apart from each other, at gate electrode due to the distance between the side wall SW of the sidewall of gate electrode GM The docking section of GM is formed with the groove making the upper surface of Semiconductor substrate 1 expose, and the upper surface of liner insulating film 6a is at docking section There is the shape caved in significantly.Specifically, the upper surface of liner insulating film 6a is positioned at ratio gate electrode GM at docking section The low region of upper surface and near the region of Semiconductor substrate 1 upper surface.It addition, the first type surface of Semiconductor substrate 1 is at grid There is portion concave the docking section of electrode GM, this is because the upper surface of Semiconductor substrate 1 is owing to forming the etching work procedure of side wall SW Etc. the reason being partly removed.Therefore, it is possible to judge that be not limited only to docking section, the half of the side in the 2nd direction of gate electrode GM The upper surface of conductor substrate 1 also there will be portion concave.

This is because, in the docking section of gate electrode GM, from the upper surface of relative side wall SW formed to sidewall each Liner insulating film 6a does not contacts each other, the reason that liner insulating film 6a is not closed out at docking section.That is, in docking section, In any region, the value of the relative width between side wall SW is all than the of the liner insulating film 6a formed on the sidewall of side wall SW More than the big twice of value of the thickness in 1 direction.

It addition, the thickness of liner insulating film 6a is about 20nm on the upper surface of gate electrode, from the side of docking section It is 10～about 15nm on the first type surface of the Semiconductor substrate 1 that wall SW exposes.The liner insulating film formed on the surface of side wall SW The thickness of 6a is the most thinning towards bottom from the top on the surface of side wall SW, such as at the thinnest position, with the table of side wall SW The thickness of the liner insulating film 6a in the direction that face is vertical is about 10nm.It addition, thickness described in present embodiment refers to, The direction perpendicular with the substrate surface that liner insulating film 6a lower surface contacts i.e. from the lower surface of liner insulating film 6a to upper table The distance in face.

When using CVD (Chemical Vapor Deposition: chemical gaseous phase deposition) method etc. on semiconductor substrate 1 When forming liner insulating film 6a, the thickness of the liner insulating film 6a that the sidewall of the figure of gate electrode GM etc. is formed, than formation Expose area comparison and connect on the first type surface of the big Semiconductor substrate 1 of the area in portion or be formed at gate electrode GM first-class with partly lead The thickness of the liner insulating film 6a on the face of the major surfaces in parallel of body substrate 1 is thin.This is because: formed on the sidewall of figure The coverage rate (tunicle rate) of dielectric film is poorer than the dielectric film formed on the face of the upper surface etc. of gate electrode GM.It addition, at grid On the sidewall of pole electrode GM when side wall SW forms liner insulating film 6a too.

In the case of the coverage rate for example, 100% of liner insulating film, the lining formed on the upper surface of gate electrode The thickness of pad dielectric film and the thickness of the liner insulating film formed on the sidewall of gate electrode are the most identical in any region.But It is that the inwall coverage rate at the narrowest groove has the tendency of deterioration, if coverage rate is poor, then the liner of the sidewall of gate electrode The thickness of dielectric film is the most thinning towards bottom by the top from described sidewall.

Form the narrow intervals that docking section is 30～about 50nm between the gate electrode GM of liner insulating film 6a, relatively Side wall SW between interval narrower, in the case of the upper surface of the Semiconductor substrate 1 exposed between side wall SW is less, it is believed that be At docking section, the liner on the Film Thickness Ratio gate electrode GM of the liner insulating film 6a from the Semiconductor substrate 1 that side wall SW exposes is exhausted The thickness of velum 6a is thin.

I.e., as shown in figure 25, if in the docking section of gate electrode GM from the upper surface of gate electrode GM relative to partly leading The upper surface of body substrate 1 forms deeper groove, then relative to side wall SW between the coverage rate of liner insulating film 6a will be deteriorated, thus It is prone to be formed above-mentioned cavity in liner insulating film 6a.It addition, cavity not shown in Figure 25.

In the semiconductor device of above-mentioned comparative example, it is believed that with grid electricity adjacent on the 1st direction shown in Figure 25 The lowest order of the liner insulating film 6a upper surface between the GM of pole is compared, at the gate electrode GM of the side in gate electrode GM the 2nd direction And the lowest order of the liner insulating film 6a upper surface formed the upper surface of the Semiconductor substrate 1 exposed from the side wall SW of GM sidewall Put and be formed at higher region.This is because, such as the bottom of the narrow groove such as the docking section between gate electrode GM, liner insulating film The coverage rate of 6a reduces, with the liner insulating film of Semiconductor substrate 1 upper surface of the side in the 2nd direction of aforementioned gate electrode GM 6a is formed at the film of wide region and compares, and thickness is relatively thin.

In the semiconductor device of the structure shown in Figure 24 and Figure 25, the docking between gate electrode GN if as discussed above It is formed with cavity in the dielectric film (the such as liner insulating film 6a shown in Figure 25) formed at portion, then clips the close of docking section By the metal parts because being formed in described cavity be short-circuited (short) between contact plunger PL, thus cause semiconductor device The problem that part cannot normally work.Once be short-circuited fault, and the reliability of semiconductor device will reduce, and yield rate will be disliked Change.Reason is as follows: i.e., form the dielectric film (such as liner insulating film) with cavity in docking section after, to clip docking section Mode forms through described dielectric film and two contact holes of interlayer dielectric being formed on described dielectric film, is then respectively connecing When filling, in contact hole, the metal material constituting contact plunger PL, described metal material also will be filled in described cavity, thus Two contact plunger PL are caused to be connected to each other because of cavity.

That is, in the case of the dielectric film formed at docking section has cavity, if near docking section and in the 1st direction The side of the 2nd both sides, direction of upper docking section between adjacent gate electrode and gate electrode forms contact plunger, then respectively Between each contact plunger may because of in cavity formed metal parts and be short-circuited.

In as of fig. 24 two structures close to each other in the way of clipping docking section for contact plunger PL easily There are the problems referred to above.But, in the construction shown in fig. 1, the such as contact plunger on contact plunger P2 and source region S5 Between PL, it is also possible to send out via the cavity in the dielectric film that the docking section between gate electrode G2 and gate electrode G4 is formed Raw short circuit.That is, it is connected to source/drain when the both sides of liner insulating film 6 formed near docking section and in docking section are formed with During the contact plunger in territory, polar region, if being formed with cavity in described liner insulating film 6, will be short-circuited between contact plunger therefore Barrier.

It addition, in the semiconductor device of present embodiment, as it is shown in figure 1, gate electrode is arranged along the 2nd direction, But arranging bigger than the docking section between the gate electrode in the 1st direction along the interval between the gate electrode of the 2nd direction arrangement, liner is exhausted The imbedibility of velum 6 (refer to Fig. 4) is better than docking section, thus without producing cavity between gate electrode.This is because, right Connect in the case of portion arranges interval with the narrower distance of 30～about 50nm and be more prone to cavity.Therefore, such as Figure 24, Tu25Suo Present embodiment shown in the comparative example illustrated and Fig. 1 is the same, uses in order to docking section is carried out the trickleest processing When end-grain cutting forms gate electrode, the interval between gate electrode may be made to be formed narrower, therefore be easier to occur because of above-mentioned sky Hole and short trouble between the contact plunger that causes.

And, SRAM as shown in Figure 1, such as, use end-grain cutting to make the less shape in interval between the gate electrode in the 1st direction In the semiconductor device become, in any region on a semiconductor substrate, all it is likely to form as of fig. 24 to clip grid The mode of the docking section of pole electrode configures the layout of contact plunger.If on the contrary, in order to avoid occur above-mentioned short trouble, and It is formed without the layout configuring contact plunger in the way of clipping gate electrode docking section shown in Figure 24, the then cloth of semiconductor element The degree of freedom of office will reduce, and thus result in the problem such as area increase of semiconductor device.

It addition, be the generation avoiding above-mentioned short trouble, also there is following methods: i.e., being set to docking section And wide as the interval between the gate electrode adjacent on the 2nd direction shown in Fig. 1, but owing to the method cannot reduction of gate electricity The interval of the docking section of pole, is accordingly difficult to realize the granular of semiconductor device.

Between gate terminal when being spaced apart the narrower region of 30～about 50nm, especially from the upper surface of gate electrode to The degree of depth of the groove of the height of Semiconductor substrate first type surface, i.e. docking section is the biggest, the most easily forms cavity in above-mentioned dielectric film.That is, In the case of being imbedded deep trouth by liner insulating film 6, easily produce cavity.On the contrary, in the present embodiment, as in figure 2 it is shown, In the way of the side wall SW major part contact of the docking section between gate electrode adjacent on the 1st direction, make relative side wall Mutually near being formed between SW, and reduce the groove being embedded with the liner insulating film 6 being formed at docking section such that it is able to prevent liner from insulating The coverage rate of film 6 is deteriorated, and can suppress to be formed cavity in liner insulating film 6.It addition, at docking section relative to side wall SW also The part contact of side can be made to be integrally forming.

Such as, in the semiconductor device shown in Fig. 2, at docking section, the upper surface of liner insulating film 6 is without bigger recessed Fall into, more smooth than the liner insulating film 6a shown in Figure 25, the aspect ratio gate electrode G2 of the upper surface that therefore liner insulating film 6 is minimum And the height of the respective upper surface of G5 is higher.That is, docking section between the gate electrode adjacent on the 1st direction shown in Fig. 2 The height of the minimum upper surface of liner insulating film 6, between being positioned at than the gate electrode adjacent on the 2nd direction shown in Fig. 4 The higher region of height of the minimum upper surface of liner insulating film 6.In other words, it is being formed in Semiconductor substrate and edge Multiple gate electrodes that same direction (the 1st direction) extends and there is the plurality of gate electrode semiconductor device in, along grid The extreme lower position of the dielectric film upper surface between the gate electrode that pole width (the 1st direction) arranges, is positioned at ratio grid length side The higher region of extreme lower position of the dielectric film upper surface between the gate electrode in (the 2nd direction).

This is because, at docking section relative to side wall SW closer to each other, thus, from side wall SW upper surface to sidewall formed Each liner insulating film 6 contact with each other with relative each side wall SW and close.That is, in docking section, have between relative side wall SW Width value become the twice area below of film thickness value in the 1st direction of the liner insulating film 6 formed on the sidewall of side wall SW. Thus, compared with the comparative example shown in Figure 24 and Figure 25, owing to the flatness of liner insulating film 6 on docking section can be improved, and can The coverage rate of suppression liner insulating film 6, thus can prevent from producing cavity in liner insulating film 6.

If representing said structure with formula, then formula is as follows:

S₁≤2×(a+αt) (1)

In present embodiment, as shown in Fig. 5 (b), S₁For the distance between gate electrode GL adjacent on the 1st direction. But, when being formed with offset spacers 4a at the sidewall of gate electrode GL, S₁For between relative offset spacers 4a away from From.A is the width of side wall SW upper end.In the upper end of side wall SW, silicon nitride film 5 is substantially eliminated, and therefore a in formula (1) can It is considered the thickness in the 1st direction of silicon oxide film 4.α is the liner insulating film of the end in the 1st direction of gate electrode GL upper surface The coverage rate (%) of 6, t is that the thickness of liner insulating film 6 sets.α t is the thickness of the liner insulating film 6 of the sidewall of side wall SW Value.It addition, Fig. 5 (b) is the profile of the semiconductor device of the present embodiment for formula (1) is described.Shown in Fig. 5 (b) Semiconductor device has a structure as the semiconductor device shown in Fig. 2, but at liner insulating film 6 not shown in Fig. 5 (b) The structure that top is formed.

In the present embodiment, by carrying out design of Structural Parameters so that above-mentioned formula (1) is set up, thus at docking section Make liner insulating film 6 close, prevent liner insulating film 6 to be formed at the bottom of deep trouth of docking section.Insulate at liner in above-mentioned cavity Film 6 is susceptible in the case of being formed at deep trouth bottom, is therefore formed at the bottom of docking section by suppression liner insulating film 6, Then without filling deep trouth by liner insulating film 6, thus cavity generation can be prevented.

Therefore, in the semiconductor device of present embodiment, it is possible to prevent from being formed cavity in the dielectric film of docking section, from And be prevented from multiple contact plunger and be short-circuited via the metal parts formed in cavity, wherein, multiple contact plunger shapes Cheng Yu is along two of the docking section between multiple gate electrode GL and gate electrode GL of the direction extension of Semiconductor substrate first type surface Side.This prevents the semiconductor elements such as such as SRAM normally to work, thus improve the reliability of semiconductor device.

It addition, the liner insulating film 6 formed under conditions of formula (1) is set up not is formed at the side of relative side wall SW The bottom of wall, but near the sidewall upper of the relative gate electrode GL of docking section, i.e. at the upper table than gate electrode GL Higher position, face is closed.Now, with liner insulating film 6 in docking section and lower at the upper surface than gate electrode GL Position is closed, i.e. the upper surface that the extreme lower position of liner insulating film 6 upper surface of docking section is positioned at than gate electrode GL is lower The situation in region compare, the liner insulating film 6 at docking section is more smooth, thus is difficult to be internally formed cavity.

And, as shown in Figure 25, though the upper surface of Semiconductor substrate 1 because formed side wall SW etching work procedure and by portion Divide and remove, thus become the shape of depression, in the semiconductor device of present embodiment, as in figure 2 it is shown, phase on the 1st direction The height of the minimum upper surface of the liner insulating film 6 of the adjacent docking section between gate electrode, be still located at than shown in Fig. 4 the The higher region of height of the upper surface that liner insulating film 6 between gate electrode adjacent on 2 directions is minimum.

It follows that be described with reference to the manufacturing process of the semiconductor device of present embodiment.Fig. 6, Fig. 7, Fig. 9 and Figure 11 ～be the semiconductor device of an embodiment of the present invention manufacturing process such as with the semiconductor device of SRAM shown in Figure 17 Profile.Fig. 6 (a), Fig. 7 (a), Fig. 9 (a), Figure 11 (a), Figure 12 (a), Figure 13 (a), Figure 14 (a), Figure 15 (a), Figure 16 (a) and The profile being on the section identical with Fig. 2 shown in Figure 17 (a).And, Fig. 6 (b), Fig. 7 (b), Fig. 9 (b), Figure 11 (b), Figure 12 (b), Figure 13 (b), Figure 14 (b), Figure 15 (b), Figure 16 (b) and be in cut open identical with Fig. 4 shown in Figure 17 (b) Profile on face.Shown in Fig. 8 and Figure 10 is that the semiconductor device of one embodiment of the present invention such as has partly leading of SRAM The plane figure of the manufacturing process of body device.

First, as shown in Fig. 6 (a) and Fig. 6 (b), prepare by having 1～10 Ω about the cm p-type monocrystal silicon etc. than resistance The Semiconductor substrate (semiconductor wafer) 1 constituted.It follows that described Semiconductor substrate 1 is carried out thermal oxide and is formed on surface Thickness is as after for the 1st dielectric film of about 11nm, then by CVD etc. at the upper strata ulking thickness of the 1st dielectric film is such as 2nd dielectric film of about 90nm.1st dielectric film is made up of silicon oxide etc., and the 2nd dielectric film is made up of silicon nitride film etc..Then, will Photoresist figure (not shown) is as etching mask, successively to the 2nd dielectric film, the 1st dielectric film and Semiconductor substrate 1 Carry out dry-etching, thus formed about such as degree of depth 300nm in the Semiconductor substrate 1 that element separation forms presumptive area Groove (element separation from groove) 2a.Groove 2a is the groove of element separation, the groove that element isolation region 2 the most described later is formed.

Then, on the first type surface of the Semiconductor substrate 1 of the inside (sidewall and bottom) including groove 2a, such as, thickness is formed The 3rd dielectric film for about 10nm.Then, on the first type surface of Semiconductor substrate 1 (on the i.e. the 3rd dielectric film), to fill groove 2a Interior mode, forms (accumulation) the 4th dielectric film by CVD etc..

3rd dielectric film is made up of silicon oxide film or silicon oxynitride film.In the case of the 3rd dielectric film is silicon oxynitride film, By the heat treatment that the 3rd dielectric film formation process is later, following effect can be obtained: can prevent because the sidewall of groove 2a aoxidizes And the volumetric expansion caused is it is thus possible to reduce the compression stress acting on Semiconductor substrate 1.

4th dielectric film is to be become by HDP-CVD (High Density Plasma CVD: high-density plasma CVD) method The silicon oxide film of film or O₃-TEOS oxide-film etc..It addition, O3-TEOS oxide-film refers to use O₃(ozone) and TEOS (Tetraethoxysilane: tetraethoxysilane, also referred to as Tetra Ethyl Ortho Silicate) is as unstrpped gas (source gas) the silicon oxide film formed by thermal cvd.

It follows that such as Semiconductor substrate 1 is carried out heat treatment with about 1150 DEG C, to the 4th insulation in embedment groove 2a After film is sintered, grind the 4th by CMP (Chemical Mechanical Polishing: cmp) method exhausted Velum and make the 2nd dielectric film expose, after using the Wet-type etching of hot phosphoric acid etc. to remove the 2nd dielectric film, utilize HF etc. to remove Remove the 4th dielectric film outside groove 2a and the 1st dielectric film, make the 3rd dielectric film, the 4th dielectric film remain in the inside of groove 2a, thus shape Become element isolation region (element separation) 2.

As it has been described above, define the element isolation region 2 being made up of the 3rd dielectric film in embedment groove 2a, the 4th dielectric film. In the present embodiment, element isolation region 2 is not by LOCOS (Local Oxidization of Silicon: silicon local Oxidation) method, preferably formed by STI (Shallow Trench Isolation: shallow-trench isolation) method.That is, present embodiment Element isolation region 2 preferably by insulator (this enforcement in the groove 2a of element separation formed in embedment Semiconductor substrate 1 Mode is the 3rd dielectric film, the 4th dielectric film) constitute.Constitute n-channel type MISFET described later and (i.e. constitute n-channel type MISFET The n-type semiconductor region of gate insulating film, gate electrode and source/drain and n⁺Type semiconductor regions) and p-channel type MISFET (i.e. constitutes the gate insulating film of p-channel type MISFET, gate electrode and the p-type semiconductor regions of source/drain And p⁺Type semiconductor regions) it is formed in (surrounding) active area specified by element isolation region 2.

It follows that from the first type surface of Semiconductor substrate 1 until prescribed depth, form p-type trap PW (refer to Fig. 6 (a)) and n Type trap NW (refer to Fig. 6 (b)).P-type trap PW can be by forming the photic anti-of presumptive area by covering p-channel type MISFET Erosion agent film (not shown) stops mask as ion implanting, such as, n-channel type MISFET is formed partly leading of presumptive area Body substrate 1 injects n-type impurity ions such as boron (B) etc. and the p-type semiconductor region that formed.And, N-shaped trap NW can be by by Other photoresist film (not shown)s covering n-channel type MISFET formation presumptive area are covered as ion implanting prevention Film, the Semiconductor substrate 1 that p-channel type MISFET is formed presumptive area injects the such as p-type impurity ion such as phosphorus (P) or arsenic (As) Deng and the n-type semiconductor region that formed.Owing to p-type trap PW and N-shaped trap NW cannot concurrently form, it is necessary to successively formed, but no matter Which is initially formed.

It follows that as shown in Fig. 7 (a) and Fig. 7 (b), such as by using the Wet-type etching etc. of Fluohydric acid. (HF) aqueous solution After making the clean surface (cleaning) of Semiconductor substrate 1, on the surface of Semiconductor substrate 1 (i.e. p-type trap PW's and N-shaped trap NW Surface) upper formation gate insulating film 3.Gate insulating film 3 is such as made up of thin silicon oxide film etc., such as by thermal oxidation method etc. Formed.

Then, on semiconductor substrate 1 (i.e. on the gate insulating film 3 of p-type trap PW and N-shaped trap NW), from Semiconductor substrate 1 Side starts to stack gradually metal level MGa and polysilicon layer PGa, using the electrically conductive film formed as gate electrode.Metal level MGa by TiN (titanium nitride) films etc. are constituted, such as, formed on semiconductor substrate 1 by sputtering method etc..Polysilicon layer PGa can also pass through After film forming, amorphous silicon film layer during film forming is become polysilicon film by the heat treatment (after ion implanting).

It follows that as shown in Fig. 8, Fig. 9 (a) and Fig. 9 (b), use photoetching process and dry etching method to metal level MGa, many Crystal silicon layer PGa and gate insulating film 3 pattern, so that having the first type surface of the Semiconductor substrate 1 of element isolation region 2 Part is exposed.Fig. 8 is the plane figure for semiconductor device manufacturing process is described.Fig. 9 (a) is to cut open along the line A-A of Fig. 8 The profile opened, Fig. 9 (b) is the profile cut open along the line C-C of Fig. 8.

Described patterning is for being formed at the 1st upwardly extending gate electrode of side along Semiconductor substrate first type surface Operation, but as shown in Figure 8, only form a part of sidewall of the gate electrode formed in aftermentioned operation.That is, aftermentioned operation is formed Gate electrode have by the sidewall extended along the 1st direction and the rectangular shape constituted along the sidewall in the 2nd direction when overlooking, And in described patterning, only form the sidewall along the 2nd direction.Thus, the upper surface of element isolation region 2 is at multiple positions The polysilicon layer PGa formed from Semiconductor substrate exposes.

Gate electrode is formed multiple along the 1st direction arrangement, therefore in Fig. 9 (a), i.e. shows the docking between gate electrode In the profile in portion, metal level MGa, polysilicon layer PGa and gate insulating film 3 are partly removed, but in Fig. 9 (b), are i.e. formed The region of gate electrode and the profile along the 2nd direction, metal level MGa, polysilicon layer PGa and gate insulating film 3 are not removed Go.

It follows that as shown in Figure 10, Figure 11 (a) and Figure 11 (b), use photoetching process and dry etching method to metal level MGa, Polysilicon layer PGa and gate insulating film 3 pattern, thus form the grid being made up of metal level MGa and polysilicon layer PGa Electrode G1～G6.In present embodiment, pattern in the way of the sidewall in each gate electrode the 1st direction by formation.By The sidewall in the 1st direction of each gate electrode formed in described operation and Fig. 8, Fig. 9 (a) and the pattern described in Fig. 9 (b) The sidewall of the preformed each gate electrode of chemical industry sequence, the gate electrode of the rectangle extended along the 1st direction is along the 1st direction arrangement shape Become to have multiple.And, as mentioned above along the 1st Directional discontinuity the structure that constitutes of multiple gate electrodes of being formed along with the 1st side Arrange to the 2nd orthogonal direction be formed multiple.In fig. 10 it is shown that be formed at the grid formed by described operation Electrode G1～G6 and the upper surface of Semiconductor substrate and from the element isolation region 2 that gate electrode G1～G6 exposes, p-type trap PW and N-shaped trap NW.

Now, in Figure 11 (a), i.e. show the docking section of gate electrode G2 and G5 and for along the section in the 1st direction In figure, metal level MGa, polysilicon layer PGa and gate insulating film 3 are the most processed, and in Figure 11 (b), i.e. along the 2nd direction In layer profile, it is shown that gate electrode G2, G1 and the G6 formed along the 2nd direction arrangement.

May be used without only by once patterning the method forming gate electrode, but as it has been described above, in present embodiment In, use the patterning operation illustrated by Fig. 8, Fig. 9 (a) and Fig. 9 (b) illustrated with Figure 10, Figure 11 (a) and Figure 11 (b) Patterning operation altogether double patterning.Fig. 8, Fig. 9 (a) and the patterning operation illustrated by Fig. 9 (b) refer to for being formed along the 1 direction extends and arranges the operation of the docking section being formed with between multiple gate electrodes along the 1st direction, it is possible to be referred to as end-grain cutting Operation.With with compared with once patterning the disposable situation forming gate electrode, add that end-grain cutting operation forms each gate electrode Docking section time can remove the metal level MGa of docking section, polysilicon layer PGa and gate insulating film 3 accurately.That is, by inciting somebody to action Patterning operation when forming gate electrode is divided into and repeatedly carries out end-grain cutting, the grid narrower owing to can form the interval of docking section Electrode, is therefore more easily implemented the granular of semiconductor device.

It addition, in the present embodiment, in including the patterning of gate electrode of end-grain cutting operation, first carry out after end-grain cutting again Carry out patterning and forming gate electrode G1～G6, but be not limited to this, it is also possible to be initially formed along gate electrode the 1st direction Side, carries out end-grain cutting the most again and forms gate electrode G1～G6.Now, be initially formed along the 1st direction extend long figure it After, this image separation is become multiple figure, thus forms gate electrode G1～G6.Now, adjacent on the 1st direction grid electricity Between pole, (docking section) is spaced apart about 40nm.

It follows that as shown in Figure 12 (a) and Figure 12 (b), the p-type trap PW of the gate electrode both sides on p-type trap PW is injected The p-type impurity ions such as phosphorus (P) or arsenic (As), thus form (a pair) n-type semiconductor region (not shown).And, to n The N-shaped trap NW of the gate electrode both sides on type trap NW injects the n-type impurity ions such as boron (B), thus forms (a pair) p-type and partly lead Body region PE.When forming n-type semiconductor region, in order to prevent p-type impurity to be imported into the district that p-type semiconductor regions PE is formed In territory, the region that p-type semiconductor regions PE is formed is formed photoresist film, in turn, is forming p-type quasiconductor During region, in order to prevent n-type impurity to be imported in the region that n-type semiconductor region is formed, in n-type semiconductor region institute shape Photoresist film is formed on the region become.Therefore, n-type semiconductor region and p-type semiconductor regions PE are with different works Sequence formed, but the formation process of n-type semiconductor region and p-type semiconductor regions PE whichever is first carried out.It addition, P-type trap PW shown in Figure 12 (a) is the channel region immediately below gate electrode G2 and G5, does not therefore import n in described operation Type impurity, thus it is formed without n-type semiconductor region.

It follows that the sidewall at gate electrode G1, G2, G5 and G6 forms offset spacers 4a as being made up of silicon oxide film Afterwards, form side wall (side wall insulating film) SW being made up of the stacked film being sequentially laminated with silicon oxide film 4 and silicon nitride film 5, with As dielectric film.Offset spacers 4a is formed in the following manner, i.e. is removed by dry etching method part and utilizes CVD etc. Be formed at the silicon oxide film in Semiconductor substrate 1 so that described silicon oxide film autoregistration residue in the side of each gate electrode Wall.Side wall SW such as can be formed in the following manner, i.e. by CVD etc., on semiconductor substrate 1 from Semiconductor substrate 1 side Start to pile up successively silicon oxide film 4 and silicon nitride film 5, and by RIE (Reactive Ion Etching: active-ion-etch) Methods etc. carry out anisotropy etching to the stacked film of silicon oxide film 4 and silicon nitride film 5.

Now, as shown in Figure 12 (a), in the docking section of gate electrode G2 and G5, with the side wall of the sidewall of each gate electrode Between SW, the mode of major part contact forms the space between side wall SW, and embedment gate electrode G2 and G5 as far as possible.I.e., more It is desired that at docking section, side wall SW is completely covered the upper surface of Semiconductor substrate 1, even if in Semiconductor substrate 1 In the case of upper surface exposes, the area also making exposed Semiconductor substrate 1 is the least.Relative side wall is made in docking section Close between SW is to make the liner insulating film being formed at side wall SW surface in aftermentioned operation close between side wall SW.Cause This, between relative side wall SW, the distance at hithermost position has the two of the thickness of the liner insulating film being subsequently formed at this position Width below times.It addition, by the etching work procedure forming side wall SW, the upper surface of the Semiconductor substrate 1 exposed partly is removed Go and become concave shape (refer to Figure 25), cover with by gate electrode G1, G2, G5, G6, offset spacers 4a and side wall SW The upper surface of Semiconductor substrate 1 compare, the height step-down of the upper surface of the Semiconductor substrate 1 exposed.But, at Figure 12 (b) ～not shown in Figure 17 (b), the first type surface of Semiconductor substrate 1 is partly removed but the shape of not shown depression.

It follows that as shown in Figure 13 (a) and Figure 13 (b), such as by the p-type trap PW to gate electrode and side wall SW both sides (not shown) injects the p-type impurity ions such as phosphorus (P) or arsenic (As), thus forms n⁺Type semiconductor regions i.e. diffusion layer (figure Not shown in).It addition, such as inject boron by the N-shaped trap NW of the side wall SW both sides to gate electrode G1, G2 and G6 and sidewall (B) the n-type impurity ion such as, thus form p⁺Type semiconductor regions i.e. diffusion layer PS.N can be initially formed⁺Type diffusion layer, or first shape Become p⁺Type diffusion layer PS.After ion implantation, the annealing of impurity imported for activation such as can also be About 1050 DEG C, the heat treatment (spike process) of about 5 seconds is utilized to carry out.n⁺The degree of depth (depth of engagement) of type diffusion layer Deeper than the degree of depth (depth of engagement) of n-type semiconductor region, p⁺The degree of depth (depth of engagement) the ratio p-type semiconductor region of type diffusion layer PS The degree of depth (depth of engagement) of territory PE is deep.

n⁺The impurity concentration of type diffusion layer is higher than the impurity concentration of n-type semiconductor region, p⁺The impurity of type diffusion layer PS is dense The degree impurity concentration higher than p-type semiconductor regions PE.Thus, source electrode or drain electrode as n-channel type MI SFET play a role N-type semiconductor region (impurity diffusion layer) by n⁺Type diffusion layer and n-type semiconductor region are formed, as p-channel type MISFET Source electrode or the p-type semiconductor region (impurity diffusion layer) that plays a role of drain electrode by p⁺Type diffusion layer PS and p-type semiconductor regions PE is formed.That is, the regions and source/drain of n-channel type MI SFET and p-channel type MI SFET has LDD (Lightly doped Drain: lightly doped drain) structure.N-type semiconductor region and p-type semiconductor regions PE are relative to gate electrode G1, G2 and G6 And be formed self-aligned, n⁺Type diffusion layer and p⁺Type diffusion layer PS is formed relative on the respective sidewall of gate electrode G1, G2 and G6 Side wall SW and be formed self-aligned.

It addition, the p-type trap PW shown in Figure 13 (a) is the channel region immediately below gate electrode G2 and G5, in described operation In do not import p-type impurity, thus do not form n⁺Type diffusion layer.It addition, as shown in Figure 13 (b), be formed at gate electrode G1 and G2 Between region in diffusion layer PS and p-type semiconductor regions PE constitute source region S3, be formed at gate electrode G1 and G6 it Between region in diffusion layer PS and p-type semiconductor regions PE constitute drain region D3.

As it has been described above, on p-type trap PW, form n-channel type MI SFETQ2 (refer to Fig. 1) as field-effect transistor. And, on N-shaped trap NW, formation has the source region S3's and drain region D3 of gate electrode G1 and gate electrode G1 both sides Field-effect transistor i.e. p-channel type MISFETQ3.

Then, by self-aligned silicide (Salicide:Self Aligned Silicide) technology, at gate electrode G1、G2、G5、G6、n⁺Each upper surfaces such as type diffusion layer (not shown) and diffusion layer PS, form low-resistance silicide layer NS.The method forming silicide layer NS is: first, at the first type surface (whole face) of the Semiconductor substrate 1 comprising each gate electrode On, such as use sputtering method to form (accumulation) metal film.Metal film is as by Ni (nickel)-Pt (platinum) alloy film (alloy of Ni and Pt Film) constitute.

After metal film formed as discussed above, noble gas or nitrogen environment use RTA (Rapid Thermal Anneal: short annealing) method carries out heat treatment to Semiconductor substrate 1 so that with the silicon fiml of metal diaphragm contacts and metal film choosing React to selecting property, form metal/semiconductor conversion zone i.e. silicide layer NS.Then wet clean process removing is being carried out not After the metal film of reaction, carry out second time heat treatment, thus carry out the sintering of silicide layer NS.

It follows that as shown in Figure 14 (a) and Figure 14 (b), the first type surface of Semiconductor substrate 1 forms liner insulating film 6. That is, in the way of covering gate electrode G1, G2, G5 and G6, in the Semiconductor substrate 1 comprising silicide layer NS, formed as by The liner insulating film 6 that silicon nitride film is constituted.It is about 450 DEG C that liner insulating film 6 such as can pass through film-forming temperature (substrate temperature) Plasma CVD method etc. formed.

Now, the distance as shown in Figure 14 (b), between gate electrode G1, the G2 on the 2nd direction or between gate electrode G1, G6 Bigger than the distance between gate electrode G2, the G5 on the 1st direction shown in Figure 14 (a), there is ratio on the sidewall being formed at side wall SW The biggest interval of the length of twice of liner insulating film 6 thickness.Therefore, between adjacent on the 2nd direction gate electrode relatively The liner insulating film 6 of side of side wall SW do not contact with each other, and do not closed by liner insulating film 6 between side wall SW. And, the liner directly over Semiconductor substrate 1 upper surface that the side wall SW between gate electrode adjacent on the 2nd direction exposes Dielectric film 6 is to be formed at more broader region than docking section in the way of the first type surface of Semiconductor substrate 1.

On the other hand, at the docking section between gate electrode G2 and G5 shown in Figure 14 (a), Semiconductor substrate 1 is almost Not exposing, the distance between side wall SW is the distance of the twice of the thickness of the liner insulating film 6 being formed on the sidewall of side wall SW Following interval, therefore the liner insulating film 6 of the sidewall between side wall SW contacts.That is, at docking section, liner insulating film 6 are formed in the wider region of smooth Semiconductor substrate 1 upper surface not along the upper surface of Semiconductor substrate 1, and It is to be formed in the way of imbedding in the narrow zone between relative and close side wall SW.Therefore, shape between the side wall SW of docking section Even the height extreme lower position of the upper surface of the liner insulating film 6 become, still ratio is shown in above-mentioned Figure 14 (b), along the 2nd side Semiconductor substrate 1 between gate electrode G1, G2 upwards or between gate electrode G1, G6 and the upper table of liner insulating film 6 that formed The height in face is the highest.

The comparative example of the semiconductor device as illustrated by Figure 24 and Figure 25, at the docking section of gate electrode, when relative When distance between side wall SW is bigger than the value of the twice of the liner insulating film 6a thickness formed on the sidewall of side wall SW, quasiconductor The liner insulating film 6a formed on the first type surface of substrate 1 is not closed.Therefore, in the upper surface of the liner insulating film 6a of docking section The height of its lowest position becomes the minimum of the liner insulating film 6a upper surface between the gate electrode adjacent with on the 2nd direction The height that the height of position is roughly the same.Further, since the decline of the coverage rate of liner insulating film 6a at docking section, docking section Liner insulating film 6a upper surface in liner between the gate electrode adjacent on the 2nd direction of the aspect ratio of its lowest position The height of the extreme lower position of dielectric film 6a upper surface is low.Now, at docking section, liner insulating film 6a is along Semiconductor substrate 1 First type surface and formed, in the narrow zone of the deep trouth bottom between gate electrode, liner insulating film 6a is with than present embodiment Big volume is formed.

Liner insulating film 6a is in the bottom of the deep and narrow groove shown in Figure 25, and in liner insulating film 6a, formation cavity can Can property uprise.When forming cavity between the multiple contact plungers being formed in Semiconductor substrate 1, if shape in described cavity Become to constitute the metal parts of contact plunger, may be electrically connected by the metal parts in cavity between the most the plurality of contact plunger Connect, thus cause semiconductor element normally to work.Therefore, in the narrow slot such as the docking section of gate electrode, for preventing Cavity is formed, it may be desirable to be formed without liner insulating film as far as possible in the bottom of groove in liner insulating film.

On the other hand, in the present embodiment, by reducing the interval between side wall SW, the docking section of gate electrode can be made The liner insulating film 6 formed on relative side wall SW each sidewall contacts with each other and closes, thus reduces the side of bottom, docking section Space between wall SW.Therefore, in the upper surface of the liner insulating film 6 of docking section extreme lower position than grid adjacent on the 2nd direction The extreme lower position of liner insulating film 6 upper surface formed on Semiconductor substrate 1 first type surface between the electrode of pole is higher such that it is able to In the bottom of docking section, i.e. it is hardly formed liner insulating film 6 near the first type surface of Semiconductor substrate 1.

Thus, in the present embodiment, the relative docking section, end between the gate electrode extended along the 1st direction, energy Cavity is produced in enough preventing dielectric film on a semiconductor substrate.Therefore, it is possible to prevent because of cavity the contact plunger that causes it Between the phenomenon of short circuit (short), thus the reliability of semiconductor device can be improved, and, it is possible to increase semiconductor device Yield rate.

It follows that as shown in Figure 15 (a) and Figure 15 (b), liner insulating film 6 forms the layer thicker than liner insulating film 6 Between dielectric film 7.Interlayer dielectric 7 is such as made up of silicon oxide film etc., can use TEOS and is about 450 DEG C by film-forming temperature Plasma CVD method etc. formed.Subsequently, by CMP method, the surface of interlayer dielectric 7 is ground, interlayer can be made exhausted The upper surface planarization of velum 7.Even if because substrate jump causes the surface of liner insulating film 6 to be concaveconvex shape, come by CMP method Grind the surface of interlayer dielectric 7, it is possible to obtain the interlayer film that surface is smooth.

It follows that as shown in Figure 16 (a) and Figure 16 (b), use the photoresist figure formed on interlayer dielectric 7 (not shown) is used as etching mask, and interlayer dielectric 7 and liner insulating film 6 are carried out dry-etching, thus at liner Dielectric film 6 and interlayer dielectric 7 form contact hole (through hole, hole) 7a.Now, first insulate than liner at interlayer dielectric 7 Film 6 be easier to etched under the conditions of carry out the dry-etching of interlayer dielectric 7, and make liner insulating film 6 stop as etching Film plays a role, thus forms contact hole 7a on interlayer dielectric 7, then, at liner insulating film 6 than interlayer dielectric 7 more Under the conditions of the most etched, the liner insulating film 6 bottom contact hole 7a is carried out dry-etching and removes.Contact hole 7a's Bottom, a part for the first type surface of Semiconductor substrate 1, such as expose n⁺Type diffusion layer, diffusion layer PS, gate electrode G1, G2, G5 And a part etc. of the silicide layer NS on G6 each top.Now, gate electrode G2 sidewall and near the side of gate electrode G1 The side wall SW of wall and offset spacers 4a are removed, and expose gate electrode G2 and source region S3 in a contact hole 7a.

It follows that in contact hole 7a, the contact plunger that formation is made up of tungsten (W) etc. (insert by connection conductor portion, embedment Plug, embedment conductor portion) PL, P2.Contact plunger PL is formed in the contact hole 7a that drain region D3 exposes, and contact plunger P2 is formed In the contact hole 7a that gate electrode G2 and source region S 3 exposes.When forming contact plunger PL, P2, such as, connect comprising On the interlayer dielectric 7 of contact hole 7a internal (on bottom and sidewall), by film-forming temperature (substrate temperature) be about 450 DEG C etc. Ionomer cvd method is formed and intercepts electrically conductive film (such as titanium film, titanium nitride film or the stacked film of described film).Then, CVD is passed through Deng, in the way of landfill contact hole 7a, form, intercepting, the leading body film being made up of tungsten film etc. on electrically conductive film, and by CMP method or Eat-back lithography etc. removes on interlayer dielectric 7 unnecessary leading body film and intercepts electrically conductive film, thus can be formed by leading body film and Intercept contact plunger PL, P2 that electrically conductive film is constituted.It is respectively formed in n⁺Type diffusion layer, diffusion layer PS, gate electrode G1, G5 and G6 On contact plunger PL bottom be respectively formed in n⁺On type diffusion layer, diffusion layer PS, each surface of gate electrode G1, G5 and G6 Silicide layer NS contact and be electrically connected.

In present embodiment, in the case of being formed with cavity in the liner insulating film 6 of the docking section shown in Figure 16 (a), Being formed with a part for the metal parts constituting contact plunger in the described cavity being connected with contact hole 7a and exposing, contact is inserted Plug is likely short-circuited because of the metal parts in cavity with other contact plungers.But, the semiconductor device of present embodiment Part is as noted previously, as and can prevent from producing cavity in liner insulating film 6, therefore can prevent from being short-circuited between contact plunger.

It addition, though Figure 16 (a) illustrates, but in gate electrode G2, G5 and the both sides in the 2nd direction of docking section, to clip The mode of the docking section of gate electrode G2, G5 or gate electrode G2, G5 is each configured with contact plunger near docking section.And And, the gate electrode, regions and source/drain in the region not shown in Figure 16 (a) and Figure 16 (b) are also formed with contact and insert Plug, gate electrode G1, G5 and G6 are electrically connected with the contact plunger being formed at respective top in other regions the most unshowned Connect.

It follows that as shown in Figure 17 (a) and Figure 17 (b), have on the interlayer dielectric 7 of contact plunger PL, P2 in embedment, depend on Secondary formation stops dielectric film 8 and the interlayer dielectric 9 of wiring formation.Stop that dielectric film 8 is that interlayer dielectric 9 is being carried out groove Add the film becoming etch stop layer man-hour, use the material relative to interlayer dielectric 9 with etching selectivity.Stop dielectric film 8 can be as the silicon nitride film such as formed by plasma CVD method, and interlayer dielectric 9 can be as such as passing through plasma The silicon oxide film that CVD is formed.It addition, stopping that dielectric film 8, with on interlayer dielectric 9, is formed with the 1st layer of wiring described later.

It follows that form the 1st layer of wiring by single inlaying process.First, by resist figure (not shown) is made For the dry-etching of mask, interlayer dielectric 9 and stop dielectric film 8 regulation region in form wiring groove 9a after, half (i.e. comprise on the bottom of wiring groove 9a and the interlayer dielectric 9 of inwall) formation on the first type surface of conductor substrate 1 and intercept electrically conductive film (barrier metal film).Intercept electrically conductive film and such as can use titanium nitride film, tantalum film or nitridation tantalum film etc..It follows that by CVD or Sputtering methods etc. form the lamella of copper intercepting on electrically conductive film, and by galvanoplastic etc., form copper plating film on lamella.By The inside of copper plating film buried wiring groove 9a.Then, by CMP method remove the copper plating film in region in addition to wiring groove 9a, Lamella and intercept electrically conductive film etc., and formed and take electric material as the leading factor with copper and by copper plating film, lamella and intercept electrically conductive film and constituted The 1st layer of metal line M1.A plurality of metal line M1 is via contact plunger PL or P2 and n⁺Type diffusion layer, diffusion layer PS, grid Electrode G1, G2, G5 and G6 are electrically connected in pole.Subsequently, by damascene process, metal line M1 forms the 2nd layer of wiring, but It is that present embodiment eliminates diagram and explanation.By above step, complete the semiconductor device of present embodiment.

In the present embodiment, as it has been described above, the interval of the relative side wall SW by the docking section of reduction of gate electrode, And prevent in comparative example as shown in figure 25, form liner insulating film in the bottom of docking section such that it is able to prevent at liner exhausted Form cavity in velum, and still prevent and be short-circuited via described cavity between multiple contact plunger.

Now, from the viewpoint of more efficiently preventing from forming cavity in liner insulating film 6, it may be desirable to, right The extreme lower position connecing liner insulating film 6 upper surface at portion is positioned at the higher region of the height than gate electrode G2, G5 upper surface.

It addition, in the present embodiment, the SRAM with the gate electrode formed by end-grain cutting is illustrated, but In the patterning operation of gate electrode, it is possible to no-go end is cut but by once etching the side disposably forming gate electrode Method.This is because, if the interval of the docking section between reduction of gate electrode, even if then the method by not using end-grain cutting carrys out shape Become gate electrode, it is also possible to there will be present patent application and invent the problem to be solved.

And, the present invention is not limited to the semiconductor device with SRAM, it is possible to be applicable to other semiconductor device.Specifically For, it being applicable to following semiconductor device: i.e. in this semiconductor device, two gate electrodes extended along the 1st direction are the 1st On direction adjacent, and near the docking section of each gate electrode, there is multiple contact plunger, wherein, the plurality of contact plunger Configure in the way of the end of relative gate electrode or docking section and produce potential difference during in action clipping double team docking section.

It addition, in the present embodiment, the structure that the sidewall at each gate electrode is formed offset spacers is said Bright, but alternatively it is formed without the structure of offset spacers.

Hereinafter, the semiconductor device of variation that is the 1st variation of semiconductor device, the 2nd deformation to present embodiment The semiconductor device of example and the 3rd variation illustrates.

Shown in semiconductor device such as Figure 18 (a) and Figure 18 (b) of 1st variation, with the semiconductor device phase shown in Fig. 2 Ratio, at the docking section between gate electrode G2 and G5 formed relative side wall SW between more widely spaced.In present embodiment, the 1 variation is to have and the semiconductor device of the semiconductor device same general configuration shown in Fig. 1～Fig. 4, shown in Figure 18 is Profile with the line A-A same position of Fig. 1.Shown in Figure 18 (b) is the present embodiment for below equation (2) are described The profile of the semiconductor device of the 1st variation.Shown in Figure 18 (b) is a figure part of Figure 18 (a) being amplified, but The structure above liner insulating film 6 it is being formed at not shown in Figure 18 (b).

As shown in Figure 18 (a) and Figure 18 (b), the interval between the relative side wall SW of gate electrode docking section is than Fig. 2 institute Interval between the side wall SW shown is big, but in the semiconductor device of Figure 18 (a) and Figure 18 (b), is also on the sidewall with side wall SW Interval below the twice of the thickness of the liner insulating film 6 formed configures, and this point is identical with the structure shown in Fig. 2.Therefore, lining Pad dielectric film 6, in the bottom of docking section, is closed between side wall SW, and between the gate electrode in the 1st direction, the liner of (docking section) is exhausted The extreme lower position of velum 6 upper surface is than the lowest order of liner insulating film 6 upper surface between gate electrode adjacent on the 2nd direction Set high.Therefore, effect similar to the above can be obtained, i.e. can prevent from producing cavity in the liner insulating film 6 of docking section, from And be prevented from causing short trouble between different contact plungers.

If the structure of the above-mentioned semiconductor device shown in Figure 18 (b) to be formulated, then formula is as follows:

S2≤2×βt (2)

In present embodiment, S2 is at docking section, the distance of side wall SW adjacent on the 1st direction.β is the 1st direction The end of side wall SW and the coverage rate of the liner insulating film 6 of end that do not contacts with gate electrode or offset spacers 4a (%), t is the thickness setting of liner insulating film 6.It addition, the liner insulating film 6 that β t is the described end being formed at side wall SW The value of thickness.Formula (2) represents the liner insulating film 6 that distance S2 is the described end being formed at side wall SW between side wall SW Below the twice of thickness.Therefore, according to formula (2), in the semiconductor device shown in Figure 18 (b), it is stipulated that relative to each other The liner insulating film 6 that the relative end of side wall SW is formed contacts and at docking section inner sealing.

And, the semiconductor device of the 2nd variation has the knot roughly the same with the semiconductor device shown in Fig. 1～Fig. 4 Structure, but as shown in figure 19, in the liner insulating film 6 of the docking section between gate electrode G2 and G5, it has been intentionally formed space SP, This point is different from the semiconductor device shown in Fig. 2.It addition, be the profile of line A-A same position with Fig. 1 shown in Figure 19.

In the semiconductor device with MISFET, there is the parasitic capacitance that the Capacitance Coupled of electrode causes, be to cause half The reason that the circuit speed (speed of action) of conductor device reduces, in order to improve speed of action, in recent years, by highly integrated And the semiconductor device closely configuring electrode pattern is all required to reduce parasitic capacitance.

To this, in the 2nd variation i.e. semiconductor device shown in Figure 19 of present embodiment, in the docking of gate electrode At portion relative to side wall SW between be intentionally formed the space SP covered by liner insulating film 6, thus have and be formed without dielectric film Deng space.Space SP is to have the region that dielectric constant is lower than side wall SW, liner insulating film 6 or interlayer dielectric 7 etc., therefore By forming space SP between gate electrode, it is possible to reduce the parasitic capacitance between gate electrode.

In the semiconductor device of the 2nd variation shown in Figure 19, except the semiconductor device illustrated by Fig. 1～Fig. 5 (b) Effect beyond, also there is the effect of above-mentioned reduction parasitic capacitance.It addition, space SP and cause the short-circuit reason between contact plunger Cavity (illustrated by comparative example) different, even if when being formed with contact hole still by blocking liner insulating film 6 in, because of This will not form the metal parts constituting contact plunger in the SP of space.That is, space SP will not be formed at the region of contact hole In.

And, the semiconductor device of the 3rd variation has the knot roughly the same with the semiconductor device shown in Fig. 1～Fig. 4 Structure, but as shown in figure 20, between gate electrode G2 and G5, do not form the silicon nitride film 5 constituting side wall SW in Fig. 2, at grid electricity On the sidewall of pole G2 and G5, it is formed with the silicon oxide film 4 with L font section across offset spacers 4a.In the 3rd variation In, it is formed in fig. 2 on the region of silicon nitride film 5, is formed with liner insulating film 6 as shown in figure 20.That is, in docking section, edge The sidewall of the upper surface and gate electrode G2, G5 of Semiconductor substrate 1 is formed continuously silica film 4, liner insulating film 6 with Across silicon oxide film 4 between the respective sidewall of gate electrode G2, G5.It addition, be the line A-A identical bits with Fig. 1 shown in Figure 20 The profile put.

As shown in figure 20, it is configured between the silicon oxide film 4 at docking section: with the major surfaces in parallel of Semiconductor substrate 1 Major part contact between the end of the bottom that ground is formed, between relative silicon oxide film 4, embedment has liner insulating film 6.Along grid The pole respective sidewall of electrode G2 and G5 and distance between the silicon oxide film 4 that formed are for being respectively formed in gate electrode G2 and G5 side The twice value below of liner insulating film 6 thickness on wall, therefore by making liner insulating film 6 contact with each other at docking section, So that the groove between gate electrode is closed.

Now, gate electrode cause the liner insulating film 6 of stress (stress) more lean on than the semiconductor device shown in Fig. 2 Nearly gate electrode G2 or G5, the stress therefore caused the raceway groove of gate electrode G2 or G5 is bigger.MISFET has the property that That is, the stress that the fixed-direction of raceway groove bears is the biggest, and electric current the most easily flows through raceway groove.Therefore in the 3rd variation shown in Figure 20 In semiconductor device, in addition to the effect of the semiconductor device illustrated by Fig. 1～Fig. 5 (b), also there is raising MISFET action The effect of speed.

In order to form the structure shown in Figure 20, after forming side wall SW in the operation of Figure 12 (a) and Figure 12 (b), pass through The Wet-type etching using phosphoric acid etc. removes silicon nitride film 5, the most only need to carry out the operation shown in Figure 13 (a) and Figure 13 (b) to figure Operation shown in 17 (a) and Figure 17 (b).

And, in the semiconductor device of the 3rd variation, it is also possible to be suitable for the structure of the 2nd variation.That is, such as Figure 21 institute Show, have with in the semiconductor device of the semiconductor device same structure of Figure 20, at the liner of the closing of docking section The inside of dielectric film 6 specially arranges space SP.Thus, except the above-mentioned effect preventing short circuit between contact plunger and increase can be obtained Stress that gate electrode is caused thus beyond the effect of the speed of action that improves MISFET, also can obtain with the 2nd variation with The parasitic capacitance reduced between gate electrode of sample, and improve the effect of the speed of action of semiconductor device.

(embodiment 2)

In the above embodiment, being illustrated SRAM, described SRAM as shown in Figure 1 to 4, has by conduct Gate electrode G1～G6 that metal gate layers MG of metal film and polysilicon layer PG are constituted.Though the semiconductor device of present embodiment Have and the SRAM same structure shown in Fig. 1～Fig. 4, but as shown in FIG. 22 and 23, have and do not comprise metal gates Layer and gate electrode G1, G2, G5 and G6 of being only made up of polysilicon layer PG, this point is different from the semiconductor device of embodiment 1. It addition, shown in Figure 22 be profile with the semiconductor device of Fig. 2 same position in present embodiment, shown in Figure 23 is this With the profile of the semiconductor device of Fig. 4 same position in embodiment.

Even having the semiconductor device of gate electrode G1, G2, G5 and G6 of being only made up of polysilicon layer PG, by Liner insulating film 6 is closed, it is also possible to prevent at liner insulating film 6 at the docking section between gate electrode adjacent on 1st direction Interior formation cavity, thus the effect as embodiment 1 can be obtained.That is, identical with embodiment 1, including that there is polycrystalline Structure in the semiconductor device of the SRAM of silicon gate, described in applicable above-mentioned 1st variation～the 3rd variation.

Employ the situation of structure described in present patent application described in embodiment 1,2, i.e. use repeatedly pattern Change and carry out end-grain cutting in the case of forming gate electrode, for there is the right of narrow intervals between the gate electrode that formed The situation meeting portion is illustrated.But, present patent application is equally applicable to the most repeatedly pattern, but by once Patterning forms the situation of the docking section of the narrow intervals with 30～about 50nm.

Specifically understand the invention that inventor is made above according to embodiment, but the present invention is not exposed to institute State the restriction of embodiment, without departing from all changes can be carried out in the range of its main idea, at this without superfluous words.

Industrial applicability

The present invention can be effectively applicable to include having the half of the semiconductor element of the gate electrode of the docking section of narrow intervals The manufacturing technology of conductor device.

Claims

1. a semiconductor device, it is characterised in that including:

Multiple gate electrodes, the plurality of gate electrode upwardly extends the 1st side of the first type surface along Semiconductor substrate, and edge Described 1st direction arrangement is formed on the semiconductor substrate；

1st dielectric film, described 1st dielectric film is formed between the plurality of gate electrode adjacent on described 1st direction；

2nd dielectric film, described 2nd dielectric film the plurality of gate electrode on 2nd direction orthogonal with described 1st direction Side, is formed at the upper surface of the described Semiconductor substrate exposed from described gate electrode；And

Multiple contact plungers, the plurality of contact plunger is arranged in the both sides on the 2nd direction of described 1st dielectric film, and connects In described Semiconductor substrate,

Wherein, described 1st dielectric film and described 2nd dielectric film constitute the 3rd dielectric film, and described 3rd dielectric film is to cover described half The mode of conductor substrate and the plurality of gate electrode is formed,

The extreme lower position of described 1st dielectric film upper surface sets high than the lowest order of described 2nd dielectric film upper surface.

2. semiconductor device as claimed in claim 1, it is characterised in that the lowest order set of described 1st dielectric film upper surface In the region higher than the upper surface of the plurality of gate electrode.

3. semiconductor device as claimed in claim 1, it is characterised in that the plurality of grid adjacent on described 1st direction Described 1st dielectric film formed respectively on the relative sidewall of pole electrode contacts each other.

4. semiconductor device as claimed in claim 1, it is characterised in that the plurality of grid adjacent on described 1st direction Between the electrode of pole, it is formed with the space covered by described 1st dielectric film.

5. semiconductor device as claimed in claim 1, it is characterised in that in the respective sidewall of the plurality of gate electrode and institute State and be formed with side wall between the 1st dielectric film.

6. semiconductor device as claimed in claim 5, it is characterised in that described side wall includes being sequentially laminated on described quasiconductor Silicon oxide film on substrate and silicon nitride film.

7. semiconductor device as claimed in claim 1, it is characterised in that at the sidewall and described the of the plurality of gate electrode Across comprising the 4th dielectric film of silicon oxide film between 1 dielectric film, described 4th dielectric film is along the side of the plurality of gate electrode The upper surface of wall and described Semiconductor substrate is continuously formed.

8. a semiconductor device, it is characterised in that including:

1st dielectric film, described 1st dielectric film is formed between the plurality of gate electrode adjacent on described 1st direction；And

Wherein, described 1st dielectric film constitutes the 3rd dielectric film, and described 3rd dielectric film is to cover described Semiconductor substrate and described many The mode of individual gate electrode is formed,

The extreme lower position of described 1st dielectric film upper surface is positioned at the region higher than the plurality of gate electrode upper surface.

9. semiconductor device as claimed in claim 8, it is characterised in that the plurality of grid adjacent on described 1st direction Between the electrode of pole, it is formed with the space covered by described 1st dielectric film.

10. semiconductor device as claimed in claim 8, it is characterised in that the respective sidewall of the plurality of gate electrode with It is formed with side wall between described 1st dielectric film.

11. semiconductor device as claimed in claim 10, it is characterised in that described side wall includes being sequentially laminated on described partly leads Silicon oxide film on body substrate and silicon nitride film.

12. semiconductor device as claimed in claim 8, it is characterised in that at the sidewall of the plurality of gate electrode with described Across comprising the 4th dielectric film of silicon oxide film between 1st dielectric film, described 4th dielectric film is along the plurality of gate electrode The upper surface of sidewall and described Semiconductor substrate is continuously formed.

The manufacture method of 13. 1 kinds of semiconductor device, it is characterised in that include following operation:

Operation (a), forms multiple gate electrode across gate insulating film on a semiconductor substrate, and the plurality of gate electrode is on edge 1st side of the first type surface described Semiconductor substrate upwardly extends, and along described 1st direction arrangement；

Operation (b), the first type surface of the Semiconductor substrate of the both sides on the 2nd direction of the plurality of gate electrode is formed source Pole/drain region；

Operation (c), forms side wall on the sidewall of the plurality of gate electrode；

Operation (d), after described operation (b) and described operation (c), on the semiconductor substrate, the plurality of to cover The mode of gate electrode, described regions and source/drain and described side wall sequentially forms the 2nd dielectric film from described semiconductor-substrate side And the 3rd dielectric film；And

Operation (e), the both sides in the region between the plurality of gate electrode adjacent on described 1st direction, form through institute After stating multiple through holes of the 2nd dielectric film and described 3rd dielectric film, formed in the respective inner side of the plurality of through hole and connect In the contact plunger of described regions and source/drain,

Wherein, the lowest order of adjacent on the described 1st direction described 2nd dielectric film upper surface between the plurality of gate electrode Put, than on 2nd direction orthogonal with described 1st direction, described in expose from the plurality of gate electrode and described side wall The lowest order of the described 2nd dielectric film upper surface that the upper surface of Semiconductor substrate is formed sets high.

The manufacture method of 14. semiconductor device as claimed in claim 13, it is characterised in that adjacent on described 1st direction The plurality of gate electrode between the extreme lower position of described 2nd dielectric film upper surface be positioned at ratio on the plurality of gate electrode The region that surface is high.

The manufacture method of 15. semiconductor device as claimed in claim 13, it is characterised in that described operation (a) including:

Operation (a1), is processed the conducting film being formed in described Semiconductor substrate, and is formed along the plurality of grid The sidewall in described 1st direction of electrode；And

Operation (a2), is processed the described conducting film being formed in described Semiconductor substrate, and is formed along the plurality of The sidewall in described 2nd direction of gate electrode.

The manufacture method of 16. semiconductor device as claimed in claim 13, it is characterised in that in described operation (d), in institute State between the plurality of gate electrode adjacent on the 1st direction, form the space covered by described 2nd dielectric film.

The manufacture method of 17. semiconductor device as claimed in claim 13, it is characterised in that in described operation (c), from institute State semiconductor-substrate side and sequentially form silicon oxide film and silicon nitride film, remove described silicon oxide film and described silicon nitride by part Film, forms the described side wall including described silicon oxide film and described silicon nitride film on the sidewall of the plurality of gate electrode, Described operation (c) afterwards and front described operation (d), has the operation removing described silicon nitride film.