JP2012099530A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the withstand voltage between a lower electrode and an upper electrode of a capacitive element composed of the lower electrode, the upper electrode, and an insulating film therebetween.SOLUTION: ONO films IF are consecutively formed between a lower electrode BE and an upper electrode TE, side-surface oxide films 9 on each side surface of the upper electrode TE, and sidewalls 10, and the sidewalls 10 composed of an intrinsic semiconductor film are formed on the side surfaces of the upper electrode TE via the side-surface oxide films 9, thereby preventing the occurrence of leakage current between the lower electrode BE and the upper electrode TE.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly, to a semiconductor device including a capacitor (hereinafter simply referred to as “PIP capacitor”) composed of a polycrystalline silicon film / insulating film / polycrystalline silicon film and the manufacturing thereof. The present invention relates to a technique effective when applied to a method.

  2. Description of the Related Art A semiconductor device including a MIS (Metal Insulator Semiconductor) transistor, a capacitor element, and a resistor element formed on the main surface of the same semiconductor substrate is applied to various fields such as an automobile field and an electric appliance field. Capacitance elements formed on the main surface of the semiconductor substrate include an MIS (Metal Insulator Semiconductor) capacitor, an MIM (Metal Insulator Metal) capacitor, and a PIP (polysilicon insulator polysilicon) capacitor.

  The PIP capacity is a stable capacity with less change in capacity due to polarity compared to the MIS capacity and the MIM capacity. Further, the PIP capacitor can be formed while suppressing an increase in the number of steps if the electrode terminal is formed of a polycrystalline silicon film formed in the same process as the polycrystalline silicon film constituting the gate electrode of the MIS transistor. .

  Patent Document 1 (Japanese Patent Application Laid-Open No. 2004-200504) includes a capacitive element including a lower electrode, a dielectric film, and an upper electrode that are sequentially formed on an element isolation region of a semiconductor substrate, and the dielectric film Describes forming a semiconductor device composed of a two-layer silicon oxide film and a silicon nitride film between the two silicon oxide films. Here, the silicon nitride film constituting the dielectric film and the silicon oxide film below the silicon nitride film are formed with a width wider than the width of the upper electrode, and the dielectric film is formed outside the end of the upper electrode. It is described that a part is extended. However, in Patent Document 1, the sidewall (spacer) formed on the sidewall of the upper electrode is an insulating film formed in the same process as the sidewall for forming the extension region of the field effect transistor formed on the semiconductor substrate. The member is made of a silicon oxide film or the like.

  In Patent Document 2 (Japanese Patent Laid-Open No. 2003-258108), in a manufacturing process of a semiconductor device having an MIM type capacitive element in which a lower electrode, a dielectric film, and an upper electrode are sequentially stacked on a semiconductor substrate, In order to protect the dielectric film directly under the edge of the electrode from etching damage, it is described that the exposed dielectric film is removed after the side wall is formed on the side wall of the upper electrode. In this case, if side etching occurs when the dielectric film is removed by isotropic etching, the capacitance value of the MIM type capacitor is reduced or the capacitance value varies. There is no description about the change in the breakdown voltage of the capacitor due to the side etching. In addition, it is described that the dielectric film is formed so as to spread outward from the edge of the upper electrode by the width of the sidewall, but it is described that a SiN film is used as a member of the sidewall, There is no description or suggestion of forming the sidewalls from a polysilicon film. Further, the sidewall of the upper electrode side wall is an insulating film formed in the same step as the sidewall for forming the extension region of the field effect transistor formed on the semiconductor substrate, or for forming the extension region. There is no description as to whether the insulating film is formed in a separate process from the sidewall. Further, there is no description that a non-volatile memory element such as a MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory cell (hereinafter simply referred to as “MONOS memory”) is formed on the semiconductor substrate.

  Patent Document 3 (Japanese Patent Laid-Open No. 9-8245) describes a capacitive element that is formed on a semiconductor substrate in order, and includes a lower electrode made of a Pt film, a capacitive insulating film, and an upper electrode made of a Pt film. . Here, by processing the capacitor insulating film using a resist mask in which the end of the capacitor insulating film is formed outside the end of the upper electrode, the capacitor insulating film is dry-etched during processing of the capacitor insulating film. Forming a capacitive element using only a capacitive insulating film in a region that is not damaged at the end of the substrate. It is described that a metal film such as Pt (platinum) or a conductive oxide film is used for members of the upper electrode and the lower electrode, and there is no description or suggestion that a semiconductor film is used. Further, the surface including the side walls of the upper electrode and the lower electrode is covered with a protective film made of a silicon oxide film, and there is no description that a semiconductor film is formed on each side wall of the upper electrode and the lower electrode. Further, there is no description that a nonvolatile memory element such as a MONOS memory is formed on the semiconductor substrate.

JP 2004-200504 A JP 2003-258108 A Japanese Patent Laid-Open No. 9-8245

When forming a PIP capacitive element including three layers of a lower electrode made of a first polycrystalline silicon film, a capacitor insulating film, and an upper electrode made of a second polycrystalline silicon film, which are sequentially formed on a semiconductor substrate, After forming the capacitive insulating film and the second polycrystalline silicon film on the first polycrystalline silicon film formed on the surface, the second polycrystalline silicon film and the capacitive insulating film are processed using the same photoresist film as a mask. A method is conceivable. The capacitor insulating film is, for example, an ONO (oxide-nitride-oxide) film having a structure in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially stacked as an insulating film. When removing the capacitor insulating film, the lower electrode, In order to prevent other regions such as the capacitor insulating film or the upper electrode or other elements from being damaged, wet etching using, for example, hot phosphoric acid (H ₂ PO ₄ ) is used. By this etching, the capacitor insulating film is overetched inward from the end of the upper electrode, and the end of the capacitor insulating film recedes from the end of the upper electrode toward the center of the capacitor insulating film. Become.

  Here, as a comparative example, a PIP capacitor element in which an upper electrode is formed by the above processing and then a sidewall made of an insulating film in which, for example, a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated on the sidewall of the upper electrode. A cross-sectional view is shown using FIG.

  As shown in FIG. 14, on the semiconductor substrate SB, the insulating film 3a constituting the capacitive element PCg, the lower electrode BE, the ONO film IFg as a capacitive insulating film, and the upper electrode TE are sequentially formed. In the direction along the main surface of the semiconductor substrate SB, the width of the ONO film IFg is narrower than the width of the upper electrode TE, and the end portion of the upper electrode TE is located outside the end portion of the ONO film IFg. A sidewall SW having a laminated structure in which a silicon oxide film 12, a silicon nitride film 13, and a silicon oxide film 14 are sequentially formed is formed on the sidewalls of the upper electrode TE and the lower electrode BE, and is formed on the sidewalls of the upper electrode TE. The lowermost silicon oxide film 12 of the sidewall SW is formed so as to enter between the lower electrode BE immediately below the end of the eaves-like upper electrode TE formed outside the end of the ONO film IFg. ing.

  That is, the ONO film IFg is formed between the upper electrode TE and the lower electrode BE, but the ONO film IFg is formed between the upper electrode TE and the lower electrode BE in the vicinity of the end of the upper electrode TE. The silicon oxide film 12 is formed instead. When such a PIP capacitive element is operated, the withstand voltage between the upper electrode TE and the lower electrode BE decreases at the end of the upper electrode TE where the ONO film IFg is not formed, and the upper electrode TE and the lower electrode BE There is a problem that leakage current easily flows between them.

  An object of the present invention is to improve the withstand voltage of a capacitor and improve the reliability of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

A semiconductor device according to a preferred embodiment of the present invention includes:
A lower electrode formed in a first region on a semiconductor substrate;
A first insulating film formed on the lower electrode;
An upper electrode formed directly on the first insulating film;
An intrinsic semiconductor film formed immediately above the first insulating film and on the side wall of the upper electrode via a second insulating film;
It is what has.

A method for manufacturing a semiconductor device according to a preferred embodiment of the present invention includes:
A method of manufacturing a semiconductor device having a capacitive element formed in a first region of a main surface of a semiconductor substrate,
(A) forming a first conductive film on the semiconductor substrate in the first region via a first insulating film;
(B) processing the first conductive film to form a lower electrode made of the first conductive film in the first region;
(C) forming a second insulating film on the lower electrode;
(D) forming a second conductive film on the entire main surface of the semiconductor substrate;
(E) processing the second conductive film in the first region to form an upper electrode made of the second conductive film directly on the lower electrode;
(F) heat-treating the semiconductor substrate to form a sidewall oxide film on the sidewall of the upper electrode;
(G) After forming an intrinsic semiconductor film on the entire main surface of the semiconductor substrate, the intrinsic semiconductor film is processed to form the sidewall oxide film on the sidewall of the upper electrode directly above the lower electrode. Forming a first sidewall made of the intrinsic semiconductor film via
(H) The exposed second insulating film is removed using the upper electrode, the sidewall oxide film, and the first sidewall as a mask, and the lower electrode, the second insulating film, the upper electrode, and the first electrode are removed. Forming the capacitive element having one sidewall;
It is what has.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the above-described preferred embodiment of the present invention, the breakdown voltage of the capacitive element can be improved.

It is sectional drawing of the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. (A) is sectional drawing of the semiconductor device which is this Embodiment 1 in a manufacturing process. (B) is sectional drawing which shows the manufacturing method of the semiconductor device following Fig.2 (a). It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. (A) is sectional drawing which shows the manufacturing method of the semiconductor device following FIG.2 (b). (B) is sectional drawing which shows the manufacturing method of the semiconductor device following Fig.3 (a). It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. (A) is sectional drawing which shows the manufacturing method of the semiconductor device following FIG.3 (b). (B) is sectional drawing which shows the manufacturing method of the semiconductor device following Fig.4 (a). It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. (A) is sectional drawing which shows the manufacturing method of the semiconductor device following FIG.4 (b). (B) is sectional drawing which shows the manufacturing method of the semiconductor device following Fig.5 (a). It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. (A) is sectional drawing which shows the manufacturing method of the semiconductor device following FIG.5 (b). (B) is sectional drawing which shows the manufacturing method of the semiconductor device following Fig.6 (a). FIG. 7 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 6 (b). FIG. 8 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 7; FIG. 9 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 8. It is sectional drawing of the semiconductor device which is Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 2 of this invention. (A) is sectional drawing which shows the manufacturing method of the semiconductor device which is this Embodiment 2 in a manufacturing process. FIG. 12B is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. It is sectional drawing of the semiconductor device which is Embodiment 3 of this invention. It is sectional drawing of the semiconductor device which is this Embodiment 3 in a manufacturing process. It is sectional drawing of the semiconductor device which is a comparative example.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

(Embodiment 1)
An example of a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a semiconductor device having a MONOS memory Mn which is a nonvolatile memory element, a PIP capacitor element PC which is a capacitor element, and a MIS transistor (MIS Field Effect Transistor) Tn which is a field effect transistor on a semiconductor substrate SB. It is sectional drawing which shows a part. In FIG. 1, the MONOS memory Mn, the PIP capacitor element PC, and the MIS transistor Tn are shown in order from the left of the drawing. Here, it is assumed that the MONOS memory Mn and the MIS transistor Tn are n-channel transistors. The MIS transistor Tn constitutes a peripheral circuit for operating the MONOS memory Mn, and is an element that is driven at a voltage lower than that of the MONOS memory Mn.

As shown in FIG. 1, the semiconductor device of the present embodiment has a semiconductor substrate SB, and a MONOS memory Mn, a PIP capacitor element PC, and a MIS transistor Tn are formed on the semiconductor substrate SB. A groove (not shown) is formed on the upper surface of the semiconductor substrate SB so as to divide each element of the MONOS memory Mn, the PIP capacitor element PC, and the MIS transistor Tn, and the groove is mainly made of, for example, a silicon oxide film. An element isolation region (not shown) is formed. For example, a well 2 that is a p ⁻ type semiconductor region into which a p type impurity (for example, B (boron)) is introduced at a relatively low concentration is formed on the upper surface of the semiconductor substrate SB made of p type single crystal silicon. In the upper surface of the semiconductor substrate SB below each of the MONOS memory Mn and the MIS transistor Tn, a p-type impurity (for example, B (boron)) is introduced into a region shallower than the well 2 at a relatively low concentration. A channel region (not shown) is formed.

  The MONOS memory Mn is a potential barrier film, for example, a silicon nitride film that is a charge storage film interposed between the bottom oxide film 5 and the top oxide film 7 made of a silicon oxide film, and the bottom oxide film 5 and the top oxide film 7. The ONO film IF which is a laminated film made of the film 6 is provided. On the ONO film, a gate electrode CG made of a polysilicon film and sidewall oxide films 9 and sidewalls 10 formed on the sidewalls on both sides thereof are formed. Is formed. Here, the sidewall oxide film 9 is made of a silicon oxide film, and the sidewall 10 is formed on the sidewall of the gate electrode CG via the sidewall oxide film 9. The sidewall 10 is formed on the semiconductor substrate SB via the ONO film IF, but is an end portion of the sidewall 10 in a direction along the main surface of the semiconductor substrate SB and in contact with the sidewall oxide film 9. The ONO film IF is not formed immediately below the opposite end. That is, the total width of the gate electrode CG in the gate length direction of the gate electrode CG, the sidewall oxide film 9 and the sidewall 10 is wider than the width in the same direction of the ONO film IF below the gate electrode CG. In the figure, the side wall oxide film 9 and the top oxide film 7 are distinguished from each other, but in actuality, they are films made of the same silicon oxide film and integrated.

  Sidewalls SW are formed on the sidewalls on both sides of the gate electrode CG via the sidewall oxide films 9 and the sidewalls 10. The sidewall SW is composed of a laminated film in which a silicon oxide film 12, a silicon nitride film 13, and a silicon oxide film 14 are laminated in order from the semiconductor substrate SB side. That is, a silicon nitride film 13 and a silicon oxide film 14 are formed in this order on the side wall 10 with the silicon oxide film 12 in contact with the side wall 10 interposed therebetween.

  As described above, the end portion of the sidewall 10 in the gate length direction has an eaves shape projecting outward from the end portion of the ONO film IF in the same direction. The ONO film IF is not formed, and instead, the silicon oxide film 12 constituting the sidewall SW is formed so as to enter the lower part of the end portion of the eaves-shaped sidewall 10. That is, at the end of the sidewall 10, there is a region in which the silicon oxide film 12 is interposed between the sidewall 10 and the semiconductor substrate SB in a direction perpendicular to the main surface of the semiconductor substrate SB.

On the upper surface of the semiconductor substrate SB below the sidewalls 10 and SW, an extension region 15 which is an n ⁻ type semiconductor deposition region into which an n type impurity (for example, P (phosphorus)) is introduced at a relatively low concentration is formed. Has been. An n-type impurity (for example, P (phosphorus)) is an extension region on the upper surface of the semiconductor substrate SB outside the gate electrode CG in the gate length direction and outside the sidewall SW and the extension region 15. A diffusion layer 16 which is an n ⁺ type semiconductor deposition region introduced at a concentration higher than 15 is formed. The diffusion layer 16 is formed with a junction depth deeper than that of the extension region. The extension region 15 and the diffusion layer 16 constitute a source / drain region of the MONOS memory Mn, and the source / drain region has a low impurity concentration and a low concentration. An LDD (Lightly Doped Drain) structure including a resistive diffusion layer 16 and an extension region 15 having an impurity concentration lower than that of the diffusion layer 16 and a high resistance is formed.

  The PIP capacitor element PC has a lower electrode BE formed on the semiconductor substrate SB via the insulating film 3a, and an upper electrode TE formed on the lower electrode BE via the ONO film IF. Yes. The upper electrode TE is a film made of a polysilicon film in the same layer as the polysilicon film constituting the gate electrode CG of the MONOS memory Mn, but the lower electrode BE and the upper electrode TE are gated in the direction along the main surface of the semiconductor substrate SB. It has a width wider than that of the electrode CG. The width of the lower electrode BE in the same direction is narrower than the width of the upper electrode TE, and the end portions on both sides of the upper electrode TE are formed immediately above the lower electrode BE.

  Sidewalls 10 are formed on the side walls on both sides of the lower electrode BE via the ONO film IF. The ONO film IF and the side wall 10 on the side wall of the lower electrode BE are made of the same members as the ONO film IF and the side wall 10 of the MONOS memory Mn, but the ONO film IF on the side wall of the lower electrode BE is the main part of the semiconductor substrate SB. It is continuously formed in an L shape along the surface and the side wall of the lower electrode BE. That is, the ONO film IF is interposed between the lower surface of the sidewall 10 of the lower electrode BE and the upper surface of the semiconductor substrate SB. In the direction along the main surface of the semiconductor substrate SB, the end portion of the side wall 10 on the side wall of the lower electrode BE and the end portion on the opposite side of the lower electrode BE are located on the lower side in the same manner as the side wall 10 of the MONOS memory Mn. The formed ONO film IF has an eaves shape projecting outward from the end in the same direction. Similarly to the MONOS memory Mn, a sidewall SW is formed on the outer sidewall of the sidewall 10 of the lower electrode BE, and not the ONO film IF in the lower portion of the outer end of the sidewall 10. A silicon oxide film 12 constituting the SW is formed. The film thickness of the top oxide film 7 constituting the ONO film IF between the upper electrode TE and the lower electrode BE is the same as that of the top oxide film 7 constituting the ONO film IF between the sidewall 10 and the lower electrode BE. It is almost the same as the film thickness.

  Similar to the ONO film IF of the MONOS memory Mn, the ONO film IF on the lower electrode BE has a laminated structure including the bottom oxide film 5, the silicon nitride film 6, and the top oxide film 7. Similar to the MONOS memory Mn, the sidewall 10 is formed on the sidewall of the upper electrode TE via the sidewall oxide film 9, and the sidewall 10, the sidewall oxide film 9, and the upper electrode TE are formed on the lower electrode BE. The ONO film IF is formed. However, in the direction along the main surface of the semiconductor substrate SB, the end of the sidewall 10 on the side wall of the upper electrode TE and opposite to the end in contact with the side wall oxide film 9 is the side wall of the MONOS memory Mn. 10 has an eaves shape protruding outward from the end portion in the same direction of the ONO film IF formed in the lower portion. Similarly to the MONOS memory Mn, a sidewall SW is formed on the outer side wall of the side wall 10 of the upper electrode TE, and not the ONO film IF on the lower side of the outer end of the side wall 10. A silicon oxide film 12 constituting the SW is formed.

  Thus, in the present embodiment, the ONO film IF between the lower electrode BE and the upper electrode TE has a width in the direction along the main surface of the semiconductor substrate SB wider than the width in the same direction of the upper electrode TE. It is formed to extend outward from the end portion of the upper electrode TE in the same direction. In other words, the sidewall (edge portion) of the upper electrode TE is formed immediately above the ONO film IF, and there is no region where the ONO film IF is not formed immediately below the sidewall of the upper electrode TE.

  The MIS transistor Tn includes a gate electrode G1 made of a polysilicon film formed on the semiconductor substrate SB via a gate insulating film 3 that is the same layer as the insulating film 3a, and semiconductors on both sides of the gate electrode G1. It has an extension region 17 and a diffusion layer 18 formed on the upper surface of the substrate SB. The extension region 17 is a semiconductor region into which an n-type impurity (for example, P (phosphorus)) is introduced at a relatively low concentration, and the diffusion layer 18 has an n-type impurity (for example, P (phosphorus)) in the extension region 17. This is a semiconductor region introduced at a high concentration. The diffusion layer 18 is formed outside the extension region 17 with respect to the well 2 immediately below the gate electrode G 1, and is formed with a deeper junction depth than the extension region 17. The extension region 17 and the diffusion layer 18 constitute a source / drain region of the MIS transistor Tn. Further, the sidewall oxide film 9, the ONO film IF, or the sidewall 10 is not formed on the sidewall of the gate electrode G1, but the sidewall SW is formed.

  The sidewall SW is formed for the purpose of defining the width of the extension region 17 of the MIS transistor Tn which is the peripheral MIS, and the extension of the upper surface of the semiconductor substrate SB in the direction along the main surface of the semiconductor substrate SB. The width of the region 17 is substantially the same as the width of the sidewall SW in contact with the upper surface of the semiconductor substrate SB. Further, the width of the extension region 15 of the MONOS memory Mn in the same direction is substantially the same as the total width of the sidewall oxide film 9, the sidewall 10, and the sidewall SW.

  A silicide layer 19 is formed on the upper surfaces of the diffusion layers 16 and 18, the gate electrodes CG and G1, the upper electrode TE, and the lower electrode BE. However, the silicide layer 19 on the lower electrode BE is formed only on the upper surface of the lower electrode BE that is not covered with the ONO film IF and the sidewall SW. The silicide layer 19 is also formed on the upper surface of the side wall 10 formed on the side walls of the gate electrode CG, the end of the upper electrode TE, and the lower electrode BE, and in the region exposed from the side wall SW. Yes.

  The width of each sidewall oxide film 9 between the sidewall 10 and the gate electrode CG and between the sidewall 10 and the upper electrode TE is extremely small, for example, about 1 to 2 nm. Therefore, the silicide layer 19 on the gate electrode CG and the silicide layer 19 on the sidewall 10 on the side wall of the gate electrode CG are connected and integrated, and the gate electrode is interposed through the conductive silicide layer 19. The upper part of the CG and the sidewall 10 is electrically connected. Similarly, the silicide layer 19 on the upper electrode TE and the silicide layer 19 on the sidewall 10 on the side wall of the upper electrode TE are connected and integrated, and the upper electrode is interposed via the conductive silicide layer 19. The upper part of the TE and the sidewall 10 is electrically connected.

  Here, the silicide layer 19 on the lower electrode BE and the silicide layer 19 on the sidewall 10 of the side wall of the lower electrode BE are separated and not electrically connected here, but are connected and integrated. It does not matter.

  On the main surface of the semiconductor substrate SB including the silicide layer 19, the sidewall oxide film 9, the sidewall 10, SW and the element isolation region (not shown), a stopper insulating film 20 made of, for example, a silicon nitride film, and a silicon oxide film, for example An interlayer insulating film 21 made of or the like is sequentially formed. In the stopper insulating film 20 and the interlayer insulating film 21, contact holes 22 reaching from the upper surface of the interlayer insulating film 21 to the upper surfaces of the silicide layers 19 are formed, and contact plugs 23 made of a conductive film are formed in the respective contact holes 22. Is formed. Note that FIG. 1 does not show a region where the contact hole 22 and the contact plug 23 are formed above the gate electrodes CG and G1 and the upper electrode TE.

  An interlayer insulating film 25 is formed on the interlayer insulating film 21 via a stopper insulating film 24. The stopper insulating film 24 and the interlayer insulating film 25 reach the upper surface of the contact plug 23 from the upper surface of the interlayer insulating film 25. A wiring groove 26 is formed, and a metal wiring 27 made of a conductor film is formed in the wiring groove 26.

  The contact plug 23 is a connection member formed through a barrier conductor film (not shown) formed on the inner wall and bottom of the contact hole 22, and the source / drain regions and upper portions of the MONOS memory Mn and the MIS transistor Tn. The electrode TE and the lower electrode BE are electrically connected to the metal wiring 27, respectively. The contact plug 23 is made of, for example, tungsten, and the barrier conductor film formed on the side wall and the bottom thereof is made of, for example, titanium nitride. In the region not shown, the gate electrodes CG and G1 and the upper electrode TE are electrically connected to a metal wiring (not shown) via the silicide layer 19 and the contact plug 23 formed on the upper part. Yes.

  The stopper insulating film 20 is made of, for example, a silicon nitride film, and functions as an etching stopper film when the contact hole 22 is formed. The interlayer insulating films 21 and 25 are made of an insulating film such as a silicon oxide film or a SiOC film. The stopper insulating film 24 is made of, for example, a silicon nitride film, and functions as an etching stopper film when the wiring trench 26 is formed.

  The metal wiring 27 is a wiring for supplying a predetermined potential to the MONOS memory Mn, the MIS transistor Tn, and the PIP capacitor element PC, and is formed by a known damascene process. The metal wiring 27 includes a barrier conductor film formed on the inner wall and bottom of the wiring groove 26 and a metal film filled in the wiring groove 26 through the barrier conductor film. The barrier conductor film is made of a laminated film of Ta (tantalum) and TaN (tantalum nitride), for example, and the metal film is a film mainly made of Cu (copper). The barrier conductor film is provided for the purpose of preventing the metal element in the metal film from diffusing into the interlayer insulating film 25 or the like. In addition to tantalum, titanium (Ti), ruthenium (Ru), manganese (Mn), or a compound thereof may be used as a member of the barrier conductor film.

  The metal wiring 27 is not limited to the damascene structure, and may be a wiring structure formed by patterning a conductor film mainly composed of aluminum.

  The silicide layer 19 has a function of reducing the contact resistance between the diffusion layers 16 and 18 and the contact plug 23 by being interposed between the diffusion layers 16 and 18 and the contact plug 23. The silicide layer 19 is a reaction layer of metal and silicon, and as its material, for example, nickel silicide, cobalt silicide, platinum silicide or titanium silicide can be used.

  The sidewalls 10 shown in FIG. 1 are all made of the same layer film formed in the same process, and similarly, the sidewalls SW are both made of the same layer film formed in the same process. In the present embodiment, it is assumed that an n-type impurity (for example, P (phosphorus)) is introduced into each of the gate electrodes CG and G1, the upper electrode TE, and the lower electrode BE. Although the side wall 10 is originally formed as an intrinsic semiconductor into which almost no impurities are introduced, the side wall 10 on the side wall of the gate electrode CG and the upper electrode TE is connected to the gate electrode CG and the upper part via a thin side wall oxide film 9. A small amount of n-type impurity (for example, P (phosphorus)) is diffused from the electrode TE.

  At this time, the impurity concentration in the side wall 10 in the vicinity of the interface with the side wall oxide film 9 at the end of the side wall 10 on the side wall of each of the gate electrode CG and the upper electrode TE is Impurities such that the concentration of impurities (for example, P (phosphorus)) decreases from the end portion on the side wall oxide film 9 side to the end portion on the opposite side. Are distributed. That is, the end portion of the side wall 10 that is opposite to the end portion on the side wall oxide film 9 side is an intrinsic semiconductor containing almost no impurities.

  Further, when the diffusion layer 16 is formed by ion implantation of an n-type impurity (for example, P (phosphorus)) on the semiconductor substrate SB, the sidewall 10 on the sidewall of the gate electrode CG serves as a mask. Although n-type impurities are introduced into the upper portion of the sidewall 10, the end portion of the sidewall 10, particularly the end portion of the sidewall 10 opposite to the end portion on the side wall oxide film 9 side, It is an intrinsic semiconductor that contains almost no impurities. The sidewall 10 is originally an intrinsic semiconductor and is a semiconductor film having lower conductivity than the gate electrode CG. However, the sidewall 10 is diffused from the gate electrode CG and ion implantation at the time of forming the diffusion layer 16 is performed. In addition, an n-type impurity (for example, P (phosphorus)) is introduced at a low concentration into the end portion on the gate electrode CG side. Further, since the gate electrode CG and the sidewall 10 on the side wall of the gate electrode CG are electrically connected via the silicide layer 19 formed on each of the gate electrodes CG, the sidewall 10 is weak in the MONOS memory Mn. It is considered to function as a gate electrode.

  Here, the MONOS memory Mn can perform writing and erasing of information by putting electrons into and out of the silicon nitride film 6 which is a charge storage layer below the gate electrode CG. There are two ways to put in and out the electrons. Writing and erasing are performed by putting electrons into and out of the entire lower surface of the silicon nitride film 6 with a tunnel current, and extension regions 15 constituting drain regions using hot carriers. There is a method in which writing is performed by putting electrons into the end of the silicon nitride film 6 in the vicinity, and erasing is performed by hot holes generated at the end of the extension region 15. The method using the tunnel current can increase the number of times of rewriting and ensure high reliability. On the other hand, in the method using the hot carrier, the operation voltage for writing / erasing can be lowered and the operation speed can be increased. can do.

  The PIP capacitor element PC holds a charge in the upper electrode TE or the lower electrode BE by forming a dielectric film such as the ONO film IF or other insulating film between the lower electrode BE and the upper electrode TE. It is a capacitive element that functions as a capacitor.

  The MIS transistor Tn constitutes a peripheral circuit (logic) for operating the MONOS memory Mn, and is a field effect transistor having a function of selecting, for example, a plurality of MONOS memories Mn formed.

  Next, the effect of the semiconductor device of this embodiment will be described using a comparative example.

  FIG. 14 is a cross-sectional view of a semiconductor device having a PIP capacitor element as a comparative example. As shown in FIG. 14, an insulating film 3a, a lower electrode BE, an ONO film IFg that is a capacitive insulating film, and an upper electrode TE that form the PIP capacitive element PCg are sequentially formed on the semiconductor substrate SB. Silicide layers 19 are formed on the upper surfaces of the lower electrode BE and the upper electrode TE. For the sake of clarity, FIG. 14 does not show contact plugs, interlayer insulating films, metal wirings, and the like formed above the silicide layer 19.

  In the direction along the main surface of the semiconductor substrate SB, the width of the ONO film IFg is narrower than the width of the upper electrode TE, and the end portion of the upper electrode TE is located outside the end portion of the ONO film IFg. Sidewalls SW having a laminated structure in which a silicon oxide film 12, a silicon nitride film 13, and a silicon oxide film 14 are sequentially formed are formed on the side walls of the upper electrode TE and the lower electrode BE. The lowermost silicon oxide film 12 of the formed sidewall SW enters between the lower electrode BE directly below the end of the eaves-like upper electrode TE formed outside the end of the ONO film IFg. Is formed.

  The silicon oxide film 12 includes a sidewall oxide film formed by heat treatment and a TEOS (Tetra Ethyl Ortho Silicate) film formed by a CVD (Chemical Vapor Deposition) method.

  That is, the ONO film IFg is formed between the upper electrode TE and the lower electrode BE, but the ONO film IFg is formed between the upper electrode TE and the lower electrode BE in the vicinity of the end of the upper electrode TE. The silicon oxide film 12 is formed instead. Since the insulating property of the silicon oxide film 12 is lower than that of the ONO film IFg, when such a PIP capacitor element is operated, the upper electrode TE and the lower electrode are formed at the end of the upper electrode TE where the ONO film IFg is not formed. There is a problem in that the withstand voltage between the BE and the lower electrode decreases, and a leak current easily flows between the upper electrode TE and the lower electrode BE. In FIG. 14, a path through which a leak current flows is indicated by an arrow.

  The above problem is that the ONO film IFg is not formed to extend outside the end portion of the upper electrode TE, and the end portion of the upper electrode TE and the end portion of the ONO film IFg are to be formed in alignment. Occur. In the manufacturing process of the semiconductor device of the comparative example, the processed insulating film 3a and the lower electrode BE are first formed on the semiconductor substrate SB, and then the ONO film IFg and the polysilicon film are formed on the entire main surface of the semiconductor substrate SB by CVD. Then, the polysilicon film and the ONO film IFg are processed using the same photoresist film as a mask by photolithography and etching to form the upper electrode TE made of the polysilicon film. The ONO film is left below.

At this time, the polysilicon film is processed by anisotropic etching, but the ONO film IFg is processed by wet etching using hot phosphoric acid (H ₂ PO ₄ ) or the like. Overetching is performed on the inner side of the end portion of the electrode TE, and the end portion of the ONO film IFg recedes from the end portion of the upper electrode TE toward the central portion of the ONO film IFg. That is, in practice, the side walls of the upper electrode TE and the ONO film IFg are not aligned on the same surface, and the end portion of the upper electrode TE has an eaves shape, so that the upper electrode formed after the upper electrode TE is formed. The silicon oxide film 12 constituting the TE sidewall SW is formed so as to fill the space below the end of the eaves-shaped upper electrode TE formed by the recessed ONO film IF.

  In the PIP capacitor element PCg having such a structure, a leakage current easily flows between the upper electrode TE and the lower electrode BE through the silicon oxide film 12 formed between the upper electrode TE and the lower electrode BE. Therefore, there is a problem that the breakdown voltage between the upper electrode TE and the lower electrode BE is lowered, and the reliability of the semiconductor device is lowered.

  Therefore, as shown in FIG. 1, the inventor does not interpose the silicon oxide film 12 between the upper electrode TE and the lower electrode BE, and extends the ONO film IF to the outside as compared with the semiconductor device of the comparative example. Thus, a semiconductor device in which the ONO film IF is disposed directly under the side wall of the upper electrode TE was examined.

  As shown in FIG. 1, in the semiconductor device of the present embodiment, the ONO film IF is continuously formed from the lower part of the side wall 10 on one side wall of the upper electrode TE to the lower part of the side wall 10 on the other side wall. Therefore, the silicon oxide film 12 constituting the sidewall SW is not formed between the lower surface of the upper electrode TE and the lower electrode BE. Thus, the ONO film IF having higher insulation than the silicon oxide film 12 is formed in all the regions immediately below the upper electrode TE, so that the upper electrode TE and the semiconductor device of the comparative example shown in FIG. The breakdown voltage between the lower electrode BE can be increased.

  At this time, as described above, n-type impurities (for example, P (phosphorus)) are diffused from the upper electrode TE into the sidewall 10 on the sidewall of the upper electrode TE through the thin sidewall oxide film 9. Conceivable. However, since the end portion of the side wall 10 opposite to the end portion in contact with the side wall oxide film 9 is an intrinsic semiconductor to which almost no impurities are introduced, the ONO film is formed immediately below the end portion of the side wall 10. Even if the IF is not formed and the silicon oxide film 12 is formed instead, a leakage current flows between the upper electrode TE and the lower electrode BE through the silicon oxide film 12 and the sidewall 10. Can be prevented. This is because, for example, when the sidewall 10 is a semiconductor film having the same impurity concentration as that of the upper electrode TE, a strong electric field is not generated in the sidewall 10 which is an intrinsic semiconductor having a low impurity concentration.

  The same applies to the MONOS memory Mn, and it is considered that the sidewall 10 of the MONOS memory Mn functions as a weak gate electrode. However, the end of the side wall 10 and the end opposite to the end in contact with the side wall oxide film 9 is an intrinsic semiconductor into which almost no impurities are introduced. For this reason, even if the ONO film IF is not formed immediately below the end portion of the sidewall 10 and the silicon oxide film 12 is formed instead, the gate electrode CG is interposed via the silicon oxide film 12 and the sidewall 10. Leakage current can be prevented from flowing between the diffusion layer 16 and the source / drain region formed of the diffusion layer 16 and the extension region 15.

  As will be described later, in the semiconductor device according to the present embodiment, the ONO film IF constituting the MONOS memory Mn and the ONO film IF constituting the PIP capacitor element PC are formed of the same layer film, so that the manufacturing process is performed. It is simplified. However, when the ONO film IF which is the gate insulating film of the MONOS memory Mn and the insulating film between the upper electrode TE and the lower electrode BE of the PIP capacitor element PC are formed separately, the upper electrode TE of the PIP capacitor element PC. The insulating film between the lower electrode BE and the lower electrode BE is not limited to the ONO film IF, and may be formed of a dielectric film (for example, a silicon nitride film) or other insulating films.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 2 (a), 2 (b), 3 (a), 3 (b), 4 (a), 4 (b), 5 (a), 5 (b), 6 FIGS. 6A, 6B, 7, 8 and 9 are cross-sectional views showing a method for manufacturing a semiconductor device in the case where a MONOS memory, a PIP capacitor, and a MIS transistor are formed on the same substrate. 2 to 9, in order from the left, a region for forming a MONOS memory (MONOS memory forming region 1A), a region for forming a PIP capacitor (PIP capacitor element forming region 1B), and a region for forming a MIS transistor (MIS). A transistor formation region 1C) is shown.

  First, as shown in FIG. 2A, a semiconductor substrate (semiconductor wafer) SB made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm is prepared. Subsequently, an element isolation layer (not shown) is formed on the main surface of each semiconductor substrate SB between the MONOS memory formation region 1A and the PIP capacitor element formation region 1B and between the PIP capacitor element formation region 1B and the MIS transistor formation region 1C. ). The element isolation layer is made of an insulator such as silicon oxide, and is formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method. For example, the element isolation layer can be formed by an insulating film embedded in a groove (not shown) formed in the semiconductor substrate SB.

Next, p ⁻ type wells 2 are formed in the MONOS memory formation region 1A, the PIP capacitor element formation region 1B, and the MIS transistor formation region 1C on the main surface of the semiconductor substrate SB, respectively. At this time, the well 2 is formed by ion-implanting a p-type impurity such as boron (B) into the upper surface of the semiconductor substrate SB. The MONOS memory formation region 1A, the PIP capacitor element formation region 1B, and the well 2 of the MIS transistor formation region 1C can be made to have different impurity concentrations by allocating impurities in separate steps using photolithography technology.

  Further, it is desirable to form a silicon oxide film (not shown) as a through film on the upper surface of the semiconductor substrate SB before ion implantation for forming the well 2 is performed. The silicon oxide film is an insulating film formed by, for example, a thermal oxidation method, an ISSG (In-Situ Steam Generation) oxidation method, or a CVD method, and the semiconductor substrate SB is damaged by ion implantation when the well 2 is formed. It has a function to prevent this. In this case, the silicon oxide film is removed by wet etching after the ion implantation step.

  Next, as shown in FIG. 2B, an insulating film 3a made of silicon oxide is formed on the semiconductor substrate SB by, eg, thermal oxidation, and then the polysilicon film 4 is formed on the insulating film 3a by CVD or the like. Is formed (deposited). Subsequently, an n-type impurity (for example, P (phosphorus)) is introduced by ion implantation only into the polysilicon film 4 in the PIP capacitor element formation region 1B by photolithography. At this time, the polysilicon film 4 in the MONOS memory formation region 1A and the MIS transistor formation region 1C is covered with a photoresist film so that n-type impurities are not introduced.

  Next, as shown in FIG. 3A, the polysilicon film 4 and the insulating film 3a in the MONOS memory formation region 1A and a part of the polysilicon film in the PIP capacitor element formation region 1B are etched by photolithography. 4 and the insulating film 3a are removed. At this time, the polysilicon film 4 and the insulating film 3a in the MIS transistor formation region 1C are not processed. As a result, the lower electrode BE made of the polysilicon film 4 is formed in the PIP capacitor element formation region 1B.

Subsequently, by implanting an n-type impurity (for example, P (phosphorus)) at a relatively low concentration by ion implantation into the main surface of the semiconductor substrate SB in the MONOS memory formation region 1A, an n ⁻ -type channel region (shown in the figure). Not). By forming the channel region, it is possible to adjust the threshold voltage of the MONOS memory Mn formed in the MONOS memory formation region 1A in a later process.

  Next, as shown in FIG. 3B, a bottom oxide film 5 made of a silicon oxide film, a silicon nitride film 6, a top oxide film 7 made of a silicon oxide film, and polysilicon over the entire main surface of the semiconductor substrate SB. The film 8 is formed sequentially. The bottom oxide film 5 and the top oxide film 7 are formed by, for example, a thermal oxidation method, and the silicon nitride film 6 and the polysilicon film 8 are formed by, for example, a CVD method. Subsequently, an n-type impurity (for example, P (phosphorus)) is introduced into the polysilicon film 8 by ion implantation.

  Thereby, the upper surface and the side wall of the lower electrode BE are covered with the ONO film IF including the bottom oxide film 5, the silicon nitride film 6, and the top oxide film 7, and the polysilicon film 8 is formed on the ONO film IF. The bottom oxide film 5 and the top oxide film 7 are not limited to the thermal oxidation method, and may be formed by a CVD method or the like. In addition, when an n-type impurity (for example, P (phosphorus)) is ion-implanted into the polysilicon film 8, ion implantation is performed in a separate process into the MONOS memory formation region 1A and the PIP capacitor element formation region 1B using photolithography technology. The impurity concentration of the polysilicon film 8 may be different between the MONOS memory formation region 1A and the PIP capacitor element formation region 1B.

  Next, as shown in FIG. 4A, the polysilicon film 8 in the MIS transistor formation region 1C is removed by anisotropic etching using a photolithography technique, and the MONOS memory formation region 1A and the PIP capacitor are formed in the same process. Part of the polysilicon film 8 in the element formation region 1B is removed. In this etching process, only the polysilicon film 8 immediately above the lower electrode BE in the PIP capacitor element formation region 1B is left. As a result, the gate electrode CG made of the polysilicon film 8 is formed on the main surface of the semiconductor substrate SB via the ONO film IF in the MONOS memory formation region 1A, and the polysilicon film 8 is formed in the PIP capacitor element formation region 1B. An upper electrode TE is formed.

  At this time, although the ONO film IF under the lower electrode BE is not removed, it is considered that the upper surface of the top oxide film 7 is actually removed by about 1 to 2 nm by anisotropic etching for removing the polysilicon film 8. It is done.

  Further, the width of the upper electrode TE in the direction along the main surface of the semiconductor substrate SB is processed to be narrower than the width of the lower electrode BE in the same direction, and the end portion of the upper electrode TE in the same direction has the same direction. The upper electrode TE is not formed outside the end portion of the lower electrode BE, and the upper electrode TE is formed only inside the side wall of the polysilicon film 4 in the PIP capacitor element formation region 1B in a plan view.

Thereafter, n-type impurities (for example, P (phosphorus)) are ion-implanted into the main surface of the semiconductor substrate SB in the MONOS memory formation region 1A, thereby forming an n ⁻⁻ type in the main surface of the semiconductor substrate SB in the MONOS memory formation region 1A. The semiconductor region (not shown) is formed. The n ⁻⁻ type semiconductor region is formed on the upper surface of the semiconductor substrate SB in regions on both sides of the gate electrode CG. Here, when ion implantation is performed in the MONOS memory formation region, the PIP capacitor element formation region 1B and the MIS transistor formation region 1C are covered with a photoresist film formed by exposure using a photomask, and the PIP capacitor element formation region 1B. Further, impurities are prevented from being introduced into the MIS transistor formation region 1C. The n ⁻⁻ type semiconductor region is formed on the side wall of the gate electrode CG shown in FIG. 1 in a later step, and the resistance of the upper surface of the semiconductor substrate SB below the side wall 10 serving as the gate electrode of the MONOS memory Mn. It is a semiconductor region formed for the purpose of reducing the value.

  Next, as shown in FIG. 4B, the semiconductor substrate SB is heat-treated, and an oxide film having a thickness of about 1 to 2 nm is formed on each surface of the exposed ONO film IF, gate electrode CG, and upper electrode TE. Is formed by, for example, a thermal oxidation method. Thus, the top oxide film 7 from which the exposed upper portion has been removed by the etching process for processing the polysilicon film 8 (see FIG. 4A) is the top oxide film 7 before the polysilicon film 8 is processed. Therefore, for example, the film thicknesses of the unexposed top oxide film 7 immediately below the gate electrode CG and the exposed top oxide film 7 on both sides of the gate electrode CG, respectively. Are almost identical.

  In addition, a silicon oxide film having a thickness of about 1 to 2 nm is formed on the side walls and the upper surface of the gate electrode CG and the upper electrode TE by this oxidation process.

  Subsequently, an intrinsic semiconductor film made of a silicon film or the like in which impurities are hardly introduced is formed on the entire main surface of the semiconductor substrate SB by, for example, a CVD method, and then the intrinsic semiconductor film is processed by anisotropic etching ( Etch back) to expose the upper surfaces of the gate electrode CG and the upper electrode TE. As a result, the silicon oxide film on each of the gate electrode CG and the upper electrode TE is removed, so that the sidewall oxide film 9 made of the silicon oxide film remains on the side walls of the gate electrode CG and the upper electrode TE. .

  In addition, sidewalls 10 made of the intrinsic semiconductor film are formed on the sidewalls of the gate electrode CG and the upper electrode TE via the sidewall oxide film 9, and the sidewalls of the lower electrode BE are formed on the sidewalls via the ONO film IF. A wall 10 is formed. Each sidewall 10 is formed on the ONO film IF. Here, the silicon oxide film formed along the top surface of the top oxide film 7 will be described as being integrated with the top oxide film 7 to form the top oxide film 7.

  A sidewall oxide film 9 is formed between the sidewall 10 and the gate electrode CG and between the sidewall 10 and the upper electrode TE. The sidewall oxide film 9 has a thickness of about 1 to 2 nm, which is very Therefore, an n-type impurity (for example, P (phosphorus)) is diffused from the gate electrode CG or the upper electrode TE into the sidewall 10. However, the n-type impurity (for example, P (phosphorus)) is diffused particularly in the sidewall 10 only at the end portion of the sidewall 10 in the vicinity of the interface between the sidewall 10 and the sidewall oxide film 9. N-type impurities hardly diffuse at the opposite end. Therefore, the end portion of the sidewall 10 opposite to the end portion in contact with the sidewall oxide film 9 maintains the intrinsic semiconductor state even after the semiconductor device is completed by the subsequent process.

Next, as shown in FIG. 5A, the exposed ONO film IF is removed by wet etching using hot phosphoric acid (H ₂ PO ₄ ) or the like. As a result, in the MONOS memory formation region 1A, the ONO film IF remains only below the gate electrode CG, the sidewall oxide film 9, and the sidewall 10, and the ONO film IF in the MIS transistor formation region 1C is removed. Further, in the PIP capacitor element formation region 1B, the L-shaped ONO film IF is continuously left on the side wall of the lower electrode BE from the main surface of the semiconductor substrate SB on both sides of the lower electrode BE, and the upper electrode TE and its side walls are left. The ONO film IF immediately below the side wall oxide film 9 and the side wall 10 remains. Thereby, the PIP capacitor element PC having the lower electrode BE, the ONO film IF, and the upper electrode TE is formed.

  At this time, the ONO film IF is continuously formed immediately below the upper electrode TE and the side wall oxide films 9 and the side walls 10 formed on the respective side walls of the upper electrode TE. The ONO film IF is also formed in the region.

  Subsequently, after introducing an n-type impurity (for example, P (phosphorus)) into the polysilicon film 8 in the MIS transistor formation region 1C by ion implantation, the polysilicon film 4 and the insulating film 3a are formed by etching using a photolithography technique. The gate electrode G1 made of the polysilicon film 4 and the gate insulating film 3 made of the insulating film 3a are formed by processing. When n-type impurities are introduced into the polysilicon film 8, the MONOS memory formation region 1A and the PIP capacitor element formation region 1B other than the MIS transistor formation region 1C are covered with a photoresist film, and the MONOS memory formation region 1A and the PIP capacitor element are covered. An n-type impurity is prevented from being introduced into the formation region 1B.

Next, as shown in FIG. 5B, n-type impurities (for example, P (phosphorus)) are ion-implanted into the main surface of the semiconductor substrate SB in the MONOS memory formation region 1A, thereby forming the MONOS memory formation region 1A. An extension region 15 that is an n ⁻ type semiconductor region is formed on the main surface of the semiconductor substrate SB. The extension region 15 is formed on the upper surface of the semiconductor substrate SB in the regions on both sides of the gate electrode CG. Here, when ion implantation is performed on the MONOS memory formation region 1A, the PIP capacitor element formation region 1B and the MIS transistor formation region 1C are covered with a photoresist film formed by exposure using a photomask, and an extension region 15 is formed. Impurities are prevented from being introduced into regions other than the region where they occur.

Similarly, an extension region 17 which is an n ⁻ type semiconductor region is formed on the main surface of the semiconductor substrate SB in the MIS transistor formation region 1C. The extension region 17 is formed on the upper surface of the semiconductor substrate SB in the regions on both sides of the gate electrode G1. That is, the extension region 17 is formed only in the MIS transistor formation region using photolithography technology. That is, when ions are implanted into the MIS transistor formation region 1C, the MONOS memory formation region 1A and the PIP capacitor element formation region 1B are covered with a photoresist film, so that impurities are introduced in addition to the region where the extension region 17 is formed. To prevent that.

  Next, as shown in FIG. 6A, a silicon oxide film 12, a silicon nitride film 13, and a silicon oxide film 14 are sequentially formed on the entire main surface of the semiconductor substrate SB by a CVD method or the like.

  Next, as shown in FIG. 6B, a part of each of the silicon oxide film 14, the silicon nitride film 13, and the silicon oxide film 12 is removed by anisotropic etching, and the upper electrode TE, the lower electrode BE, The upper surfaces of the gate electrodes CG and G1 and the semiconductor substrate SB are exposed. As a result, sidewalls SW made of the silicon oxide film 12, the silicon nitride film 13, and the silicon oxide film 14 are formed on the respective sidewalls of the upper electrode TE, the lower electrode BE, and the gate electrodes CG and G1. Note that a sidewall SW is formed on the sidewalls of the gate electrode CG and the upper electrode TE via the sidewall oxide film 9 and the sidewall 10, and the sidewall of the lower electrode BE is interposed on the ONO film IF and the sidewall 10. SW is formed.

Next, as shown in FIG. 7, an n-type impurity (for example, P (phosphorus)) is ion-implanted at a higher concentration than the step of forming the extension region 15 in the main surface of the semiconductor substrate SB in the MONOS memory formation region 1A. Thus, the diffusion layer 16 that is an n ⁺ type semiconductor region is formed on the main surface of the semiconductor substrate SB in the MONOS memory formation region 1A. The diffusion layer 16 is formed on the upper surface of the semiconductor substrate SB in the regions on both sides of the gate electrode CG and outside the extension region 15. Thereby, the MONOS memory Mn having the gate electrode CG, the sidewall 10, the ONO film IF, the extension region 15, and the diffusion layer 16 is formed.

In addition, an n-type impurity (for example, P (phosphorus)) is ion-implanted into the main surface of the semiconductor substrate SB in the MIS transistor formation region 1C at a higher concentration than in the step of forming the extension region 17, thereby forming the MIS transistor formation region 1C. A diffusion layer 18 that is an n ⁺ type semiconductor region is formed on the main surface of the semiconductor substrate SB. The diffusion layer 18 is formed on the upper surface of the semiconductor substrate SB in the regions on both sides of the gate electrode G 1 and outside the extension region 17. Thereby, the MIS transistor Tn having the gate electrode G1, the extension region 17, and the diffusion layer 18 is formed. Since the diffusion layers 16 and 18 have a higher impurity concentration than the extension regions 15 and 17, the diffusion layers 16 and 18 have a higher conductivity than the extension regions 15 and 17.

  It should be noted that the diffusion layer 16 of the MONOS memory Mn and the diffusion layer 18 of the MIS transistor Tn can be made to have different impurity concentrations by allocating impurities by separate processes using photolithography technology. Further, when the diffusion layers 16 and 18 are formed, the PIP capacitor element formation region 1B is covered with a photoresist film to prevent impurities from being introduced into the PIP capacitor element PC. In particular, it is important to prevent high-concentration impurities from being introduced by the sidewall 10 of the PIP capacitor element PC.

  At this time, since the diffusion layer 16 is implanted into the semiconductor substrate SB using the gate electrode CG, the sidewall oxide film 9, the sidewall 10 and SW as a mask, an n-type impurity (for example, also on the sidewall 10 made of an intrinsic semiconductor film) P (phosphorus)) is introduced, but almost no impurities are introduced into the lower part (bottom part) of the sidewall 10.

  Next, as shown in FIG. 8, silicide layers are formed on the exposed surfaces of the gate electrodes CG and G1, the diffusion layers 16 and 18, the sidewall 10, the upper electrode TE, and the lower electrode BE by a known salicide process. 19 is formed. As a silicidation procedure, first, a metal film is deposited on the main surface of the semiconductor substrate SB by sputtering, and then the semiconductor substrate SB is heat treated, and then the unreacted metal film is removed by wet etching, thereby forming a silicide layer. 19 is formed. Examples of the member of the silicide layer 19 include nickel silicide, cobalt silicide, titanium silicide, or platinum silicide.

  At this time, since the distance between the gate electrode CG and the sidewall 10 is about 1 to 2 nm, which is the thickness of the sidewall oxide film 9, the upper portions of the gate electrode CG and the sidewalls 10 on the sidewall 10 are respectively. The silicide layers 19 are integrated in the formation process, and the sidewall 10 and the gate electrode CG are electrically connected. Similarly, the upper silicide layers 19 of the upper electrode TE and the sidewalls 10 on the side walls of the upper electrode TE and the sidewalls 10 are connected and integrated, and the sidewall 10 and the upper electrode TE are electrically connected.

  Thereafter, a stopper insulating film 20 made of a silicon nitride film and an interlayer insulating film 21 made of a silicon oxide film are sequentially formed (deposited) on the entire main surface of the semiconductor substrate SB by, for example, a CVD method.

  Next, as shown in FIG. 9, contacts reaching the silicide layers 19 formed on the upper surfaces of the gate electrodes CG and G1, the diffusion layers 16 and 18, the upper electrode TE and the lower electrode BE from the upper surface of the interlayer insulating film 21, respectively. Hole 22 is formed.

  Subsequently, after forming a thin barrier conductor film such as titanium or titanium nitride in the contact hole 22, the contact hole 22 is filled with a tungsten film, thereby forming a contact plug 23 made of the tungsten film. In other regions not shown, contact holes and contact plugs reaching the silicide layers 19 formed on the gate electrodes CG and G1 and the upper electrode TE from the upper surface of the interlayer insulating film 21 by the same process. It is formed.

  Subsequently, a stopper insulating film 24, an interlayer insulating film 25, and a metal wiring 27 are formed on the interlayer insulating film 21 and the contact plug 23 by a known damascene process, thereby completing the semiconductor device of the present embodiment. To do.

  That is, after the stopper insulating film 24 and the interlayer insulating film 25 are sequentially formed on the interlayer insulating film 21 and the contact plug 23 by the CVD method or the like, the interlayer insulating film 25 and the stopper insulating film 24 are used by photolithography and dry etching. Then, a wiring trench 26 exposing the upper surfaces of the interlayer insulating film 21 and the contact plug 23 is formed.

  Thereafter, a barrier conductor film made of tantalum, tantalum nitride, or the like or a laminated film thereof, and a conductor film mainly composed of copper are formed on the upper surface of the interlayer insulating film 25 and the inner wall and bottom of the wiring groove 26 by a plating method or the like. To do. Subsequently, the barrier conductor film and the conductor film are polished by a CMP (Chemical Mechanical Polishing) method to expose the upper surface of the interlayer insulating film 25, so that the barrier conductor film and the conductor film are formed inside the wiring groove 26. A metal wiring 27 made of is formed.

  In the present embodiment, as described above, the ONO film IF is continuously formed from the lower part of the sidewall 10 on one side wall of the upper electrode TE to the lower part of the sidewall 10 on the other side wall. The silicon oxide film 12 constituting the sidewall SW is not formed between the lower surface of the upper electrode TE and the lower electrode BE. Thus, the ONO film IF having higher insulation than the silicon oxide film 12 is formed in all the regions immediately below the upper electrode TE, so that the upper electrode TE and the semiconductor device of the comparative example shown in FIG. The breakdown voltage between the lower electrode BE can be increased.

  Also, since the ONO film IF constituting the MONOS memory Mn and the PIP capacitor element PC is the same layer insulating film formed in the same process, the insulating film between the upper electrode TE and the lower electrode BE and the MONOS memory Mn The manufacturing process of the semiconductor device can be simplified as compared with the case where the ONO film is formed as a different film in another process.

  Further, as described above, in the semiconductor device of the present embodiment, n-type impurities (for example, near the end portion in contact with the sidewall oxide film 9 are diffused into the sidewall 10 of the MONOS memory Mn due to diffusion from the gate electrode CG. P (phosphorus)) is introduced, and the sidewall 10 and the gate electrode CG are electrically connected to each other by the silicide layer 19 on the upper side. For this reason, during the operation of the MONOS memory Mn, the sidewall 10 made of an intrinsic semiconductor film functions as a weak gate electrode.

  In this case, in order to easily control characteristics such as threshold voltage or charge retention of the MONOS memory Mn, the thickness of the gate electrode CG functioning as the gate electrode and the ONO film below the sidewall 10 may be constant. Preferably, in the step of forming the gate electrode CG and the upper electrode TE shown in FIG. 4A, a part of the upper surface of the top oxide film 7 constituting the ONO film IF is removed by etching, and the exposed top oxide film 7 is exposed. The surface of the retreat.

  In contrast, in the present embodiment, the thickness of the receded top oxide film 7 is returned to the original by the oxidation process for forming the sidewall oxide film 9 described with reference to FIG. The gate electrode CG and the sidewall 10 keep the thickness of the top oxide film 7 in the lower part uniform. Therefore, it is possible to easily control the characteristics of the MONOS memory Mn as compared with the case where the gate electrode CG and the sidewall 10 are different from each other in the case where a MONOS memory having a different thickness of the top oxide film 7 is formed. The reliability of the semiconductor device can be improved.

  As a method for improving the breakdown voltage between the drain and gate or between the drain and well of the MIS transistor including the MONOS memory, an extension region having an impurity concentration lower than that of the diffusion layer constituting the drain is formed between the channel region and the diffusion layer. In addition, a method of forming the extension region wider than the low breakdown voltage MIS transistor that operates at a voltage lower than that of the MIS transistor can be considered. However, in this case, in the MIS transistor having a gate length of 340 nm, the width of the extension region of the main surface of the semiconductor substrate in the gate length direction is considered to be required to be 150 nm. Therefore, the width of the extension region of 150 nm should be further reduced. This is difficult and hinders miniaturization of semiconductor devices.

  In contrast, in the semiconductor device of the present embodiment, as described above, the end of the side wall 10 that functions as the gate electrode and the end opposite to the end in contact with the side wall oxide film 9 is almost free of impurities. By using an intrinsic semiconductor that has not been introduced, even if the gate length of the MONOS memory Mn including the width of the sidewall 10 is 340 nm and the width of the extension region 15 is less than 150 nm, the breakdown voltage between the drain and the gate can be reduced. It is possible to keep. That is, by forming the sidewall 10 which is a weak gate electrode on the sidewall of the gate electrode CG, the width of the extension region 15 can be reduced while ensuring the drain breakdown voltage. This is because the end portion of the sidewall 10 is an intrinsic semiconductor and has a low conductivity and a low impurity concentration, and the electric field weakens in the vicinity.

  Therefore, the gate-drain breakdown voltage can be maintained even if the extension region 15 is narrowed, so that the area of the MONOS memory Mn can be reduced and the semiconductor device can be miniaturized.

  Further, as described using the comparative example shown in FIG. 14, the end portion of the ONO film IFg recedes, and the silicon oxide film 12 constituting the sidewall SW between the eaves-shaped upper electrode TE and the lower electrode BE. Is present, there is a problem that a leak current is likely to be generated between the upper electrode TE and the lower electrode BE through the silicon oxide film 12. In the present embodiment, as shown in FIG. 1, the ONO film IF between the end portion of the sidewall 10 electrically connected to the upper electrode TE and the lower electrode BE recedes, and the end portion of the sidewall 10 Although the silicon oxide film 12 is interposed between the lower electrode BE and the end portion of the sidewall 10 is made of an intrinsic semiconductor as described above, the conductivity and impurity concentration are low and the electric field is difficult to increase. Therefore, it is possible to prevent a leak current from being generated between the lower electrode BE and the sidewall 10 and increase the breakdown voltage between the upper electrode TE and the lower electrode BE electrically connected to the sidewall 10. be able to.

  This effect is the same not only in the PIP capacitor element PC but also in the MONOS memory Mn, and between the extension region 15 constituting the drain region of the MONOS memory Mn and the end portion of the sidewall 10 on the side wall of the gate electrode CG. Has a region where the ONO film IF is not formed and the silicon oxide film 12 is formed. However, since the end portion of the sidewall 10 is an intrinsic semiconductor, it is possible to prevent a leak current from being generated between the sidewall 10 and the extension region 15.

  When the gate electrode is formed on the semiconductor substrate via the ONO film and the ONO film is removed by wet etching before forming the sidewall on the side wall of the gate electrode, the ONO film recedes from the end of the gate electrode. As a result, the breakdown voltage between the gate electrode and the source / drain regions may be reduced. On the other hand, in the present embodiment, the ONO film IF extends outward from the end portion of the gate electrode CG, and the end portion outside the sidewall 10 electrically connected to the gate electrode CG is defined as an intrinsic semiconductor. This makes it possible to increase the breakdown voltage between the drain and the gate.

  Note that although a semiconductor device including an n-channel MIS transistor and a MONOS memory is described as an example in this embodiment, the present invention may be applied to a p-channel MIS transistor. In this case, the well 2 shown in FIG. 1 is formed as an n-type well, and the extension regions 15 and 17 and the diffusion layers 16 and 18 are formed as p-type semiconductor regions. Further, it is desirable that the impurity introduced into the gate electrodes CG, G1, the upper electrode TE, and the lower electrode BE is a p-type impurity (for example, B (boron)).

  The present invention may be applied to a semiconductor device having an n-channel MIS transistor and a MONOS memory, and a p-channel MIS transistor and a MONOS memory. That is, the present invention can be applied to a CMIS transistor (Complementary MIS transistor) having an n-channel MIS transistor and a p-channel MIS transistor.

(Embodiment 2)
Next, a semiconductor device having a MONOS memory, a PIP capacitance element, and a MIS transistor, and a sidewall oxide film thicker than the semiconductor device of the first embodiment is formed on each sidewall of the upper electrode and each gate electrode. A semiconductor device will be described.

  FIG. 10 is a cross-sectional view of the semiconductor device of this embodiment. As shown in FIG. 10, the semiconductor device according to the present embodiment has substantially the same structure as the semiconductor device according to the first embodiment. That is, the upper electrode TE of the PIP capacitor element PC, the sidewall oxide film 28 formed on the sidewall of the upper electrode TE, and the continuous ONO film IF are formed between the sidewall 10 and the lower electrode BE. The gate electrode CG of the MONOS memory Mn, the sidewall oxide film 28 formed on the sidewall of the gate electrode CG, and the continuous ONO film IF are formed between the sidewall 10 and the semiconductor substrate SB. Therefore, as with the semiconductor device of the first embodiment, the breakdown voltage between the upper electrode TE and the lower electrode BE can be increased as compared with the semiconductor device of the comparative example shown in FIG. In addition, the breakdown voltage between the gate electrode CG and the source / drain regions can be increased.

  However, in the semiconductor device shown in FIG. 10, sidewall oxide film 28 formed on each sidewall of upper electrode TE and gate electrode CG is compared with sidewall oxide film 9 shown in FIG. 1 in the first embodiment. Thick film. Specifically, the thickness of the sidewall oxide film 28 is, for example, about 10 to 20 nm.

  For this reason, the impurities in the upper electrode TE hardly diffuse into the sidewall 10 formed on the sidewall of the upper electrode TE via the sidewall oxide film 28, and the sidewall 10 is in contact with the sidewall oxide film 28. The second embodiment is different from the first embodiment in that it is made of an intrinsic semiconductor film including the vicinity of 10 side walls. Similarly, the impurities in the gate electrode CG hardly diffuse into the sidewall 10 formed on the sidewall of the gate electrode CG via the sidewall oxide film 28. However, since the sidewall 10 formed on the sidewall of the gate electrode CG via the sidewall oxide film 28 functions as a mask when forming the diffusion layer 16, an n-type impurity is introduced into the upper portion thereof. In the figure, the side wall oxide film 28 and the top oxide film 7 are distinguished from each other, but in actuality, they are films made of the same silicon oxide film and integrated.

  Here, as shown in FIG. 10, the gap between the gate electrode CG and the sidewall 10 on the side wall and the gap between the upper electrode TE and the sidewall 10 on the side wall are larger than those in the semiconductor device of the first embodiment. It is assumed that the silicide layers 19 on the gate electrodes CG and the sidewalls 10 are connected to each other, and the silicide layers 19 on the upper electrodes TE and the sidewalls 10 are connected to each other. However, the side wall 10 formed on the side wall of the upper electrode TE via the side wall oxide film 28 is mostly composed of an intrinsic semiconductor, and therefore functions as a part of the electrode of the PIP capacitor element PC. Absent.

  Further, the sidewall 10 formed on the sidewall of the gate electrode CG via the sidewall oxide film 28 functions as a mask when forming the diffusion layer 16, so that n-type impurities are introduced, but the MONOS memory Mn It does not function as part of the electrode. This is because the sidewall oxide film 28 is formed thick, so that the thickness of the top oxide film 7 constituting the ONO film IF in the region not covered by the gate electrode CG is the top oxide immediately below each of the gate electrodes CG. This is because it is thicker than the film 7.

  As described above, in the semiconductor device according to the present embodiment, the impurity concentration of the sidewall 10 is lower than that of the semiconductor device according to the first embodiment, and the ONO film IF in the region not covered with the gate electrode CG is formed thick. Therefore, the generation of leakage current between the upper electrode TE and the lower electrode BE and the generation of leakage current between the gate electrode CG and the source / drain regions via the silicon oxide film 12 formed on the side wall of the ONO film IF is prevented. Can do. Therefore, the breakdown voltage of the MONOS memory Mn and the PIP capacitor element PC can be increased as compared with the semiconductor device of the first embodiment.

  Similarly to the first embodiment, since the ONO film IF constituting the MONOS memory Mn and the PIP capacitor element PC is the same insulating film formed in the same process, the upper electrode TE and the lower electrode BE The manufacturing process of the semiconductor device can be simplified as compared with the case where the insulating film between them and the ONO film of the MONOS memory Mn are formed as different films in different processes.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 11 (a) and 11 (b). FIG. 11A and FIG. 11B are cross-sectional views showing a method for manufacturing a semiconductor device in the case where a MONOS memory, a PIP capacitor, and a MIS transistor are formed on the same substrate. The manufacturing method of the semiconductor device of the present embodiment is almost the same as that of the first embodiment. However, in the first embodiment, the extension region 15 is formed in the step of FIG. In the embodiment, the extension region 15 is formed in a process corresponding to FIG. Unlike the sidewall oxide film 9 formed in FIG. 4B, a sidewall oxide film 28 having a thickness larger than that of the sidewall oxide film 9 is formed in the step corresponding to FIG.

  First, since the first manufacturing process is performed in the same manner up to FIG. 4A of the first embodiment, detailed description is omitted. That is, after depositing an ONO film and a polysilicon film on a lower electrode formed on a semiconductor substrate, the polysilicon film is processed to form a gate electrode and an upper electrode, and then an n-type memory is formed in the MONOS memory formation region. Impurities (for example, P (phosphorus)) are ion-implanted.

However, in the ion implantation after forming the gate electrode and the upper electrode, the ion implantation is performed at a higher concentration than the ion implantation in FIG. 4A in the first embodiment. As a result, as shown in FIG. 11A, extension regions 15 that are n ⁻ type semiconductor regions are formed on the upper surface of the semiconductor substrate SB on both sides of the gate electrode CG. FIG. 11A is a diagram corresponding to FIG. 4A of the first embodiment, and is a cross-sectional view illustrating the method for manufacturing the semiconductor device of the present embodiment.

  Next, as shown in FIG. 11B, a sidewall oxide film 28 and a sidewall 10 are sequentially formed on the sidewalls of the upper electrode TE and the gate electrode CG in the same manner as in the step of FIG. 4B. . Here, the sidewall oxide film 28 corresponds to the sidewall oxide film 9 shown in FIG. 4B. However, by adjusting the time or temperature of the heat treatment, the thickness of the sidewall oxide film 28 is larger than that of the sidewall oxide film 9. It is thick. Specifically, the thickness of the sidewall oxide film 28 shown in FIG. 11B is about 10 to 20 nm. The exposed top oxide film 7 is also thicker than that of the first embodiment, and the top oxide film 7 in the other region is thicker than the top oxide film 7 directly below the gate electrode CG and the upper electrode. The oxide film 7 is thicker.

  Since the side wall oxide film 28 is thicker than the side wall oxide film 9 (see FIG. 4B), the side wall oxide film 28 hardly diffuses into the side wall 10 on the side walls of the gate electrode CG and the upper electrode TE. Even after the semiconductor device is completed through the subsequent steps, the sidewall 10 maintains the state of an intrinsic semiconductor film in which almost no impurities are introduced.

  Subsequent steps are performed in substantially the same manner as in the first embodiment, whereby the semiconductor device of the present embodiment shown in FIG. 10 is completed. However, in this embodiment, since the extension region 15 has already been formed in the step of FIG. 11A corresponding to the step of FIG. 4A, it corresponds to the step described with reference to FIG. In this step, it is not necessary to perform ion implantation in the MONOS memory formation region 1A, and a step of forming the extension region 15 is not necessary.

  That is, after the step shown in FIG. 11B, after removing the exposed ONO film IF, ions are implanted only into the MIS transistor formation region 1C to form the extension region 17 (see FIG. 10). Subsequently, a sidewall SW is formed. Thereafter, after the diffusion layers 16 and 18 are formed, the silicide layer 19 is formed, and then the stopper insulating film 20 and the interlayer insulating film 21 are sequentially formed on the semiconductor substrate SB. Thereafter, after forming a contact hole 22 reaching the silicide layer 19 from the upper surface of the interlayer insulating film 21, a contact plug 23 is embedded in the contact hole 22, and the upper surface of the interlayer insulating film 21 is exposed by CMP. Subsequently, a stopper insulating film 24 and an interlayer insulating film 25 are sequentially formed on the interlayer insulating film 21 and the contact plug 23, and then the stopper insulating film 24 and the interlayer insulating film on the contact plug 23 by a known damascene method. By forming the metal wiring 27 in the wiring groove 26 formed in 25, the semiconductor device of the present embodiment is completed.

  In the manufacturing method of the semiconductor device of the present embodiment, the upper electrode TE of the PIP capacitor element PC, the side wall oxide film 28 formed on the side wall of the upper electrode TE, and the ONO film continuous between the side wall 10 and the lower electrode BE. The IF is formed, and the sidewall oxide film 28 is made thicker than the sidewall oxide film 9 (see FIG. 1) to prevent impurities from diffusing into the sidewall 10.

  Similarly, the gate electrode CG of the MONOS memory Mn, the side wall oxide film 28 formed on the side wall of the gate electrode CG, and the continuous ONO film IF are formed between the side wall 10 and the semiconductor substrate SB. The film 28 is made thicker than the side wall oxide film 9 (see FIG. 1) to prevent impurities from diffusing into the side wall 10.

  Therefore, the breakdown voltage between the upper electrode TE and the lower electrode BE can be increased as compared with the semiconductor device of the first embodiment. In addition, the breakdown voltage between the gate electrode CG and the source / drain regions can be increased.

  In the first embodiment, in the step shown in FIG. 4A, a photoresist film is formed using a photomask, and impurities are ion-implanted into the MONOS memory formation region 1A. Further, FIG. Also in the process shown in FIG. 5B, a photoresist film is formed using a photomask, and impurities are ion-implanted into the MONOS memory formation region 1A to form the extension region 15.

  On the other hand, in the manufacturing process of the semiconductor device of the present embodiment, the extension region 15 is formed in the MONOS memory forming region in the step shown in FIG. 11A corresponding to FIG. The manufacturing process is simplified compared to the first embodiment, and one photomask to be used is omitted. For this reason, the manufacturing cost of the semiconductor device can be reduced.

  Similarly to the first embodiment, since the ONO film IF constituting the MONOS memory Mn and the PIP capacitor element PC is the same insulating film formed in the same process, the upper electrode TE and the lower electrode BE The manufacturing process of the semiconductor device can be simplified as compared with the case where the insulating film between them and the ONO film of the MONOS memory Mn are formed as different films in different processes.

(Embodiment 3)
Next, a semiconductor device having a MONOS memory, a PIP capacitance element, and a MIS transistor, in which a sidewall 29 made of an insulating film is formed on each side wall of the gate electrode and the upper electrode will be described.

  FIG. 12 shows a cross-sectional view of the semiconductor device of this embodiment. As shown in FIG. 12, the semiconductor device according to the present embodiment has substantially the same structure as the semiconductor device according to the first embodiment. That is, a continuous ONO film IF is formed between the upper electrode TE of the PIP capacitor element PC and the side wall 29 formed on the side wall of the upper electrode TE and the lower electrode BE. Similarly, the MONOS memory Mn A continuous ONO film IF is formed between the gate electrode CG and the sidewall 29 formed on the sidewall of the gate electrode CG and the semiconductor substrate SB. Therefore, as with the semiconductor device of the first embodiment, the breakdown voltage between the upper electrode TE and the lower electrode BE can be increased as compared with the semiconductor device of the comparative example shown in FIG. In addition, the breakdown voltage between the gate electrode CG and the source / drain regions can be increased.

  However, in the semiconductor device shown in FIG. 12, the members of the sidewalls 29 formed on the respective sidewalls of the upper electrode TE and the gate electrode CG are the sides made of the intrinsic semiconductor film shown in FIG. Unlike the wall 10, it is an insulating film made of a silicon oxide film, a silicon nitride film, or the like, which is different from the first embodiment. Therefore, the sidewall 29 does not work as the upper electrode of the PIP capacitor element PC together with the upper electrode TE, and does not work as the gate electrode of the MONOS memory Mn together with the gate electrode CG.

  Also, the silicide layer 19 is not formed on the sidewall 29, and the sidewall oxide film is not formed on the sidewalls of the gate electrode CG and the upper electrode TE, which is different from the first embodiment. Further, since the heat treatment for forming the sidewall oxide film 9 (see FIG. 1) is not performed, the upper surface of the top oxide film 7 constituting the ONO film IF remains retreated, and is directly below the upper electrode TE and the gate electrode CG. Compared with the film thickness of the top oxide film 7, the film thickness of the top oxide film 7 in other regions remains thin.

  As in the first embodiment, in the method of manufacturing the semiconductor device of the present embodiment, the upper electrode TE of the PIP capacitor element PC and the side wall 29 formed on the side wall of the upper electrode TE and the lower electrode BE are disposed. A continuous ONO film IF is formed.

  Similarly, a continuous ONO film IF is formed between the gate electrode CG of the MONOS memory Mn and the sidewall 29 formed on the side wall of the gate electrode CG and the semiconductor substrate SB.

  Therefore, the breakdown voltage between the upper electrode TE and the lower electrode BE can be increased as compared with the semiconductor device of the comparative example described with reference to FIG. In addition, the breakdown voltage between the gate electrode CG and the source / drain regions can be increased.

  In the present embodiment, the sidewall 29 shown in FIG. 12 is an insulating film made of a silicon oxide film, a silicon nitride film, or the like, and does not function as a gate electrode of the MONOS memory Mn. Therefore, the sidewall of the ONO film IF of the MONOS memory Mn It is not necessary to keep the film thickness uniform.

  Similarly to the first embodiment, since the ONO film IF constituting the MONOS memory Mn and the PIP capacitor element PC is the same insulating film formed in the same process, the upper electrode TE and the lower electrode BE The manufacturing process of the semiconductor device can be simplified as compared with the case where the insulating film between them and the ONO film of the MONOS memory Mn are formed as different films in different processes.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIG. FIG. 13 is a cross-sectional view showing a method for manufacturing a semiconductor device when a MONOS memory, a PIP capacitor, and a MIS transistor are formed on the same substrate. The manufacturing method of the semiconductor device of the present embodiment is almost the same as that of the first embodiment, but in the first embodiment, the sidewall 10 made of the sidewall oxide film 9 and the intrinsic semiconductor film in the step of FIG. In the present embodiment, the sidewall oxide film is not formed in the step corresponding to FIG. 4B, but the sidewall 29 made of an insulating film is formed.

  First, since the first manufacturing process is similarly performed up to FIG. 11A of the second embodiment, detailed description thereof is omitted. That is, after depositing an ONO film and a polysilicon film on a lower electrode formed on a semiconductor substrate, the polysilicon film is processed to form a gate electrode and an upper electrode, and then an n-type memory is formed in the MONOS memory formation region. Impurities (for example, P (phosphorus)) are ion-implanted to form extension regions 15 (see FIG. 13).

  Next, as shown in FIG. 13, an insulating film made of, for example, a silicon oxide film is formed on the entire main surface of the semiconductor substrate SB on which the extension region 15 is formed by, for example, a CVD method, and then the insulating film is etched. By performing the back, side walls 29 made of the insulating film are formed on the side walls of the gate electrode CG, the lower electrode BE, and the upper electrode TE.

  At this time, the top oxide film 7 exposed immediately before the step shown in FIG. 13 is thinned by removing a part of the upper surface by etching for forming the gate electrode CG and the upper electrode TE. In addition, the thickness of the top oxide film 7 in the other regions remains thinner than the thickness of the top oxide film 7 immediately below the upper electrode TE and the gate electrode CG.

  Subsequent steps are performed in substantially the same manner as in the second embodiment, whereby the semiconductor device of the present embodiment shown in FIG. 10 is completed. However, in the present embodiment, the silicide layer 19 is not formed on the sidewall 29 in the step corresponding to the step of FIG.

  That is, after the step shown in FIG. 13, after the exposed ONO film IF is removed, only the MIS transistor formation region 1C is ion-implanted to form the extension region 17 (see FIG. 12), and then the side A wall SW is formed. Thereafter, after the diffusion layers 16 and 18 are formed, a silicide layer 19 is formed on the upper surfaces of the gate electrodes CG and G1, the upper electrode TE, and the lower electrode BE. Subsequently, after the stopper insulating film 20 and the interlayer insulating film 21 are sequentially formed on the semiconductor substrate SB, the contact hole 22 reaching the silicide layer 19 from the upper surface of the interlayer insulating film 21 is formed. Thereafter, a contact plug 23 is embedded in the contact hole 22 and the upper surface of the interlayer insulating film 21 is exposed by CMP. Subsequently, a stopper insulating film 24 and an interlayer insulating film 25 are sequentially formed on the interlayer insulating film 21 and the contact plug 23, and then the stopper insulating film 24 and the interlayer insulating film on the contact plug 23 by a known damascene method. By forming the metal wiring 27 in the wiring groove 26 formed in 25, the semiconductor device of the present embodiment is completed.

  When the same member as that constituting the ONO film IF is used for the side wall 29, the surface of the side wall 29 may be slightly removed in the step of removing the ONO film IF, and the side wall 29 may be slightly reduced. . From the viewpoint of preventing the side wall 29 from becoming small in this way, it is more desirable to use a silicon oxide film as a member of the side wall 29 rather than a silicon nitride film.

  In the manufacturing method of the semiconductor device of the present embodiment, the continuous ONO film IF is formed between the upper electrode TE of the PIP capacitor element PC and the sidewall 29 formed on the side wall of the upper electrode TE and the lower electrode BE. Yes.

  Similarly, a continuous ONO film IF is formed between the gate electrode CG of the MONOS memory Mn and the sidewall 29 formed on the side wall of the gate electrode CG and the semiconductor substrate SB.

  Therefore, the breakdown voltage between the upper electrode TE and the lower electrode BE can be increased as compared with the semiconductor device of the comparative example described with reference to FIG. In addition, the breakdown voltage between the gate electrode CG and the source / drain regions can be increased.

  In the first embodiment, in the step shown in FIG. 4A, a photoresist film is formed using a photomask, and impurities are ion-implanted into the MONOS memory formation region 1A. Further, FIG. Also in the process shown in FIG. 5B, a photoresist film is formed using a photomask, and impurities are ion-implanted into the MONOS memory formation region 1A to form the extension region 15.

  On the other hand, in the manufacturing process of the semiconductor device according to the present embodiment, the extension region 15 is formed in the MONOS memory forming region in the step corresponding to FIG. The manufacturing process is simplified compared to the first embodiment, and one photomask to be used is omitted. For this reason, the manufacturing cost of the semiconductor device can be reduced.

  Similarly to the first embodiment, since the ONO film IF constituting the MONOS memory Mn and the PIP capacitor element PC is the same insulating film formed in the same process, the upper electrode TE and the lower electrode BE The manufacturing process of the semiconductor device can be simplified as compared with the case where the insulating film between them and the ONO film of the MONOS memory Mn are formed as different films in different processes.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is widely used for semiconductor devices having a capacitive element.

1A MONOS memory formation region 1B PIP capacitor element formation region 1C MIS transistor formation region 2 well 3 gate insulating film 3a insulating film 4 polysilicon film 5 bottom oxide film 6 silicon nitride film 7 top oxide film 8 polysilicon film 9 sidewall oxide film 9a Silicon oxide film 10 Side wall 12 Silicon oxide film 13 Silicon nitride film 14 Silicon oxide film 15 Extension region 16 Diffusion layer 17 Extension region 18 Diffusion layer 19 Silicide layer 20 Stopper insulation film 21 Interlayer insulation film 22 Contact hole 23 Contact plug 24 Stopper insulation Film 25 Interlayer insulating film 26 Wiring groove 27 Metal wiring 28 Side wall oxide film 29 Side wall BE Lower electrode CG Gate electrode G1 Gate electrode IF ONO film IFg ONO film Mn MONOS memory SB Semiconductor substrate SW Side wall TE Upper electrode Tn MIS transistor

Claims (17)

A lower electrode formed in a first region on a semiconductor substrate;
A first insulating film formed on the lower electrode;
An upper electrode formed directly on the first insulating film;
An intrinsic semiconductor film formed immediately above the first insulating film and on the side wall of the upper electrode via a second insulating film;
A semiconductor device comprising a capacitor element having A semiconductor device having a nonvolatile memory in a second region on the semiconductor substrate,
The nonvolatile memory is
A laminated film including a bottom potential barrier film formed in the second region, a charge storage film formed on the bottom potential barrier film, and an upper potential barrier film formed on the charge storage film; 3 insulating films;
A gate electrode formed directly on the third insulating film;
The intrinsic semiconductor film formed immediately above the third insulating film and on the side wall of the gate electrode via the second insulating film;
A side wall made of an insulator formed on a side wall of the intrinsic semiconductor film opposite to the side wall in contact with the second insulating film;
Source / drain regions formed on the upper surface of the semiconductor substrate on both sides of the gate electrode;
Have
The intrinsic semiconductor film does not function as a gate of the nonvolatile memory,
The first insulating film is a film in the same layer as the third insulating film, and is a stacked film in which the bottom potential barrier film, the charge storage film, and the upper potential barrier film are sequentially stacked. Item 14. A semiconductor device according to Item 1. A semiconductor device having a nonvolatile memory in a second region on the semiconductor substrate,
The nonvolatile memory is
A laminated film including a bottom potential barrier film formed in the second region, a charge storage film formed on the bottom potential barrier film, and an upper potential barrier film formed on the charge storage film; 3 insulating films;
A gate electrode formed directly on the third insulating film;
The intrinsic semiconductor film formed immediately above the third insulating film and on the side wall of the gate electrode via the second insulating film;
A side wall made of an insulator formed on a side wall of the intrinsic semiconductor film opposite to the side wall in contact with the second insulating film;
Source / drain regions formed on the upper surface of the semiconductor substrate on both sides of a structure including the gate electrode and the intrinsic semiconductor film;
Have
The gate electrode and the intrinsic semiconductor film are electrically connected via a silicide layer formed on the gate electrode and the intrinsic semiconductor film,
The intrinsic semiconductor film functions as a gate of the nonvolatile memory,
The first insulating film is a film in the same layer as the third insulating film, and is a stacked film in which the bottom potential barrier film, the charge storage film, and the upper potential barrier film are sequentially stacked. Item 14. A semiconductor device according to Item 1.   2. The semiconductor device according to claim 1, wherein the upper electrode, the lower electrode, and the intrinsic semiconductor film are each made of a polysilicon film. A semiconductor device having a capacitive element formed in a first region on a semiconductor substrate and a nonvolatile memory formed in a second region,
The capacitive element is
A lower electrode formed in the first region;
A first insulating film formed on the lower electrode;
An upper electrode formed directly on the first insulating film;
A fourth insulating film formed immediately above the first insulating film and on the side wall of the upper electrode via a second insulating film;
A first sidewall made of an insulating film formed on a side wall of the fourth insulating film opposite to the side wall in contact with the second insulating film;
Have
The nonvolatile memory is
A laminated film including a bottom potential barrier film formed in the second region, a charge storage film formed on the bottom potential barrier film, and an upper potential barrier film formed on the charge storage film; 3 insulating films;
A gate electrode formed directly on the third insulating film;
The fourth insulating film formed immediately above the third insulating film and on the side wall of the gate electrode via the second insulating film;
A second sidewall made of an insulating film formed on the side wall of the fourth insulating film opposite to the side wall in contact with the second insulating film;
Source / drain regions formed on the upper surface of the semiconductor substrate on both sides of the gate electrode;
Have
The semiconductor device according to claim 1, wherein the first sidewall and the second sidewall are made of the same layer film and have the same width in a direction along the main surface of the semiconductor substrate. A semiconductor device having a capacitive element formed in a first region on a semiconductor substrate and a field effect transistor formed in a second region,
The capacitive element is
A lower electrode formed in the first region;
A laminated film including a bottom potential barrier film formed on the lower electrode, a charge storage film formed on the bottom potential barrier film, and an upper potential barrier film formed on the charge storage film; 1 insulating film;
An upper electrode formed directly on the first insulating film;
A first sidewall formed immediately above the first insulating film and on the side wall of the upper electrode via a second insulating film;
A second sidewall made of an insulating film formed on the side wall of the first sidewall and opposite to the side wall in contact with the second insulating film;
Have
The field effect transistor is
A fifth insulating film formed in the second region;
A gate electrode formed on the fifth insulating film;
A third sidewall formed on the sidewall of the gate electrode;
Source / drain regions formed on the upper surface of the semiconductor substrate on both sides of the gate electrode;
Have
The semiconductor device, wherein the second sidewall and the third sidewall are made of the same layer and have the same width in a direction along the main surface of the semiconductor substrate.   7. The semiconductor device according to claim 6, wherein the first sidewall is made of a polysilicon film that is an intrinsic semiconductor film.   7. The semiconductor device according to claim 6, wherein the first sidewall is made of an insulating film mainly including a silicon oxide film or a silicon nitride film. A method of manufacturing a semiconductor device having a capacitive element formed in a first region of a main surface of a semiconductor substrate,
(A) forming a first conductive film on the semiconductor substrate in the first region via a first insulating film;
(B) processing the first conductive film to form a lower electrode made of the first conductive film in the first region;
(C) forming a second insulating film on the lower electrode;
(D) forming a second conductive film on the entire main surface of the semiconductor substrate;
(E) processing the second conductive film in the first region to form an upper electrode made of the second conductive film directly on the lower electrode;
(F) heat-treating the semiconductor substrate to form a sidewall oxide film on the sidewall of the upper electrode;
(G) After forming an intrinsic semiconductor film on the entire main surface of the semiconductor substrate, the intrinsic semiconductor film is processed to form the sidewall oxide film on the sidewall of the upper electrode directly above the lower electrode. Forming a first sidewall made of the intrinsic semiconductor film via
(H) The exposed second insulating film is removed using the upper electrode, the sidewall oxide film, and the first sidewall as a mask, and the lower electrode, the second insulating film, the upper electrode, and the first electrode are removed. Forming the capacitive element having one sidewall;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device having a nonvolatile memory in a second region on the semiconductor substrate,
In the step (b), the first conductive film in the second region is removed,
In the step (c), a bottom potential barrier film, a charge storage film, and an upper potential barrier film are sequentially formed on the lower electrode in the first region and the semiconductor substrate in the second region, and the bottom potential barrier is formed. Forming the second insulating film comprising a film, the charge storage film and the upper potential barrier film;
In the step (e), a gate electrode is formed by processing the second conductive film on the second insulating film in the second region,
After the step (e) and before the step (f), impurities are introduced into the main surface of the semiconductor substrate in the second region, and a semiconductor is formed on the main surface of the semiconductor substrate on both sides of the gate electrode. Forming a region,
In the step (g), by processing the intrinsic semiconductor film in the second region, the first sidewall made of the intrinsic semiconductor film is formed on the sidewall of the gate electrode via the sidewall oxide film,
In the step (h), the exposed second insulating film is removed using the gate electrode, the sidewall oxide film, and the first sidewall in the second region as a mask,
further,
(I1) After the step (h), forming a second sidewall made of an insulating film on the sidewall of the first sidewall opposite to the sidewall in contact with the sidewall oxide film;
(J1) The same conductivity type as the semiconductor region on the main surface of the semiconductor substrate in the second region using the gate electrode, the sidewall oxide film, the first sidewall and the second sidewall in the second region as a mask Is introduced at a higher concentration than the semiconductor region, and a diffusion layer is formed on the main surface of the semiconductor substrate, whereby the second insulating film, the upper electrode, the first sidewall, the semiconductor region, and the Forming the non-volatile memory having a diffusion layer;
Have
The method of manufacturing a semiconductor device according to claim 9, wherein the first sidewall does not function as a gate of the nonvolatile memory.   11. The step (j1) is characterized in that the diffusion layer is formed by introducing an impurity into the second region in a state where the first sidewall of the first region is covered with a photoresist film. The manufacturing method of the semiconductor device of description.   11. The method of manufacturing a semiconductor device according to claim 10, wherein the upper electrode, the lower electrode, and the first sidewall are made of a polysilicon film. A method of manufacturing a semiconductor device having a nonvolatile memory in a second region,
In the step (b), the first conductive film in the second region is removed,
In the step (c), a bottom potential barrier film, a charge storage film, and an upper potential barrier film are sequentially formed on the lower electrode in the first region and the semiconductor substrate in the second region, and the bottom potential barrier is formed. Forming the second insulating film comprising a film, the charge storage film and the upper potential barrier film;
In the step (e), a gate electrode is formed by processing the second conductive film on the second insulating film in the second region,
In the step (g), by processing the intrinsic semiconductor film in the second region, the first sidewall made of the intrinsic semiconductor film is formed on the sidewall of the gate electrode via the sidewall oxide film,
In the step (h), the exposed second insulating film is removed using the gate electrode, the sidewall oxide film, and the first sidewall in the second region as a mask,
further,
(H2) After the step (h), impurities are introduced into the main surface of the semiconductor substrate in the second region using the gate electrode and the first sidewall as a mask, and the gate electrode and the first sidewall are Forming a semiconductor region on the main surface of the semiconductor substrate on both sides of the structure,
(I2) after the step (h2), forming a second sidewall made of an insulating film on the side wall of the first sidewall opposite to the side wall in contact with the sidewall oxide film;
(J2) The same conductivity type as the semiconductor region on the main surface of the semiconductor substrate in the second region using the gate electrode, the sidewall oxide film, the first sidewall and the second sidewall in the second region as a mask Is introduced at a higher concentration than the semiconductor region, and a diffusion layer is formed on the main surface of the semiconductor substrate, whereby the second insulating film, the upper electrode, the first sidewall, the semiconductor region, and the Forming the non-volatile memory having a diffusion layer;
(K2) A silicide layer is formed on each of the diffusion layer, the first sidewall, the gate electrode, and the upper electrode, and the first sidewall and the gate in the second region are interposed via the silicide layer. Electrically connecting the electrodes;
Have
The method of manufacturing a semiconductor device according to claim 9, wherein the first sidewall functions as a gate of the nonvolatile memory. A method for manufacturing a semiconductor device, comprising: a capacitive element formed in a first region of a main surface of a semiconductor substrate; and a nonvolatile memory formed in a second region of the main surface of the semiconductor substrate,
(A) forming a first conductive film on the semiconductor substrate in the first region and the second region via a first insulating film;
(B) processing the first conductive film to form a lower electrode made of the first conductive film in the first region, and removing the first conductive film in the second region;
(C) A potential barrier film, a charge storage film, and a potential barrier film are sequentially formed on the semiconductor substrate in the second region and the lower electrode in the first region, and the potential barrier film, the charge storage film, and the potential barrier film are formed. Forming a second insulating film comprising:
(D) forming a second conductive film on the second insulating film in the first region and the second region;
(E) processing the second conductive film in the first region to form an upper electrode made of the second conductive film directly on the lower electrode, and processing the second conductive film in the second region; Forming a gate electrode;
(F) introducing an impurity into the main surface of the semiconductor substrate in the second region, and forming a semiconductor region on the main surface of the semiconductor substrate on both sides of the gate electrode;
(G) A third insulating film is formed on the entire main surface of the semiconductor substrate, and then the third insulating film is processed, so that the third insulating film is formed directly on the side wall of the upper electrode directly above the lower electrode. Forming a first sidewall made of an insulating film, and forming a first sidewall made of the third insulating film on a side wall of the gate electrode;
(H) The exposed second insulating film is removed using the upper electrode, the gate electrode, and the first sidewall as a mask, and the lower electrode, the second insulating film, the upper electrode, and the first electrode are removed. Forming the capacitive element having a sidewall;
(I) after the step (h), forming a second sidewall made of an insulating film on the side wall of the first sidewall opposite to the side wall in contact with the upper electrode or the gate electrode; ,
(J) Impurities having the same conductivity type as the semiconductor region are formed on the main surface of the semiconductor substrate in the second region using the gate electrode, the first sidewall, and the second sidewall in the second region as a mask. Introducing at a higher concentration than the region, and forming a diffusion layer on the main surface of the semiconductor substrate, the second insulating film, the upper electrode, the first sidewall, the semiconductor region, and the diffusion layer Forming a non-volatile memory;
A method for manufacturing a semiconductor device, comprising: A method for manufacturing a semiconductor device, comprising: a capacitive element formed in a first region of a main surface of a semiconductor substrate; and a field effect transistor formed in a second region of the main surface of the semiconductor substrate,
(A) forming a first conductive film on the semiconductor substrate in the first region and the second region via a first insulating film;
(B) processing the first conductive film in the first region, forming a lower electrode made of the first conductive film, and leaving the first conductive film in the second region;
(C) A potential barrier film, a charge storage film, and a potential barrier film are sequentially formed on the entire main surface of the semiconductor substrate, and a second insulating film including the potential barrier film, the charge storage film, and the potential barrier film is formed. Process,
(D) forming a second conductive film on the entire main surface of the semiconductor substrate;
(E) Process of processing the second conductive film in the first region to form an upper electrode made of the second conductive film directly on the lower electrode, and removing the second conductive film in the second region When,
(F) heat-treating the semiconductor substrate to form a sidewall oxide film on the sidewall of the upper electrode;
(G) Forming a film on the entire main surface of the semiconductor substrate, and then processing the film, so that the film is directly above the lower electrode and on the side wall of the upper electrode via the side wall oxide film. Forming a first sidewall comprising:
(H) The exposed second insulating film is removed using the upper electrode, the sidewall oxide film, and the first sidewall as a mask, and the lower electrode, the second insulating film, the upper electrode, and the first electrode are removed. Forming the capacitive element having one sidewall and removing the second insulating film in the second region;
(I) forming a gate electrode made of the first conductive film by processing the first conductive film in the second region in a state where the first region is covered with a photoresist film;
(J) Impurities are introduced into the main surface of the semiconductor substrate in the second region using the gate electrode as a mask in a state where the first region is covered with a photoresist film, and the main regions of the semiconductor substrate on both sides of the gate electrode are introduced. Forming a semiconductor region on the surface;
(K) Forming an insulating film on the entire main surface of the semiconductor substrate, and processing the insulating film, thereby forming a side wall of the first side wall opposite to the side wall in contact with the side wall oxide film. And forming a second sidewall made of the insulating film on each of the sidewalls of the gate electrode;
(L) Same as the semiconductor region on the main surface of the semiconductor substrate in the second region with the gate electrode and the second sidewall in the second region as a mask with the first region covered with a photoresist film The field effect transistor having the gate electrode, the semiconductor region, and the diffusion layer is formed by introducing a conductivity type impurity at a higher concentration than the semiconductor region and forming a diffusion layer on the main surface of the semiconductor substrate. And a process of
A method for manufacturing a semiconductor device, comprising:   16. The method of manufacturing a semiconductor device according to claim 15, wherein the first sidewall is made of a polysilicon film which is an intrinsic semiconductor film.   16. The method of manufacturing a semiconductor device according to claim 15, wherein the first sidewall is made of an insulating film mainly including a silicon oxide film or a silicon nitride film.

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