JP2003060071A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device provided with an embedded impurity layer for an α ray soft error measure and provided with an SRAM capable of reducing taps for grounding for each cell. SOLUTION: An embedded n-type layer B-N is disposed as an intermediate layer on a p-type semiconductor substrate P-sub. On the n-type layer B-N, a p-type well region PWEL is uniformly provided. On the n-type layer B-N, the p-type substrate P-sub is present for prescribed thickness, and the p-type well region PWEL and an n-type well region NWEL are provided in equal depth. A CMOS circuit is constituted of respective wells. A power supply voltage VDD is supplied to the source of a P channel MOS transistor Qp and the well region NWEL. Also, since the well region PWEL is connected to the p-type substrate P-sub, it does not float. Thus, for supply of a ground potential VSS to the well region PWEL, the number of the taps is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device which is required to be highly integrated including an integrated circuit formed in a well region by disposing an impurity-embedded layer in a substrate as a countermeasure against .alpha. Regarding

[0002]

2. Description of the Related Art When radiation enters a semiconductor substrate that constitutes a semiconductor integrated circuit, electron-hole pairs are generated in the process in which incident particles lose energy due to interaction with substrate atoms. The signal generated by the generated electrons or holes becomes noise, which may cause malfunction of the semiconductor device.

In particular, α rays generate many electron-hole pairs in the substrate. When α rays enter silicon, the range is about 25 μm, and 1.4 × 10 ⁶ electron-hole pairs are generated along the locus. When the generated minority carriers flow into the diffusion layer, the potential of the diffusion layer changes, causing a soft error.

For example, when an N ⁺ diffusion layer is formed on a P type substrate, the minority carrier collecting process is as follows. All the minority carriers (electrons) generated in the depletion layer flow into the diffusion layer due to the electric field applied in the depletion layer. Minority carriers generated in the neutral region of the substrate spread inside the substrate by diffusion. Of the diffused minority carriers, those that have reached the depletion layer flow into the diffusion layer, and the others recombine with holes in the substrate or flow into the substrate-side electrode.

Such a phenomenon causes an α ray soft error in the semiconductor memory circuit. That is, when α rays emitted from a small amount of radioactive elements contained in the packaging material or the wiring metal enter the chip, a large number of electron-hole pairs are generated, and the stored information is destroyed.

Therefore, a technique for providing a buried impurity layer is known as a countermeasure against α-ray soft error. That is, a buried impurity layer is provided in the entire lower portion of the element forming the memory cell array to prevent minority carriers generated at the time of incidence of α rays from flowing into the element region.

Of semiconductor memory circuits, SRAM is more difficult to integrate than DRAM (dynamic RAM).
Also in (static type random access memory), high integration is being promoted. The SRAM has an advantage in high-speed reading, and is suitable for a cache memory of a system such as a portable device in which the number of parts is limited, a personal computer, a workstation, or the like. This SRAM
In many cases, a buried impurity layer is provided as a countermeasure against α-ray soft error.

As is well known, a unit circuit (memory cell) for storing 1-bit information of SRAM has a flip-flop circuit as a basic structure, and a CMOS circuit is indispensable. A memory cell is formed by providing an N-type well and a P-type well on the substrate.

FIGS. 5A and 5B are SRAMs, respectively.
Of the memory cell region of FIG.
(B) is sectional drawing which follows the BB line of (a). Figure 5
As shown in (a), N well regions NWEL and P well regions PWEL are arranged alternately. The hatched portion is a region used for one memory cell, and each well and element are insulated and isolated by trench isolation (not shown) or the like. Memory cells (not shown) are integrated in an array with the shaded area as a unit area.

As shown in FIG. 5B, NWEL, PW
A buried impurity layer, here an N-type layer BN, is provided under each well region of the EL. The N-type layer B-N is formed by forming a deep well in the P-type substrate P-sub, for example. The N-type layer B-N is laid, for example, in one entire memory cell block (broken line in FIG. 5A).
This prevents the minority carriers generated upon incidence of α rays from flowing into the element structure in the well.

FIG. 6 is a circuit diagram showing an example of an SRAM memory cell. A flip-flop FF is formed by connecting the inputs and outputs of the CMOS inverters each including a P-channel MOS transistor Qp1 (Qp2) and an N-channel MOS transistor Qn1 (Qn2) between the power supply and the ground.
1 and FF2 are configured.

The selection transistor Qs is a word line WL.
The potential control contributes to the transmission of each signal (write or read data) on the bit lines BLL and BLR. The selection transistor Qs may be a P-channel MOS transistor or an N-channel MOS transistor.

With such a structure, the SRAM cell maintains the stored information continuously as long as the power supply voltage VDD is applied, and the refresh operation is unnecessary. CMO
With the S circuit, the current consumption during standby is extremely small and a high-speed access time is realized.

The P channel MOS transistor Qp
1, Qp2 and N-channel MOS transistor Qn1,
Qn2 is formed in a layout according to the design, using the N well region NWEL and the P well region NWEL in FIGS. 5A and 5B as element regions, respectively. The selection transistor Qs is also formed in a layout according to the design, using either the NWEL or PWEL as the element region.

In the SRAM cell having the above-mentioned structure, the power supply voltage VDD is normally the N-well region NWEL and the P-channel MOS transistor Qp1 formed on it.
It is supplied to the source diffusion layer of Qp2. Power supply voltage VDD
Are transmitted through the vias from the power supply lines respectively connected to the power supply pads (not shown) and arranged at predetermined positions. In addition, the N-type layer B-N shown in FIG.
It is electrically connected to WEL and supplied with NWEL potential).

On the other hand, the ground potential VSS is the P well region PW.
It is connected to the EL and the drain diffusion layers of the N-channel MOS transistors Qn1 and Qn2 formed on the EL. Further, in the P well region PWEL, P ⁺ taps of the high concentration P type region are taken for each cell (or every predetermined distance). P
Each ⁺ tap is connected to a second polysilicon (or a metal wiring) arranged at a predetermined position, and is connected to a ground pad (not shown).

[0017]

SUMMARY OF THE INVENTION S having the above-mentioned configuration
In the RAM cell, a buried N-type layer B-N layer is uniformly provided as a countermeasure against α-ray soft error. For this reason, it is necessary to dispose P ⁺ taps for setting the P well region to the ground potential in each cell or at a predetermined distance so that the P well region does not float in each cell. The provision of P ⁺ taps is one of the factors that hinder the reduction of cell area.

The present invention has been made in consideration of the above-mentioned circumstances, and a semiconductor having an SRAM capable of reducing the grounding tap for each cell while providing an embedded impurity layer against α-ray soft error. An attempt is made to provide an integrated circuit device.

[Means for Solving the Problems]

The semiconductor integrated circuit device according to the present invention is the first
A second conductivity type buried impurity layer provided as an intermediate layer on the conductivity type semiconductor substrate, and a first conductivity type well region provided at a predetermined depth in the semiconductor substrate without contacting the buried impurity layer. And a second conductive type well region provided at a predetermined depth in the semiconductor substrate without contacting the buried impurity layer, and a device in each of the first conductive type well region and the second conductive type well region. And an integrated circuit element related to each other are provided.

According to the semiconductor integrated circuit device of the present invention, the well regions of both the first conductivity type and the second conductivity type are formed on the first conductivity type semiconductor substrate without contacting the buried impurity layer. Provided at the depth. As a result, it is possible to prevent the well region of the first conductivity type from floating while the second conductivity type buried impurity layer for soft error countermeasures is provided. As a result, the well region of the first conductivity type can be entirely biased with reference to the semiconductor substrate of the first conductivity type even if the number of taps is reduced.

Further, in the semiconductor integrated circuit device according to the present invention, the second conductivity type buried impurity layer provided as an intermediate layer on the first conductivity type semiconductor substrate and the first conductivity type buried impurity layer thereon. A first conductivity type well region and a second conductivity type well region provided in the semiconductor substrate on the first conductivity type buried impurity layer;
An integrated circuit element in which elements are provided in the well region of the conductivity type and the well region of the second conductivity type and are related to each other.

According to the semiconductor integrated circuit device of the present invention, the buried impurity layer of the first conductivity type is formed immediately below the well regions of both the first conductivity type and the second conductivity type, and the buried impurity layer of the first conductivity type is formed. A second conductivity type buried impurity layer is disposed below the layer. As a result, the first conductivity type well region is prevented from floating by the reference bias of the buried impurity layer while the second conductivity type buried impurity layer for soft error countermeasures is provided, which contributes to the reduction in the number of taps.
Further, the resistance of the first-conductivity-type buried impurity layer and the first-conductivity-type well region can be reduced, and it becomes difficult to raise the reference potential. This contributes to improving the stability of circuit characteristics.

The integrated circuit elements according to the former and latter inventions are characterized by including a CMOS type circuit. Further, a memory circuit having a flip-flop type memory cell is formed. In the memory cell configured by the flip-flop, the tap of the reference potential of the CMOS type circuit can be reduced, and the configuration for the soft error countermeasure (the second conductivity type embedded impurity layer) is maintained.

[0024]

FIG. 1 is a sectional view showing a main part of a semiconductor integrated circuit device according to a first embodiment of the present invention. P
An N-type buried impurity, here a buried N-type layer B-N, is provided as an intermediate layer on the semiconductor substrate P-sub of the type.
The N-type layer B-N is formed by forming a deep well in the P-type substrate P-sub, for example. A P-type substrate P-sub is present on the N-type layer B-N with a predetermined thickness, and a P-type well region P is formed.
WEL and N-type well regions NWEL are provided at the same depth. That is, the buried N-type layer B-N does not contact the well regions PWEL and NWEL and has a depth such that the region of the P-type substrate P-sub enters between the well regions PWEL and NWEL. It is formed.

Elements are provided in each of the well regions PWEL and NWEL, and integrated circuit elements related to each other are provided. At least an N-channel MOS transistor Qn and a P-channel MOS transistor Qp are formed to form a CMOS circuit.

In these CMOS circuits, the power supply voltage VDD is supplied to the source of the P-channel MOS transistor Qp and the well region NWEL. The ground potential VSS is N
Source and well region P of channel MOS transistor
Supplied to WEL.

At this time, since the well region PWEL is connected to the P-type substrate P-sub, it does not float. Therefore, the number of taps for supplying the ground potential VSS, which has been conventionally provided, can be significantly reduced. A high-concentration region (not shown) that biases the P-type substrate P-sub may be provided at a specific position around the well region PWEL. That is, the P ⁺ tap may be provided at a predetermined position on the P-type substrate P-sub.

The power supply voltage VDD is transmitted via a via from a power supply line connected to a power supply pad (not shown) and arranged at a predetermined position. The buried N-type layer B
-N is a predetermined outer peripheral portion of the CMOS circuit integrated area (not shown)
It is sufficient if the bias of the power supply voltage VDD is applied at.

According to the above structure, the well regions PWEL and NWEL are provided with a predetermined depth on the P-type substrate P-sub without making contact with the buried N-type layer B-N.
As a result, it is possible to prevent the well region PWEL from floating while the buried N-type layer B-N for soft error measures is provided. As a result, the well region PWE
Even if the number of taps is reduced, L can be entirely reference biased by the P-type substrate P-sub. This contributes to suppressing the latch-up and reducing the element area.

FIG. 2 is a sectional view showing a main part of a semiconductor integrated circuit device according to the second embodiment of the present invention. A buried impurity, here a buried N-type layer B-N, and a buried P-type layer B-P are disposed on the P-type semiconductor substrate P-sub as an intermediate layer. The both buried layers B-N and B-P are formed by forming deep wells at a predetermined depth in the P-type substrate P-sub, for example.

A P-type well region PWEL and an N-type well region NWEL are provided in the substrate on the buried P-type layer BP at the same depth. The well region PWEL is in contact with at least the buried P-type layer BP.

An element is provided in each of the well regions PWEL and NWEL, and integrated circuit elements related to each other are provided. At least an N-channel MOS transistor Qn and a P-channel MOS transistor Qp are formed to form a CMOS circuit.

In these CMOS circuits, the power supply voltage VDD is supplied to the source of the P-channel MOS transistor Qp and the well region NWEL. The ground potential VSS is N
Source and well region P of channel MOS transistor
Supplied to WEL.

At this time, since the well region PWEL is connected to the P-type buried layer BP, it does not become a floating state. Therefore, the number of taps for supplying the ground potential VSS, which has been conventionally provided, can be significantly reduced. A P-type buried layer BP is formed at a specific position around the well region PWEL.
A high-concentration region (not shown) may be provided for biasing. That is, P ⁺ taps may be provided at predetermined locations in the P-type buried layer BP.

The power supply voltage VDD is transmitted via a via from a power supply line connected to a power supply pad (not shown) and arranged at a predetermined position. The buried N-type layer B
-N is a predetermined outer peripheral portion of the CMOS circuit integrated area (not shown)
It is sufficient if the bias of the power supply voltage VDD is applied at.

According to the above structure, the well regions PWEL and NWEL are provided with a predetermined depth so as to be in contact with the buried P-type layer BP while arranging the buried N-type layer B-N. Become. As a result, the well region PWE remains with the buried N-type layer B-N provided as a soft error countermeasure.
Measures to prevent floating of L can be taken. As a result, the well region PWEL is embedded P even if the number of taps is reduced.
The reference bias can be entirely applied to the mold layers BP. This allows
It contributes to the reduction of the element area. In addition, the embedded P-type layer B
Since -P and the well region PWEL have low resistance, it is difficult to raise the reference potential. This contributes to improving the stability of circuit characteristics.

FIG. 3 is a characteristic diagram showing an example of the concentration profile in the depth direction in the structure of FIG. Channel dope region for MOS transistors, punch through
There are stoppers and channel cut regions that promote separation characteristics. The well region PWEL and the P-type layer BP have the same concentration profile.

FIG. 4 is a circuit diagram showing an example of an SRAM memory cell constructed on the configuration of the present invention according to FIG. P-channel MOS transistor Qp1 (Q
p2), N-channel MOS transistor Qn1 (Qn
The flip-flops FF1 and FF2 are configured by connecting the inputs and outputs of the CMOS inverters configured in 2).

The selection transistor Qs is a word line WL.
The potential control contributes to the transmission of complementary signals (write or read data) on the bit lines BLL and BLR. The selection transistor Qs is a P-channel MOS transistor or an N-channel MOS transistor.
It may be composed of transistors.

With such a configuration, the SRAM cell maintains the stored information continuously as long as the power supply voltage VDD is applied, and the refresh operation is unnecessary. CMO
With the S circuit, the current consumption during standby is extremely small and a high-speed access time is realized.

The P-channel MOS transistor Qp
1, Qp2 and N-channel MOS transistor Qn1,
Qn2 is formed in a layout according to the design using the N well region NWEL and the P well region NWEL in FIG. 2 as element regions, respectively. The selection transistor Qs is also formed in a layout according to the design, using either the NWEL or PWEL as the element region.

In the SRAM cell having the above-mentioned structure, the power supply voltage VDD is usually the N-well region NWEL and the P-channel MOS transistor Qp1 formed on it.
It is supplied to the source diffusion layer of Qp2. Power supply voltage VDD
Are transmitted through the vias from the power supply lines respectively connected to the power supply pads (not shown) and arranged at predetermined positions. The buried N-type layer B-N (see FIG. 2) is also formed by, for example, SRA.
Power supply voltage VD from the outer peripheral portion (not shown) of the M cell block
The bias of D is taken.

On the other hand, the ground potential VSS is the P well region PW.
It is connected to the EL and the drain diffusion layers of the N-channel MOS transistors Qn1 and Qn2 formed on the EL. Here, the ground potential VSS is supplied to the P well region PWEL as follows.
Since it can be obtained from the buried P-type layer B-P immediately below the well region PWEL, it is not necessary to provide a tap region for each P well region PWEL, and a minimum number of taps may be provided.
That is, the ground potential of each cell can be compensated by the P ⁺ tap provided in the P-type layer B-P.

According to the configuration of each of the above-mentioned embodiments, regarding the SRAM cell block in which the embedded N-type layer B-N layer is uniformly laid to prevent the α-ray soft error, the P-well region PWEL of each cell is grounded. The number of potential VSS supply taps can be significantly reduced. As a result, the reference potential (ground potential) regarding the memory cell array can be collectively obtained around the cell block while providing the embedded impurity layer against the soft error. This contributes to the reduction of the area of the SRAM cell.

[0045]

As described above, according to the present invention, immediately below the well regions of both the first conductivity type and the second conductivity type, a semiconductor substrate of the first conductivity type is provided between the well regions, or the first conductivity type semiconductor substrate is provided. It is used as a buried impurity layer of the mold. As a result, it is possible to prevent the well region of the first conductivity type from floating while the second conductivity type buried impurity layer for soft error countermeasures is provided. Accordingly, the well region of the first conductivity type can be entirely biased as a reference even if the number of taps is reduced.
As a result, it is possible to provide a semiconductor integrated circuit device having an SRAM in which a grounding tap for each cell can be omitted while providing a buried impurity layer as a countermeasure against α-ray soft error.

[Brief description of drawings]

FIG. 1 is a sectional view showing a main part of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a main part of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 3 is a characteristic diagram showing an example of a concentration profile in the depth direction in the configuration of FIG.

4 is an SRAM configured on the configuration of the present invention according to FIG. 2;
It is a circuit diagram which shows an example of a memory cell.

5A and 5B respectively show a memory cell region of an SRAM, FIG. 5A is a plan view of a well, and FIG. 5B is a sectional view taken along line BB of FIG.

FIG. 6 is a circuit diagram showing an example of an SRAM memory cell.

[Explanation of symbols]

P-sub ... P type semiconductor substrate B-N ... Embedded N-type layer B-P ... Embedded P-type layer PWEL ... P-type well region NWEL ... N-type well region Qp, Qp1, Qp2 ... P-channel MOS transistor Qn, Qn1, Qn2 ... N-channel MOS transistor Qs ... Transistor for selection FF1, FF2 ... Flip-flop VDD ... Power supply voltage VSS ... Ground potential

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F048 AA01 AA03 AA06 AA09 AB01                       AB04 AC03 BA03 BA05 BA07                       BA13 BB05 BC06 BE01 BE03                       BE05 BE09 BG14                 5F083 BS17 BS27 GA09 GA18 HA01                       HA10 NA01

Claims (6)

[Claims] 1. An embedded impurity layer of a second conductivity type provided as an intermediate layer on a semiconductor substrate of a first conductivity type, and a predetermined depth provided on the semiconductor substrate without contacting the embedded impurity layer. A first conductive type well region, a second conductive type well region provided at a predetermined depth in the semiconductor substrate without contacting the buried impurity layer, the first conductive type well region and the second conductive type A semiconductor integrated circuit device comprising: an element provided in each well region of the mold and an interrelated integrated circuit element. 2. The semiconductor integrated circuit device according to claim 1, wherein the integrated circuit element includes a CMOS type circuit. 3. The semiconductor integrated circuit device according to claim 1, wherein the integrated circuit element includes a CMOS type circuit and constitutes a memory circuit having a flip-flop type memory cell. 4. A second conductivity type buried impurity layer provided as an intermediate layer on a first conductivity type semiconductor substrate, a first conductivity type buried impurity layer thereon, and the first conductivity type buried impurity layer. An element is provided in each of the first conductivity type well region and the second conductivity type well region and the first conductivity type well region and the second conductivity type well region provided on the semiconductor substrate on the layer; And an integrated circuit element related to the semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 4, wherein the integrated circuit element includes a CMOS type circuit. 6. The semiconductor integrated circuit device according to claim 4, wherein the integrated circuit element includes a CMOS type circuit and constitutes a memory circuit having a flip-flop type memory cell.