JP2014116765A - Image reading device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image reading device having a CCD line sensor which minimizes deterioration in processing performance other than line gap compensation, when a memory band of SDRAM which is used for the line gap compensation is crowded.SOLUTION: An image reading device 1 has: a document reading section for reading a document using a CCD line sensor 11 having a plurality of colors; an SDRAM 18; a line gap compensation section 14 for performing line gap compensation using the SDRAM 18; a determination section 16 for determining whether or not a memory band of the SDRAM 18 is crowded; and an SRAM 19. When the determination section 16 determines that the memory band of the SDRAM 18 is crowded, the line gap compensation section 14 temporarily stores a part or all of data of each color which is obtained by reading in the document reading section in the SRAM 19 instead of the SDRAM 18, and line gap compensation is performed to each color data stored in the SDRAM 18 or the SRAM 19 to be outputted.

Description

  The present invention relates to an image reading apparatus, and more specifically, reads a document using a multi-color CCD (Charge Coupled Device) line sensor with a line gap, and uses a delay memory to read the line. The present invention relates to an image reading apparatus that corrects and outputs a gap.

  2. Description of the Related Art Conventionally, image reading apparatuses include an apparatus that reads (scans) a document using a CCD line sensor. For example, Patent Document 1 discloses an image reading apparatus that has a line gap correction function and thins out read data when the scan speed is low so as not to increase the capacity of a memory used for line gap correction. Has been.

  In addition, Patent Document 2 discloses an image reading apparatus in which a plurality of CCD line sensors are arranged and scanned at a scanning speed according to the line gap. Patent Document 3 discloses a technique for correcting a color shift within one line.

  Further, in Patent Document 4, a line gap is corrected by a delay using a memory, and shading correction is performed on image data obtained by reading a document based on shading correction data obtained by reading a reference white plate. A possible image reading device is disclosed. In this image reading apparatus, the image data and the shading correction data are accurately obtained by switching the image path between when reading a document placed on a platen and when reading a document sent by an automatic document feeder. Corresponds.

JP 2011-24140 A JP 2002-16762 A Japanese Patent Laid-Open No. 11-308449 JP 2006-14214 A

  By the way, as a memory used for line gap correction, although it is slower than an SRAM (Static Random Access Memory) or the like, the price is cheap, and an SDRAM (Synchronous Dynamic Random Access Memory) is generally adopted. With the unification of memories accompanying the integration of the control unit of the image reading apparatus into one chip, this SDRAM is increasingly used for processes other than line gap correction. Here, the scan process is generally executed with priority over other processes, and the other processes are interrupted at the start of the scan process depending on the memory usage.

  In recent years, with the increase in scanning speed, resolution, and functionality, the memory bandwidth of the memory used for line gap correction tends to become congested, and the performance of other processing during scanning processing becomes increasingly slower. End up. Therefore, a means for reducing the congestion of the memory bandwidth of the SDRAM used for line gap correction is desired.

  However, the image reading apparatus described in Patent Document 1 only saves the memory use capacity by thinning out data, and cannot cope with high resolution, and the memory bandwidth is not reduced without reducing the data. It does not relieve. Note that Patent Documents 2 to 4 do not describe a technique for reducing the congestion of the memory band.

  The present invention has been made in view of the above-described actual situation, and the object of the present invention is when the memory bandwidth of the SDRAM used for line gap correction is congested in an image reading apparatus having a CCD line sensor. The purpose is to minimize the decrease in performance of processing other than line gap correction.

  In order to solve the above-described problem, the first technical means of the present invention uses a plurality of color CCD (Charge Coupled Device) line sensors to read a document in a state where a line gap is provided for each color reading line. A document reading unit, SDRAM (Synchronous Dynamic Random Access Memory), and data of each color obtained by reading by the document reading unit are temporarily stored in the SDRAM, and line gap correction is performed on the stored data of each color A line gap correction unit that outputs in a state of performing a determination, a determination unit that determines whether the memory bandwidth of the SDRAM is congested, an SRAM (Static Random Access Memory), The line gap correction unit is obtained by reading with the document reading unit when it is determined that the determination unit is congested. Further, a part or all of the data of each color is temporarily stored in the SRAM instead of the SDRAM, and the data of each color stored in the SDRAM or the SRAM is output with the line gap corrected. It is characterized by that.

  According to a second technical means of the present invention, in the first technical means, the determination unit determines a degree of congestion of the memory bandwidth of the SDRAM, and the line gap correction unit is determined by the determination unit. Based on the degree of congestion, the proportion of data temporarily stored in the SRAM increases as the congestion is increased.

  According to a third technical means of the present invention, in the first or second technical means, the line gap correction unit accesses the SRAM in an access unit to the SDRAM.

  According to a fourth technical means of the present invention, in any one of the first to third technical means, the line gap correction unit applies the data to each SDRAM among the data of each color obtained by reading by the original reading unit. The color data having the shortest time required from writing to reading is preferentially stored in the SRAM with priority.

  According to the present invention, in an image reading apparatus having a CCD line sensor, when the memory bandwidth of the SDRAM used for line gap correction is congested, the performance degradation of processes other than line gap correction is minimized. Can do.

1 is a block diagram illustrating a configuration example of an image reading apparatus according to the present invention. It is a schematic diagram showing an example of a document reading mechanism that reads a document with a CCD line sensor. FIG. 2 is a flowchart for explaining an example of a writing process among the line gap correction processes executed by the image reading apparatus of FIG. 1. FIG. 4 is a diagram showing a specific example of the writing process of FIG. 3 in a case where the CCD line sensor has a line gap of two lines between R and G and between G and B, and is a diagram showing an example of an SDRAM memory map. . FIG. 5 is a diagram for explaining an example of an SRAM history memory in the specific example of FIG. 4. FIG. 5 is a diagram illustrating an example of an SRAM memory map in the specific example of FIG. 4. FIG. 2 is a flowchart for explaining an example of a reading process among the line gap correction processes executed by the image reading apparatus of FIG. 1. FIG. 4 is a flowchart for explaining an example of a memory band congestion determination process in the writing process of FIG. 3. FIG. 2 is a diagram illustrating an example of mounting an SDRAM in the image processing apparatus of FIG. 1. FIG. 10 is a timing diagram for explaining the number of Write / Read cycles of the SDRAM of FIG. 9. It is a figure which shows an example of the access request table | surface of SDRAM of FIG. FIG. 4 is a flowchart for explaining an example of a writing color determination process in the writing process of FIG. 3. FIG. 5 is a diagram for explaining another example of the SRAM history memory in the specific example of FIG. 4. It is a figure which shows an example of the memory map of SDRAM used for the writing color determination process of FIG. It is a figure which shows an example of the memory map of SRAM used for the writing color determination process of FIG. It is a figure which shows the other example of the memory map of SRAM used for the writing color determination process of FIG. It is a figure which shows the other example of the memory map of SRAM used for the writing color determination process of FIG.

  FIG. 1 is a block diagram illustrating a configuration example of an image reading apparatus according to the present invention. FIG. 2 is a schematic diagram showing an example of a document reading mechanism that reads a document with a CCD line sensor, and is a diagram for explaining the principle that a line gap occurs in an image reading apparatus equipped with a CCD line sensor.

  As illustrated in FIG. 1, the image reading apparatus 1 according to the present invention includes a document reading unit having a CCD line sensor unit 11, a line gap correction unit 14, and an SDRAM 18. The CCD line sensor unit 11 has a plurality of color CCD line sensors so that a plurality of different colors can be read. Each of the CCD line sensors for each color has a plurality of light receiving elements (imaging elements) to which corresponding color filters are attached arranged in the main scanning direction, and the data for one line (corresponding to the plurality of light receiving elements) Color image data) to be acquired.

  As the plurality of colors, three colors of R, G, and B are generally adopted, and such examples are given below, but other combinations of colors may be adopted. In the CCD line sensor unit 11 illustrated in FIG. 2, the CCD line sensors 11r, 11g, and 11b for the three colors R, G, and B are spaced apart in the direction (sub-scanning direction) perpendicular to the longitudinal direction (main scanning direction). Opened up and arranged.

  As illustrated in FIG. 2, the document reading unit includes the CCD line sensors 11r, 11g, and 11b, the carriage 31 on which the light source 32 and the mirror 33 are mounted, the lens 34, and the document table on which the document P is placed and an automatic document. It consists of a feeding device (not shown).

  With such a configuration, in the document reading unit, the light irradiated to the document P from the light source 32 is reflected by the reading lines Lr, Lg, and Lb including the points 35r, 35g, and 35b on the lower surface of the document P, and reflected by each line. Light enters the CCD line sensors 11r, 11g, and 11b through the mirror 33 and the lens 34, respectively. As a result, the CCD line sensors 11r, 11g, and 11b acquire image data for one line for the corresponding colors.

  Here, the positions on the original P where the originals are simultaneously read by the RGB CCD line sensors 11r, 11g, and 11b are not the same positions but shifted in the sub-scanning direction as can be seen from the points 35r, 35g, and 35b. Yes. That is, the images simultaneously received by the CCD line sensors 11r, 11g, and 11b are sub-images corresponding to the line gap (in this example, the line gap number 36a for the lines Lr and Lg and the line gap number 36b for the lines Lg and Lb). It is shifted in the scanning direction. Therefore, the CCD line sensors 11r, 11g, and 11b read the image data shifted by the line gap in this way.

  The document reading unit includes an A / D conversion unit 12 as illustrated in FIG. The CCD line sensors 11r, 11g, and 11b transfer respective light reception signals as image data to the A / D conversion unit 12. The A / D converter 12 A / D converts it and passes it to the subsequent stage.

  Further, when the image data is transferred from the CCD line sensors 11r, 11g, and 11b, the document reading unit moves the carriage 31 in the direction indicated by the arrow in FIG. By repeating such transfer and movement of the carriage 31 in the sub-scanning direction, the document reading unit can obtain image data for the entire area of the document P. As described above, the original reading unit uses the CCD line sensors 11r, 11g, and 11b to read the original P with the line gaps provided in the reading lines for the respective colors. As illustrated here, when the plurality of colors are three colors of RGB, the CCD line sensor unit 11 corresponds to a three-line color line sensor.

  In addition, the line gap correction unit 14 temporarily stores the data (image data) of each color obtained by reading by the document reading unit in the SDRAM 18 and performs the line gap correction on the stored data of each color. To output. Examples of the SDRAM 18 include a DDR (Double-Data-Rate) SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, and its successor. The image reading apparatus 1 includes an SDRAM control unit 17 for controlling reading and writing to the SDRAM 18, and the line gap correction unit 14 performs reading and writing to the SDRAM 18 via the SDRAM control unit 17.

  Here, the data (image data) of each color obtained by reading by the document reading unit indicates image data for one line of each color after A / D conversion in this example, and is first output to the image processing unit 13 to obtain an image. The data is stored in the SDRAM 18 from the processing unit 13. However, as will be described later, in the present invention, image data may be stored in the SRAM 19 instead of the SDRAM 18.

  The state in which the line gap correction is performed refers to a state in which RGB image data for the same reading position (for example, point 35r) is read simultaneously. That is, the line gap correction unit 14 outputs data of each color so as to eliminate the line gap. Note that the present invention can be basically applied in accordance with the number of line gaps in the CCD line sensor unit 11 as will be apparent from the following description.

  1 includes a CPU (Central Processing Unit) 15, an image processing unit 13, an HDD (Hard disk drive) 20, a rotation unit 21, a JPEG (Joint Photographic Experts Group) compression unit 22, and A network I / F 23 is provided, and these are bus-connected together with the line gap correction unit 14 and the SDRAM control unit 17. Although not specifically described in detail, the CPU 15 controls the entire image reading apparatus 1 including document reading control in the document reading unit.

  The image processing unit 13 includes, for example, a shading correction unit 13a, an input γ correction unit 13b, a region separation / filter unit 13c, a zoom processing unit 13d, and the like, and performs various types of image processing. The shading correction unit 13a corrects each pixel of the image data output from the A / D conversion unit 12 with a correction coefficient so that the pixel value of the image data becomes a constant value on the reading line when the blank original is read. To do. The input γ correction unit 13 b uses an internal memory such as SRAM (or SRAM 19 described later) to perform density correction on the image data output from the shading correction unit 13 a and pass it to the line gap correction unit 14. .

  The region separation / filter unit 13c determines the type of photograph, character, halftone dot, etc. for each pixel from the density distribution of the image data subjected to the line gap correction by the line gap correction unit 14, and for each type. Do different filtering. The zoom processing unit 13d performs zoom processing on the image data output from the region separation / filter unit 13c by a linear linear interpolation method or the like.

  It should be noted that each unit in the image processing unit 13 may use an internal memory (or SRAM 19 or the like described later) as necessary, and an existing technique may be used as the processing in each unit, and the order of the processing Are not limited to those exemplified here. In addition, it is arbitrary at which stage the line gap correction is performed by passing to the line gap correction unit 14, but the image data after the line gap correction is used for the processing in the region separation / filter unit 13 c and the zoom processing unit 13 d. preferable.

  The rotating unit 21 accepts an instruction to collect and print originals when a plurality of pages are aggregated or a vertical and horizontal rotation process is performed on the original read image, and further from a printing unit (not shown) connected to the image reading apparatus 1. In some cases, the image data is rotated to change the aspect. The JPEG compression unit 22 compresses the image data that has been read in the JPEG format. The network I / F 23 can transmit document read image data to the outside via a connection terminal, a LAN (Local Area Network), or the like, and can receive image data from the outside.

  In the rotation unit 21, the JPEG compression unit 22, and the network I / F 23, the SDRAM 18 is used as a working memory. That is, the SDRAM 18 is used for processing in each of the units 21 to 23 in addition to the line gap correction. However, when reading a document, since processing in real time is required, it is preferentially used for line gap correction. The rotation unit 21, the JPEG compression unit 22, and the network I / F 23 are examples of processing units other than the line gap correction unit 14 that perform processing using the SDRAM 18, and the image processing apparatus according to the present invention is as described above. It is not limited to a simple configuration.

  The image reading apparatus 1 according to the present invention includes an SDRAM memory bandwidth determination unit 16 and an SRAM 19 as main features. The SRAM 19 is connected to the CPU 15 by a bus, but the connection form of each part in the image reading apparatus 1 is not limited. The SDRAM memory bandwidth determination unit 16 is a determination unit that determines whether the bandwidth of the SDRAM 18 is congested. For example, when the number of access requests to the SDRAM control unit 17 is seen, It is determined that

  When it is determined that the SDRAM memory bandwidth determination unit 16 is congested, the line gap correction unit 14 converts part or all of the data of each color obtained by reading by the document reading unit into the SRAM 19 instead of the SDRAM 18. Are temporarily stored, and the data of each color stored in the SDRAM 18 or the SRAM 19 is output in a state where the line gap correction is performed. As described above, the image reading apparatus 1 includes the SDRAM 18 and the SRAM 19 that store the image data from the CCD line sensors 11 r, 11 g, and 11 b for the line gap correction in the line gap correction unit 14.

  More specifically, the line gap correction unit 14 receives image data of three colors having a line gap from the image processing unit 13, and generates an address for the image data by the address generation unit 14a. The data is stored (written) in the SDRAM 18 or the SRAM 19 at the address. For example, the line gap correction unit 14 or the CPU 15 or the image processing unit 13 may be executed as a bus master according to the generated address, but in the following, the line gap correction unit 14 basically performs the writing. Will be described.

  Here, the line gap correction unit 14 has an SRAM history memory 14b. When the storage to the SRAM 19 is executed, the start address of the SDRAM 18 and the start address of the SRAM 19, which is the storage destination, are stored in the SRAM history memory 14b. Remember. As a result, the line gap correction unit 14 can also read the image data in the SRAM 19 serving as a storage destination instead of the SDRAM 18 when reading the image data from the SDRAM 18. Data read / write from / to the SDRAM 18 is executed by the SDRAM control unit 17 in accordance with an instruction from the line gap correction unit 14. In this example, since it is assumed that the SDRAM 18 is externally attached to a chip including the line gap correction unit 14 and the like, the SDRAM control unit 17 is provided in the chip, but the SDRAM control unit 17 is separately provided. Even if it is not provided, the line gap correction unit 14 may directly read / write data from / to the SDRAM 18.

  The line gap correction unit 14 reads out the image data for three colors and transmits the image data to the image processing unit 13 when the image data for three colors is prepared for each line by writing. The image processing unit 13 receives the image data and executes each process after the line gap correction. Note that the last received color image data may be returned to the image processing unit 13 without being stored in the SDRAM 18 or the SRAM 19 (or not even transmitted from the image processing unit 13 to the line gap correction unit 14). However, in order to make it easy to adjust the readout timing for the data of each color, it is preferable to write the data once for all the colors as illustrated here.

  As described above, real-time processing is required when reading a document. Therefore, in the conventional configuration, the SDRAM 18 is used for line gap correction for other processing in the rotating unit 21 using the SDRAM 18. On the other hand, it was only possible to postpone it for preferential use. On the other hand, in the present invention, it is detected that the memory band of the SDRAM 18 used for line gap correction is congested, and the memory band of the SDRAM 18 is relaxed by using the SRAM 19, so that the other processing (line gap) is performed. With respect to processing other than correction and processing using the SDRAM 18), it is possible to minimize (relieve) a decrease in performance. Of course, when the memory bandwidth is not congested, only the SDRAM 18 is used for line gap correction, so the SRAM 19 can be assigned to another process.

  Even in a configuration in which an SDRAM other than the SDRAM 18 is additionally connected, congestion in the SDRAM 18 can be avoided. However, SDRAM is slower than SRAM, and even if another SDRAM is added, the speed is not improved unless a new connection port with the chip is provided. The cost to increase will increase. Further, unlike the SDRAM, the SRAM 19 is often originally provided in the chip, and even when it is not provided, the design to be provided in the chip can be easily performed.

  Next, an example of a writing process in the line gap correction process will be described with reference to FIGS. FIG. 3 is a flowchart for explaining an example of the writing process among the line gap correction processes executed by the image reading apparatus of FIG. 1. FIGS. FIG. 4 is a diagram illustrating a specific example of the writing process of FIG. 3 when there is a line gap of two lines between G and B. Here, FIG. 4 is a diagram showing an example of an SDRAM memory map, FIG. 5 is a diagram for explaining an example of an SRAM history memory in which history data is written, and FIG. 6 is an example of an SRAM memory map. FIG.

  First, RGB image data (hereinafter simply referred to as RGB data) is captured from the CCD line sensor unit 11 (step S1). As described above, the RGB data has a line gap for each color.

  Since unnecessary data exists due to the presence of the line gap, not all of the captured RGB data is used. Therefore, after the process of step S1, it is determined whether the image data of each color is data of a color within the valid range (step S2). If the color data is outside the valid range (that is, the color data in the invalid range) (NO in step S2), the data is not written to the SDRAM 18 or the SRAM 19 but discarded as it is and the color of the read line is changed. The process for the current access unit is terminated.

  Note that FIG. 3 illustrates a process executed for obtaining one access unit in one document reading process in the main scanning direction, that is, for obtaining one access unit of RGB data. Therefore, in practice, the process of FIG. 3 is repeated for one line, then the carriage 31 is moved in the sub-scanning direction, and the process of FIG. 3 is repeated for one line again. The image data for the original document is stored with the line gap corrected.

  If the color data is within the valid range (YES in step S2), the address generation unit 14a generates the address of the corresponding SDRAM 18 (step S3). As shown in FIG. 4, the address generation example in step S <b> 3 first secures memory areas 41 r, 41 g, 41 b for each of R, G, and B on the SDRAM 18, and issues an address for each access unit of the SDRAM 18. . When the address is within the valid range, the address is issued for each color. That is, in step S3, the address of the corresponding SDRAM 18 is generated for each color for data within the valid range.

  Here, the access unit of the SDRAM 18 may be determined in advance based on the bandwidth of the bus, and can be determined by, for example, “bit width of the SDRAM 18” × “maximum number of bytes of the SDRAM 18 that is the maximum or sufficiently large number of bursts”. The longer the number of bursts, the smaller the command cycle issued to the SDRAM 18, but the larger the buffer for writing / reading data, the more efficient access unit differs depending on the system design.

  FIG. 4 shows an example in which the access unit is 32 bytes and the number of RGB lines gaps is 2 lines. In addition, as described above, processing is actually performed until one original is read. However, in order to simplify the description, FIG. 4 shows an example in which three lines of data within the valid range for each color are acquired. Yes. Further, in FIG. 4, reference numeral 43 indicates the number of lines of input data, that is, for example, R indicates the input order from the CCD line sensor 11r, and W indicates the above-mentioned access unit (32 bytes in this case). Is shown.

  Describing R, as shown in the memory area 41r, the first to fourth lines of the R data are discarded as an invalid area 42r of the image and discarded from the fifth to seventh lines. Addresses (head addresses) rad11 to rad34 of the SDRAM 18 are sequentially issued within the effective range. For example, for the head data on the fifth line of R, the address of the SDRAM 18 is generated as rad11 in step S3. In the example of FIG. 3, processing for each line is described, and an address is issued for each line. For example, addresses rad11 to rad14 are issued for the R data on the fifth line, and addresses rad21 to rad24 are issued for the R data on the sixth line as the carriage 31 moves in the sub-scanning direction.

  The same applies to G and B. As shown in the memory area 41g, the first to second lines of input data and the sixth to seventh lines of the G data are discarded as the invalid range 42g of the image and discarded. The addresses gad11 to gad34 are issued up to the eye as the effective range of the image. In addition, as shown in the memory area 41b, the first to third lines of the B data are the effective range of the image, and the addresses bad11 to bad34 are issued, and the fourth to seventh lines are input. The invalid area 42b of the image is discarded.

  After the address of the SDRAM 18 is generated in this way, the SDRAM memory bandwidth determination unit 16 confirms and determines whether or not the memory bandwidth of the SDRAM 18 is congested (step S4). An example of the determination in step S4 will be described later with reference to FIG. If it is congested (YES in step S4), the SDRAM memory determination unit 16 determines whether or not the SRAM 19 is free (step S5). In step S <b> 5, a determination is made based on whether or not there is at least one vacant size of the SRAM 19 for one access unit of the SRAM 19. Therefore, if the free size is smaller than one access unit, NO is returned in step S5. In addition, the order of step S4 and step S5 is not ask | required.

  In the case of NO in step S4 and NO in step S5, that is, when there is no congestion or there is no space in the SRAM 19, the line gap correction unit 14 sends the data of each color to the SDRAM 18 based on the address generated in step S3. Write (step S10), the process for the current access unit of the read line is terminated.

  On the other hand, if YES is obtained in steps S4 and S5, that is, if the memory band is congested, the address generation unit 14a executes a write color determination processing example described later with reference to FIG. The color to be written to the SRAM 19 is determined (step S6).

  Next, the address generation unit 14a determines whether or not the data to be processed at present is color data to be written to the SRAM 19 based on the determination (step S7). If the data is not the color data to be written to the SRAM 19 (NO in step S7), the line gap correction unit 14 writes the color data to the SDRAM 18 based on the address generated in step S3 (step S10) and reads the data. The process for the current access unit of that color of the line is terminated.

  On the other hand, if the color data is to be written to the SRAM 19 (YES in step S7), the address generation unit 14a records the valid bit, the start address of the SDRAM 18, and the start address of the SRAM in the SRAM history memory 14b. Then, the line gap correction unit 14 writes the color data from the head address of the SRAM 19 designated here (step S9). With the processing in step S9, the processing for the current access unit of the color of the reading line is completed.

  Specific examples of steps S8 and S9 will be described with reference to FIGS. Here, the memory areas 46r, 46g, and 46b for each color shown in FIG. 5 are the same as the memory areas 41r, 41g, and 41b in FIG. 4, respectively, and reference numeral 43 in FIG. ing. 5 and 6 show an example in which the memory bandwidth of the SDRAM 18 is determined to be congested when writing to the addresses rad12, gad33, and bad34 in the memory areas 46r, 46g, and 46b.

  An example will be described in which it is determined that the start address rad12 which is the address of the SDRAM 18 for R is congested and the corresponding data is written to the SRAM 19. In this case, the address generation unit 14a records the start address of the SDRAM 18 in the SRAM history memory 14b as illustrated in the SRAM history memory 47 of FIG. 5 (step S8), and the line gap correction unit 14 is targeted. Data is stored in the SRAM 19 (step S9). As described in the case of NO in step S7, even if the same R data is not mixed, that is, data of a color other than the color written to the SRAM 19 is written to the SDRAM 18.

  The start address of the SDRAM 18 recorded in the SRAM history memory 47 is “rad12” when it is determined that the SDRAM 18 is congested when writing to the address rad12. In step S8, for the color data to be written to the SRAM 19, in addition to the start address of the SDRAM 18, the valid bit = 1 and the start address of the write destination SRAM 19 are recorded in the SRAM history memory 47. For example, when the memory area of the SRAM 19 is all free, the data of the rad 12 from the first address “0” is stored in the SRAM 19 in step S9 as shown by the memory map 48 in FIG. In this case, “0” is recorded in the SRAM history memory 47 in association with the address rad12 as the start address of the write destination SRAM 19 in step S8.

  In this example, it is assumed that the same access unit as the access unit of the SDRAM 18 is used when writing to the SRAM 19. As described above, the line gap correction unit 14 accesses the SRAM 19 in the access unit to the SDRAM 18, in other words, matches the data unit for switching the data storage destination between the SDRAM 18 and the SRAM 19 to the access unit of the SDRAM 18. The memory bandwidth of the SDRAM 18 can be reduced efficiently. Of course, a configuration in which the SRAM 19 is accessed in an access unit other than the access unit of the SDRAM 18 may be employed. In such a configuration, an access size indicating the access unit may be added to the SRAM history memory 47.

  Similarly, for G and B, when it is determined that the memory band of the SDRAM 18 is congested when writing to the addresses gad33 and bad34, the start address of the SDRAM 18 is stored in the SRAM history memory 47 in step S8. , Gad33 and bad34 are recorded, respectively, and “32” and “64” are recorded as the top addresses of the SRAM 19 to be written. In step S9, as shown in the memory map 48, data corresponding to the addresses gad33 and bad34 from the top addresses 32 and 64 are stored in the SRAM 19, respectively. Note that the reason why the head address at the time of writing to the SRAM 19 is every 32 bytes is because the access unit to the SRAM 19 is fixed to 32 bytes like the access unit of the SDRAM 18 as described above. is there.

  Next, an example of a reading process in the line gap correction process executed after data is written in the SDRAM 18 or the SRAM 19 in this way will be described with reference to FIG. FIG. 7 is a flowchart for explaining an example of the reading process among the line gap correction processes executed by the image reading apparatus of FIG.

  First, the line gap correction unit 14 refers to the memory map of the SDRAM 18 described with reference to FIG. 5 to determine whether or not the RGB data of the line to be read is written in all colors (step S21). Wait until they are ready (until YES). Next, the address generation unit 14a generates the head address of the corresponding SDRAM 18 on the reading side for each color (step S22). Next, the line gap correction unit 14 determines whether or not the read start address matches the start address of the SDRAM 18 in the SRAM history memory 47 and the corresponding effective bit is 1 (step S23). ).

  If there is such a history (YES in step S23), the line gap correction unit 14 reads data from the start address of the corresponding SRAM 19 with reference to the memory map 48 (step S24). After reading from the SRAM 19, the address generation unit 14a sets the effective bit in the SRAM history memory 47 to 0 to release the memory area of the SRAM 19 (step S25), and the process for the line to be read is terminated.

  On the other hand, if NO in step S23, that is, if the start address of the SDRAM 18 at the time of reading is valid bit = 1 in the SRAM history memory 47 and there is no match with the start address of the SDRAM 18, the line gap correction unit 14 The data is read from the SDRAM 18 as it is (step S26), and the process for the line to be read is terminated.

  By such a reading process, as shown in the address 44 for each output line in the example of FIG. 4, first, the data of the addresses rad1n, gad1n, bad1n (n = 1 to 4) are simultaneously output for the first output line. Is done. Here, reference numeral 45 indicates an output order (output line order) after the line gap correction.

  More specifically, first, data of addresses rad11, gad11, and bad11 (data of n = 1) are output simultaneously, then data of addresses rad12, gad12, and bad12 are output simultaneously, followed by addresses rad13 and gad13. , Bad13 data is output simultaneously, and finally, data of addresses rad14, gad14, bad14 are output simultaneously. In this way, the fifth input line data for R, the third input line data for G, and the first input line data for B are simultaneously output as the output first line data after line gap correction. Then, the reading of the first line of each color in the data within the effective range is completed.

  Thereafter, addresses rad2n, gad2n, bad2n (n = 1 to 4) are simultaneously output for the next output line, and addresses rad3n, gad3n, bad3n (n = 1 to 4) are output for the next line. Regarding the step S25, how the SRAM history memory 47 of FIG. 5 is rewritten after the reading process will be briefly described later as an explanation of FIG.

  Thus, in the present invention, when the memory band of the SDRAM 18 used for line gap correction is congested, the memory band of the SDRAM 18 is relaxed by using the SRAM 19. As a result, in the present invention, the possibility that the SDRAM 18 can be used in the other processes in the rotating unit 21 and the like is improved, and the decrease in performance of the other processes is minimized.

  Next, an example of the memory band congestion determination process in step S4 of FIG. 3 will be described with reference to FIGS. FIG. 8 is a flowchart for explaining an example of memory bandwidth congestion determination processing in the writing processing of FIG. 9 is a diagram showing an example of mounting the SDRAM in the image processing apparatus of FIG. 1, FIG. 10 is a timing diagram for explaining the number of write / read cycles of the SDRAM of FIG. 9, and FIG. 11 is a diagram of FIG. It is a figure which shows an example of the access request table | surface of SDRAM. The congestion determination process is not limited to the example described here, and any process that can determine the degree of congestion can be used.

  First, the SDRAM memory bandwidth determination unit 16 calculates the number of cycles necessary for the SDRAM 18 from the access size (number of access bytes) of the Read / Write access request of the SDRAM 18 for each access request to the SDRAM 18 (step S31).

  A processing example of step S31 will be described with reference to FIGS. As illustrated in FIG. 9, the control IC (Integrated Circuit) 10 corresponding to the SDRAM control unit 17 in FIG. 1 controls reading and writing in the SDRAM 18. The control IC 10 only needs to include the SDRAM control unit 17. For example, as described above with respect to the configuration of the chip, the image processing unit 13, the line gap correction unit 14, the CPU 15, the SDRAM memory band determination unit 16, The SDRAM control unit 17, the SRAM 19, the rotation unit 21, the JPEG compression unit 22, and the network I / F 23 may be included.

  Control to the SDRAM 18 in the control IC 10 is executed by a command signal 52 and a clock 51 as illustrated in FIG. Of course, the interface of the SDRAM 18 has a data line in addition to such a line for sending a command signal or a clock. In this example, it is assumed that the data width between the control IC 10 and the SDRAM 18 is 64 bits.

  As exemplified by the command signal 52, the command signal for Write includes ACT (active command), WRIT (Write command), and PRE (precharge command). Based on the clock 51, the control IC 10 performs burst transfer of the target data from the data line in an access unit (64-bit width) when a write command is issued. The target data in the example of FIG. 10 refers to D1, D2, D3, and D4 illustrated under WRIT in the data group 53, and each is transferred by one burst transfer.

  Therefore, in this example, a total of 32 bytes (64 bits × 4) of data for 4 bursts are transferred to the SDRAM 18 and written for each write access. In this example, a total of 8 cycles (8 clocks) are required for the four burst transfers and the issuance of ACT and PRE. If the amount of data to be written is double this 64 bytes, double 16 cycles are required. Similarly, Read command signals include ACT, READ (Read command), and PRE, and 8 cycles are required for one Read access.

  As described above, the write and read command cycles of the SDRAM 18 are determined in advance according to the data amount. Therefore, for example, as exemplified in the SDRAM access request table 55 of FIG. 11, the number of access bytes (or the number of cycles required for each request) is stored in the control IC 10 for each request, and when there is a request, this SDRAM With reference to the access request table 55, the number of access bytes required according to the request is converted to the required number of cycles (or the number of cycles required for the request is read). For example, in the case of request 1, the number of access bytes (access size) is 32 bytes, and the number of cycles required for it is the same as that illustrated in FIG. In the case of request 3, the access size (the number of access bytes) is 64 bytes, and the number of cycles required for it is twice that illustrated in FIG.

  Next, the SDRAM memory bandwidth determination unit 16 adds up the number of cycles obtained by converting all the access requests (step S32), and determines whether or not it is larger than a predetermined congestion determination cycle number set separately. (Step S33). The SDRAM memory bandwidth determination unit 16 determines that it is congested if it is larger than the predetermined congestion determination cycle number (YES in step S33) (step S34), and congests if NO in step S33. It determines with not having carried out (step S35).

  For example, if the access request to the SDRAM 18 is the request 1, the request 2 and the request 3 in the SDRAM access request table 55, the number of cycles required for them can be calculated as 32 cycles in step S32. The total request preferably includes an access request to the SDRAM 18 in processing other than the line gap correction. When the predetermined congestion determination cycle number (threshold value) is 50 cycles, NO is determined in step S33, and it is determined that there is no congestion as in step S35. The access SDRAM memory bandwidth determination unit 16 passes the determination result to the line gap correction unit 14 and ends the process.

  Next, an example of the writing color determination process in step S6 of FIG. 3 will be described with reference to FIGS. 12 is a flowchart for explaining an example of the writing color determination process in the writing process of FIG. 3, and FIG. 13 is a diagram for explaining another example of the SRAM history memory in the specific example of FIG. is there.

  First, define the words as follows: The color having the shortest “(writing time) − (reading time)” is defined as “the shortest storage color”. Here, “(write time) − (read time)” refers to the time required from the start of writing to the end of reading (or the start of reading). In addition, the second shortest color “(writing time) − (reading time)” is “intermediate storage color”, and the longest color is “maximum storage color”. Further, the maximum used memory size of the shortest stored color is “shortest color Size_all”, and the memory size currently used by the shortest stored color in the SRAM 19 is “shortest color Size_used”. Similarly, the maximum used memory size of the intermediate storage color is “intermediate color Size_all”, and the memory size currently used by the intermediate storage color in the SRAM 19 is “intermediate color Size_used”.

  The process of step S6 of FIG. 3 will be described along FIG. First, the address generation unit 14a determines whether or not the empty size of the SRAM 19 is equal to or less than “shortest color Size_all−shortest color Size_used” (step S41). If YES in step S41, one of the shortest stored colors is selected (step S44), and the process ends. Since step S6 is executed when YES is obtained in step S5, at the time of the processing of step S41, there is at least one free unit of SRAM 19 corresponding to one access unit of SRAM 19, and the free size is one access. It does not exist if it is smaller than the unit.

  With reference to FIG. 13, the memory size used when the shortest storage color is determined will be described. In the example of FIG. 13, since the R data is read immediately after writing the output line, R is the shortest storage color. Note that the example of FIG. 13 shows a case where priority is given to a color that takes a short time from writing to reading in the SRAM 19, and the time required for writing the input line and the output line after the line gap correction are shown. It is assumed that the time required for reading is equal. In addition, B data must be held for two lines until R data can be output together after writing, and G data can be output together after writing. It is necessary to hold one line until it becomes. Therefore, B is the maximum stored color and G is the intermediate stored color.

  13 are basically the same as the memory areas 41r, 41g, and 41b in FIG. 4 and the memory areas 46r, 46g, and 46b in FIG. 5, and the number of lines is three. It has only increased from 7 to 7. Also, reference numeral 63 in FIG. 13 indicates the input order in the same manner as reference numeral 43 in FIGS. Reference numeral 64 is the same as the address 44 for each output line in FIG. 4, and reference numeral 65 is the same as the reference numeral 45 in FIG.

  First, the data size of one line will be described. In the case of the data size of the first line within the effective range in the memory area 61r, since the four data of the head addresses rad11 to rad14 correspond to one line, the data size of one line is 128 bytes, which is four times the access unit. . Of course, for G and B, the data size of one line is 128 bytes, which is four times as large as the access unit is 32 bytes.

  When the write color to the SRAM 19 is determined to be the shortest storage color R, the data corresponding to the head address rad11 is written to the SRAM 19, so that the SRAM history memory corresponding to the SRAM history memory 47 of FIG. In the area 67, rad11 is written as the SDRAM head address, and valid bit = 1 is written.

  In the memory area 61r of FIG. 13, another memory area of the SRAM 19 is assigned as the write destination of the top addresses rad31 to rad34 when writing the seventh data in the input order 63 of the R data.

  However, when writing the sixth data in the input order 63, the data of rad11 to rad14 has already been read. By this reading, the valid bit of the SRAM history memory 67 is rewritten to “0” as shown by the SRAM history memory 68 (corresponding to step S25 in FIG. 7), and the corresponding memory areas of the SRAM 19 and SDRAM 18 are released. Will be. Therefore, the data of the head addresses rad31 to rad34 can be overwritten on the data of the head addresses rad11 to rad14. At the time of overwriting, as shown by the SRAM history memory 69, the valid bit of the SRAM history memory 68 is rewritten to “1”, and the SDRAM head address is rewritten to rad31.

  Thus, in the example of FIG. 13, the data of R has a storage cycle every two lines. Therefore, the required memory size required for the R data in this example can be calculated as 128 bytes × 2 lines = 256 bytes at the minimum.

  On the other hand, if NO in step S41, that is, if the vacant size of the SRAM 19 is larger than “shortest color Size_all−shortest color Size_used”, the address generation unit 14a determines “(shortest color Size_all−shortest color Size_used) + (intermediate color). It is determined whether or not it is equal to or smaller than (Size_all-intermediate color Size_used) "(step S42). In the case of NO in step S42, that is, when the vacant size of the SRAM 19 is larger than “shortest color Size_all−shortest color Size_used” and larger than “(shortest color Size_all−shortest color Size_used) + (intermediate color Size_all−intermediate color Size_used)”. All three colors are selected (step S43), and the process ends. If YES in step S42, two colors of the shortest stored color and intermediate color are selected (step S45), and the process ends.

  Here, an example is given in which a color that takes a short time from writing to reading is preferentially written to the SRAM 19, but the advantage of adopting such priority processing will be described below from the viewpoint of the usage frequency of the SRAM 19. Again, referring to FIG. 13, when the shortest stored color is R (that is, when comparing the color of any output line, the color from which data is read last among the CCD line sensors 11r, 11g, 11b is R). ) As an example. Note that, as described above, the example of FIG. 13 shows the case where the color that has a short time from writing to reading is preferentially written to the SRAM 19, and the time required to write the input line and the line gap after correction It is assumed that the time required for reading the output line is equal, and the access unit (storage unit) to the SRAM 19 is the same as the access unit of the SDRAM 18.

  As shown in the memory area 61r of FIG. 13, if the fifth data in the input order 63 (data written corresponding to the start address rad11 of the SDRAM 18) among the R data is written to the SRAM 19, the input order 63 becomes six. By the completion of the writing of the first data, the output of the first line data after the line gap correction is already completed as shown as the output of the first line at the address 64 for each output line. As a result, during the writing of the sixth data in the input sequence 63 to the SDRAM 18, the data written in the SRAM 19 corresponding to the head address rad11 is read, and the memory area in the SRAM 19 can be released. Therefore, in this example, read / write to the SRAM 19 can be performed in units of two lines.

  On the other hand, when B data having the longest time from writing to reading is stored in the SRAM 19, it takes time until the memory area of the SRAM 19 is released. This point will be specifically described.

  When the B data is stored in the SRAM 19, the time from writing the data to reading it is the time required for writing lines corresponding to the number of line gaps (four lines) and the time required for reading the first line (one line). Min) and the time required to release the first read line (1 line), a total of 6 lines. That is, in this case, read / write to the SRAM 19 can be performed in units of 6 lines, and the use frequency of the SRAM 19 becomes lower than when the R data is stored in the SRAM 19, and as a result, the memory bandwidth of the SDRAM 18 can be reduced. Such access to the SRAM 19 is reduced.

  Therefore, writing to the SRAM 19 with priority given to colors that require a short time from writing to reading increases the memory release time of the SRAM 19 compared to writing other colors to the SRAM 19, resulting in the memory bandwidth of the SDRAM 18 being reduced. Can be relaxed efficiently. This effect is particularly remarkable when the memory area of the SRAM 19 that can be substituted is small.

  As described above, the line gap correction unit 14 gives priority to the color data having the shortest time from writing to reading to the SDRAM 18 among the data of each color obtained by reading by the document reading unit, and temporarily stores the data in the SRAM 19. Preferably, it is stored (assigned to the SRAM 19). As a result, more data can be allocated to the SRAM 19 and can contribute to the reduction of the memory bandwidth of the SDRAM.

  In this example, it is assumed that all data is once written in either the SDRAM 18 or the SRAM 19. However, in this example, even for R corresponding to “the color that takes the shortest time from writing to reading”, even writing is performed. A configuration is also possible in which the image processing unit 13 returns to the image processing unit 13 without performing the processing (or even the transmission from the image processing unit 13 to the line gap correction unit 14 is not performed). In this case, it is preferable to preferentially assign the G data as the intermediate storage color to the SRAM 19.

  Next, a specific example in the writing color determination process of FIG. 12 will be described with reference to FIGS. FIG. 14 is a diagram showing an example of an SDRAM memory map (SDRAM memory map before writing to the SRAM) used in the writing color determination process of FIG. FIGS. 15 to 17 are diagrams showing examples of SRAM memory maps used for the writing color determination process of FIG. Note that the write color determination process is not limited to the example described here, and may be based on another determination method, for example, a predetermined color is determined to be written. 15 to 17, W represents an access unit.

  A case where the line gap has two lines of R and G and two lines of G and B as illustrated in FIG. As illustrated in the memory map 70 of FIG. 14, in the memory map of the SDRAM 18 before the storage destination is replaced in the SRAM 19, the storage area 71r for the shortest storage color is read until the first line can be read after the line gap correction. As a result, the first line of 128 bytes (32 bytes × 4) and the second line of 128 bytes require a total of 256 bytes. Similarly, for the storage area 71g for the intermediate storage color, 128 bytes are required for each of the first to fourth lines, and a total of 512 bytes are required. Similarly, for the storage area 71b for the maximum storage color, 128 bytes are required for each of the first to sixth lines, and a total of 768 bytes are required.

  A numerical example based on the empty size and the used size of the SRAM 19 will be described based on the memory map 70 of the SDRAM 18.

(1) When the Memory Size of the SRAM 19 is Less Than the Shortest Color Size_all As this example, a case where the memory size of the SRAM 19 is 128 bytes (32 bytes × 4) will be described.

(1) -1: When not stored When not stored, the free space of the SRAM 19 is also 128 bytes. The shortest color Size_all is 256 bytes as described above. In this case, if the shortest color Size_used is 0 Byte (32 Bytes × 0), the expression of Step S41 in FIG. 12 is 128 bytes on the left side and 256 Bytes−0 Bytes = 256 Bytes on the right side, which is YES. Therefore, in this case, one color of the shortest stored color is determined as a write color to the SRAM 19.

(1) -2: When stored (when determination is one color)
As illustrated in FIG. 15, when the memory map 81 of the SRAM 19 is used for three access units for the shortest storage color, the free size of the SRAM 19 is 32 bytes × 1 = 32 bytes, and the shortest color Size_used is 32 × 3. = 96 bytes. The shortest color Size_all is 256 bytes as described above. Therefore, in this case, the expression of step S41 is 32 bytes on the left side and 256 bytes−96 bytes = 160 bytes on the right side, and is YES. Therefore, in this case, one color of the shortest stored color is determined as a write color to the SRAM 19.

(2) Case where Memory Size of SRAM 19 is More Than Shortest Color Size_all and Less than Shortest Color Size_all + Intermediate Color Size_all As an example, a case where the memory size of the SRAM 19 is 384 bytes (32 bytes × 12) will be described.

(2) -1: When not stored When not stored, the empty size of the SRAM 19 is also 384 bytes. In this case, if the shortest color Size_used is 0 bytes (32 bytes × 0), the expression of step S41 is 384 bytes on the left side and 256 bytes−0 bytes = 256 bytes on the right side, which is NO. Since it is not stored, the intermediate color Size_used is also 0 bytes (32 bytes × 0). Therefore, in the expression of step S42, the left side is 384 bytes, and the right side is (256 bytes−0 bytes) + (512 bytes−0 bytes) = 768 bytes, which is YES. Therefore, in this case, the two colors of the shortest storage color and the intermediate storage color are determined as the writing colors to the SRAM 19.

(2) -2: When stored 1 (when determination is two colors)
As illustrated in FIG. 16A, when the memory map 82 of the SRAM 19 is used for 3 access units for the shortest storage color and 3 access units for the intermediate storage color, the free size of the SRAM 19 is 32 bytes × 6 = 192 bytes, and the shortest color Size_used and the intermediate color Size_used are both 32 × 3 = 96 bytes. The shortest color Size_all and the intermediate color Size_all are 256 bytes and 512 bytes, respectively, as described above. Therefore, in this case, the expression of step S41 is 192 bytes on the left side and 256 bytes-96 bytes = 160 bytes on the right side, and is NO. Next, in the expression of step S42, the left side is 192 bytes and the right side is (256 Bytes−96 Bytes) + (512 Bytes−96 Bytes) = 576 Bytes, which is YES. Therefore, in this case, the two colors of the shortest storage color and the intermediate storage color are determined as the writing colors to the SRAM 19.

(2) -3: 2 during storage (when determination is one color)
As illustrated in FIG. 16B, when the memory map 83 of the SRAM 19 is used for 5 access units for the shortest storage color and 4 access units for the intermediate storage color, the free size of the SRAM 19 is 32 bytes × 3 = 96 bytes, and the shortest color Size_used and the intermediate color Size_used are 32 × 5 = 160 bytes and 32 × 4 = 128 bytes, respectively. The shortest color Size_all and the intermediate color Size_all are 256 bytes and 512 bytes, respectively, as described above. Therefore, the expression of step S41 in this case is 96 bytes on the left side and 256 bytes-160 bytes = 160 bytes on the right side, which is YES. Therefore, in this case, one color of the shortest stored color is determined as a write color to the SRAM 19.

(3) When the size of the SRAM 19 is larger than the shortest color Size_all + the intermediate color Size_all As this example, a case where the memory size of the SRAM 19 is 1024 bytes (32 bytes × 32) will be described.

(3) -1: When not stored When not stored, the free space of the SRAM 19 is also 1024 bytes. In this case, if the shortest color Size_used is 0 bytes (32 bytes × 0), the expression of step S41 is 1024 bytes on the left side and 256 bytes−0 bytes = 256 bytes on the right side, which is NO. Since it is not stored, the intermediate color Size_used is also 0 bytes (32 bytes × 0). Therefore, in the expression of step S42, the left side is 1024 bytes, and the right side is (256 bytes−0 bytes) + (512 bytes−0 bytes) = 768 bytes, which is NO. Therefore, in this case, all three colors are determined as writing colors to the SRAM 19.

(3) -2: 1 when stored (when judgment is 3 colors)
As illustrated in FIG. 17, when the memory map 84 of the SRAM 19 is used for three access units for all three colors, the free size of the SRAM 19 is 32 bytes × 19 = 608 bytes, and the shortest color Size_used and the intermediate color Size_used are set. In both cases, 32 × 3 = 96 bytes. The shortest color Size_all and the intermediate color Size_all are 256 bytes and 512 bytes, respectively, as described above. Therefore, the expression of step S41 in this case is 608 bytes on the left side and 256 bytes-96 bytes = 160 bytes on the right side, and is NO. Next, in the expression of step S42, the left side is 608 bytes, and the right side is (256 bytes−96 bytes) + (512 bytes−96 bytes) = 576 bytes, which is NO. Therefore, in this case, all three colors are determined as writing colors to the SRAM 19.

(3) -2: 2 at the time of storage (when the judgment is two colors)
Since it can be described in the same manner as (2) -2 above, it will be omitted.
(3) -3: When stored 3 (when determination is one color)
Since it can be described in the same manner as (2) -3 above, it will be omitted.

  Further, in the various forms described above, the SDRAM memory bandwidth determination unit 16 may be configured to determine the degree to which the memory bandwidth of the SDRAM 18 is congested. In that case, the line gap correction unit 14 is based on the degree of congestion determined by the SDRAM memory bandwidth determination unit 16 and the proportion of data temporarily stored in the SRAM 19 for line gap correction as the congestion is increased. Increase. Thus, by increasing the rate of utilizing the SRAM 19 for line gap correction according to the degree of congestion of the memory band of the SDRAM 18, the performance of processing other than the line gap correction is reduced according to the congestion of the memory band of the SDRAM 18. Can be minimized.

  As described above, the image reading apparatus according to the present invention uses a multi-color CCD (Charge Coupled Device) line sensor, and a document reading unit that reads a document in a state where a line gap is provided in each color reading line; In a state where data of each color obtained by SDRAM (Synchronous Dynamic Random Access Memory) and reading by the original reading unit is temporarily stored in the SDRAM and line gap correction is performed on the stored data of each color. An output line gap correction unit, and further comprising: a determination unit that determines whether or not the memory bandwidth of the SDRAM is congested; and an SRAM (Static Random Access Memory); The line gap correction unit, when it is determined that the determination unit is congested, the data of each color obtained by reading by the document reading unit. A part or all of the data is temporarily stored in the SRAM instead of the SDRAM, and output in a state in which line gap correction is performed on the data of each color stored in the SDRAM or the SRAM. It is what. As a result, when the memory bandwidth of the SDRAM used for line gap correction is congested, it is possible to minimize a decrease in performance of processes other than line gap correction.

  Further, the determination unit determines the degree of congestion of the SDRAM memory bandwidth, and the line gap correction unit is congested based on the degree of congestion determined by the determination unit. It is preferable to increase the ratio of data temporarily stored in the SRAM. As a result, it is possible to minimize a decrease in processing performance other than the line gap correction in accordance with the congestion of the SDRAM memory bandwidth.

  The line gap correction unit may access the SRAM in units of access to the SDRAM. Thereby, the memory bandwidth of the SDRAM can be efficiently reduced.

  In addition, the line gap correction unit gives priority to the color data having the shortest time from writing to reading to the SDRAM among the data of each color obtained by reading by the document reading unit. It is preferable to store temporarily. As a result, more data can be allocated to the SRAM, which can contribute to (reduce) the memory bandwidth of the SDRAM.

DESCRIPTION OF SYMBOLS 1 ... Image reading device, 11 ... CCD line sensor part, 11r, 11g, 11b ... CCD line sensor, 12 ... A / D conversion part, 13 ... Image processing part, 13a ... Shading correction part, 13b ... Input gamma correction part, 13c ... Area separation / filter unit, 13d ... Zoom processing unit, 14 ... Line gap correction unit, 14a ... Address generation unit, 14b ... History memory for SRAM, 15 ... CPU, 16 ... Access SDRAM memory bandwidth determination unit, 17 ... SDRAM Control unit, 18 ... SDRAM, 19 ... SRAM, 21 ... rotating unit, 22 ... JPEG compression unit, 23 ... network I / F.

Claims (4)

A document reading unit that reads a document in a state where each color reading line has a line gap using a multi-color CCD (Charge Coupled Device) line sensor, an SDRAM (Synchronous Dynamic Random Access Memory), and the document reading unit And a line gap correction unit that temporarily stores the data of each color obtained by reading in the SDRAM and outputs the stored data of each color in a state in which the line gap correction is performed. Because
A determination unit for determining whether or not the memory bandwidth of the SDRAM is congested; and an SRAM (Static Random Access Memory);
When the determination unit determines that the line gap correction unit is congested, a part or all of the data of each color obtained by reading by the document reading unit is replaced with the SRAM instead of the SDRAM. An image reading apparatus that outputs data in a state where line gap correction is performed on the data of each color stored in the SDRAM or the SRAM. The determination unit determines the degree of congestion of the memory bandwidth of the SDRAM,
2. The line gap correction unit according to claim 1, wherein the line gap correction unit increases a ratio of data temporarily stored in the SRAM as it is congested based on the degree of congestion determined by the determination unit. The image reading apparatus described.   The image reading apparatus according to claim 1, wherein the line gap correction unit accesses the SRAM in an access unit to the SDRAM.   The line gap correction unit gives priority to the color data having the shortest time from writing to reading to the SDRAM among the data of each color obtained by reading by the document reading unit, and temporarily stores the data in the SRAM. The image reading apparatus according to claim 1, wherein the image reading apparatus is stored in the image reading apparatus.

Images