JP2013103372A - Image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image forming apparatus capable of preventing control from becoming complicated, and also capable of preventing a print output speed of multiple pages from being decreased even if a storage capacity necessary for writing a setting is decreased.SOLUTION: An information memory unit stores a setting data, and a start address and end address of the setting data on an address space, as an information corresponding to the setting. A memory control unit controls to make the information memory unit store information when decided that an image processing module is in operation, and to make a setting memory unit store the setting data based on the information when decided that the image processing module being in operation after the information memory unit stores the information is not in operation.

Description

  The present invention relates to an image forming apparatus that forms an image by changing settings for each page.

  There is known an image forming apparatus that stores settings for a plurality of image processes in an internal register and performs each image process in accordance with the settings stored in the register. It is also known that when continuous printing of a plurality of pages is performed, a setting is made between the printing of the current page and the printing of the next page. An image forming apparatus that writes information related to print settings for the next page into the FIFO during printing of the current page is also known.

  For example, Patent Document 1 discloses an image forming apparatus that stores write data, address, and access (Byte / Word) for the next page in a FIFO for storing information related to print settings for the next page during printing of the current page. It is disclosed.

  Patent Document 2 discloses an image forming apparatus in which a gradation processing circuit stores an index table and a gradation processing table in an internal register and performs gradation processing.

  However, as the number of image processes performed on an image increases, the settings for image processing increase. In order to write the setting without reducing the speed of printing output of a plurality of pages, there is a problem that the control becomes complicated. In addition, when the setting for image processing increases, there is a problem that the storage capacity necessary for writing the setting increases.

  The present invention has been made in view of the above, and prevents the control from becoming complicated, and even if the storage capacity necessary for writing the setting is reduced, the print output speed of a plurality of pages is reduced. An object of the present invention is to provide an image forming apparatus that can prevent this from happening.

  In order to solve the above-described problems and achieve the object, the present invention includes a setting storage unit that stores setting data indicating a setting for image processing in a predetermined address space, and the setting is performed on the image data. A plurality of image processing modules that respectively perform image processing according to data; a determination unit that determines whether or not the image processing module is operating; the setting data; and a start address of the setting data in the address space And an information storage unit that stores the end address as information corresponding to the setting, and if it is determined that the image processing module is operating, the information storage unit stores the information, and the information storage unit If it is determined that the image processing module that was in operation is no longer in operation after the unit stores the information, A storage control unit that controls to store the setting data in the setting storage unit, and an image forming unit that forms an image on a recording medium according to the image data processed by the image processing module. .

  According to the present invention, it is possible to prevent the control from becoming complicated and prevent the print output speed of a plurality of pages from decreasing even if the storage capacity necessary for writing the setting is reduced. There is an effect.

FIG. 1 is a block diagram illustrating an outline of an image forming apparatus according to an embodiment. FIG. 2 is a block diagram showing the details of the image processing ASIC and the surrounding configuration. FIG. 3 is an example of an image interface signal between each image processing module in the image processing ASIC. FIG. 4 is a timing chart showing an example of operation timing of each signal shown in FIG. FIG. 5 is a conceptual diagram illustrating signals input / output by the I / F unit. FIG. 6 is a timing chart showing an example of write access timing for the image processing ASIC of the engine CPU. FIG. 7 is a block diagram conceptually showing the configuration of the I / F unit and each image processing module. FIG. 8 is a block diagram illustrating the configuration of the write access storage unit. FIG. 9 is a block diagram illustrating the configuration of the access control unit. FIG. 10 is an example of an address map of the image processing ASIC. FIG. 11 is a flowchart showing the operation of the access control unit. FIG. 12 is a timing chart illustrating the operation timing of the write access storage unit and each image processing module. FIG. 13 is a sequence diagram illustrating a setting operation for performing continuous page printing. FIG. 14 is a block diagram illustrating a hardware configuration example of an image forming apparatus such as a multifunction peripheral according to the embodiment.

  Exemplary embodiments of an image forming apparatus will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram illustrating an outline of an image forming apparatus 1 according to the embodiment. As illustrated in FIG. 1, the image forming apparatus 1 includes a controller 10 and an engine unit 60.

  The controller 10 includes a CPU 11, a system memory 12, an ASIC (Application Specific Integrated Circuit) 16, and a hard disk drive (HDD) 18.

  The CPU 11 controls the entire image forming apparatus 1 and generates a print image. The system memory 12 is a storage area used as a work area for executing a program by the CPU 11 and stores image data, a DMAC (Direct Memory Access Controller) descriptor, and the like.

  The ASIC 16 accesses the system memory 12 and the HDD 18 under the control of the CPU 11 and transmits / receives data to / from the engine unit 60. The HDD 18 stores a program executed by the CPU 11, image data, and the like.

  The engine unit 60 includes an image processing ASIC 61, a scanner 62, an engine CPU 64, a writing control ASIC 66, and a plotter 68. The engine unit 60 performs processing of an image read by the scanner 62 and processing of an image output by the plotter 68, and forms an image on a recording medium such as paper.

  The scanner 62 converts the reflected light of the lamp irradiation on the document into an RGB (Red-Green-Blue color model) image data signal by a CCD (Charge Coupled Device) (not shown) and outputs it. The image processing ASIC 61 is connected to the controller 10 via a general-purpose interface such as PCIe (PCI Express). The image processing ASIC 61 performs image processing such as correction processing, which will be described later, on the image read by the scanner 62, and Output. Further, the image processing ASIC 61 receives image data from the controller 10, performs image processing such as gradation processing described later, and outputs it to the writing control ASIC 66.

  The writing control ASIC 66 controls a polygon motor and a laser diode (not shown) of the plotter 68, generates a synchronization signal to be output to the image processing ASIC 61, and outputs image data to the plotter 68. The plotter 68 includes a photosensitive drum (not shown) that carries four color images of cyan (C), magenta (M), yellow (Y), and black (K), and superimposes the four color images on a recording medium. The superimposition control unit 680 is controlled to perform the control. The plotter 68 superimposes and forms four color images on a recording medium such as paper in accordance with the image data received from the writing control ASIC 66. The engine CPU 64 controls each unit constituting the engine unit 60.

  Next, the image processing ASIC 61 will be described in detail. FIG. 2 is a block diagram showing the details of the image processing ASIC 61 and the surrounding configuration. As shown in FIG. 2, the image processing ASIC 61 includes a first module 610, a second module 612, a third module 614, a fourth module 616, a PCIe control unit 618, a fifth module 620, a sixth module 622, and a seventh module. 624, an eighth module 626, and an interface unit (I / F unit) 628.

  The first module 610 receives the image data read by the scanner 62, converts it into a format suitable for internal processing in the second module 612, and outputs it to the second module 612 (scanner I / F unit).

  The second module 612 corrects the CCD line deviation and the light amount unevenness with respect to the image data (scanner image) received from the first module 610 and outputs it to the third module 614 (interline correction / shading correction). Part).

  The third module 614 performs correction of γ characteristics and MTF (Modulation Transfer Function) on the image data received from the second module 612 and outputs the result to the fourth module 616 (scanner γ / filter unit). .

  The fourth module 616 converts the RGB image data received from the third module 614 into CMYK image data, performs processes such as color correction, UCR (under color removal), and UCA (under color addition), and the PCIe control unit 618. (Color correction / UCR / UCA section).

  The PCIe control unit 618 performs control to output image data (scanner image) received from the fourth module 616 to the controller 10 and read control of image data (plotter image) from the controller 10.

  The fifth module 620 converts the plotter image received from the controller 10 so as to match the resolution of the plotter 68, and outputs it to the sixth module 622 (resolution converter).

  The sixth module 622 performs centering and adjustment of the output image size on the plotter image received from the fifth module 620, and outputs the result to the seventh module 624 (shift unit).

  The seventh module 624 performs correction of printer output γ characteristics and gradation processing of a multi-value image on the plotter image received from the sixth module 622 (printer γ / gradation processing unit).

  The eighth module 626 generates a control signal to the write control ASIC 66 and packs data for the plotter image received from the seventh module 624, and outputs the control signal to the write control ASIC 66 (printer I / F unit). .

  The I / F unit 628 controls access from the engine CPU 64 to each image processing module (first module 610, second module 612, third module 614, fourth module 616, PCIe control unit 618, fifth module 620, sixth Module 622, seventh module 624, and eighth module 626) (engine CPU I / F unit).

  Hereinafter, the first module 610 to the eighth module 626 and the PCIe control unit 618 may be simply referred to as image processing modules. Further, when any one of the image processing modules is indicated without being specified, it may be simply referred to as an image processing module.

  Furthermore, a path for sending image data output from the scanner 62 to the PCIe control unit 618 via the first module 610, the second module 612, the third module 614, and the fourth module 616 may be referred to as a scanner path. In addition, a path for sending image data output from the PCIe control unit 618 to the write control ASIC 66 via the fifth module 620, the sixth module 622, the seventh module 624, and the eighth module 626 may be referred to as a plotter path.

  FIG. 3 is an example of an image interface signal between the image processing modules in the image processing ASIC 61. FIG. 4 is a timing chart showing an example of operation timing of each signal shown in FIG. fgate is a control signal indicating an image area in the sub-scanning direction. lsync is a control signal for synchronizing main scanning. lgate is a control signal indicating an image area in the main scanning direction. “data” is image data. In FIG. 3, _i is attached to the input signal and _o is attached to the signal name of the output signal.

  Each image processing module performs image processing on the received image data in accordance with the received control signal (the input signal), and outputs the control signal and the image data after the image processing to the subsequent image processing module. Each image processing module also outputs fgate to the I / F unit 628.

  FIG. 5 is a conceptual diagram illustrating signals input / output by the I / F unit 628. In FIG. 5, the signal shown on the left side of the I / F unit 628 is a signal that the I / F unit 628 transmits and receives to and from the engine CPU 64 via the external terminal of the image processing ASIC 61. For example, an address (addr_i), a write enable (we_i), a write data (wdata_i), a read enable (re_i), a read data (rdata_o), and an interrupt are signals that are transmitted to and received from the engine CPU 64 by the I / F unit 628. There is (irq_o).

  The signal shown on the right side of the I / F unit 628 is a signal that the I / F unit 628 transmits to and receives from each image processing module. The signals that the I / F unit 628 transmits to and receives from each image processing module include a common signal and a signal that is individually transmitted to and received from the image processing module.

  For example, common signals transmitted and received by the I / F unit 628 include an address (addr_o), a read enable (re_o), a write enable (we_o), and a write data (wdata_o). In addition, the signals that the I / F unit 628 individually transmits and receives to the image module include a chip select signal (cs1_o, cs2_o,... Csn_o) that is generated for each image processing module by decoding an address, and each image There are read data (rdata1_i, rdata2_i,..., Rdatan_i) and sub-scanning direction image area signals (fgate1_i, fgate2_i,... Fgaten_i) input from the processing module. In FIG. 5, _i is attached to the input signal, and _o is attached to the output signal.

  FIG. 6 is a timing chart showing an example of write access timing for the image processing ASIC 61 of the engine CPU 64. When writing (register write access) from the engine CPU 64 to the image processing ASIC 61 is asynchronous, as shown in FIG. 6, a setup period (Tsu), a write enable period (Twe), a hold period (Tho), and a disable period ( Tcw) is required. That is, even when the engine CPU 64 continuously performs write access to the image processing ASIC 61, several clocks are required for one write access.

  FIG. 7 is a block diagram conceptually showing the configuration of the I / F unit 628 and each image processing module. As illustrated in FIG. 7, the I / F unit 628 includes an access control unit 630, a write access storage unit 632, and an interrupt control unit 634.

  The access control unit 630 generates and outputs an access control signal to each image processing module and the write access storage unit 632 according to the access from the engine CPU 64. The write access storage unit 632 is an information storage unit that operates according to the control of the access control unit 630. For example, when the image processing module is operating, the write access storage unit 632 holds a write access from the engine CPU 64 as described later with reference to FIG. The interrupt control unit 634 controls interrupt signal output to the engine CPU 64.

  Each image processing module includes a register control unit 700, a processing unit 702, and a control signal generation unit 704, respectively. The register control unit 700 includes a register 701 as a setting storage unit. The register control unit 700 sets the image processing mode and parameters (setting data) performed by the processing unit 702 by holding the register 701, and controls the processing unit 702 according to the setting data. In each of the registers 701 included in each image processing module, an address for storing setting data is determined in advance on an address map (address space) described later with reference to FIG.

  The processing unit 702 performs image processing on the image data received by the image processing module based on the mode and parameters (setting data) set by the register control unit 700, and passes the processed image data to the subsequent image processing module. Output. The control signal generation unit 704 generates a control signal reflecting the pixel delay caused by the image processing of the processing unit 702 in accordance with the control signal (see FIG. 3) received from the previous image processing module. Output to the I / F unit 628.

  FIG. 8 is a block diagram illustrating the configuration of the write access storage unit 632. As shown in FIG. 8, the write access storage unit 632 includes an address storage unit 632a and a data storage unit 632b. The address storage unit 632a holds a start address and an end address in a series of write accesses from the engine CPU 64. Here, the start address and end address in write access indicate the actual start address and end address of write data (setting data) stored in a predetermined address space for each register 701. The data storage unit 632b holds write data (setting data) in write access. That is, for each setting data stored in the data storage unit 632b, the address storage unit 632a holds a start address and an end address corresponding to the setting data.

  FIG. 9 is a block diagram illustrating the configuration of the access control unit 630. As illustrated in FIG. 9, the access control unit 630 includes a write access specifying unit 630a, an operation state detection unit 630b, a storage control unit 630c, a determination unit 630d, and a write access generation unit 630e.

  The write access specifying unit 630a compares the address and write enable signal input from the engine CPU 64 with the address map (described later with reference to FIG. 10) of the image processing ASIC 61, and specifies the image processing module that is the target of write access. To do.

  The operation state detection unit 630b receives the sub-scanning direction image region signal (fgate) from the control signal generation unit 704 of each image processing module, detects the operation state and operation end of each image processing module, and stores them in the storage control unit 630c. Output.

  The storage control unit 630c controls the location where the setting data for each image processing module is stored according to the determination result of the determination unit 630d.

  The determination unit 630d issues (outputs) a write access (write) to the image processing module specified by the write access specification unit 630a or outputs a write access in accordance with a signal received from the write access specification unit 630a and the operation state detection unit 630b. It is determined whether to store (hold) write access in the access storage unit 632.

  Then, when storing the write access in the write access storage unit 632, the storage control unit 630c generates a start address and an end address corresponding to the setting data, and generates the generated start address and end address and the setting data. The data is output to the write access storage unit 632. In addition, the storage control unit 630c reads the start address, end address, and setting data stored in the write access storage unit 632 according to the signals received from the write access specification unit 630a and the operation state detection unit 630b, and generates a write access. To the unit 630e.

  The write access generation unit 630e receives the start address, end address, and setting data from the storage control unit 630c, and generates a write access signal to the image processing module in which the setting data is to be written. Then, the write access generation unit 630e outputs the generated write access signal to the register control unit 700 of the image processing module in which the setting data is to be written.

  FIG. 10 is an example of an address map of the image processing ASIC 61. As shown in FIG. 10, the overall control address 800 used by the I / F unit 628, the parameter setting address 802 used by the image processing module for image processing in the scanner path, and the image processing module used for image processing in the plotter path The setting address 804 to be mapped is mapped in the same address space.

  At the parameter setting address 802, the scanner I / F used by the first module 610, the line interpolation / shading correction used by the second module 612, the scanner γ / filter used by the third module 614, and the fourth module 616 used Up to the color correction / UCR / UCA addresses, RGB three-channel image data is processed.

  In the parameter setting address 802, the image data converted into the four channels of CMYK is processed at the addresses after the color correction / UCR / UCA used by the fourth module 616. In the parameter setting address 802 in the scanner path, even if the number of channels of image data is changed, the operation timing of each channel is common, so the addresses are collected for each image processing module.

  On the other hand, at the setting address 804 in the plotter path, the resolution conversion used by the fifth module 620, the shift used by the sixth module 622, the printer γ / gradation processing used by the seventh module 624, and the eighth module 626 are used. Up to the printer I / F address, CMYK 4-channel image data is processed.

  In the case where the plotter 68 has, for example, CMYK four-color photosensitive drums, the timing from the reading of the image data to the output is shifted for each color according to the photosensitive drum interval. Therefore, especially when the plotter 68 outputs a plurality of pages of images, the timing at which the setting can be written is shifted for each color. Therefore, the setting address 804 is a mapping in which addresses are collected for each color (for each plate), not for each image processing module.

  Next, the operation of the access control unit 630 will be described. FIG. 11 is a flowchart showing the operation of the access control unit 630. As shown in FIG. 11, in step 10 (S10), the access control unit 630 determines whether there has been a write access from the engine CPU 64 to each image processing module. If the access control unit 630 determines that there is a write access (S10: Yes), the process proceeds to S12, and if it determines that there is no write access (S10: No), the process proceeds to S24.

  In step 12 (S12), the access control unit 630 determines whether or not the image processing module targeted for write access is in operation (operation state) based on the fgate signal. If the access control unit 630 determines that the image processing module is not operating (during fgate negation) (S12: No), the process proceeds to S14, and the image processing module is operating (fgate is being asserted). If it is determined (S12: Yes), the process proceeds to S16.

  In step 14 (S14), the access control unit 630 outputs a write access signal to each image processing module.

  In step 16 (S16), the access control unit 630 determines whether the previous write access and the address are continuous. If the access control unit 630 determines that the previous write access and the address are continuous (S16: Yes), the process proceeds to S18, and if the previous write access and the address are determined not to be continuous ( In S16: No), the process proceeds to S20.

  In step 18 (S18), the access control unit 630 outputs the setting data, start address, and end address to the write access storage unit 632 as write access.

  In step 20 (S20), the access control unit 630 outputs the previous end address to the write access storage unit 632.

  In step 22 (S22), the access control unit 630 outputs the next address after the previous end address as the current start address, and outputs the current start address, end address, and setting data as write access to the write access storage unit 632. That is, the access control unit 630 outputs a write access including the current start address to the write access storage unit 632.

  In step 24 (S24), the access control unit 630 determines whether or not the negation of the fgate signal output by each image processing module has been detected. If the access control unit 630 determines that the negate of the fgate signal has been detected (S24: Yes), the process proceeds to S26, and if it determines that the negate of the fgate signal has not been detected (S24: No). The process proceeds to S10.

  In step 26 (S26), the access control unit 630 reads, for example, the start address from the write access storage unit 632, and the write access storage unit 632 stores it for writing to the image processing module that detected the negation of the fgate signal. It is determined whether there is a write access. If the access control unit 630 determines that there is a write access stored in the write access storage unit 632 (S26: Yes), the access control unit 630 proceeds to the process of S28, and the write access stored in the write access storage unit 632 is stored. If it is determined that there is not (S26: No), the process proceeds to S10.

  In step 28 (S 28), the access control unit 630 reads the start address and end address from the write access storage unit 632.

  In step 30 (S30), the access control unit 630 reads the setting data from the write access storage unit 632, and outputs a write access signal to the image processing module that detected the negation of the fgate signal in the process of S24.

  In step 32 (S32), the access control unit 630 determines whether or not the write access to the end address has been completed for the setting data read in the process of S30. If the access control unit 630 determines that the write access up to the end address has been completed (S32: Yes), the process proceeds to S34, and otherwise (S32: No), the process proceeds to S30.

  In step 34 (S34), the access control unit 630 clears the start address and end address stored in the write access storage unit 632.

  Next, the operation timing of the access control unit 630, the write access storage unit 632, and each image processing module will be described in detail. FIG. 12 is a timing chart illustrating the operation timing of the write access storage unit 632 and each image processing module.

  As illustrated in FIG. 12, the access control unit 630 first reads a set of a start address (Start Address: SA) and an end address (End Address: EA) from the address storage unit 632 a of the write access storage unit 632.

  Next, the access control unit 630 calculates the number of data to be written based on the start address and end address read from the address storage unit 632a, and reads a series of setting data of the calculated data number from the data storage unit 632b.

  The access control unit 630 generates a write address (setting address) for the image processing module from the read start address, end address, and setting data, and writes the write address (addr) together with the write enable (we) and chip select (csn), Write data (wdara) is output to the image processing module.

  When the access control unit 630 reads the setting data stored in the write access storage unit 632 and writes the setting data to each image processing module, continuous writing is possible with one clock. In addition, since the access control unit 630 can easily increase the internal clock speed, the write time can be shortened.

  Next, a setting operation for performing continuous page printing will be described. FIG. 13 is a sequence diagram illustrating a setting operation for performing continuous page printing. In FIG. 13, it is assumed that the C, M, Y, and K versions of the scanner path and plotter path operate at independent timings.

  As shown in FIG. 13, in step 100 (S100), the engine CPU 64 starts register setting for the first page (writing of setting data to the register 701) for the image processing module such as the first module 610, for example. In the register setting for the first page, since the fgate of each plate (color) is negated in each image processing module, the setting data is written to the register as it is at the write access timing from the engine CPU 64. In the plotter pass, there is no problem even if the image processing module continuously writes to the register without leaving an interval for each plate.

  In step 102 (S102), the engine CPU 64 ends the register setting for the first page for the image processing module such as the first module 610, for example.

  In step 104 (S104), the image processing module outputs to the access control unit 630 that the fgate signal is asserted.

  In step 106 (S106), the engine CPU 64 starts register setting for the second page via the access control unit 630. In step 106, since the fgate signal of the image processing module is asserted, the engine CPU 64 stores the start address in the address storage unit 632a via the access control unit 630 and stores the setting data in the data storage unit 632b. To start. That is, the register setting for the second page is not yet performed for the register 701 of the image processing module.

  There is no restriction on the timing at which the engine CPU 64 starts register setting for the second page. For example, the engine CPU 64 starts register setting for the second page after setting data for the next page is transmitted from the controller 10 through a communication buffer or the like. Normally, the setting data of the next page is transmitted during image transfer of the current page.

  In step 108 (S108), the engine CPU 64 stores the end address in the address storage unit 632a via the access control unit 630, finishes writing the setting data in the data storage unit 632b, and registers the second page. Finish the setting.

  In step 110 (S110), when the image forming operation for the first page is completed, the image processing module outputs to the access control unit 630 that the fgate signal is negated.

  In step 112 (S112), the access control unit 630 reads the start address from the address storage unit 632a when determining that the fgate signal is negated by the processing of S110.

  In step 114 (S114), the access control unit 630 reads the end address from the address storage unit 632a.

  In step 116 (S116), the access control unit 630 starts reading the setting data from the data storage unit 632b using the start address read in the process of S112 (for example, generated by incrementing the address).

  In step 118 (S118), the access control unit 630 starts register setting for the second page for the image processing module.

  In step 120 (S120), the access control unit 630 finishes reading the setting data from the data storage unit 632b.

  In step 122 (S122), the access control unit 630 ends register setting for the second page for the image processing module.

  In step 124 (S124), the access control unit 630 outputs an interrupt indicating that the register setting is completed to the engine CPU 64 via the interrupt control unit 634.

  That is, even during the printing of the first page on a recording medium such as paper, the second page is printed for the image processing module that has finished the processing operation for the printing of the first page. The corresponding register setting can be started.

  FIG. 14 is a block diagram illustrating a hardware configuration example of the image forming apparatus 1 such as a multifunction peripheral according to the embodiment. As shown in the figure, the image forming apparatus 1 has a configuration in which a controller 10 and an engine unit (Engine) 60 are connected by a PCI (Peripheral Component Interface) bus. The controller 10 is a controller that controls the entire image forming apparatus 1 and controls the drawing, communication, and input from the operation display unit 20. The engine unit 60 is a printer engine that can be connected to a PCI bus, and is, for example, a monochrome plotter, a one-drum color plotter, a four-drum color plotter, a scanner, or a fax unit. The engine unit 60 may include an image processing part such as error diffusion and gamma conversion in addition to a so-called engine part such as a plotter.

  The controller 10 includes a CPU 11, a north bridge (NB) 13, a system memory (MEM-P) 12, a south bridge (SB) 14, a local memory (MEM-C) 17, an ASIC 16, and an HDD 18. The north bridge (NB) 13 and the ASIC 16 are connected by an AGP (Accelerated Graphics Port) bus 15. The MEM-P 12 further includes a ROM (Read Only Memory) 12a and a RAM (Random Access Memory) 12b.

  The CPU 11 performs overall control of the image forming apparatus 1 and includes a chip set including the NB 13, the MEM-P 12, and the SB 14, and is connected to other devices via the chip set.

  The NB 13 is a bridge for connecting the CPU 11 to the MEM-P 12, SB 14, and the AGP bus 15, and includes a memory controller that controls reading / writing with respect to the MEM-P 12, a PCI master, and an AGP target.

  The MEM-P 12 is a system memory used as a memory for storing programs and data, a memory for developing programs and data, a memory for drawing a printer, and the like, and includes a ROM 12a and a RAM 12b. The ROM 12a is a read-only memory used as a program / data storage memory, and the RAM 12b is a writable / readable memory used as a program / data development memory, a printer drawing memory, or the like.

  The SB 14 is a bridge for connecting the NB 13 to a PCI device and peripheral devices. The SB 14 is connected to the NB 13 via a PCI bus, and a network interface (I / F) unit and the like are also connected to the PCI bus.

  The ASIC 16 is an IC (Integrated Circuit) for image processing having hardware elements for image processing, and has a role of a bridge for connecting the AGP bus 15, the PCI bus, the HDD 18, and the MEM-C 17. The ASIC 16 includes a PCI target and an AGP master, an arbiter (ARB) that forms the core of the ASIC 16, a memory controller that controls the MEM-C 17, and a plurality of DMACs (Direct Memory) that rotate image data using hardware logic. Access Controller) and a PCI unit that performs data transfer between the engine unit 60 via the PCI bus. An FCU (Facsimile Control Unit) 30, a USB (Universal Serial Bus) 40, and an IEEE 1394 (the Institute of Electrical and Electronics Engineers 1394) interface 50 are connected to the ASIC 16 via a PCI bus. The ASIC 16 is also connected to a host PC and a network (not shown). The operation display unit 20 is a touch panel, for example, and receives an input to the controller 10 and displays the state of the image forming apparatus 1 and the like. The operation display unit 20 is directly connected to the ASIC 16.

  The MEM-C 17 is a local memory used as an image buffer for copying and a code buffer, and an HDD (Hard Disk Drive) 18 is a storage for storing image data, programs, font data, and forms. It is.

  The AGP bus 15 is a bus interface for a graphics accelerator card proposed for speeding up graphics processing. The AGP bus 15 speeds up the graphics accelerator card by directly accessing the MEM-P 12 with high throughput. It is.

  The storage medium 19 is, for example, a CD-R (Compact Disk Recordable) that can be written once, and is used when a stored program or data is copied to the HDD 18 (or copied from the HDD 18).

  In the above embodiment, the image forming apparatus 1 of the present invention has been described as an example in which the image forming apparatus 1 is applied to a multi-function machine having at least two functions among a copy function, a printer function, a scanner function, and a facsimile function. The present invention can be applied to any image forming apparatus such as a printer, a scanner apparatus, and a facsimile apparatus.

  As described above, the image forming apparatus according to the present invention prevents the control from becoming complicated, and the print output speed of a plurality of pages decreases even if the storage capacity necessary for writing the setting is reduced. It is useful to prevent this.

1 Image forming apparatus 10 Controller 16 ASIC
60 Engine part 61 Image processing ASIC
610 First module 700 Register control unit 701 Register (setting storage unit)
702 processing unit 704 control signal generation unit 612 second module 614 third module 616 fourth module 618 PCIe control unit 620 fifth module 622 sixth module 624 seventh module 626 eighth module 628 interface unit (I / F unit)
630 Access control unit 630a Write access identification unit 630b Operation state detection unit 630c Storage control unit 630d Judgment unit 630e Write access generation unit 632 Write access storage unit 632a Address storage unit 632b Data storage unit 634 Interrupt control unit 62 Scanner 64 Engine CPU
66 Write Control ASIC
68 Plotter 680 Superimposition controller 800 Overall control address 802 Parameter setting address 804 Setting address

JP 2008-302583 A JP 2005-333499 A

Claims (4)

A plurality of image processing modules each including a setting storage unit that stores setting data indicating settings for image processing in a predetermined address space;
A determination unit for determining whether or not the image processing module is operating;
An information storage unit for storing the setting data and a start address and an end address of the setting data on the address space as information corresponding to the setting;
When it is determined that the image processing module is in operation, the information storage unit stores the information, and after the information storage unit stores the information, the image processing module in operation A storage control unit that controls to store the setting data in the setting storage unit based on the information when it is determined that it is no longer in operation;
An image forming unit that forms an image on a recording medium in accordance with image data processed by the image processing module;
An image forming apparatus comprising: The storage control unit
The image forming apparatus according to claim 1, wherein when it is determined that the image processing module is not in operation, the setting data is stored in the setting storage unit. When the storage control unit finishes controlling the setting storage unit to store the setting data based on the information, the storage control unit further includes an interrupt control unit that outputs an interrupt signal indicating that the control has ended. ,
The image forming apparatus according to claim 1, wherein: The image forming unit includes:
A superposition control unit that controls to superimpose a plurality of different color images on the recording medium;
The setting storage unit included in each of the image processing modules that operates when the image forming unit forms an image on a recording medium,
The image forming apparatus according to claim 1, wherein an address space is mapped such that addresses are continuous for each color of the image to be superimposed by the superimposition control unit.

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