JP2009193338A - Memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily change a circuit to mount a page memory instead of an FIFO memory in an image processor. <P>SOLUTION: This memory controller determines whether a page memory is connected to a page memory connection part and an FIFO memory is connected to an FIFO memory connection part. When the page memory is connected, the memory controller cyclically perform delay processing in which, based on a command signal generated by the FIFO memory controller, the memory controller successively writes color component signals to be time-sequentially transmitted from a color imaging device into the page memory while changing an address signal to be transmitted to the page memory in a predetermined order and then reads the color component signals from the page memory. When the FIFO memory is connected, the memory controller controls the write/read of the FIFO memory based on the FIFO command signal, thereby adjusting the time difference of the color component signals different in type for the same pixel and outputs it to an image processing circuit. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an improvement in a memory controller for connecting a page memory and an image processing circuit in an image processing apparatus such as a copying apparatus or a facsimile apparatus.

  A color imaging device such as a CCD (charge coupled device) used in the image processing apparatus as described above has three line type sensors for R (red), B (blue), and G (green) in the sub-scanning direction. In general, a configuration in which they are arranged at a predetermined interval (gap).

  FIG. 9 is a schematic diagram of a color image sensor in which the predetermined interval is 4 lines. The color image sensor 11 is composed of a line type sensor that is long in the main scanning direction, and shoots the original while moving in the sub-scanning direction indicated by the arrow. Therefore, the same line of the original photographed by the R line type sensor is used. The G line type sensor takes an image with a delay of 4 lines, and the B line type sensor takes an image with a delay of 8 lines. Conventionally, the time difference between R, G, and B color component signals output from such a color image sensor 11 is adjusted by a FIFO (First In First Out) memory, as will be described below.

  FIG. 10 is a schematic block diagram of a color component signal processing system from the color imaging device 11 to the image processing circuit 16 of the conventional image processing apparatus. This processing system includes independent line sensors for R, G, and B. The color image sensor 11 provided, an R FIFO memory 17 # 1 for delaying the R color component signal by 8 lines, and a G FIFO memory 17 # 2 for delaying the G color component signal by 4 lines And a FIFO memory controller 12 that controls the FIFO memory 17 and an image processing circuit 16.

In addition, there is an image processing apparatus that has a page memory instead of such a configuration and performs more advanced image processing using the page memory, and the page memory has R, G, and B color components for the same pixel. It is also known to adjust the time difference between signals. For example, in the following Patent Document 1, a page memory is used as a storage means for line image signals, and the line image signals are stored in a state in which the positional deviation between the color components is corrected by address control when writing to the storage means. Technology is disclosed.
JP2006-025269

When the page memory is added to the image processing apparatus as shown in FIG. 10 to achieve high functionality, the time difference of the color component signals is adjusted by the page memory if the technique disclosed in Patent Document 1 is adopted. Therefore, the FIFO memory 17 becomes unnecessary. However, such a circuit change requires a major change, such as removing the FIFO memory controller and providing a control circuit having a function of handling the page memory like the FIFO memory 17 instead. There was a problem that was overwhelming.
An object of the present invention is to solve this problem and provide a memory controller that can easily change a circuit from a configuration in which a FIFO memory 17 is mounted to a configuration in which a page memory is mounted in an image processing apparatus.

  The present invention is a memory controller for controlling a page memory that temporarily stores and holds pixel information, a page memory connection unit connected to the page memory, a FIFO memory connection unit connected to the FIFO memory, An image processing circuit connection unit connected to the image processing circuit, a FIFO command input unit for receiving a command signal from the FIFO memory controller connected to the FIFO memory controller to which the color image sensor is connected, and an address in the page memory Signals, writing and reading signals are sent at a predetermined timing to control page memory writing and reading, while command signals are sent to the FIFO memory to control writing and reading to the FIFO memory. The memory control unit, the memory control unit, The page memory is connected to the page memory and the FIFO memory is connected to the FIFO memory. When the page memory is connected, the color image sensor sends out the data in time series based on the command signal. While a predetermined delay process is performed on the incoming color component signal, when the FIFO memory is connected, the write and read control of the FIFO memory is performed based on the command signal, so The time difference between different color component signals is adjusted and sent to the image processing circuit. Here, in the delay process, the address signal to be sent to the page memory is sequentially written to the page memory while being changed in a predetermined order, and then the operation of reading from the page memory is cyclically performed. The FIFO memory controller may be provided inside the present invention or may be provided outside as a separate body.

  Further, the page memory includes a color classification page area section for temporarily storing the color component signals corresponding to the respective pixels constituting the image information according to the respective color types, and the color imaging device. And a color segment time difference adjustment area for temporarily storing and storing color component signals transmitted in time series from each color type, and the color segment time difference adjustment area In the unit, the same address is set for a color component signal of the same pixel in a predetermined word unit including at least one pixel, and the memory controller sends address signals to be sent to the page memory in a predetermined order. The delay processing operation may be performed in a cyclic manner.

  Alternatively, the page memory is configured to be divided into color types of color component signals corresponding to the respective pixels constituting the image information, and each page memory divided into the types of color component signals is The color classification page area that temporarily stores and stores the color component signals corresponding to each pixel that constitutes the image information, and the color component signals that are sent in time series from the color imaging device are temporarily stored. The memory controller may perform the delay processing operation by cyclically changing the address signal together with an enable signal designating the page memory in a predetermined order.

The present invention is compatible with both the FIFO memory and the page memory, and can be used in common between the specifications for mounting the FIFO memory of the image processing apparatus and the specifications for mounting the page memory. When developing the board, it is easy to use a common mounting board, and the development cost can be reduced.
In addition, since the color classification time difference adjustment area is set in an area other than the color classification page area used for the original purpose of the page memory, that is, a surplus area in the prior art, There is no need to provide a dedicated memory for the process of adjusting the time difference between the different color component signals. Therefore, the circuit configuration is simplified and the cost of the memory can be suppressed.

  In particular, in the configuration in which the same address is set for each of the divided page area portion and the color division time difference adjustment area portion for a color component signal of the same pixel in a predetermined word unit including at least one pixel, the color division Since at least one pixel or more of the color component signals sent in time series from the color image sensor can be processed by one writing or reading to the time difference adjustment area, the number of accesses can be reduced and power consumption can be reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic block diagram of a partial configuration in which the present invention is applied to an image processing apparatus such as a copying apparatus or a facsimile apparatus, that is, a color component signal processing system from a color imaging device to an image processing circuit.

  This processing system or the like is a FIFO memory controller 12 having a function of adjusting the time difference between signals of a color image sensor 11 for electronically photographing a document and color component signals output from the color image sensor 11 by a FIFO memory 17. A memory controller 14 for controlling the page memory 13 constituted by, for example, SRAM (Static Random Access Memory) or SDRAM (Synchronous Dynamic Random Access Memory), and predetermined image processing, for example, shading processing And an image processing circuit 16 for performing. The image processing circuit 16 stores the color component signals constituting the image in the page memory 13 through the local bus and the memory controller 14 and refers to them.

  As shown in FIG. 9, the color image sensor 11 is composed of three independent line-type sensors for R, G, and B. Each line-type sensor is predetermined in the sub-scanning direction in parallel with the main scanning direction. Are arranged at intervals (gap). At the time of shooting, the color image sensor 11 moves in the sub-scanning direction relative to the document. However, since each line type sensor is arranged at a predetermined interval in the sub-scanning direction, three line type sensors are arranged on the document. Different parts (lines) are shot at the same time. For example, when the R, G, B line sensors are arranged in that order every four lines, the line taken by the R line sensor at the head is the time when the sub-scan advances by four lines thereafter. Then, the image is taken by the G line type sensor, and then taken by the B line type sensor when the sub-scanning further advances by 4 lines. Therefore, there is a specific time difference between the R, G, and B color component signals output from the color image sensor 11.

  The FIFO memory controller 12 has the same configuration as that of the prior art, and has a function of adjusting the time difference between the R, G, and B color component signals by the FIFO memory 17. That is, when the FIFO memory 17 is connected to the memory controller 12, the FIFO memory 17 is controlled via the memory controller. Specifically, among the R, G, and B color component signals, the color component signal that is temporally preceded with respect to the same pixel is temporarily accumulated in the FIFO memory 17, and the preceding time is obtained. The time difference between the signals is adjusted by reading out when the time has elapsed.

  In order to control the FIFO memory 17 having an arbitrary capacity, the FIFO memory controller 12 initializes, for example, a signal wrst for initializing data writing as a command signal to the FIFO memory 17 and data reading. A signal rrst, a control clock, and the like are generated. On the other hand, for example, when receiving the signal wrst, the FIFO memory 17 sequentially writes data from the top of the storage area provided internally for each control clock, and when receiving the signal rrst, Thereafter, the data is sequentially read from the top of the storage area for each control clock. Therefore, the time difference between the signal wrst and the signal rrst is a delay time until the written data is read.

  The memory controller 14 is connected to the FIFO command input unit (terminal) 14 a for connecting to the FIFO memory controller 12, the page memory connecting unit (terminal) 14 b for connecting to the page memory 13, and the image processing circuit 16. The layer processing circuit connection unit (terminal) 14c, the FIFO memory connection unit (terminal) 14k to which the FIFO memory 17 is connected, and the address signal and write / read control signals are sent to the page memory at a predetermined timing. The memory control unit 14j for controlling the writing and reading of the page memory while sending the command signal to the FIFO memory 17 and controlling the writing and reading to the FIFO memory 17 is provided. Functions as an interface for accessing the page memory 13 , And a delay processing function to adjust by using the FIFO memory 17 or the page memory 13 the time difference between the different color component signals of the type for the same pixel.

  The memory control unit 14j includes a timing control unit 14d that generates a page memory control signal for controlling the page memory 13, an address control unit 14e that generates an address signal to be supplied to the page memory 13, and a FIFO memory controller connection unit 14a. And a data buffer circuit section 14f interposed between the page memory connection section 14b. Then, it is determined whether or not the page memory is connected to the page memory connection unit 14b and the FIFO memory 17 is connected to the FIFO memory connection unit 14k. When the page memory is connected, the time from the color image sensor 11 is determined based on the command signal. The color component signals sent in series are sequentially written in the page memory 11 while changing the address signals sent to the page memory in a predetermined order, and then a delay processing operation for reading out from the page memory 11 is performed cyclically. On the other hand, when the FIFO memory 17 is connected, writing and reading of the FIFO memory 17 are controlled according to the FIFO memory controller 12, thereby adjusting the time difference between the different color component signals for the same pixel. Send to processing circuit. It should be noted that the presence / absence of the page memory and the FIFO memory 17 may be determined automatically, or a control register or the like may be further provided, and a predetermined code may be set therein to notify from the outside.

  Next, an example in which the delay processing operation when the page memory 13 is connected to the memory controller 14 is simplified will be described. Here, in order to simplify the explanation, it is assumed that the word serving as a unit of access is 8 bits, and the data width of the color component signals of R, G, and B is 8 bits. In the color imaging device, it is assumed that R, G, and B line sensors are arranged every four lines in that order, and one line includes one pixel. In this case, the R color component signal is output for eight lines ahead of the B color component signal for the same pixel, and the G color component signal is the time difference of four lines (with respect to the B color component signal). Output four lines ahead).

FIG. 2 is a map for explaining the setting of various areas in the page memory 13.
In the area on the lower address side of the page memory 13, there is a color classification page area section 13a for temporarily accumulating and storing color component signals corresponding to each pixel constituting one image according to each color type. Is set. Such a color classification page area part 13a may be prepared for a plurality of images. In addition, there is a surplus area on the higher address side, and color classification for temporarily storing the color component signals transmitted in time series from the color image pickup device 11 according to the respective color types. A time difference adjustment area 13b is set. Specifically, the color division time difference adjustment area for R is, for example, an area for 10 lines from address value R-1 to address value R-10, and the color division time difference adjustment area for G is, for example, address value G This is an area for 10 lines from -1 to the address value G-10.

  FIG. 3 is a timing diagram for explaining a basic example of the delay processing operation. The command signals wrstR, rrstR, wrstG, rrstG, the R color component signal transmitted from the color image sensor, the G color component signal, A color component signal of B, an address value of an address for the page memory 13, a signal r / w (read / write) which is a control signal for controlling the page memory 13, and the contents of write and read data to the page memory 13 are shown. .

  Here, the timing control unit 14d generates de (data enable) or the like based on a command signal such as the signal wrstR, for example, and the address control unit 14e uses R-1 to R as address values to be supplied to the page memory 13. Each value of −10 and each value from G−1 to G−10 are cyclically selected in a predetermined order.

  Specifically, the address values R-1, R-2,..., R-10 are designated each time an R color component signal is transmitted from the color image sensor 11 after receiving the signal wrstR. Then, the transmitted R color component signal is written into the page memory 13, and each time the R color component signal is transmitted from the color image sensor 11 after receiving the signal rrstR, the address value R- 1, R-2,..., R-10 are designated and the R color component signal is read from the page memory 13. Here, the signal rrstR is output with a delay of 8 lines from the output of the signal wrstR. In addition, every time a color component signal of G is transmitted from the color image sensor 11 after receiving the signal wrstG, the address values G-1, G-2,..., G-10 are designated and transmitted. The received G color component signal is written into the page memory 13 and each time the G color component signal is transmitted from the color image sensor 11 after receiving the signal rrstG, the address values G-1, G -2,..., G-10 are designated, and the G color component signal is read from the page memory 13. Here, the signal wrstR is output with a delay of 4 lines after the output of the signal wrstR. Further, the signal rrstR is outputted with a delay of 4 lines from the output of the signal wrstR.

  Accordingly, in such a delay processing operation, the G color component signal is delayed by 8 lines, and the G color component signal is delayed by 4 lines. As a result, for the same pixel, R , G, B color component signals are synchronized.

  The R and G color component signals read from the page memory 13 may be directly transferred from the memory controller to the image processing circuit 16 or may be transferred to the image processing circuit 16 via the FIFO memory controller. Good.

  As described above, in the present invention, the memory controller 14 is connected to the FIFO memory controller 12 and the page memory 13 is controlled based on the command signal received from the FIFO memory controller 12. It is very easy to change the circuit from the configuration in which the FIFO memory 17 is mounted to the configuration in which the page memory 13 is mounted, and the development cost can be suppressed.

Next, a modification of the present invention will be described with reference to the drawings.
FIG. 4 is a circuit block diagram of a color component signal processing system of an image processing apparatus including a memory controller according to a modification. In the following, the same components as those in FIG.

  Each of the input / output data buffer circuits 14f constituting the memory control unit 14j is composed of a three-stage shift register. The input / output data buffer circuit 14f has a function of simultaneously outputting data input in time series, or a time series of data input simultaneously. It has a function to output automatically.

Reference numeral 14g denotes an input selection circuit that selects either the address signal generated by the address control unit 14d or the address signal sent from the image processing circuit 16 via the local bus.
Reference numeral 14h denotes a color component signal of each pixel that forms one image sent from the image processing circuit 16 via the local bus as data to be written to the page memory 13, and an input data buffer circuit 14f for R. 3 is an input selection circuit that selects either the R color component signal for three pixels held in the G and the G color component signal for three pixels held in the G input data buffer circuit 14f.
Reference numeral 14i denotes a selection circuit that selects any one of the local bus, the R output data buffer circuit 14f, and the G output data buffer circuit 14f as an output destination of the data read from the page memory 13. . The R and G color component signals for three pixels simultaneously read from the page memory 13 are held in the R and G output data buffer circuits 14f, respectively, and are extracted in time series for each pixel.

  In the page memory 13, the color component signal corresponding to each pixel constituting one image is classified into each color type and temporarily accumulated and stored, and from the color image sensor. A color division time difference adjustment area unit 13b is provided in advance to divide the color component signals sent in series into respective color types and temporarily store and store them. Further, in the color classification time difference adjustment area 13b, the same address value is set for each color component signal of the same pixel in a predetermined word unit including at least one pixel. For example, in one word data assigned to one address value, R color component signals for three pixels or G color component signals for three pixels are stored together.

FIG. 5 is a diagram for explaining the delay processing operation in this modification, and the order of writing and reading the R and G color component signals sent from the color image sensor 11 in time series to the page memory 13. Is shown. The memory controller 14 performs the delay processing operation by cyclically changing the address value of the address signal sent to the page memory 13 in a predetermined order.
That is, in writing, the R color component signal and the G color component signal are collectively written into the page memory as one word of data for three pixels each. Here, after the R color component signal is accumulated for 8 lines and the G color component signal is accumulated for 4 lines, the address value is selected so as to return to the beginning, and writing is performed cyclically.
On the other hand, in the read operation, the R color component signal and the G color component signal before being overwritten are read out immediately before the R color component signal and the G color component signal written in the page memory 13 are overwritten by circulation. Then, in combination with the B component sent from the color image pickup device 11 at that time, it is transferred to the image processing circuit. In this way, the R color component signal is delayed for 8 lines, and the G color component signal is delayed for 4 lines.

Further, other modifications will be described with reference to the drawings.
FIG. 6 is a circuit block diagram of a color component signal processing system of an image processing apparatus including a memory controller which is another modification. In the following, the same components as those in FIG.

Here, the input / output data buffer circuit 14f constituting the memory control unit 14j is constituted by a register.
Reference numeral 14g denotes an input selection circuit that selects either the address signal generated by the address control unit 14d or the address signal sent from the image processing circuit 16 via the local bus.
Reference numeral 14h denotes a color component signal of each pixel and input data for R and G constituting one image sent from the image processing circuit 16 via the local bus as data to be written to the page memory 13. This is an input selection circuit that selects one of the R and G color component signals held in the buffer circuit 14f. Reference numeral 14i denotes a selection circuit that selects either the local bus or the output data buffer circuit 14f for R and G as an output destination of data read from the page memory 13.

  The page memory 13 is composed of three memory elements and is supplied with a common address signal, but writing and reading can be controlled for each element. Further, the page memory 13 includes a color classification page area section 13a for temporarily accumulating and storing color component signals corresponding to the respective pixels constituting one image according to the respective color types, and the color image sensor 11. A color segment time difference adjustment area unit 13b is set in advance for classifying the color component signals sent in time series from the above into respective color types and temporarily storing and storing them. Further, in the color classification time difference adjustment area 13b, the same address is set for each color component signal of the same pixel in a predetermined word unit including at least one pixel.

  FIG. 7 is a diagram for explaining an example of the delay processing operation in this modified example, and shows the order of writing and reading of the color component signals sent from the color image sensor 11 in time series to the page memory 13. Yes. The memory controller 14 performs the delay processing operation by cyclically changing the address signal transmitted to the page memory 13 in a predetermined order.

That is, in writing, the R color component signal and the G color component signal sent simultaneously from the color image sensor 11 are combined and written to the page memory 13 as word data having the same address value. For each of the R and G color component signals, eight lines are set as the color division time difference adjustment area, and the memory controller returns to the beginning when writing the R and G color component signals for eight lines. To control.
On the other hand, in reading, at the timing immediately before the written R color component signal is further overwritten, the R color component signal before being overwritten, and the G color that is 4 lines behind the R color component signal. (For example, read the R color component signal of the address value R-1 and the G color component signal of the address value G-5), and send the B color signal sent at this timing Transfer in combination with the color component signal. In this way, the R color component signal is delayed for 8 lines, and the G color component signal is delayed for 4 lines.

FIG. 8 is a diagram for explaining another example of the delay processing operation in this modification.
In writing, the R and G color component signals sent simultaneously from the color image sensor 11 are written in the page memory 13 as word data at different addresses. That is, the address value of the word to which the G color component signal is written is four lines behind the address value of the word to which the R color component signal is written. Note that both the R and G color component signals are controlled to return to the beginning when 8 lines are written.
On the other hand, in reading, at the timing immediately before the written R color component signal is further overwritten, the R color component signal before being overwritten and the G color component signal are simultaneously read as word data of the same address value. The data is transferred in combination with the B component sent at this timing. In this way, the R color component signal is delayed for 8 lines, and the G color component signal is delayed for 4 lines.

It is a schematic block diagram explaining the partial structure which applied this invention to the image processing apparatus. It is a memory map figure explaining the area allocation of a page memory. It is a timing diagram for explaining a delay processing operation. It is a circuit block diagram of an image processing apparatus including a memory controller which is a modification. It is drawing for demonstrating the delay processing operation | movement in a modification. It is a circuit block diagram of the color component signal processing system of the image processing apparatus including the memory controller which is another modification. It is a figure for demonstrating an example of the delay processing operation | movement in another modification. It is a figure for demonstrating the other example of the delay processing operation | movement in another modification. It is a schematic diagram of a color image sensor. It is a schematic block diagram of the imaging signal processing system from the color image sensor of the conventional image processing apparatus to the image processing circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Color imaging device 12 FIFO memory controller part 13 Page memory 13a Color division page area part 13b Color division time difference adjustment area part 14 Memory controller 14a FIFO command input part 14b Page memory connection part 14c Image processing circuit connection part 14j Memory control part 17 FIFO memory

Claims (3)

A memory controller for controlling a page memory that temporarily stores and holds pixel information,
A page memory connection connected to the page memory;
A FIFO memory connection connected to the FIFO memory;
An image processing circuit connection unit connected to the image processing circuit;
A FIFO command input unit for receiving a command signal from the FIFO memory controller connected to the FIFO memory controller to which the color image sensor is connected;
An address signal, a write / read signal are sent to the page memory at a predetermined timing to control writing / reading of the page memory, while a command signal is sent to the FIFO memory to write to the FIFO memory, A memory control unit for performing read control,
The memory control unit
It is determined whether or not a page memory is connected to the page memory connection unit and a FIFO memory is connected to the FIFO memory connection unit. While sequentially sending the color component signal sent out to the page memory while changing the address signal sent to the page memory in a predetermined order, the delay processing operation for reading out from the page memory is performed cyclically, When the FIFO memory is connected, the time difference of the different color component signals for the same pixel is adjusted by controlling the writing and reading of the FIFO memory based on the command signal to the image processing circuit. A memory controller that sends data. In claim 1,
In the page memory, the color component signal corresponding to each pixel constituting the image information is classified into each color type, and a color classification page area unit for temporarily storing and storing the color information,
A color component time difference adjustment area for temporarily storing and storing the color component signals transmitted in time series from the color image sensor in respective color types; and
In the color classification time difference adjustment area part, the same address is set for a color component signal of the same pixel in a predetermined word unit including at least one pixel,
The memory controller is configured to perform the delay processing operation by cyclically changing an address signal transmitted to the page memory in a predetermined order. In claim 1,
The page memory is configured to be divided into color types of color component signals corresponding to each pixel constituting image information,
Each page memory divided into color component signal types includes a color division page area part for temporarily accumulating and storing color component signals corresponding to each pixel constituting image information, and a time from the color image sensor. It is configured to temporarily store and save the color component signals sent out in series,
The memory controller performs the delay processing operation by cyclically changing the address signal together with an enable signal for designating the page memory in a predetermined order.

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