JP2014107662A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a tolerance to surge voltage while keeping a low parasitic capacitance of a gate and maintaining high speed switching performance.SOLUTION: When an off driving signal turns a FET 5 off, a surge voltage occurs to bring a drain-source voltage VDS of the FET 5 to or above a protective voltage Vm1. Meanwhile, a detection voltage by a first voltage detection circuit 6A becomes higher than a threshold voltage Vth to turn a FET 13 off and a FET 14 on in a control circuit 9, which in turn turns a FET 11 off to bring a switch circuit 8 to a high impedance. A detection voltage by a second voltage detection circuit 6B later raises a gate voltage VGS of the FET 5 to or above a gate threshold voltage via a diode 15. The FET 5 then shoots through to release energy of the surge voltage to a source side.

Description

  The present invention relates to a semiconductor device having an increased overvoltage capability.

  Of course, inductance elements such as coils are often inductive due to the presence of wiring inductance, etc., even with resistive loads. If the transistor drives such an inductive load, a back electromotive force is generated when turning off. In a load driving circuit, a switching power supply circuit, an inverter circuit, and the like, a reflux diode is provided in parallel with a transistor or a load in order to prevent generation of a counter electromotive force. However, even in this case, since a surge voltage is generated due to switching, a means for protecting the transistor from the surge voltage is required.

  Patent Document 1 discloses a protection circuit in which a Zener diode group is connected between the gate and drain of a MOSFET, and the Zener diode group breaks down when a surge voltage is applied to the drain. In order to suppress an increase in gate voltage due to breakdown, a Zener diode group is also connected between the gate and source of the MOSFET.

JP 2000-77537 A

  When a Zener diode is connected between the gate and the drain and between the gate and the source as in the protection circuit described above, parasitic capacitance is added to the gate, and the switching speed is reduced. A semiconductor device having an AlGaN / GaN junction (hereinafter referred to as a GaN-HEMT) has a much lower on-resistance than a conventional Si device and is excellent in current interruption characteristics. Application to circuits is expected.

  However, since the GaN-HEMT having a high DC transfer conductance gm has a small gate capacitance of the device itself (for example, about 1/4 of the conventional element), it is more susceptible to parasitic capacitance than the conventional semiconductor element. Since GaN-HEMT has a low gate threshold (for example, about 2V) and a low gate breakdown voltage (for example, about 5V), it is difficult to take measures to increase the gate voltage and improve the switching speed.

  Further, since a conventional Si device, for example, a MOS transistor has an avalanche resistance, even if a voltage exceeding the breakdown voltage is applied between the drain and the source, it does not fail until a certain energy is reached. On the other hand, since GaN-HEMT does not have an avalanche resistance, even a small amount cannot exceed the breakdown voltage.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of increasing a withstand voltage against a surge voltage while keeping a parasitic capacitance of a gate low and maintaining a high-speed switching performance.

  The semiconductor device according to claim 1 is a first switching element that changes a conduction state between the second terminal and the first terminal in accordance with a gate voltage applied between the gate terminal and the first terminal. A voltage detection circuit, a second voltage detection circuit, a switch circuit, a unidirectional element, and a control circuit are added. Here, the first terminal corresponds to a source or emitter, the second terminal corresponds to a drain or collector, and the switching element is an insulated gate semiconductor element such as a GaN-HEMT, MOSFET, or IGBT.

  The first and second voltage detection circuits each output a detection voltage corresponding to a voltage applied between the second terminal and the first terminal of the switching element. The switch circuit is provided in series with a gate drive line connected to the gate terminal of the switching element, and switches to a high impedance state or a low impedance state according to a control signal. The unidirectional element is connected between the output terminal of the second voltage detection circuit and the gate terminal of the switching element, and allows a current to flow from the output terminal to the gate terminal.

  The control circuit has a threshold voltage. The threshold voltage is a first detection output from the first voltage detection circuit when a voltage in a range in which the voltage protection operation of the switching element is to be performed is applied between the second terminal and the first terminal of the switching element. It is set lower than the voltage. The voltage in the range where the voltage protection operation is to be performed includes at least a voltage exceeding the withstand voltage of the switching element. Further, the threshold voltage is output by the first voltage detection circuit when a voltage in a range in which the voltage protection operation of the switching element should be unnecessary is applied between the second terminal and the first terminal of the switching element. Is set higher than the first detection voltage. The voltage in the range where the voltage protection operation is not required is a voltage lower than the withstand voltage of the switching element and does not need to protect the switching element at all.

  The control circuit outputs a control signal for switching the switch circuit to a low impedance state when the first detection voltage becomes equal to or lower than the threshold voltage. As a result, the drive signal is applied to the gate terminal through the switch circuit, and the switching element is turned on and off in accordance with the drive signal. On the other hand, when the first detection voltage exceeds the threshold voltage due to generation of a surge voltage, the control circuit outputs a control signal for switching the switch circuit to a high impedance state. As a result, the gate terminal of the switching element is cut off and enters a high impedance state.

  The gate voltage after being cut off increases toward a potential determined by the voltage applied between the second terminal and the first terminal and the gate capacitance (for example, the gate-drain capacitance and the gate-source capacitance). Start. In parallel with this, the second detection voltage output from the second voltage detection circuit reliably guides the switching element to self-turn-on.

  The voltage dividing ratio of the second voltage detection circuit is such that when a voltage in a range in which a voltage protection operation is to be performed is applied between the second terminal and the first terminal of the switching element, the second detection voltage is the gate of the switching element. It is set to be higher than the voltage obtained by adding the threshold voltage and the energization voltage of the unidirectional element. Further, the voltage dividing ratio of the second voltage detection circuit is such that when the first detection voltage is equal to or lower than the threshold voltage of the control circuit, the second detection voltage is the gate threshold voltage of the switching element and the energization voltage of the unidirectional element. It is set to be lower than the voltage obtained by adding.

  According to this setting, when the voltage between the second terminal and the first terminal of the switching element rises rapidly, the first detection voltage first exceeds the threshold voltage and the switch circuit enters a high impedance state. Thereafter, the gate voltage is raised above the gate threshold voltage through the unidirectional element by the second detection voltage, and the switching element is turned on. According to this order, the second detection voltage does not turn on the switching element when the switch circuit is in the low impedance state.

  When the switching element self-turns on, the energy of the surge voltage is released through the switching element, and the voltage between the second terminal and the first terminal of the switching element is equal to or lower than the element withstand voltage and corresponds to the second detection voltage. Limited. While the energy of the surge voltage is released, the voltage is balanced in a state where the voltage between the second terminal and the first terminal does not increase.

  When the release of energy ends, the voltage between the second terminal and the first terminal starts to decrease, and the first detection voltage and the second detection voltage also start to decrease. At this time, first, the second detection voltage becomes lower than the voltage obtained by adding the gate threshold voltage of the switching element and the energization voltage of the unidirectional element, and the second detection voltage cannot drive the gate on. However, as long as the switch circuit maintains a high impedance state, the switching element is kept on. Thereafter, when the first detection voltage falls below the threshold voltage of the control circuit, the switch circuit enters a low impedance state and returns to the switching operation according to the drive signal.

  According to this means, since there is no (or small) parasitic capacitance added to the gate of the switching element, it is possible to increase the resistance to surge voltage applied between the second terminal and the first terminal while maintaining high-speed switching performance. be able to. In addition, when a voltage in a range in which a voltage protection operation is to be performed is applied to the switching element, the switching element can be reliably self-turned on.

  According to the means of claim 2, the first voltage detection circuit is connected in series between the second terminal of the switching element and the first terminal with the output terminal of the first detection voltage interposed therebetween. And the second circuit. The second voltage detection circuit includes a third circuit and a fourth circuit that are connected in series between the second terminal and the first terminal of the switching element, with the output terminal of the second detection voltage interposed therebetween.

  Since the first to fourth circuits according to claims 3 and 4 also serve as a C snubber or an RC snubber, respectively, an effect of suppressing a surge voltage can be obtained and the number of components and a mounting space can be saved. Since the first to fourth circuits according to the fifth and sixth aspects further include a resistor in parallel, the voltage dividing ratio is easily determined, and the voltage can be detected more accurately and reliably.

  8. The first voltage detection circuit and the second voltage detection circuit according to claim 7, wherein the first and second voltage detection circuits are shared between the second circuit and the fourth circuit and the first terminal of the switching element. It has. The common circuit is obtained by sharing a part of the capacity of the second circuit and the capacity of the fourth circuit used for voltage division. As a result, the total capacitance value of the first and second voltage detection circuits can be reduced and the relative error between the first detection voltage and the second detection voltage can be reduced compared to a configuration that does not use a common circuit. Can do. The common circuit according to claim 8 has the same configuration as the first circuit and the second circuit or the third circuit and the fourth circuit with respect to the connection configuration of the capacitor and / or the resistor.

  The semiconductor device according to claim 9 has a configuration similar to that of the semiconductor device according to claim 1, but includes only one voltage detection circuit, and the output voltage is obtained by switching the impedance state of the switch circuit. The difference is that it contributes to both self-turn-on of the switching element. Between the output terminal of the voltage detection circuit that outputs the first detection voltage and the gate terminal of the switching element, a unidirectional element that allows current to flow from the output terminal to the gate terminal is connected. The threshold voltage of the control circuit is lower than the voltage obtained by adding the gate threshold voltage of the switching element and the energization voltage of the unidirectional element in addition to the conditions of the semiconductor device according to claim 1. Is set to

  According to this configuration, the control circuit switches the switch circuit to the high impedance state when the first detection voltage exceeds the threshold voltage due to generation of a surge voltage or the like. As a result, the gate terminal of the switching element is cut off and enters a high impedance state. The gate voltage after being cut off increases toward a potential determined by the voltage applied between the second terminal and the first terminal and the gate capacitance (for example, the gate-drain capacitance and the gate-source capacitance). Start. In parallel with this, the first detection voltage output from the voltage detection circuit reliably guides the switching element to self-turn-on.

  When the voltage between the second terminal and the first terminal of the switching element rises rapidly, the switch circuit first enters a high impedance state. Thereafter, the unidirectional element is energized by the first detection voltage, the gate voltage is raised above the gate threshold voltage, and the switching element is surely self-turned on. According to this order, the first detection voltage does not turn on the switching element when the switch circuit is in the low impedance state. The operation after the self-turn-on is the same as that of the semiconductor device described in claim 1. According to this means, the same effect as that of the means described in claim 1 can be obtained. In addition, since only one voltage detection circuit is required, the configuration can be further simplified.

  According to a tenth aspect of the present invention, the voltage detection circuit includes a first circuit and a second circuit that are connected in series with the output terminal interposed between the second terminal and the first terminal of the switching element. ing. Since the first circuit and the second circuit according to the eleventh aspect are each composed of a resistor, the voltage can be detected accurately and reliably.

  The first circuit and the second circuit according to claim 12 are configured by an energization circuit that shifts to an energized state when the applied voltage exceeds a specified voltage, and therefore the detected voltage is the specified voltage of the second circuit in the energized state. Therefore, the protection operation can be performed under a stable detection voltage.

  According to the means of claim 13, the energization circuit is composed of one or more semiconductor elements selected from a diode, a Zener diode, a MOS transistor and a bipolar transistor, and its forward voltage, Zener voltage, The specified voltage is constituted by a threshold voltage or a combination of the voltages. This increases the degree of freedom in generating the specified voltage.

  According to the means of the fourteenth aspect, the control circuit includes an inverter circuit configured by the transistor having the threshold voltage between the power supply lines for supplying the DC voltage necessary for outputting the control signal. Yes. By applying the first detection voltage to the gate of this transistor, the impedance state of the switch circuit can be controlled.

  According to the means of claim 15, the switching element is a GaN device. A GaN device such as a GaN-HEMT has characteristics that it has no avalanche resistance, a low gate breakdown voltage, and a small gate capacitance of the element itself. If each of the above-described means is applied to a GaN device, it is possible to increase the withstand voltage against surge voltage without substantially reducing the switching speed. As a result, a voltage exceeding the element breakdown voltage may be applied, and the GaN device can be applied even in a circuit environment that requires high-speed switching, for example, a circuit that cuts off an inductive load.

The block diagram of the load drive device which shows 1st Embodiment Waveform diagram Equivalent circuit of input capacitance added to the gate of switching element FIG. 1 equivalent diagram showing the second embodiment FIG. 1 equivalent view showing the third embodiment FIG. 1 equivalent view showing the fourth embodiment FIG. 1 equivalent diagram showing the fifth embodiment FIG. 1 equivalent view showing the sixth embodiment FIG. 1 equivalent diagram showing a seventh embodiment FIG. 1 equivalent diagram showing the eighth embodiment FIG. 1 equivalent view showing the ninth embodiment FIG. 1 equivalent diagram showing the tenth embodiment FIG. 1 equivalent diagram showing the eleventh embodiment FIG. 1 equivalent diagram showing the twelfth embodiment FIG. 1 equivalent view showing the thirteenth embodiment FIG. 1 equivalent diagram showing the fourteenth embodiment 3 equivalent figure FIG. 1 equivalent diagram showing the fifteenth embodiment

  In each embodiment, parts that are substantially the same as the configurations of the above-described embodiments are assigned the same reference numerals, and descriptions thereof are omitted. In addition, each of the second and subsequent embodiments has basically the same operations and effects as those of the first embodiment except for the operations and effects based on the configuration unique to each of the embodiments.

(First embodiment)
Hereinafter, a first embodiment will be described with reference to FIGS. 1 to 3. The load driving device 1 (corresponding to a semiconductor device) is used in, for example, an electronic control device mounted on a vehicle, and performs an on / off operation in accordance with a driving signal input from an external circuit (not shown), whereby battery voltage A current is passed through the coil 2 which is an inductive load that has been supplied with VB. The load driving device 1 includes an element module 3 and a driving IC 4.

  The element module 3 is configured by molding an N-channel FET 5 and first and second voltage detection circuits 6A and 6B in one package. The FET 5 conducts between the drain terminal D (corresponding to the second terminal) and the source terminal S according to the gate voltage VGS applied between the gate terminal G and the source terminal S (corresponding to the first terminal). It is a switching element such as a MOSFET or GaN-HEMT that changes the state. An IGBT may be used instead of the FET. A parasitic diode 5 a is formed in the FET 5.

  The first voltage detection circuit 6A is composed of capacitors C1 and C2 (corresponding to a first circuit and a second circuit) connected in series with an output terminal n1A sandwiched between the drain and source of the FET5. These capacitors C1 and C2 output a first detection voltage obtained by dividing the voltage applied between the drain and source of the FET 5 and function as a C snubber. The capacitance value of the capacitor C1 is smaller than the capacitance value of the capacitor C2, and is set to a ratio of about C1: C2 = 1: (5 to 500), for example.

  The second voltage detection circuit 6B includes capacitors C3 and C4 (corresponding to a third circuit and a fourth circuit) connected in series with the output terminal n1B sandwiched between the drain and source of the FET 5. These capacitors C3 and C4 output a second detection voltage obtained by dividing the voltage applied between the drain and source of the FET 5 and function as a C snubber. The capacitance value of the capacitor C3 is smaller than the capacitance value of the capacitor C4, and is set to a ratio of about C3: C4 = 1: (5 to 500), for example.

  The drive IC 4 includes a drive circuit 7, a switch circuit 8, a control circuit 9, and a diode 15. The drive circuit 7 has a common ground potential with the source potential of the FET 5 and outputs a gate drive signal (hereinafter simply referred to as a drive signal) to the FET 5 in accordance with a drive signal input from an external circuit such as a microcomputer. The switch circuit 8 includes an N-channel MOSFET 11 provided in series with a gate drive line 10 connected to the gate of the FET 5. In the MOSFET 11, a parasitic diode 11 a is formed in parallel in the forward direction in the direction reaching the gate of the FET 5 through the gate drive line 10.

  The control circuit 9 includes an inverter circuit including a P-channel type MOSFET 13 and an N-channel type MOSFET 14 that are connected between the terminals of the power supply 12 with the output terminal n2 interposed therebetween. Parasitic diodes 13a and 14a are formed in the MOSFETs 13 and 14, respectively. The element size of the MOSFETs 13 and 14 may be an element size sufficient to drive the MOSFET 11, and a small element size is sufficient.

  The gates of the MOSFETs 13 and 14 are connected to the output terminal n1A of the first voltage detection circuit 6A. The output terminal n2 is connected to the gate of the MOSFET 11 and supplies a control signal. The DC voltage Vc supplied by the power supply 12 may be a voltage necessary for outputting a control signal for turning on / off the MOSFET 11. A diode 15 (corresponding to a unidirectional element) is connected between the output terminal n1B of the second voltage detection circuit 6B and the gate of the FET 5 to flow current from the output terminal n1B to the gate.

Next, the operation of the present embodiment will be described with reference to FIGS. The first voltage detection circuit 6A outputs the first detection voltage represented by the equation (1) with respect to the drain-source voltage VDS of the FET 5.
First detection voltage = (C1 / (C1 + C2)) · VDS (1)

The control circuit 9 has a threshold voltage Vth used for the voltage protection operation of the FET 5. In order to reliably protect the FET 5 from a voltage exceeding the withstand voltage VDSS, the voltage range in which the voltage protection operation of the FET 5 is to be performed is set to a range equal to or higher than the voltage Vm1 set lower than the withstand voltage VDSS of the FET 5 by a predetermined margin. The threshold voltage Vth is set lower than the detection voltage output by the first voltage detection circuit 6A when a voltage in a range where the voltage protection operation is to be performed is applied between the drain and source of the FET 5. This can be expressed by equation (2).
Vth <(C1 / (C1 + C2)). Vm1 <(C1 / (C1 + C2)). VDSS (2)

On the other hand, the voltage protection operation of the FET 5 is set within a voltage range lower than the voltage Vm2 set higher by a predetermined margin than the battery voltage VB applied to the load driving device 1 (a range lower than the voltage range in which the voltage protection operation is to be performed). Is a range that should be unnecessary. The threshold voltage Vth is set higher than the detection voltage output from the first voltage detection circuit 6A when a voltage in a range where the voltage protection operation is not required is applied between the drain and source of the FET 5. Yes. This can be expressed by equation (3).
Vth> (C1 / (C1 + C2)). Vm2> (C1 / (C1 + C2)). VB (3)

  The threshold voltages of the elements of the MOSFETs 13 and 14 constituting the control circuit 9 are set equal to the threshold voltage Vth, and an appropriate DC voltage Vc is set accordingly.

The second voltage detection circuit 6B outputs the second detection voltage expressed by the equation (4) with respect to the drain-source voltage VDS of the FET 5.
Second detection voltage = (C3 / (C3 + C4)) · VDS (4)

  The voltage dividing ratio of the second voltage detection circuit 6B is such that when the first detection voltage is less than or equal to the threshold voltage Vth of the control circuit 9, the second detection voltage is the gate threshold voltage Vth (FET) of the FET 5 and the diode 15 It is set to be lower than the voltage (= Vth (FET) + Vf) obtained by adding the forward voltage Vf (energization voltage). Further, the voltage division ratio of the second voltage detection circuit 6B is set so that the second detection voltage is higher than Vth (FET) + Vf when a voltage in the range of the voltage Vm1 or higher is applied to the FET 5.

  FIG. 2 is a waveform diagram showing the drain current ID, the drain-source voltage VDS, and the gate voltage VGS of the FET 5. In a period T1 from time t1 to t2, an off drive signal is input and the FET 5 is off. In a period T2 from time t2 to t3, an ON drive signal is input, and the FET 5 is ON. The drain-source voltage VDS of the FET 5 in the periods T1 and T2 is the battery voltage VB, which is approximately 0 V (strictly, a voltage determined by the relationship between the on-resistance of the FET 5 and the drain current ID).

  Since the voltage applied to the element module 3 in the periods T1 and T2 is at most the voltage Vm2, the detection voltage output from the first voltage detection circuit 6A is lower than the threshold voltage Vth. Therefore, the MOSFET 13 is turned on and the MOSFET 14 is turned off, and the voltage Vc is applied to the gate of the MOSFET 11 via the MOSFET 13. As a result, the MOSFET 11 is turned on, and the switch circuit 8 connects the drive circuit 7 and the gate of the FET 5 with a low impedance. On the other hand, the detection voltage output from the second voltage detection circuit 6B is lower than Vth (FET) + Vf as described above. Therefore, the FET 5 performs a normal switching operation according to the drive signal.

  When an off drive signal is input at time t3 and the FET 5 is turned off, a surge voltage (including the back electromotive force itself) due to the back electromotive force is generated, and the drain-source voltage VDS of the FET 5 becomes equal to or higher than the voltage Vm1. At this time, the detection voltage output by the first voltage detection circuit 6A is equal to or lower than the gate breakdown voltage of the MOSFETs 13 and 14, and is higher than the threshold voltage Vth. Therefore, the MOSFET 13 is turned off, the MOSFET 14 is turned on, and the gate voltage VGS of the MOSFET 11 becomes 0V. As a result, the MOSFET 11 is turned off, and the switch circuit 8 interrupts the drive circuit 7 and the gate of the FET 5 with high impedance. Along with this, the gate of the FET 5 is in an open state.

Thereafter, the gate voltage VGS of the FET 5 starts to increase toward the voltage represented by the equation (5) based on the drain-source voltage VDS, the gate-drain capacitance CGD, and the gate-source capacitance CGS.
VGS = (CGD / (CGD + CGS)) · VDS (5)

  In parallel with the rising operation of the gate voltage VGS, the second detection voltage output from the second voltage detection circuit 6B leads the FET 5 to self-turn on. That is, according to the voltage dividing ratio of the second voltage detection circuit 6B described above, when the drain-source voltage VDS of the FET 5 rises to the voltage Vm1 or higher, the first detection voltage first becomes higher than the threshold voltage Vth. . Thereby, the switch circuit 8 becomes a high impedance state.

  Thereafter, the second detection voltage becomes higher than Vth (FET) + Vf. At this time, the gate voltage VGS applied to the FET 5 is below the gate breakdown voltage. As a result, the gate voltage VGS of the FET 5 is raised to the gate threshold voltage Vth (FET) or more through the diode 15, and the FET 5 is self-turned on. According to this order, the second detection voltage does not turn on the FET 5 when the switch circuit 8 is in the low impedance state.

  When the FET 5 is turned on, the energy of the surge voltage applied between the drain and source is released to the source side through the FET 5, and the drain-source voltage VDS is a voltage corresponding to the second detection voltage and not more than the element breakdown voltage. (For example, 600V). While the surge voltage energy is released, the drain-source voltage VDS is balanced without increasing. The gate voltage is also balanced at a voltage lower by Vf than the second detection voltage.

  When the release of energy ends at time t4, the drain-source voltage VDS starts to decrease, and the first detection voltage and the second detection voltage also start to decrease. At this time, the second detection voltage is initially lower than Vth (FET) + Vf, and the second detection voltage cannot drive the gate on. Even in this case, as long as the switch circuit 8 maintains the high impedance state, the FET 5 is kept on. Thereafter, when the first detection voltage falls below the threshold voltage Vth, the switch circuit 8 enters a low impedance state and returns to the switching operation according to the drive signal.

  In the above operation, the maximum value of the gate current of the FET 5 is about several A, but since the turn-on time / turn-off time through which the gate current flows is very short, the rated currents of the MOSFET 11 and the diode 15 may be small. Further, since the MOSFETs 13 and 14 drive the MOSFET 11, similarly small elements are sufficient. For this reason, the switch circuit 8 and the control circuit 9 can be configured with an element size sufficiently smaller than that of the FET 5.

  Capacitors C1 and C2 act to charge and discharge the gate capacitances of MOSFETs 13 and 14 in accordance with the detected voltage. Therefore, the capacitors C1 and C2 need to have a capacitance value that can sufficiently drive the gate capacitances of the MOSFETs 13 and 14. As an example, the capacitance values of the capacitors C1 and C2 are preferably set to be about 1 to 100 times the gate capacitance of the MOSFETs 13 and 14.

  Capacitors C3 and C4 have a function of charging the gate capacitance of FET 5 in accordance with the detected voltage and turning it on. Therefore, the capacitors C3 and C4 need to have sufficient capacitance values to guide the FET 5 to self-turn-on in parallel with the operation of increasing the gate voltage VGS according to the equation (5). For example, the capacitance values of the capacitors C3 and C4 are preferably set to be about 1 to 100 times the gate capacitance of the FET 5.

  The MOSFET 11 constituting the switch circuit 8 includes a parasitic diode 11a having the drive circuit 7 side as an anode and the FET 5 gate side as a cathode. Therefore, even when the switch circuit 8 is in the cut-off state, an ON drive signal having a positive voltage output from the drive circuit 7 can be applied to the gate of the FET 5 through the parasitic diode 11a. As a result, the FET 5 can be turned on with priority given to the ON drive signal from the drive circuit 7 regardless of the state of the switch circuit 8. In addition, when using IGBT or a bipolar transistor instead of MOSFET11, the same effect is acquired by attaching a parallel diode.

  According to the present embodiment, when the drain-source voltage VDS of the FET 5 becomes equal to or higher than the voltage Vm1 set lower than the element withstand voltage VDSS, the switch circuit 8 interposed in the gate drive line 10 is cut off and the gate of the FET 5 is opened. It becomes a state. Some conventional Si devices, such as MOS transistors, are difficult to self-turn on when the gate is open, but according to this embodiment, the FET 5 can be reliably self-turned on using the second detection voltage.

  Capacitors C 3 and C 4 are connected to the gate of the FET 5 through a diode 15. When the capacitance added to the gate of the FET 5 is represented by an equivalent circuit, it is as shown in FIG. Here, Ciss = Cgd + Cgs is an input capacitance of the FET 5, and Cd is a junction capacitance of the diode 15 when a reverse voltage is applied to the diode 15.

  As described above, since the rated current of the diode 15 is very small, Cd << C3 and C4. For this reason, when the capacitors C3 and C4 are viewed from the gate of the FET 5 via the diode 15, the equivalent capacitance value is a minute value substantially equal to the junction capacitance value of the diode 15. Further, a diode having a large rated current for escaping a surge is not connected to the gate of the FET 5. Therefore, the parasitic capacitance added to the gate is smaller than that in the conventional configuration, and the voltage resistance can be ensured while maintaining the high-speed switching performance (particularly the turn-on characteristic) of the FET 5.

  The load driving device 1 is particularly suitable for a FET 5 made of a GaN device, for example, a GaN-HEMT. GaN-HEMT does not have avalanche resistance (L load resistance), has a low gate breakdown voltage, and has a small gate capacitance of the element itself. According to the present embodiment, it is possible to increase the withstand capability against surge voltage without substantially reducing the switching speed. Of course, the present invention can also be applied to MOSFETs and IGBTs.

  Since the voltage detection circuits 6A and 6B have a C snubber configuration, dV / dt and ringing during turn-off can be suppressed, and the number of components and mounting space can be saved. Further, the voltage protection operation condition can be easily set based on the relationship between the capacitance ratio of the capacitors C1 and C2, the capacitance ratio of the capacitors C3 and C4, and the element breakdown voltage of the FET 5.

  The element module 3 may be configured by forming capacitors C1 to C4 on the same semiconductor substrate as the FET 5. Alternatively, the discrete component FET5 and capacitors C1 to C4 may be molded after being mounted on the substrate. Further, the FET 5, the capacitors C1 to C4, the switch circuit 8, the control circuit 9, and the diode 15 may be formed on the same semiconductor substrate. In this case, the drive circuit 7 can also be formed together. Further, only the capacitors C1 to C4 may be externally attached. In this way, the degree of freedom in circuit configuration is high and downsizing can be achieved.

(Second Embodiment)
A second embodiment will be described with reference to FIG. The driving IC 22 of the load driving device 21 includes a control circuit 23. The control circuit 23 includes an inverter circuit including a resistor 24 and a MOSFET 14 connected in series with an output terminal n2 between terminals of the power supply 12. The threshold voltage of the MOSFET 14 is set equal to the above-described threshold voltage Vth.

  When the surge voltage is not applied, the first detection voltage is lower than the threshold voltage Vth. For this reason, the MOSFET 14 is turned off, and the voltage Vc is applied to the gate of the MOSFET 11 via the resistor 24. On the other hand, when the surge voltage is generated and the drain-source voltage VDS of the FET 5 becomes equal to or higher than the voltage Vm1, the first detection voltage is lower than the gate breakdown voltage of the MOSFET 14 and higher than the threshold voltage Vth. As a result, the MOSFET 14 is turned on and the switch circuit 8 is cut off. Thereafter, the FET 5 is self-turned on by the rise of the gate voltage VGS shown in the equation (5) or the second detection voltage as described above.

  According to the present embodiment, since the control circuit 23 can be configured using one MOSFET 14, the circuit area can be further reduced. However, when the MOSFET 14 is turned on, a current flows from the power source 12 through a path via the resistor 24 and the MOSFET 14. However, the frequency with which the MOSFET 14 is turned on is low and the turn-on time is short, so that there is almost no increase in power consumption.

(Third embodiment)
A third embodiment will be described with reference to FIG. The driving IC 26 of the load driving device 25 includes a control circuit 27. The control circuit 27 includes an inverter circuit including a MOSFET 13 and a resistor 28 that are connected in series with the output terminal n2 between the terminals of the power supply 12. The MOSFET 13 is configured to be turned off when the first detection voltage exceeds the threshold voltage Vth.

  When the surge voltage is not applied, the first detection voltage is lower than the threshold voltage Vth. Therefore, the MOSFET 13 is turned on, and the voltage Vc is applied to the gate of the MOSFET 11 through the MOSFET 13. On the other hand, when a surge voltage is generated and the drain-source voltage VDS of the FET 5 becomes equal to or higher than the voltage Vm1, the first detection voltage is lower than the gate breakdown voltage of the MOSFET 13 and higher than the threshold voltage Vth. As a result, the MOSFET 13 is turned off and the switch circuit 8 is cut off. Thereafter, the FET 5 is self-turned on by the rise of the gate voltage VGS shown in the equation (5) or the second detection voltage as described above. According to the present embodiment, since the control circuit 23 can be configured using one MOSFET 13, the circuit area can be further reduced.

(Fourth embodiment)
A fourth embodiment will be described with reference to FIG. The load driving device 29 includes an element module 30 and a driving IC 4. The element module 30 includes an FET 5, a first voltage detection circuit 31A, and a second voltage detection circuit 31B.

  In the first voltage detection circuit 31A, a first circuit 31Aa composed of a series circuit of a resistor R1 and a capacitor C1 and a second circuit 31Ab composed of a series circuit of a resistor R2 and a capacitor C2 are arranged in series with an output terminal n1A interposed therebetween. It is equipped with the structure connected to. Similarly, in the second voltage detection circuit 31B, a third circuit 31Ba composed of a series circuit of a resistor R3 and a capacitor C3 and a fourth circuit 31Bb composed of a series circuit of a resistor R4 and a capacitor C4 are connected to the output terminal n1B. It has a configuration in which they are connected in series.

  The capacitance value of the capacitor C1 is smaller than the capacitance value of the capacitor C2, and is set to a ratio of about C1: C2 = 1: (5 to 500), for example. The resistance value of the resistor R1 is larger than the resistance value of the resistor R2, and is set to a ratio of, for example, R1: R2 = (5 to 500): 1. Similarly, the capacitance value of the capacitor C3 is smaller than the capacitance value of the capacitor C4, and is set to a ratio of, for example, C3: C4 = 1: (5 to 500). The resistance value of the resistor R3 is larger than the resistance value of the resistor R4, and is set to a ratio of about R3: R4 = (5 to 500): 1, for example.

  Since the first and second voltage detection circuits 31A and 31B of the present embodiment have an RC snubber configuration, the surge energy accumulated in the capacitors C1, C2, C3, and C4 is converted into resistors R1, R2, R3, and R4, respectively. The effect of further suppressing the voltage surge can be obtained. Further, since the resistors R1, R2, R3, and R4 are provided in series, the ripple current flowing through the capacitors C1, C2, C3, and C4 can be reduced.

  In this case, if the constants are set so that τ1 = C1 · R1≈C2 · R2 and τ2 = C3 · R3≈C4 · R4, the charge / discharge states of the first circuit 31Aa and the second circuit 31Ab, the third circuit 31Ba And the charge / discharge states of the fourth circuit 31Bb are equal to each other, and the voltage division ratio of the first voltage detection circuit 31A and the second voltage detection circuit 31B can be stabilized to a desired value.

  Furthermore, when τ1 = τ2, the time required for the first detection voltage and the second detection voltage to stabilize becomes equal, so that the state change of the switch circuit 8 when the surge voltage is applied and the self turn-on / off of the FET 5 The turn-off can be reliably performed according to the above-described order. If at least τ1 ≦ τ2 is set, the FET 5 can be turned on after the switch circuit 8 is in a high impedance state.

(Fifth embodiment)
A fifth embodiment will be described with reference to FIG. The load driving device 32 includes an element module 33 and a driving IC 4. The element module 33 includes an FET 5, a first voltage detection circuit 34A, and a second voltage detection circuit 34B.

  The first voltage detection circuit 34A includes a first circuit 34Aa and a second circuit 34Ab that are connected in series with the output terminal n1A interposed therebetween. The first circuit 34Aa and the second circuit 34Ab include resistors R5 and R6 in parallel with the first circuit 31Aa and the second circuit 31Ab (see FIG. 6) described above, respectively. Similarly, the second voltage detection circuit 34B includes a third circuit 34Ba and a fourth circuit 34Bb connected in series with the output terminal n1B interposed therebetween. The third circuit 34Ba and the fourth circuit 34Bb include resistors R7 and R8 in parallel with the third circuit 31Ba and the fourth circuit 31Bb (see FIG. 6), respectively.

  The capacitance ratio of the capacitors C1 and C2 and the resistance ratio of the resistors R1 and R2, and the capacitance ratio of the capacitors C3 and C4 and the resistance ratio of the resistors R3 and R4 are equal to those of the fourth embodiment. The resistance value of the resistor R5 is larger than the resistance value of the resistor R6, and is set to a ratio of about R5: R6 = (5 to 500): 1, for example. Similarly, the resistance value of the resistor R7 is larger than the resistance value of the resistor R8, and is set to a ratio of about R7: R8 = (5 to 500): 1, for example.

  Since the first and second voltage detection circuits 34A and 34B of the present embodiment also have an RC snubber configuration, the effect of further suppressing voltage surges can be obtained as in the fourth embodiment. Also, τ1 = C1 · R1≈C2 · R2, C2: C1≈R1: R2≈R5: R6, τ2 = C3 · R3≈C4 · R4, C4: C3≈R3: R4≈R7: R8 Is set, the charge / discharge states of the first circuit 34Aa and the second circuit 34Ab and the charge / discharge states of the third circuit 34Ba and the fourth circuit 34Bb are equal to each other, and the first voltage detection circuit 34A and the second voltage detection circuit 34B. Can be stabilized to a desired value. The operations and effects when τ1 = τ2 or τ1 ≦ τ2 are set are the same as in the fourth embodiment.

  In particular, since the balance resistors R5 to R8 are provided, the followability with respect to the voltage change is enhanced, and the voltage division ratio at the time of transition can be further stabilized. The resistance values of the resistors R5 to R8 may be determined based on the balance between stabilization of the voltage division ratio and resistance loss.

(Sixth embodiment)
A sixth embodiment will be described with reference to FIG. The load driving device 35 includes an element module 36 and a driving IC 4, and the element module 36 includes an FET 5, a first voltage detection circuit 37 </ b> A, and a second voltage detection circuit 37 </ b> B.

  In the first voltage detection circuit 37A, a first circuit 37Aa composed of a parallel circuit of a capacitor C1 and a resistor R5 and a second circuit 37Ab composed of a parallel circuit of a capacitor C2 and a resistor R6 are connected in series with an output terminal n1A interposed therebetween. It is equipped with the structure connected to. Similarly, in the second voltage detection circuit 37B, a third circuit 37Ba composed of a parallel circuit of a capacitor C3 and a resistor R7 and a fourth circuit 37Bb composed of a parallel circuit of a capacitor C4 and a resistor R8 are connected to the output terminal n1B. It has a configuration in which they are connected in series. The capacitance ratio of the capacitors C1 and C2 and the resistance ratio of the resistors R5 and R6 and the capacitance ratio of the capacitors C3 and C4 and the resistance ratio of the resistors R7 and R8 are set in the same manner as in the fifth embodiment.

  If constants are set so that C1: C2≈R6: R5 and C3: C4≈R8: R7, the charge / discharge states of the first circuit 37Aa and the second circuit 37Ab, and the charge / discharge state of the third circuit 37Ba and the fourth circuit 37Bb The discharge states become equal, and the voltage division ratio of the first voltage detection circuit 37A and the second voltage detection circuit 37B can be stabilized to a desired value. Further, by providing the balance resistors R5 to R8, the same effect as that of the fifth embodiment can be obtained.

(Seventh embodiment)
A seventh embodiment will be described with reference to FIG. The load driving device 38 includes an element module 39 and a driving IC 4. The element module 39 includes an FET 5, a first voltage detection circuit 40A, and a second voltage detection circuit 40B. The voltage detection circuits 40A and 40B respectively include a capacitor C5 as a common circuit between the common connection node n3 of the capacitors C2 and C4 and the source of the FET 5 with respect to the voltage detection circuits 6A and 6B of the first embodiment. Yes. The capacitor C5 has a part of the common capacitance among the capacitances that the capacitors C2 and C4 should have instead of the capacitors C2 and C4.

The voltage V3, the first detection voltage V1, and the second detection voltage V2 at the node n3 are expressed by the following equations (6), (7), and (8), respectively. Here, CA is a series combined capacitance value of the capacitors C1 and C2, and CB is a series combined capacitance value of the capacitors C3 and C4.
V3 = (CA + CB) / (CA + CB + C5) · VDS (6)
V1 = 1 / (C1 + C2) · (C1 · VDS + C2 · V3) (7)
V2 = 1 / (C3 + C4). (C3.VDS + C4.V3) (8)

  The threshold voltage Vth is based on the detection voltage V1 output from the first voltage detection circuit 40A when a voltage in a range in which a voltage protection operation should be performed (voltage Vm1 or higher) is applied between the drain and source of the FET 5. Is set too low. The threshold voltage Vth is output by the first voltage detection circuit 40A when a voltage in a range where a voltage protection operation is not required between the drain and the source of the FET 5 (voltage less than the voltage Vm2) is applied. It is set higher than the detection voltage.

  The voltage division ratio of the second voltage detection circuit 40B is set so that the second detection voltage V2 is lower than Vth (FET) + Vf when the first detection voltage V1 is equal to or lower than the threshold voltage Vth. The voltage dividing ratio of the second voltage detection circuit 40B is set such that the second detection voltage is higher than Vth (FET) + Vf when a voltage in the range of the voltage Vm1 or higher is applied to the FET 5.

  According to this embodiment, the same operation and effect as the first embodiment can be obtained. Furthermore, since the capacitor C5 is provided as a common circuit, the total capacitance values of the capacitors C2, C4, and C5 of this embodiment can be made smaller than the total capacitance values of the capacitors C2 and C4 of the first embodiment. The total capacitance values of the capacitors C1 to C4 (C5) can be similarly reduced. As a result, the element module 39 can be further reduced in size. In addition, since the relative capacitance error between the capacitors C2 and C4 is reduced, the relative error between the first detection voltage V1 and the second detection voltage V2 is also reduced, and the voltage detection accuracy is improved. .

(Eighth embodiment)
The eighth embodiment will be described with reference to FIG. The load driving device 41 includes an element module 42 and a driving IC 4, and the element module 42 includes an FET 5, a first voltage detection circuit 43 </ b> A, and a second voltage detection circuit 43 </ b> B. Between the node n3 and the source of the FET 5, a common circuit 44 shared by the voltage detection circuits 43A and 43B is provided. The configuration of the first circuit 43Aa to the fourth circuit 43Bb is the same as that of the first circuit 31Aa to the fourth circuit 31Bb shown in FIG. Similarly, the common circuit 44 includes a series circuit of a capacitor C5 and a resistor R9.

  The capacitance values of the capacitors C1 to C5 are set in the same manner as in the fourth and seventh embodiments. Each constant is preferably set so that τ1 = C1 · R1≈C2 · R2, τ2 = C3 · R3≈C4 · R4, and τ1 = τ2 (at least τ1 ≦ τ2), as in the fourth embodiment. . Furthermore, if τ3 = C5 · R9 is set so that τ1 = τ2 = τ3, the time required for the first detection voltage and the second detection voltage to be equalized becomes equal.

  According to this embodiment, the same operation and effect as those of the fourth and seventh embodiments can be obtained. In addition, the surge energy accumulated in the capacitor C5 can be consumed by the resistor R9, and the ripple current flowing in the capacitor C5 can be reduced.

(Ninth embodiment)
A ninth embodiment will be described with reference to FIG. The load driving device 45 includes an element module 46 and a driving IC 4. The element module 46 includes an FET 5, a first voltage detection circuit 47A, and a second voltage detection circuit 47B. Between the node n3 and the source of the FET 5, a common circuit 48 shared by the voltage detection circuits 47A and 47B is provided. The configurations of the first circuit 47Aa to the fourth circuit 47Bb are the same as those of the first circuit 34Aa to the fourth circuit 34Bb shown in FIG. Similarly, the common circuit 48 has a configuration in which a resistor R10 is connected in parallel to a series circuit of a capacitor C5 and a resistor R9.

  The capacitance values of the capacitors C1 to C5 and the resistance values of the resistors R1 to R4 are set in the same manner as in the fifth and eighth embodiments. As in the fifth embodiment, the constants are τ1 = C1 · R1≈C2 · R2, C2: C1≈R1: R2≈R5: R6, τ2 = C3 · R3≈C4 · R4, C4: C3≈R3: It is preferable to set R4≈R7: R8. Furthermore, if τ3 = C5 · R9 is set so that τ1 = τ2 = τ3, the time required for the first detection voltage and the second detection voltage to be equalized becomes equal.

  According to this embodiment, the same operation and effect as those of the eighth embodiment can be obtained. In particular, since the balance resistors R5 to R8 and R10 are provided, the followability with respect to the voltage change is improved, and the voltage division ratio at the time of transition can be further stabilized. The resistance values of the resistors R5 to R8 and R10 may be determined based on the balance between the stabilization of the voltage division ratio and the resistance loss.

(Tenth embodiment)
A tenth embodiment will be described with reference to FIG. The load driving device 49 includes an element module 50 and a driving IC 4. The element module 50 includes an FET 5, a first voltage detection circuit 51A, and a second voltage detection circuit 51B. Between the node n3 and the source of the FET 5, a common circuit 52 shared by the voltage detection circuits 51A and 51B is provided. The configurations of the first circuit 51Aa to the fourth circuit 51Bb are the same as those of the first circuit 37Aa to the fourth circuit 37Bb shown in FIG. Similarly, the common circuit 52 includes a parallel circuit of a capacitor C5 and a resistor R10.

  The capacitance values of the capacitors C1 to C5 are set in the same manner as in the sixth and seventh embodiments. The resistance ratio of the resistors R5 to R8 and R10 is preferably set equal to the voltage dividing ratio of the capacitors C1 to C4 and C5 as in the sixth embodiment. According to this setting, the resistance ratio of the resistors R5 to R8 and R10 is expressed by the equation (9).

R5: R6: R7: R8: R10 =
C2 / C5 (C3 + C4):
C1 · C5 (C3 + C4):
C4 · C5 (C1 + C2):
C3 · C5 (C1 + C2):
C1 · C2 (C2 + C4) + (C1 + C2) C3 · C4 (9)
According to this embodiment, the same operation and effect as those of the sixth and seventh embodiments can be obtained. The resistance values of the resistors R5 to R8 and R10 may be determined based on the balance between the stabilization of the voltage division ratio and the resistance loss.

(Eleventh embodiment)
The eleventh embodiment will be described with reference to FIG. The load driving device 53 includes an element module 54 and a driving IC 55, and the element module 54 includes an FET 5 and a voltage detection circuit 56.

  The voltage detection circuit 56 is a circuit that outputs a first detection voltage corresponding to the drain-source voltage of the FET 5, and is a Zener of the illustrated polarity that is connected in series with the output terminal n 1 interposed between the drain and source of the FET 5. It is composed of diodes ZD1 and ZD2 (corresponding to the first circuit and the second circuit). The Zener diodes ZD1 and ZD2 connected in series are energization circuits that shift to an energized state when a voltage exceeding a Zener voltage (specified voltage) set lower than the voltage Vm1 and higher than the voltage Vm2 is applied.

  The drive IC 55 includes a drive circuit 7, a switch circuit 8, a control circuit 9, and a diode 15. The gates of the MOSFETs 13 and 14 of the control circuit 9 are connected to the output terminal n 1 of the voltage detection circuit 56. Between the output terminal n1 and the gate of the FET 5, a diode 15 (corresponding to a unidirectional element) is connected to flow current from the output terminal n1 to the gate.

  The control circuit 9 has a threshold voltage Vth used for the voltage protection operation of the FET 5. The threshold voltage Vth is lower than the detection voltage (the Zener voltage VZD2) output from the voltage detection circuit 56 when a voltage higher than the voltage Vm1 is applied between the drain and source of the FET 5 and the Zener diodes ZD1 and ZD2 are energized. Is set. The threshold voltage Vth is set higher than the detection voltage output by the voltage detection circuit 56 when a voltage equal to or lower than the voltage Vm2 is applied between the drain and source of the FET 5 and the Zener diodes ZD1 and ZD2 are in a non-energized state. Has been.

  Further, the threshold voltage Vth is lower than the voltage (= Vth (FET) + Vf) obtained by adding the gate threshold voltage Vth (FET) of the FET 5 and the forward voltage Vf (energization voltage) of the diode 15. Is set to Further, the voltage dividing ratio of the voltage detection circuit 56 (that is, the Zener voltages VZD1, VZD2) is such that the first detection voltage becomes higher than Vth (FET) + Vf when a voltage in the range of the voltage Vm1 or higher is applied to the FET5. Is set to

  The operation of this embodiment is almost the same as that of the first embodiment. That is, when the drain-source voltage VDS of the FET 5 becomes equal to or higher than the voltage Vm1 due to the generation of the surge voltage, the Zener diodes ZD1 and ZD2 are energized. At this time, the first detection voltage output from the voltage detection circuit 56 is equal to or lower than the gate breakdown voltage of the MOSFETs 13 and 14 and is higher than the threshold voltage Vth. As a result, the switch circuit 8 interrupts the drive circuit 7 and the gate of the FET 5 with high impedance.

  Thereafter, the gate voltage VGS of the FET 5 starts to increase toward the voltage shown by the equation (5). In parallel with the rising operation of the gate voltage VGS, the first detection voltage guides the FET 5 through the diode 15 to self-turn on. That is, when the drain-source voltage VDS of the FET 5 rises to the voltage Vm1 or higher, the first detection voltage first becomes higher than the threshold voltage Vth, and the switch circuit 8 enters a high impedance state.

  Thereafter, the first detection voltage becomes higher than Vth (FET) + Vf. At this time, the gate voltage VGS applied to the FET 5 is below the gate breakdown voltage. As a result, the gate voltage VGS of the FET 5 is raised to the gate threshold voltage Vth (FET) or more through the diode 15 and the FET 5 is self-turned on. According to this order, the first detection voltage does not turn on the FET 5 when the switch circuit 8 is in the low impedance state.

  When the release of energy ends, the drain-source voltage VDS starts to decrease, and the first detection voltage also starts to decrease. At this time, the first detection voltage initially becomes lower than Vth (FET) + Vf, but as long as the switch circuit 8 maintains the high impedance state, the FET 5 continues to be turned on. Thereafter, when the first detection voltage falls below the threshold voltage Vth, the switch circuit 8 enters a low impedance state and returns to the switching operation according to the drive signal.

  According to this embodiment, when the drain-source voltage VDS of the FET 5 becomes equal to or higher than the voltage Vm1, the Zener diodes ZD1 and ZD2 are energized, and the voltage at the output terminal n1 is maintained almost constant. Thereby, the switch circuit 8 can be stably cut off, and the FET 5 can be self-turned on accurately and reliably.

  The Zener diodes ZD1 and ZD2 are not for releasing the energy of the surge voltage but for detecting the voltage. Therefore, it is sufficient that the Zener diodes ZD1 and ZD2 have an element size sufficient to drive the gate capacitances of the MOSFETs 13 and 14. For this reason, the capacitance value when the Zener diodes ZD1 and ZD2 are viewed from the gate of the FET 5 via the diode 15 is smaller than the junction capacitance value of the diode 15. Therefore, the parasitic capacitance added to the gate is reduced, and the withstand voltage can be ensured while maintaining the high-speed switching performance (particularly the turn-on characteristic) of the FET 5. In addition, the same effects as those of the first embodiment can be obtained.

(Twelfth embodiment)
A twelfth embodiment will be described with reference to FIG. The load driving device 57 includes an element module 58 and a driving IC 55, and the element module 58 includes an FET 5 and a voltage detection circuit 59. The voltage detection circuit 59 includes resistors R11 and R12 (corresponding to a first circuit and a second circuit) connected in series with the output terminal n1 interposed between the drain and source of the FET 5. The resistors R11 and R12 have a ratio of about R11: R12 = (5 to 500): 1 and are set to relatively high resistance values so as to reduce resistance loss.

  Since the voltage detection circuit 59 outputs the detection voltage by resistance voltage division, the voltage detection circuit 59 has good followability with respect to a voltage change, and a stable voltage division ratio can be obtained. Also according to this embodiment, the switch circuit 8 can be stably cut off, and the FET 5 can be self-turned on accurately and reliably.

(13th Embodiment)
A thirteenth embodiment will be described with reference to FIG. The load driving device 60 includes an element module 61 and a driving IC 55. The element module 61 includes an FET 5 and a Zener diode ZD1 (voltage detection circuit). This configuration is equivalent to a configuration in which the Zener diode ZD2 is deleted from the load driving device 53 shown in the eleventh embodiment.

  The threshold voltage Vth of the control circuit 9 is set lower than the detection voltage output from the anode of the Zener diode ZD1 when a voltage equal to or higher than the voltage Vm1 is applied between the drain and source of the FET 5. The threshold voltage Vth is set higher than the voltage output from the anode of the Zener diode ZD1 when a voltage equal to or lower than the voltage Vm2 is applied between the drain and source of the FET 5 and the Zener diode ZD1 is in a non-energized state. Yes. Further, the threshold voltage Vth is set to be lower than Vth (FET) + Vf. The Zener voltage VZD1 is set such that the detection voltage output by the anode when a voltage in the range of the voltage Vm1 or higher is applied to the FET 5 is higher than Vth (FET) + Vf.

  This embodiment can provide the same operations and effects as those of the eleventh embodiment. Furthermore, since the voltage detection circuit can be constituted by one Zener diode ZD1, further miniaturization can be achieved.

(Fourteenth embodiment)
A fourteenth embodiment will be described with reference to FIGS. 16 and 17. The load driving device 62 includes the element module 3 and a driving IC 63. In the driving IC 63, a protection circuit 64 is provided between the output terminal n1A of the first voltage detection circuit 6A and the source of the FET 5, and protection is provided between the output terminal n1B of the second voltage detection circuit 6B and the source of the FET 5. A circuit 65 is provided.

  The protection circuit 64 is configured by a series circuit of a Zener diode ZD3 and a resistor R13, and the protection circuit 65 is configured by a series circuit of a Zener diode ZD4 and a resistor R14. Instead of this, it may be constituted only by a high resistance or may be constituted only by a Zener diode. Further, the protection circuits 64 and 65 may be provided on the element module side.

  The protection circuit 64 limits the first detection voltage to be equal to or lower than the gate breakdown voltage of the MOSFETs 13 and 14 when an excessive surge voltage is applied between the drain and source of the FET 5. The protection circuit 65 limits the magnitude of the second detection voltage so that when an excessive surge voltage is applied between the drain and source of the FET 5, the gate voltage of the FET 5 is less than or equal to the gate breakdown voltage.

  Since the protection circuit 64 is connected to the MOSFETs 13 and 14 constituting the inverter circuit of the control circuit 9, it does not affect the gate capacitance of the FET 5. On the other hand, for the protection circuit 65, the parasitic capacitance Czd of the Zener diode ZD4 is connected between the output terminal n1B of the second voltage detection circuit 6B and the source of the FET 5. For this reason, the capacitors C3, C4, and Czd are connected to the gate of the FET 5 through the diode 15. When the capacitance added to the gate of the FET 5 is represented by an equivalent circuit, it is as shown in FIG. Here, Cp = C3 + C4 + Czd.

  As described above, since the rated current of the diode 15 is very small, Cd << C3 and C4, and the relationship between the combined capacitances Cp and Cd is Cd << Cp. For this reason, when the capacitors C3, C4, and Czd are viewed from the gate of the FET 5 through the diode 15, the equivalent capacitance value is a minute value that is substantially equal to the junction capacitance value of the diode 15. Further, a diode having a large rated current for escaping a surge is not connected to the gate of the FET 5. Therefore, the parasitic capacitance added to the gate is smaller than that in the conventional configuration, and the voltage resistance can be ensured while maintaining the high-speed switching performance (particularly the turn-on characteristic) of the FET 5. As a result, the first detection voltage input to the control circuit 9 and the second detection voltage input to the gate of the FET 5 are stabilized, so that the control circuit 9 and the FET 5 can be prevented from malfunctioning due to noise or the like.

  It is preferable to provide protection circuits 64 and 65 at the output section of the first voltage detection circuit 6A and the output section of the second voltage detection circuit 6B, respectively, but depending on the operating conditions, the characteristics of the control circuit 9 and the FET 5, etc. The same effect can be obtained with only one of the protection circuits.

(Fifteenth embodiment)
A fifteenth embodiment will be described with reference to FIG. The load driving device 66 includes the element module 3 and a driving IC 67. In the switch circuit 68 provided in the drive IC 67, a resistor 69 is connected in parallel with the MOSFET 11. The resistance value Rp of the resistor 69 is set to a value about 10 times the normal gate resistances Rgon and Rgoff.

  When the surge voltage is generated and the drain-source voltage VDS of the FET 5 becomes equal to or higher than the voltage Vm1, the control circuit 9 controls the MOSFET 11 to be turned off. At this time, the impedance between the output terminal of the drive circuit 7 and the gate of the FET 5 is Rp, and the gate of the FET 5 is close to the open state. By providing the resistor 69, the voltage value at which the FET 5 self-turns on can be adjusted.

(Other embodiments)
As mentioned above, although preferred embodiment of this invention was described, this invention is not limited to embodiment mentioned above, A various deformation | transformation and expansion | extension can be performed within the range which does not deviate from the summary of invention.

  In each embodiment, the case where the surge voltage (including back electromotive force) generated when the energization to the coil 2 that is an inductive load is cut off is applied to the FET 5 has been described. The same applies when an overvoltage due to induction noise, battery voltage VB fluctuation, or the like is applied.

  In the eleventh embodiment, the Zener diodes ZD1 and ZD2 are used as the energization circuits constituting the first circuit and the second circuit. In the thirteenth embodiment, the Zener diode ZD1 is used as the energizing circuit. The energization circuit may have another circuit configuration as long as it is a circuit that shifts to an energized state when the applied voltage exceeds a specified voltage. For example, it is composed of one or a plurality of semiconductor elements selected from a diode, a Zener diode, a MOS transistor and a bipolar transistor, and a specified voltage is obtained by its forward voltage, Zener voltage, threshold voltage or a combination of these voltages It may be configured.

The control circuits 23 and 27 described in the second and third embodiments can be similarly applied to the fourth to fourteenth embodiments.
The protection circuits 64 and 65 described in the fourteenth embodiment can be similarly applied to the second to tenth and fifteenth embodiments. In this case, only one of the protection circuits 64 and 65 may be applied. The protection circuit 64 or 65 can also be applied to the 11th to 13th embodiments.

The switch circuit 68 described in the fifteenth embodiment can be similarly applied to the second to fourteenth embodiments.
The first voltage detection circuit and the second voltage detection circuit described in the first to tenth, fourteenth and fifteenth embodiments and the voltage detection circuit described in the first to thirteenth embodiments are the drain and source of the FET 5. Any circuit that outputs a detection voltage corresponding to the voltage VDS applied between them may be used, and it is not always necessary to configure a series circuit of the first circuit and the second circuit or a series circuit of the third circuit and the fourth circuit.

  In each embodiment except the thirteenth embodiment, the first circuit and the second circuit, and the third circuit and the fourth circuit may be different from each other. For example, in the fourth embodiment, a configuration excluding the resistors R1 and R2 or a configuration excluding the resistors R3 and R4 may be employed. In the fifth and sixth embodiments, a configuration excluding the resistors R5 and R6 or a configuration excluding the resistors R7 and R8 may be employed. The same applies to the eighth to tenth embodiments. When the configurations of the first circuit and the second circuit and the configurations of the third circuit and the fourth circuit are different, the common circuit has the same configuration as any one (that is, the first, second circuit, or the third, fourth circuit). That's fine.

  Although the application to the load driving device has been described, the present invention is not limited to this, and can be applied to a switching power supply circuit, an inverter circuit, and the like.

  In the drawings, 1, 21, 25, 29, 32, 35, 38, 41, 45, 49, 53, 57, 60, 62, 66 are load driving devices (semiconductor devices), 5 is an FET (switching element), 6A , 31A, 34A, 37A, 40A, 43A, 47A, 51A are first voltage detection circuits, 6B, 31B, 34B, 37B, 40B, 43B, 47B, 51B are second voltage detection circuits, 8, 68 are switch circuits, 9, 23 and 27 are control circuits, 10 is a gate drive line, 13 and 14 are MOSFETs (transistors), 31Aa, 34Aa, 37Aa, 43Aa, 47Aa, 51Aa are first circuits, 31Ab, 34Ab, 37Ab, 43Ab, 47Ab, 51Ab is the second circuit, 31Ba, 34Ba, 37Ba, 43Ba, 47Ba, 51Ba is the third circuit, 31Bb, 34Bb, 37Bb 43Bb, 47Bb, 51Bb is a fourth circuit, 44, 48, 52 are common circuits, 56, 59 are voltage detection circuits, C1 to C4 are capacitors (first circuit to fourth circuit), C5 is a capacitor (common circuit), n1A, n1B and n2 are output terminals, R1 to R10 are resistors, R11 and R12 are resistors (first circuit and second circuit), and ZD1 and ZD2 are zener diodes (energizing circuit / first circuit and second circuit). .

Claims (15)

A switching element (5) that changes a conduction state between the second terminal (D) and the first terminal (S) according to a gate voltage applied between the gate terminal (G) and the first terminal (S). )When,
A first voltage detection circuit (6A, 31A, 34A, 37A, 40A, 43A, 47A, 51A) that outputs a first detection voltage corresponding to a voltage applied between the second terminal and the first terminal of the switching element. )When,
Second voltage detection circuits (6B, 31B, 34B, 37B, 40B, 43B, 47B, 51B) that output a second detection voltage corresponding to a voltage applied between the second terminal and the first terminal of the switching element. )When,
A switch circuit (8, 68) which is provided in series with a gate drive line (10) connected to the gate terminal of the switching element and switches to a high impedance state or a low impedance state according to a control signal;
A unidirectional element (15) connected between the output terminal of the second voltage detection circuit and the gate terminal of the switching element, and for passing a current from the output terminal to the gate terminal;
The first detection voltage output from the first voltage detection circuit when a voltage in a range where the voltage protection operation of the switching element is to be performed is applied between the second terminal and the first terminal of the switching element. The first voltage detection circuit is set when a voltage that is set to a low level and a voltage protection operation of the switching element is not required between the second terminal and the first terminal of the switching element is applied. The threshold voltage is set higher than the first detection voltage to be output, and when the first detection voltage falls below the threshold voltage, the switch circuit is switched to a low impedance state, and the first detection voltage A control circuit (9, 23, 27) for outputting the control signal for switching the switch circuit to a high impedance state when the threshold voltage exceeds the threshold voltage;
When the first detection voltage is equal to or lower than the threshold voltage of the control circuit, the second detection voltage is higher than a voltage obtained by adding the gate threshold voltage of the switching element and the energization voltage of the unidirectional element. The second detection voltage becomes a gate threshold value of the switching element when a voltage in a range in which the voltage protection operation is to be performed is applied between the second terminal and the first terminal of the switching element. A semiconductor device, wherein a voltage dividing ratio of the second voltage detection circuit is set to be higher than a voltage obtained by adding a voltage and a conduction voltage of the unidirectional element. The first voltage detection circuit includes a first circuit (C1, 31Aa, 34Aa, 34Aa, serially connected between the second terminal and the first terminal of the switching element with the output terminal of the first detection voltage interposed therebetween. 37Aa, 43Aa, 47Aa, 51Aa) and a second circuit (C2, 31Ab, 34Ab, 37Ab, 43Ab, 47Ab, 51Ab),
The second voltage detection circuit includes a third circuit (C3, 31Ba, 34Ba, and C3) connected in series between the second terminal and the first terminal of the switching element, with the output terminal of the second detection voltage interposed therebetween. 37. The semiconductor device according to claim 1, further comprising a fourth circuit (C4, 31Bb, 34Bb, 37Bb, 43Bb, 47Bb, 51Bb) and 37Ba, 43Ba, 47Ba, 51Ba).   3. The semiconductor device according to claim 2, wherein each of the first to fourth circuits includes a capacitor (C1, C2, C3, C4).   4. The first circuit and the second circuit and / or the third circuit and the fourth circuit each include a resistor (R1, R2, R3, R4) in series with the capacitor. Semiconductor device.   When the first to fourth circuits are composed of a series circuit of a capacitor and a resistor, they are provided with resistors (R5, R6, R7, R8) in parallel with the series circuit, and are composed of a capacitor. The semiconductor device according to claim 4, further comprising a resistor (R5, R6, R7, R8) in parallel with the capacitor.   4. The first circuit and the second circuit and / or the third circuit and the fourth circuit each include a resistor (R5, R6, R7, R8) in parallel with the capacitor. Semiconductor device.   The first voltage detection circuit and the second voltage detection circuit are shared by the first and second voltage detection circuits between the second circuit and the fourth circuit and the first terminal of the switching element. The semiconductor device according to claim 2, further comprising (C5, 44, 48, 52).   8. The semiconductor according to claim 7, wherein the common circuit has the same configuration as the first circuit and the second circuit or the third circuit and the fourth circuit with respect to a connection configuration of a capacitor and / or a resistor. apparatus. A switching element (5) that changes a conduction state between the second terminal (D) and the first terminal (S) according to a gate voltage applied between the gate terminal (G) and the first terminal (S). )When,
A voltage detection circuit (56, 59, ZD1) for outputting a first detection voltage corresponding to a voltage applied between the second terminal and the first terminal of the switching element;
A switch circuit (8, 68) which is provided in series with a gate drive line connected to the gate terminal of the switching element and switches to a high impedance state or a low impedance state according to a control signal;
A unidirectional element (15) connected between the output terminal of the voltage detection circuit and the gate terminal of the switching element, and for passing a current from the output terminal to the gate terminal;
Setting is lower than the first detection voltage output by the voltage detection circuit when a voltage in a range in which the voltage protection operation of the switching element is to be performed is applied between the second terminal and the first terminal of the switching element. And the voltage detection circuit outputs a voltage when a voltage in a range in which the voltage protection operation of the switching element is not required is applied between the second terminal and the first terminal of the switching element. A threshold voltage set higher than a detection voltage and set lower than a voltage obtained by adding a gate threshold voltage of the switching element and a conduction voltage of the unidirectional element; When the detection voltage falls below the threshold voltage, the switch circuit is switched to a low impedance state, and when the first detection voltage exceeds the threshold voltage, the switch And a control circuit for outputting the control signal for switching the road in a high impedance state (9),
When a voltage in a range in which the voltage protection operation is to be performed is applied between the second terminal and the first terminal of the switching element, the first detection voltage is a gate threshold voltage of the switching element and the gate voltage. A semiconductor device, wherein a voltage dividing ratio of the voltage detection circuit is set to be higher than a voltage obtained by adding an energization voltage of a unidirectional element.   The voltage detection circuit includes a first circuit (ZD1, R11) and a second circuit (ZD2, R12) connected in series with an output terminal interposed between the second terminal and the first terminal of the switching element. 10. The semiconductor device according to claim 9, wherein the semiconductor device is formed.   11. The semiconductor device according to claim 10, wherein each of the first circuit and the second circuit includes a resistor (R11, R12).   11. The semiconductor device according to claim 10, wherein each of the first circuit and the second circuit includes an energization circuit (ZD1, ZD2) that shifts to an energization state when an applied voltage exceeds a specified voltage.   The energization circuit is composed of one or a plurality of semiconductor elements selected from a diode, a Zener diode, a MOS transistor, and a bipolar transistor, and its forward voltage, Zener voltage, threshold voltage, or the voltage of these voltages. 13. The semiconductor device according to claim 12, wherein the specified voltage is configured by a combination.   The control circuit includes an inverter circuit including transistors (13, 14) having the threshold voltage between power supply lines for supplying a DC voltage necessary for outputting the control signal. 14. The semiconductor device according to claim 1, wherein the first detection voltage is applied to a gate.   The semiconductor device according to claim 1, wherein the switching element is a GaN device.

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