JP2014102607A - Electronic device, and control program and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quicken a boot start.SOLUTION: Operation of a processor (4) booted by power-on is monitored by an operation monitoring unit (6). In response to the monitoring result of the operation monitoring unit (6), a control unit (warm air control unit 8) causes the processor (4) to execute warm air processing if the processor (4) has an operation abnormality in booting the processor (4), and boots an operating system if the processor (4) does not have an operation abnormality. This quickens a boot start.

Description

The present invention relates to an electronic device such as a personal computer, a control program thereof, and a control method thereof.

  In an electronic apparatus such as a personal computer, various semiconductor components and mechanical components are used, and component selection and circuit design are performed so as to operate in an assumed operating environment. For this reason, normal operation may not be obtained under unexpectedly high or low temperature environments. In a high-temperature environment or a low-temperature environment, there is a risk of a change in characteristics of the semiconductor component, a change in the impedance of the capacitor, a hardening of the movable part of the mechanical component, a change in the circuit impedance due to condensation. A highly integrated semiconductor component such as a CPU or a chip set may be strongly influenced by a characteristic change as compared with a simple TTL logic element. An electronic device that is unattended and scheduled, such as a station premises or a street, may fail to start due to an unexpected temperature drop, such as in winter. In order to avoid such a start-up failure at a low temperature, measures such as warming up by installing a heater in or near the apparatus are taken.

  With respect to an electronic device that performs unattended operation, it is known to perform control such as temperature monitoring in the device, time of automatic input, and retry of operation (for example, Patent Document 1).

It is known that when the computer is started, it is confirmed that the temperature falls within the guaranteed operating range, self-diagnosis, etc., and if it is abnormal, it is repeatedly started (for example, Patent Document 2).

JP-A-1-48118 JP 2005-321949 A

  By the way, an operation guarantee temperature is set for an electronic device such as a PC. This operation guarantee temperature is a temperature range that guarantees the operation of the electronic device. In an electronic device with such a guaranteed operating temperature, even if there is a temperature margin between this guaranteed operating temperature and the temperature at which it can actually operate, the internal temperature of the device is equal to the guaranteed operating temperature. If it does not reach, the operation cannot be started. That is, it is necessary to raise the temperature of the electronic device to the operation guarantee temperature, and it is necessary to wait until the operation guarantee temperature is reached. For this reason, there is a problem that it takes time to start the start and the start of the start is delayed.

Therefore, in view of the above problems, the configuration of the present disclosure aims to speed up the start of startup.

In order to achieve the above object, in the configuration of the present disclosure, the operation monitoring unit monitors the operation of the processor that is activated when the power is turned on. The control unit receives the monitoring result of the operation monitoring unit when the processor is activated, and causes the processor to execute a warm-up process if the processor is abnormal in operation, and activates the operating system if the processor is not abnormal in operation. .

  According to the configuration of the present disclosure, an abnormal operation of the processor is monitored at the time of activation, and if there is no abnormal operation, the activation of the operating system is started.

Other objects, features, and advantages of the present invention will become clearer with reference to the accompanying drawings and each embodiment.

It is a figure which shows PC concerning 1st Embodiment. It is a flowchart which shows the process sequence at the time of starting. It is a flowchart which shows the process sequence of a warm-up process. It is a figure which shows PC concerning 2nd Embodiment. It is a figure which shows an example of an operation | movement monitoring part. It is a figure which shows the input / output operation | movement of an AND circuit. It is a timing chart which shows operation | movement of an operation | movement monitoring part. It is a flowchart which shows the process sequence at the time of starting. It is a flowchart which shows the multi-core loop operation | movement of a processor. It is a flowchart which shows the bit inversion loop write operation of memory. 5 is a flowchart showing HDD spindle start-up and seek repeat operations. It is a flowchart which shows the process sequence at the time of starting which concerns on 3rd Embodiment. It is a figure which shows reset operation | movement of the power-on control part which concerns on 4th Embodiment.

[First Embodiment]

  FIG. 1 shows a PC according to the first embodiment. The configuration shown in FIG. 1 is an example, and the present invention is not limited to such a configuration.

  A PC (personal computer) 2-1 is an example of the electronic apparatus of the present disclosure. The PC 2-1 includes a processor 4, an operation monitoring unit 6, and a warm-up control unit 8.

  The processor 4 is composed of, for example, a CPU (Central Processing Unit). Various programs such as an OS (Operating System), a firmware program, and a startup program stored in a ROM (Read-Only Memory) (not shown) are executed. The activation program is, for example, a software program for activating the processor 4 described above, such as BIOS (Basic Input / Output System), and is, for example, basic software for starting the processor 4 by turning on the power. The BIOS is a program that is executed at power-on, diagnoses peripheral devices such as a memory, and initializes settings.

  The operation monitoring unit 6 is connected to the processor 4 via a PCI (Peripheral Component Interconnect) bus 10. The PCI bus 10 is a bus for exchanging data. The operation monitoring unit 6 monitors the operation of the processor 4 through the PCI bus 10 and detects an operation error of the processor 4. The detected operation error is notified to the warm-up control unit 8.

  The warm-up control unit 8 receives the operation error detection of the operation monitoring unit 6 and shifts to the warm-up operation. In the warming-up operation, the power is turned off and on again, and the processor 4 performs the warming-up operation.

  If the processor 4 shifts to normal operation as a result of repeated power-off and power-on, the processor 4 executes the OS.

  The BIOS is stored in the BIOS-ROM 12 connected to the processor 4. The BIOS is a program for controlling various peripheral devices (not shown) connected to the processor 4 and is a basic input / output system. As described above, the BIOS is executed when the power is turned on, diagnoses peripheral devices such as a memory, and executes initialization of settings. Also in the BIOS process, the peripheral device is warmed up.

<Operation at startup>

  FIG. 2 shows a processing procedure when the PC 2-1 is activated. This processing procedure is an example of a control program and a control method for an electronic device according to the present disclosure.

  In this processing procedure, for example, activation is performed by turning on the power switch (S101). In response to this activation, the operation monitoring unit 6 starts operation monitoring and monitors the operation state of the processor 4 (S102).

  In this operation monitoring, it is determined whether an operation error has occurred in the processor 4 (S103). For example, the operation error may be monitored by monitoring a signal state generated in the PCI bus 10 of the processor 4.

  If it is an operation error (YES in S103), warm-up processing is executed (S104). After this warm-up process, the process returns to S103, and it is determined again whether there is an abnormal operation (S103). If there is an operation abnormality (YES in S103), the warming-up operation of the processor 4 is continuously performed until the operation abnormality is resolved.

  If there is no abnormal operation (NO in S103), the operating system (OS) is activated (S105). As a result, if there is no abnormal operation, it is possible to shift to OS startup, so that the startup start is speeded up.

<Warming treatment>

  FIG. 3 shows the procedure of the warm-up process of the PC 2-1. This processing procedure is an example of a control program and a control method for an electronic device according to the present disclosure. This processing procedure is a subroutine of S104 (FIG. 2) of the processing procedure at the time of activation.

  If there is an operation abnormality (YES in S103), the power supply is turned off (power supply = OFF) (S104104). After the power is turned off, the power is turned on again (S1042), and the process returns to S104 (FIG. 2). That is, power-on (S1041) and re-power (S1042) are automatically continued until the operation abnormality is cleared. Thereby, a warm-up process is performed continuously.

<Effect of the first embodiment>

  (a) When the power is turned on, the operation state of the processor 4 is monitored, and the power supply is turned off and on again automatically until the operation error is cleared, so that the processor 4 enters a warm-up state. In such a configuration, abnormal operation of the processor 4 in a low temperature state such as winter can be avoided, and normal operation of the processor 4 can be quickly secured by warm air.

  (b) If such a warm-up operation is performed, it is possible to avoid the inconvenience that the PC 2-1 that performs the schedule operation under unattended operation continues to operate abnormally.

  (c) If the peripheral device is warmed up by initialization of the peripheral device executed by the BIOS in parallel with the warming-up operation of the PC 2-1, the PC 2-1 can be shifted to normal operation.

  (d) Even if the guaranteed operating temperature is set, the startup can be started before the guaranteed operating temperature is reached, so that the startup start can be speeded up.

[Second Embodiment]

  FIG. 4 shows a PC 2-2 according to the second embodiment. The PC 2-2 is an example of the electronic device of the present disclosure. In FIG. 4, the same parts as those in FIG.

  A memory 14 is connected to the processor 4 of the PC 2-2, and a BIOS-ROM 12 and an HDD (Hard Disk Drive) 18 are connected via a chipset 16.

  The processor 4 is a central part of a computer that executes processing such as data exchange and calculation. The processor 4 is composed of a single or a plurality of CPU cores. In this embodiment, the processor 4 is composed of CPU cores 4-1 and 4-2 as an example. The memory 14 is an example of a RAM (Random-Access Memory) directly connected to the processor 4, and constitutes a work area for data processing executed by the processor 4.

  The chip set 16 is an LSI (Large Scale Integration circuit) that manages the exchange of data between the processor 4 and the memory 14 and other peripheral devices, and is composed of, for example, two chips, a north bridge and a south bridge. The The memory 14 is connected to the north bridge side, and the HDD 18 is connected to the south bridge side. The HDD 18 includes a spindle motor 20.

  The BIOS is stored in the BIOS-ROM 12. This BIOS is executed when the power is turned on, diagnoses peripheral devices such as the memory 14, and executes initialization of settings.

  The HDD 18 is a hard disk device or a hard disk, and is an example of a ROM (Read-Only Memory). The HDD 18 is an example of a recording medium. The HDD 18 stores various programs such as an OS and a firmware program. In this embodiment, a control program for realizing the control method of the electronic device of the present disclosure by the processing of the processor 4 is stored in the HDD 18.

  The above-described operation monitoring unit 6 is connected to the chip set 16 via the PCI bus 10. The operation monitoring unit 6 is a hardware circuit connected to the south bridge side of the chip set 16, and monitors the operation of the processor 4 based on the operation waveform of the processor 4. That is, the operation monitoring unit 6 is, for example, a hardware circuit that monitors the operation of the processor 4 in a low temperature environment. The power monitoring control unit 22 is connected to the operation monitoring unit 6, and the power supply unit 24 is connected to the power restarting control unit 22. The power supply unit 24 is an example of a power supply unit that supplies power to functional units such as the operation monitoring unit 6 and the processor 4 via the power supply reactivation control unit 22.

  The power-on control unit 22 is an example of the warm-up control unit 8 described above. In the power reactivation control unit 22, when the operation monitoring unit 6 detects an abnormality in the processor 4, the power reactivation control unit 22 repeatedly performs power reactivation by supplying power from the power supply unit 24. The power supply unit 24 generates, for example, a stabilized DC output based on an input of a commercial AC power supply (AC) 26 and supplies the stabilized DC output to the power supply reactivation control unit 22.

  The PCI bus 10 may include a display unit 28 as an example of a display unit. The display unit 28 may be controlled by the processor 4 to visually display display information such as the number of power-on cycles with an image. The display information can be made visible. As another example of information display, audio output may be used in combination with image display.

  In such a configuration, it is detected whether the signal waveform of the processor 4 is abnormal or normal, and the processor 4 is warmed up by repeating power-off and reboot (reboot), and the processor 4 is shifted to a normal operation state. Can be made.

<Operation monitoring unit 6>

  FIG. 5 shows an example of the operation monitoring unit 6. The operation monitoring unit 6 includes a down counter 60 and flag registers 62 and 64.

  The down counter 60 is a down counter of a watch dog timer. The watchdog timer periodically updates the count value (counter initial value) set by the processor 4 (FIG. 4) of the down counter 60 by software (firmware) so that the count value (timer value) does not become zero. To control. If there is an abnormality in the processor, the count value by the firmware is not updated, so that value becomes zero. Thereby, an abnormality of the processor can be detected. In this embodiment, there is no need to periodically update the count value by software (firmware), and the count value is automatically updated by a bus signal. Thereby, while the processor 4 is operating, the count value is automatically controlled so as not to become zero. When an abnormality occurs, the bus signal does not change and the count value becomes zero. Thereby, abnormality detection is performed.

  A clock signal (CLOCK) is input to a clock input of the down counter 60 from a clock generation circuit (not shown). A first AND circuit 66 is connected to the set input (SET) of the down counter 60. The AND circuit 66 receives a reset signal (PCI-RESET) and a frame signal (PCI-FRAME) output from the processor 4. That is, the down counter 60 is reset by the logical product output of PCI-RESET and PCI-FRAME by the AND circuit 66.

  The down counter 60 receives the counter initial value 70 from the processor 4 and sets the counter initial value 70. When the counter initial value 70 is not updated and the counter initial value 70 becomes zero, an abnormality detection output signal (ZERO) = H is output from the down counter 60.

  A POST end flag signal is written from the processor 4 to the flag register 62 when the BIOS is executed. That is, the flag register 62 is an example of a storage main unit that holds a POST end flag.

  The abnormality detection output signal of the down counter 60 and the output of the flag register 62 are applied to the second AND circuit 68. An AND circuit 68 obtains an error detection signal 72 representing error detection by the logical product of the abnormality detection output signal H and the output L of the flag register 62. This error detection signal 72 is used for power-off and power-on instructions.

  The output of the AND circuit 68 is input to the flag register 64 and written to the flag register 64. The flag register 64 holds an operation abnormality detection flag indicating an operation abnormality of the processor 4. The flag register 64 receives an instruction to turn off and turn on the power to the processor 4 when ON, and performs access (OS read and flag clear) 74 of the processor 4 when the BIOS is executed. In addition, when the flag register 64 is OFF, the flag register 64 always operates as a power source instead of turning off and turning on the power at the time of ON.

  As described above, the operation monitoring unit 6 does not require periodic update of the count value by software (firmware). The count value of the down counter 60 is automatically updated by the bus signal. That is, when the processor 4 is operating normally, it is automatically controlled so that the count value of the down counter 60 does not become zero. When an abnormality occurs in the processor 4, the bus signal is not changed, and the count value of the down counter 60 becomes zero, which indicates an abnormal state.

<Logical Operation of AND Circuit 66 of Operation Monitoring Unit 6>

  In the AND circuit 66, the logical operation shown in FIG. 6 is obtained. When -PCI-RESET = L and -PCI-FRAME = L, the output of the AND circuit 66 is L. When -PCI-RESET = L and -PCI-FRAME = H, the output of the AND circuit 66 becomes L. When -PCI-RESET = H and -PCI-FRAME = L, the output of the AND circuit 66 is L. When -PCI-RESET = H and -PCI-FRAME = H, the output of the AND circuit 66 is H.

<Operation of Operation Monitoring Unit 6>

  FIG. 7 shows the input / output of the operation monitoring unit 6 and the operation of each unit. In FIG. 7, A is a CLOCK signal, B is a -PCI-RESET signal, C is a -PCI-FRAME signal, D is a counter value of a down counter, and E is a ZERO output. F indicates an error detection signal, and G indicates a control state of the power source.

  When the power is turned on, a clock signal generation circuit (not shown) operates. As a result, the CLOCK signal shown in FIG. 7A is generated from the clock signal generation circuit. This CLOCK signal is added to the down counter 60 and counted by the down counter 60.

  The -PCI-RESET signal indicates a reset state at L and a reset release state at H, as shown in B of FIG. The PCI bus is accessed when the -PCI-FRAME signal shown in FIG. 7C shifts from the H state to the L state.

  In FIG. 7, D indicates the transition of the counter value, and Max indicates the counter initial value. Count values “2”, “1”, and “0” indicate a reduction state of the count value. When the count value shifts to “0”, an H output representing “0” is generated in the ZERO output.

  Both ZERO = H and the POST end flag = L from the flag register 62 are added to the AND circuit 68. As a result, an error detection signal = H representing error detection is obtained in the AND circuit 68 as shown in F of FIG. This error detection signal is applied to the flag register 64 as a power-off / re-instruction.

  As a result, as shown in FIG. 7G, abnormality detection is performed in the H output state, the power is turned off by transition from the H output to the L output, and the power is turned off by continuing the L output, and then the L output from the L output. The power is turned on again by the transition of. At time t1, the power is turned off, and power is turned on again at time t2. T indicates a continuous power off state. In this case, if the operation abnormality continues, the power ON and the power OFF are repeatedly executed.

<Processing procedure at startup>

  FIG. 8 shows a processing procedure when the PC 2-2 is activated. In this processing procedure, at the time of start-up (that is, power supply = ON), if an error is detected in the operation monitoring unit 6, a warm-up process is executed to warm up the PC 2-2. That is, if the error flag is set, the device heat generation processing by the BIOS is executed as the BIOS control.

  In this processing procedure, the power is turned on from the power-off state (S201), and the operation monitoring unit 6 monitors the operation of the processor 4 (S202). By this operation monitoring, it is determined whether or not there is an operation error. Then, the hardware is initialized by executing the BIOS based on the power supply = ON (S203).

  As an operation monitoring process, an error flag is confirmed (S204). If the error flag is ON, warm-up processing is executed (S205).

  In this warm-up process (S205), a device heat generation process is executed by executing the BIOS. In this warm-up process, for example, device heat generation process is included as BIOS control for accelerating warm-up. In the device heat generation processing, for example, in the case of the processor 4, a multi-core loop operation, in the case of the memory 14, for example, a bit inversion loop write operation, and in the case of the HDD 18, for example, the spindle is started and the seek is repeatedly executed. Is included.

  If the error flag is OFF, the operation is normal, and the OS (Operating System) is read by executing the BIOS skipping S205 (S206). By executing the BIOS, the error flag is cleared and the processor 4 writes the POST end flag to the flag register 62 (S207). The OS is started by executing the BIOS (S208).

  After the OS is started, an OS such as Windows (registered trademark) is started (S209), and this process is terminated.

  In the warm-up process (S205) of this embodiment, the multi-core loop operation of the processor 4, the bit inversion loop write operation of the memory 14, the spindle activation of the HDD 18 and the seek are repeated. Any one or two or more of these operations may be selectively executed.

<Control of BIOS for accelerating warm air = BIOS temperature increase program>

  (1) Multi-core loop operation of processor 4

  In a normal BIOS program, when the processor 4 is composed of a single CPU core, the CPU core is used for processing. For example, when the processor 4 is composed of two CPU cores 4-1 and 4-2, all the CPU cores 4-1 and 4-2 are operated by this multi-core loop operation to warm up the processor 4. Accelerate. Such a processor 4 uses a cache memory for a loop process of a simple addition operation, and increases the heat generation amount of the CPU cores 4-1 and 4-2 by operating for a long time (for example, about 30 [seconds]). And warm up can be accelerated. Such a multi-core loop operation is executed by incorporating the processing program (FIG. 9).

  FIG. 9 shows a processing procedure of a multi-core loop operation between two CPU cores 4-1 and 4-2.

  In this processing procedure, the multi-core CPU is initialized at the start of processing (S221). In this initialization process, the programs for the CPU cores 4-1 and 4-2 are loaded in the memory 14, and the CPU cores 4-1 and 4-2 are started (S221).

  The start time is recorded for each of the CPU cores 4-1 and 4-2 (S222-1, S222-2). After recording the start time, initialization processing (CX = 0xFFFF, L1: CX = CX-1, JNZ L1) is executed as an example on the CPU core 4-1 (S223-1). At the same time, initialization processing (CX = 0xFFFF, L2: CX = CX-1, JNZ L1) is executed as an example for the CPU core 4-2 (S223-2).

  The elapsed time of each initialization process is monitored, and it is determined whether each elapsed time is equal to or longer than the scheduled time (S224-1, S224-2). If each elapsed time is less than the scheduled time (NO in S224-1, NO in S224-2), the initialization operation is repeated and continued.

  If the elapsed time of each initialization process reaches the scheduled time or more (YES in S224-1, YES in S224-2), the initialization operation is completed, and the process returns from the multicore loop operation to S205 (FIG. 8).

  (2) Bit inversion loop write operation of memory 14

  A normal BIOS program performs only the process of clearing the memory to zero. On the other hand, in the bit inversion loop write operation of the memory 14, the memory data written to the memory 14 is inverted from “0” to “1”, and the process of inversion from “1” to “0” is repeated, thereby Accelerate.

  In a dynamic random-access memory (DRAM) used for the memory 14, the internal structure of the memory element is configured to store data by accumulating charges in a capacitor. For this reason, a current flows due to an inversion operation between “0” and “1”, and heat is generated by this current. By repeating this storage operation, the heat generation of the memory 14 can be increased.

  FIG. 10 shows a processing procedure of bit inversion loop writing in the memory 14.

  In this processing procedure, the start time is recorded (S231). After recording the start time, the bit inversion writing process of the memory 14 is executed (S232).

This bit inversion writing process is as follows.
“DX = 0xFFFFFFFF
L1:
AX = MaxAddress
(AX) = DX
AX = AX-4
JNZ L1
DX = 0x00000000
L2:
AX = MaxAddress
(AX) = DX
AX = AX-4
JNZ L2 "

  The elapsed time is monitored from the start time recording (S233). If the elapsed time is less than the scheduled time (NO in S233), S232 is repeatedly executed. Thereby, the bit inversion write process is repeated, and the bit inversion loop process is executed.

  If the elapsed time reaches the scheduled time (YES in S233), the bit inversion write is completed, and the process returns from this bit inversion loop process to S205 (FIG. 8).

  (3) HDD18 spindle start / seek repeated operation

  The normal BIOS program does not operate the HDD 18 until the OS (operating system) is read. On the other hand, in the spindle activation / seek repetition operation of the HDD 18, the spindle motor 20 is activated to repeatedly seek the head of the HDD 18. Thereby, the current consumption of the HDD 18 increases, and the heat generation of the HDD 18 can be increased by this current consumption.

  FIG. 11 shows a processing procedure of the spindle start-up / seek repetition operation of the HDD 18.

  In this processing procedure, the start time is recorded (S241). After recording the start time, spindle activation / seek repetition processing is executed (S242).

  In this process, the maximum number of blocks of the HDD 18 is read, the HDD cache is invalidated, the HDD spindle is activated, the read block is set to 0, the read of the HDD 18 is set, and the read block is set to the maximum block.

  The elapsed time is monitored from the start time recording (S243). If the elapsed time is less than the scheduled time (NO in S243), S242 is repeatedly executed. Thereby, seek repetition processing is executed.

  If the elapsed time reaches the scheduled time (YES in S243), the seek repetition process is completed, and the process returns to S205 (FIG. 8) from this spindle activation / seek repetition operation.

<Effects of Second Embodiment>

  (a) In the above-described warm-up operation, the power is turned on after the power is turned off, the BIOS temperature increasing program is executed through the BIOS initialization process, and the OS is started. In such a series of operation procedures, based on the operation monitoring of the processor 4, warm-up processing is executed by a power-off instruction and a power-on instruction.

  (b) Conventionally, an operation margin is secured by circuit design, and operation in a low temperature environment is secured by component selection. In contrast to such circuit design and component selection, in the above-described embodiment, the warm-up operation is preceded at the time of start-up to enable transition to normal operation. The start of the operation of the PC 2-2 at a low temperature can be speeded up.

[Third Embodiment]

  FIG. 12 shows a processing procedure at the time of activation according to the third embodiment. In this processing procedure, a limiting operation based on the number of power-on cycles is added to the processing procedure (FIGS. 2 and 3) of the first embodiment.

  In this processing procedure, after the power is turned on again (S301), the operation of the processor 4 is monitored (S302). If there is an operation error in the processor 4 (YES in S303), the power is turned off (S304), and after a predetermined time has passed (S305), the power is turned on again (S306).

  Then, the number of power-on times is monitored (S307). In this case, a predetermined number is set as an upper limit value for the number of times the power is turned on again. After the power is turned on again, if the number of times the power is turned on does not reach the predetermined number or more (NO in S307), the process returns to S302, and the processes from S303 to S307 are executed. Thereby, a warm-up process is performed.

  If the number of times the power is turned on again reaches the predetermined number or more (YES in S307), it is determined that the operation is abnormal (S308), the warming-up operation is completed, and this process is terminated. As a result, it is possible to prevent the power-off / re-on operation from being performed indefinitely.

  If there is no operation error as a result of the operation monitoring (NO in S303), the OS is started (S309). As described above, it is possible to speed up the start of activation.

[Fourth Embodiment]

  FIG. 13 shows a PC 2-3 according to the fourth embodiment. In FIG. 13, the same parts as those in FIG.

  In the operation monitoring unit 6, when an abnormal operation occurs in the processor 4 due to a factor such as a low temperature state, the power reactivation control unit 22 is operated to perform warm-up control so that the abnormal operation can be recovered. The operation monitoring unit 6 constantly monitors the bus access of the processor 4. When there is no bus access of the processor 4 within a certain time (for example, 1 second), it is determined that the state is abnormal.

  In this embodiment, a signal indicating an abnormality is sent to the power supply restart control unit 22. A warm-up process (FIGS. 9, 10, and 11) is added to the BIOS process of the PC 2-3. Specifically, when the program content repeatedly accesses (for example, about 30 [seconds]) to the processor 4, memory, graphics, disk, etc., the temperature of the device inside the PC 2-3 is rapidly increased. Can do.

  If such processing is performed, even if an abnormality occurs in the processor 4 in the low temperature state, that is, in the BIOS processing, the operation monitoring unit 6 can detect the abnormality, and the power is turned off and on again based on the detection result. . That is, the temperature of the PC 2-3 can be rapidly increased by the warm-up process by the BIOS process. By repeating this operation, the PC 2-3 transits to an operable state, and the OS is started.

  Such an operation is repeatedly executed until a normal operation is performed, and even when the connected device is faulty, the power is repeatedly turned off and on in the same manner as at low temperatures. In order to prevent such inconvenience, the maximum number of times of power off and on can be set in advance and the number of operations may be monitored (FIG. 12). In other words, if the maximum number of times of power-off and power-on is reached, if the maximum number is reached, the power-off and power-on operations exceeding the maximum number of times are stopped, and excessive power-off and power-off. It is possible to prevent the abnormal operation from being continued due to charging.

  In the fourth embodiment, as shown in FIG. 13, the power supply ready signal 82 generated from the power supply unit 24 forms a part of the reset signal for the main board 80. Therefore, an AND circuit 84 is provided. The AND circuit 84 is supplied with a power supply ready signal 82 and a detection signal of the temperature sensor 86. In the AND circuit 84, a logical product of the power supply ready signal 82 and the detection signal of the temperature sensor 86 is taken, and a reset signal 88 is generated by the logical product. The temperature sensor 86 detects the operating temperature of the PC 2-3 and generates an H output at a predetermined temperature, for example, 10 [° C.] or higher. The power-on control unit 22 receives the reset signal 88 from the AND circuit 84 and is reset by the reset signal 88.

  Therefore, when the power is turned on in a low temperature state, for example, 5 [° C.], the H output is obtained from the temperature sensor 86 when the temperature reaches 10 [° C.] or higher. That is, since the detection signal from the temperature sensor 86 responds to the temperature rise, the reset period becomes longer depending on the temperature rise. For example, when the power is turned on at a detected temperature of 5 [° C.], the device reset is in an output state that continues for a while after the power is turned on. For this reason, the PC 2-3 is not activated. That is, the start of activation is delayed.

  On the other hand, a DC power supply 90 is supplied from the power supply unit 24 to the main board 80. If this state is maintained, each component such as the power supply unit 24 and the main board 80 is warmed up, and the temperature of the PC 2-3 rises. As a result, the temperature detected by the temperature sensor 86 increases. When the detected temperature reaches 10 [° C.] or higher, the detection signal of the temperature sensor 86 becomes H output. As a result, a power-off control unit 22 temporarily outputs a disconnection instruction to the power supply unit 24, and the PC 2-3 starts operating when the power is turned on again. That is, start-up can be speeded up.

  Normally, when power is turned on, a reset signal 88 is output from the power supply unit 24. After the reset signal 88, for example, 1 [second] or less as a predetermined time, the reset is released and the processor 4 or the like starts its operation.

  When the power is turned on in a low temperature environment, the reset signal 88 is output, and the reset signal 88 is continuously output until the temperature inside the PC 2-3 rises to the operable temperature. A temperature sensor 86 is installed inside the PC 2-3, and the output of the temperature sensor 86 is used for reset release control. In reset release, the power may be turned off and turned on again to start the operation.

  When the power is turned on in a low-temperature environment, each device (processor 4, memory 14, graphics, etc.) including the PC 2-3 is initialized by an initialization program such as BIOS for the purpose of increasing the temperature inside the housing. , Disks, etc.) are repeatedly accessed to accelerate the temperature rise. At this time, if the processor 4 stops operating due to a malfunction due to low temperature, it is detected that the processor 4 has stopped, and the power source of the PC 2-3 is temporarily turned off and then turned on again. If an abnormality does not occur, such as a stop of the processor 4 in the BIOS initialization diagnosis process and the temperature rise program, and the BIOS process is completed normally, the start of the OS is started. If the temperature detected by the temperature sensor 86 rises to a predetermined range, as described above, after the power is turned off and turned on again, normal operation such as OS activation is started.

[Other Embodiments]

  In the said embodiment, although PC2-1, 2-2, 2-3 was illustrated as an electronic device containing the processor 4 which performs a starting program etc., it is not limited to these. The electronic device including the processor 4 may be, for example, an electronic game machine, an automobile, a television receiver, an electric bulletin board, and the like.

As described above, the most preferable embodiment of the configuration of the present disclosure has been described. The present invention is not limited to the above description. Various modifications and changes can be made by those skilled in the art based on the gist of the invention described in the claims or disclosed in the embodiments for carrying out the invention. It goes without saying that such modifications and changes are included in the scope of the present invention.

2-1, 2-2, 2-3 PC
4 Processor 4-1, 4-2 CPU Core 6 Operation Monitoring Unit 8 Warm-up Control Unit 10 PCI Bus 12 BIOS-ROM
14 Memory 16 Chipset 18 HDD
20 Spindle motor 22 Power supply reactivation control unit 24 Power supply unit 26 Commercial AC power supply 28 Display unit 60 Down counter 62, 64 Flag register 66 First AND circuit 68 Second AND circuit 70 Counter initial value 72 Error detection signal 74 Access 80 Main board 82 Power supply ready signal 84 AND circuit 86 Temperature sensor 88 Reset signal 90 DC power supply

Claims (4)

A processor that boots upon power-up;
An operation monitoring unit for monitoring the operation of the processor;
A control unit that receives a monitoring result of the operation monitoring unit at the time of startup of the processor, causes the processor to perform warm-up processing if there is an operation abnormality in the processor, and activates an operating system if there is no operation abnormality in the processor;
An electronic device comprising:   The control unit is connected to the processor when there is an abnormal operation in the processor, a multi-core loop operation by a plurality of CPU cores provided in the processor, a bit inversion loop write operation to a memory connected to the processor, The electronic apparatus according to claim 1, wherein one or two or more seek repeated operations are performed on the HDD. A control program to be executed by a computer mounted on an electronic device,
Monitors the operation of the processor that starts when the power is turned on.
A control program for causing the processor to execute a warm-up process if there is an operation abnormality in the processor, and causing the computer to execute a process for starting an operating system if there is no operation abnormality in the processor. Monitors the operation of the processor that starts when the power is turned on.
An electronic device control method, comprising: when starting up the processor, causing the processor to perform a warm-up process if there is an operation abnormality in the processor, and starting up an operating system if there is no operation abnormality in the processor.

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