JP2014093007A - Data transfer apparatus, image processing apparatus, image forming apparatus, data transfer method, and data transfer program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transfer data properly at a high speed.SOLUTION: In an image forming apparatus 1, a controller ASIC 21 generates a false line synchronization signal of the same period as a line synchronization signal to be output from a plotter 33 to an engine ASIC 31, and transfers image data of a memory 25 in synchronization with the false line synchronization signal. The engine ASIC 31 detects the amount of receiving time lag between the image data and the line synchronization signal, and outputs a data receiving timing error signal to the controller ASIC 21 when a data receiving timing error determination value is exceeded. On receipt of the error signal, the controller ASIC 21 corrects generation timing of the false line synchronization signal, to perform data transfer at the same timing as transfer in synchronization with the line synchronization signal.

Description

  The present invention relates to a data transfer apparatus, an image processing apparatus, an image forming apparatus, a data transfer method, and a data transfer program, and more particularly, a data transfer apparatus, an image processing apparatus, an image forming apparatus, and data that appropriately shorten a data transfer time. The present invention relates to a transfer method and a data transfer program.

  In an image forming apparatus such as a copying apparatus, a printer apparatus, a facsimile apparatus, and a composite apparatus, an image processing unit on a plotter side that records and outputs an image on a recording medium such as paper (hereinafter simply referred to as paper), and the plotter A controller-side image processing unit that outputs image data subjected to necessary image processing to the side image processing unit is connected by a high-speed universal standard transmission line (for example, PCI (Peripheral Component Interconnect)). Yes.

  Conventionally, in such an image forming apparatus, as shown in FIG. 15, a plotter issues a frame synchronization signal FSYNC, which is an image data transfer start request for one page, to the plotter side image processing unit, and the first one line When the line synchronization signal LSYNC, which is an image data transfer start request, is issued to the plotter-side image processing unit, the plotter-side image processing unit issues a read request to the controller-side image processing unit. When there is a read request from the plotter-side image processing unit, the controller-side image processing unit reads image data for one line from the memory and transfers it to the plotter-side image processing unit. The plotter-side image processing unit One line of image data sent from the processing unit is transferred to the plotter. When the plotter forms an image based on the image data for one line sent from the plotter-side image processing unit, it again outputs a line synchronization signal LSYNC to the plotter-side image processing unit. The image forming apparatus forms an image for one page by repeatedly performing the above operation process of issuing a read request with the line synchronization signal LSYNC as a trigger for each line.

  Therefore, the conventional image forming apparatus issues a read request to the controller for a delay time t1 from when the line synchronization signal LSYNC is issued to the plotter-side image processing unit until the plotter-side image processing unit issues a read request to the controller. The total of the delay time t2 from the time when the controller reads the image data from the memory to the start of the transfer and the transfer time t3 of the image data is determined by the image data being transferred to the plotter after the plotter issues the line synchronization signal LSYNC. This is the time required to acquire the image data before it comes.

  As described above, in the image forming apparatus, image data is transferred to the plotter by read transfer using the line synchronization signal LSYNC as a trigger. Therefore, the image data is actually transferred from the issuance of the line synchronization signal LSYNC. There was a problem in that there was latency before the data came and the data transfer efficiency was poor.

  As a result, in the conventional image forming apparatus, when the plotter speed is high and the line cycle is short, or when the data amount of one line is large depending on the resolution and gradation of the image, the image data can be stored within one line cycle. Data transfer cannot be completed and an abnormal image occurs.

  For this problem, the data transfer between the controller-side image processing unit and the plotter-side image processing unit is not a transfer based on the synchronization of the line synchronization signal LSYNC. A countermeasure may be considered in which the image data is output to the plotter in synchronization with the line synchronization signal LSYNC at the plotter side image processing unit.

  However, in the case of this countermeasure, it is necessary to provide a buffer memory for storing image data for one page in the plotter-side image processing unit, which causes a problem that the circuit scale increases and the cost increases.

  In addition, in response to the above problems, measures to prevent the occurrence of abnormal images by detecting that the data transfer performance is insufficient with respect to the image output performance of the plotter by some method and relaxing the plotter output performance. Can be considered.

  However, in the case of this countermeasure, there is a problem that the performance inherent in the plotter cannot be sufficiently exhibited, and the plotter output performance as the image forming apparatus is deteriorated.

  Conventionally, an image forming apparatus equipped with a plurality of functions, sends a request by the plurality of functions to access a shared memory, transfers data according to a line synchronization signal, and outputs the transferred data to a plotter A pseudo line synchronization signal generating means for generating a pseudo line synchronization signal having a cycle shorter than the cycle of the line synchronization signal, and a data transfer performance for detecting a decrease in data transfer performance based on the pseudo line synchronization signal. An image forming apparatus including a monitoring unit and an output performance control unit that relaxes plotter output performance when a decrease in data transfer performance is detected has been proposed (see Patent Document 1).

  That is, this conventional technique detects the presence or absence of data transfer performance degradation based on a pseudo line synchronization signal having a cycle shorter than the cycle of the line synchronization signal, and reduces the plotter output performance when the data transfer performance is degraded. Yes.

  However, in the prior art described in the above publication, a drop in data transfer performance is detected based on a pseudo line sync signal having a cycle shorter than the cycle of the line sync signal, and the plotter output performance is matched to the data transfer performance drop. Is mitigated to prevent the occurrence of abnormal images. As a result, there is a problem that not only the image forming processing speed is lowered but also the data transfer speed cannot be improved.

  Therefore, an object of the present invention is to improve the data transfer speed without increasing the circuit scale.

  In order to achieve the above object, a data transfer apparatus according to claim 1, wherein a data providing unit for transferring and outputting the data stored in the storage means by a predetermined unit data amount, and the data from the data providing unit. A data transfer unit connected to the data output unit that receives and outputs the data in response to an output timing signal of a predetermined cycle, wherein the data output unit transfers the data transferred from the data providing unit Data receiving means for receiving the data, data output means for outputting the data of the unit data amount received by the data receiving means in response to the output timing signal, and the data receiving means for the data of the unit data amount Detecting the amount of timing deviation between the data reception timing received and the output timing signal, Timing deviation monitoring means for transmitting to the data providing unit an error signal for notifying the occurrence of timing deviation along with the deviation direction when the amount of timing deviation exceeds a predetermined allowable range, and the data providing unit includes the output timing A transfer timing signal generating means for generating a transfer timing signal having a transfer period substantially the same as the period of the data, and a data transfer for transferring the data of the unit data amount of the storage means to the data output unit in synchronization with the transfer timing signal And when the error signal is transmitted from the data output unit, the transfer timing signal generated by the transfer timing signal generating means is set in a direction to correct the timing deviation based on the error signal. A signal timing correction means that generates a time lag and It is characterized in that it comprises a.

  According to the present invention, the data transfer rate can be improved without increasing the circuit scale.

1 is a block diagram of a main part of an image forming apparatus to which an embodiment of the present invention is applied. The block block diagram of engine ASIC. The block block diagram of controller ASIC. The sequence diagram of image data transfer. The figure which shows image data transfer timing. FIG. 6 is an image data transfer sequence diagram including timing adjustment processing when the pseudo line synchronization signal has a shorter cycle than the actual line synchronization signal. The figure which shows the image data transfer timing in the case of performing the correction which delays the issuing timing of a pseudo line synchronizing signal. FIG. 6 is an image data transfer sequence diagram including a timing adjustment process when a pseudo line synchronization signal has a longer cycle than an actual line synchronization signal. The figure which shows the image data transmission timing in the case of performing the correction which makes the issuing timing of a pseudo | simulation line synchronizing signal early. The block block diagram of engine ASIC which performs data transfer of 4 channels. The block block diagram of the controller ASIC which performs data transfer of 4 channels. The block block diagram of engine ASIC which notifies a timing related signal via CPU. The block block diagram of controller ASIC which notifies a timing related signal via CPU. FIG. 5 is a transmission sequence diagram of image data transfer in which timing adjustment processing is performed via a CPU when a pseudo line synchronization signal has a shorter cycle than an actual line synchronization signal. FIG. 6 is a diagram illustrating image data transfer timing in a conventional image forming apparatus.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The range of this invention is unduly limited by the following description. However, not all the configurations described in the present embodiment are essential constituent elements of the present invention.

  1 to 14 are diagrams showing one embodiment of a data transfer apparatus, an image processing apparatus, an image forming apparatus, a data transfer method, and a data transfer program according to the present invention. FIG. 1 shows a data transfer apparatus according to the present invention, 1 is a block diagram of a main part of an embodiment of an image forming apparatus to which an image processing apparatus, an image forming apparatus, a data transfer method, and a data transfer program are applied.

  In FIG. 1, an image forming apparatus 1 includes a controller unit 2, an engine unit 3, an operation display unit (not shown), a network I / F, an external I / F, and the like, and includes a copying apparatus, a facsimile apparatus, a printer apparatus, and a composite apparatus. Etc.

  The image forming apparatus 1 is connected to a network I / F such as a LAN (Local Area Network) and communicates with an image processing apparatus such as a computer or a composite apparatus connected to the network via the network I / F. Then, the image data is exchanged. In the image forming apparatus 1, a scanner or the like is connected to the external I / F, and image data acquired by the scanner or the like is input via the external I / F.

  The controller unit 2 includes a controller ASIC (Application Specific Integrated Circuit) 21, a hard disk (HDD) 22, a chip set 23, a controller CPU (Central Processing Unit) 24, a memory 25, and the like. The engine unit 3 includes an engine ASIC 31 and an engine CPU 32. And a plotter 33 and the like.

  In the image forming apparatus 1, the controller ASIC 21 of the controller unit 2 and the engine ASIC 31 of the engine unit 3 are connected by a bus such as PCI (Peripheral Component Interconnect) Express.

  In the controller unit 2, a hard disk 22 and a chip set 23 are connected to the controller ASIC 21, and the chip set 23 is further connected to a controller CPU 24 and a memory 25.

  The hard disk 22 stores image data acquired from an external device via the network I / F or external I / F, a program such as the basic program of the image forming apparatus 1 and the data transfer control program of the present invention, and necessary system data. The data is stored and read out via the controller ASIC 21 under the control of the controller CPU 24.

  The controller ASIC (data providing unit) 21 performs various image processing on the image data and stores it in the memory 25 as described later. The controller ASIC 21 reads out the image data stored in the memory 25 one line at a time in synchronization with a predetermined pseudo line synchronization signal LSYNCa (see FIGS. 4 and 5), as will be described later. Transfer to ASIC 31.

  The chip set 23 incorporates a memory controller and various I / Fs, and performs access control to the memory 25, the controller ASIC 21, the hard disk 22, and the like by the controller CPU 24, and access control to the memory 25 by the controller ASIC 21.

  A controller CPU (providing unit control means) 24 controls each part of the image forming apparatus 1 based on a program in the hard disk 22 to execute basic processing as the image forming apparatus 1, and the controller ASIC 21 and engine of the present invention. A data transfer control method with the ASIC 31 is executed. The controller ASIC 21 and the engine ASIC 31 function as a data transfer device (data transfer unit) as a whole.

  That is, the image forming apparatus 1 includes a ROM, an EEPROM (Electrically Erasable and Programmable Read Only Memory), an EPROM, a flash memory, a flexible disk, a CD-ROM (Compact Disc Read Only Memory), a CD-RW (Compact Disc Rewritable), and a DVD. A data transfer control program for executing the data transfer control method of the present invention recorded on a computer-readable recording medium such as a (Digital Versatile Disk), an SD (Secure Digital) card, or an MO (Magneto-Optical Disc) is read. Thus, it is constructed as an image forming apparatus that executes a data transfer control method for improving the transfer speed of image data in the memory 25, which will be described later, to the engine unit 3 without increasing the circuit scale. ing. This data transfer control program is a computer-executable program written in a legacy programming language such as assembler, C, C ++, C #, Java (registered trademark) or an object-oriented programming language, and is stored in the recording medium. And can be distributed.

  The memory (storage means) 25 has a capacity for storing image data for a maximum size of one page in the plotter 33, and temporarily stores image data for image formation in the plotter 33.

  In the engine unit 3, an engine CPU 32 and a plotter 33 are connected to an engine ASIC 31, and the engine ASIC 31 receives image data and control signals from the controller ASIC 21 of the controller unit 2.

  The engine CPU (output control means) 32 controls the operation of the engine ASIC 31 and the plotter 33 based on the program of the hard disk 22 and controls image processing in the engine ASIC 31 and image formation on the paper by the plotter 33. In particular, the engine CPU 32 executes a data transfer control method between the controller ASIC 21 and the engine ASIC 31 based on the data transfer control program of the present invention stored in the hard disk 22 or the like.

  As will be described later, the engine ASIC (data output unit) 31 acquires image data from the controller ASIC 21 of the controller unit 2, performs necessary image processing, and causes the plotter 33 to form an image on a sheet.

  The plotter 33 uses, for example, a recording apparatus of an image forming system such as an electrophotographic system or an ink ejection system, and receives received image data or image data read by a scanner from the engine ASIC 31 and records the image on a sheet. Output.

  When forming an image for one page, the plotter 33 first issues a frame synchronization signal FSYNC to the engine ASIC 31, and then issues a line synchronization signal LSYNC (see FIGS. 4 and 5) to the engine ASIC 31. In response to the line synchronization signal LSYNC, the plotter 33 outputs image data for a predetermined amount of data (for example, one line, in the following description, one line for clarity) from the engine ASIC 31. Upon receipt, an image is formed on the sheet for each line, and when the image formation for one line is completed, the process of repeatedly issuing the line synchronization signal LSYNC to the engine ASIC 31 is repeated to form an image for one page.

  As shown in FIG. 2, the engine ASIC (data output unit) 31 includes a controller I / F control unit 41, an MtoP (Memory to Plotter) buffer 42, an MtoP image processing unit 43, a plotter control unit 44, and a data reception timing. A monitoring unit 45, a register 46, a communication buffer 47, a CPU I / F control unit 48, and the like are provided. The frame synchronization signal FSYNC and the line synchronization signal LSYNC are received from the plotter 33, and the image data is output to the plotter 33 line by line. .

  The controller I / F control unit (data receiving means) 41 receives various parameters and image data from the controller ASIC 21 of the controller unit 2. The controller I / F control unit 41 sets the received various parameters in a register (not shown) and transfers image data received thereafter to the MtoP buffer 42.

  The MtoP buffer 42 is a buffer memory having a predetermined capacity, temporarily stores a predetermined amount of image data, and passes it to the MtoP image processing unit 43.

  The MtoP image processing unit 43 performs various image processing necessary for forming an image with the plotter 33 on the image data passed from the MtoP buffer 42 and outputs the processed image data to the plotter control unit 44.

  The plotter control unit (data output means) 44 receives the frame synchronization signal FSYNC and the line synchronization signal LSYNC from the plotter 33. Every time the plotter control unit 44 receives the line synchronization signal LSYNC from the plotter 33 after receiving the frame synchronization signal FSYNC from the plotter 33 until it receives the next frame synchronization signal FSYNC, Output to the plotter 33.

  The engine ASIC 31 is provided with a signal line for inputting the line synchronization signal LSYNC from the plotter 33 to the data reception timing monitoring unit 45.

  The data reception timing monitoring unit (timing shift monitoring unit) 45 receives the line synchronization signal LSYNC, acquires the transfer timing of image data from the controller I / F control unit 41 to the MtoP buffer 42, and registers 46 To obtain the data reception timing error judgment value (allowable range).

  That is, the register (allowable range storage means) 46 stores a data reception timing error determination value in advance. The data reception timing error determination value is determined by the image data transfer timing from the controller I / F control unit 41 to the MtoP buffer 42 with respect to the signal timing of the line synchronization signal LSYNC having a correlation with the plotter performance of the plotter 33. This is a determination value for determining whether or not it is within the timing at which image formation by the plotter 33 can be appropriately executed. That is, the data reception timing error determination value is the signal timing of the line synchronization signal LSYNC in which the transfer timing of the image data acquired from the controller unit 2 via the controller I / F control unit 41 is correlated with the plotter performance of the plotter 33. On the other hand, a determination value (allowable range) for determining whether or not it is within the timing at which image formation by the plotter 33 can be appropriately executed is set in advance.

  Specifically, the data reception timing monitoring unit 45 sets the time interval from the line synchronization signal LSYNC to the start of image data transfer (hereinafter simply referred to as the transfer start time interval), and the next line from the end of the image data transfer. The time to the synchronization signal LSYNC (hereinafter simply referred to as the synchronization signal time interval as appropriate) is monitored, and these time intervals are compared with the data reception timing error determination value.

  When the transfer start time interval is shorter than the data reception timing error determination value, the data reception timing monitoring unit 45 determines that the data reception timing Under error is detected, and the data reception timing Under error signal (error) to the controller I / F control unit 41 is determined. Signal). Further, when the synchronization signal time interval is longer than the data reception timing error determination value, the data reception timing monitoring unit 45 determines that the data reception timing is over error, and the data reception timing over error signal to the controller I / F control unit 41. (Error signal) is asserted.

  When receiving the data reception timing error signal (data reception timing Under error signal, data reception timing Over error signal), the controller I / F control unit 41 asserts the data reception timing error signal to the controller ASIC 21.

  When the controller I / F control unit 41 receives a data reception timing error clear signal (correction completion signal) to be described later from the controller ASIC 21, the controller I / F control unit 41 outputs the data reception timing error clear signal to the data reception timing monitoring unit 45, and the data reception timing When receiving the data reception timing error clear signal, the monitoring unit 45 negates the data reception timing error signal.

  When the data reception timing error signal from the data reception timing monitoring unit 45 is negated, the controller I / F control unit 41 negates the data reception timing error signal to the controller ASIC 21.

  A CPU I / F control unit 48 is connected to the controller I / F control unit 41 via a communication buffer 47, and the engine CPU 32 is connected to the CPU I / F control unit 48.

  The engine ASIC 31 passes necessary information to the engine CPU 32 connected to the CPU I / F control unit 48 and operates based on a control signal from the engine CPU 32.

  As shown in FIG. 3, the controller ASIC 21 includes a system I / F control unit 51, a register control unit 52, a memory arbiter 53, an image processing WDMAC (Write Direct Memory Access Controller) 54, an image processing RDMAC (Read Direct Memory Access Controller). ) 55, a controller image processing unit 56, an image processing buffer 57, an image output RDMAC 58, an image output buffer 59, an image output unit 60, a pseudo line synchronization signal generation unit 61, a register 62, an engine I / F control unit 63, and the like. Yes.

  The system I / F control unit 51 is connected to the hard disk 22 and the chip set 23, and is connected to each module and the engine I / F control unit 63 via the register control unit 52.

  The register control unit 52 sets the register value from the controller CPU 24 in each register in the controller ASIC 21.

  The memory arbiter 53 performs access control to the memory 25 and the hard disk 22 via the system I / F control unit 51 by the image processing WDMAC 54, the image processing RDMAC 55, and the image output RDMAC 58.

  The image processing RDMAC 55 reads image data from the hard disk 22 or the like via the memory arbiter 53 and passes it to the controller image processing unit 56.

  The controller image processing unit 56 executes various types of image processing using the image processing buffer 57, and the image processing buffer 57 is used as a buffer for image processing by the controller image processing unit 56.

  The image processing WDMAC 54 writes the image data processed by the controller image processing unit 56 in the memory 25 via the memory arbiter 53 and the system I / F control unit 51.

  The image output RDMAC 58 reads the image data from the memory 25 in units of lines via the memory arbiter 53 and the system I / F control unit 51 and temporarily stores the image data in the image output buffer 59.

  The image output buffer 59 has a predetermined capacity, temporarily stores the image data from the image output RDMAC 58, and the stored image data is read by the image output unit 60.

  The image output unit (data transfer means) 60 reads the image data of the image output buffer 59 for each line in synchronization with the pseudo line synchronization signal LSYNCa input from the pseudo line synchronization signal generation unit 61, and performs engine I / F control. To the unit 63.

  The engine I / F control unit 63 transfers the image data for one line sent from the image output unit 60 to the controller I / F control unit 41 of the engine ASIC 31.

  The pseudo line synchronization signal generation unit (transfer timing signal generation means) 61 acquires the pseudo line synchronization signal period data from the register 62, and obtains the pseudo line synchronization signal (data timing signal) LSYNCa corresponding to the acquired line synchronization signal period data. The image is output to the image output unit 60.

  The register (transfer cycle storage means) 62 stores pseudo line synchronization signal cycle data (transfer timing signal transfer cycle) of a cycle corresponding to the line synchronization signal LSYNC output from the plotter 33 in advance, and this pseudo line synchronization signal. The periodic data is output to the pseudo line synchronization signal generator 61.

  The pseudo line synchronization signal generation unit 61 receives a data reception timing error signal from the data reception timing monitoring unit 45 of the engine ASIC 31 via the controller I / F control unit 41 and the engine I / F control unit 63.

  When the data reception timing error signal is input to the pseudo line synchronization signal generation unit 61, the pseudo line synchronization signal to be issued to the image output unit 60 next when the data reception timing error signal is the data reception timing Under error signal. The output timing of LSYNCa is delayed by a predetermined timing set in advance.

  Further, when the input data reception timing error signal is the data reception timing Over error signal, the pseudo line synchronization signal generation unit 61 sets the output timing of the pseudo line synchronization signal LSYNCa to be issued next to the image output unit 60 in advance. Advance the set timing.

  Then, the pseudo line synchronization signal generation unit 61 adjusts the output timing of the pseudo line synchronization signal LSYNCa based on the data reception timing error signal, via the engine I / F control unit 63 and the controller I / F control unit 41. A data reception timing error clear signal (correction completion signal) is transmitted to the data reception timing monitoring unit 45.

  That is, the controller ASIC 21 does not receive the line synchronization signal LSYNC from the engine unit 3, and the pseudo line synchronization signal LSYNCa having substantially the same cycle as the line synchronization signal LSYNC issued by the pseudo line synchronization signal generation unit 61 inside the controller ASIC 21. Based on the above, the image output unit 60 transfers the image data to the engine unit 3.

  Next, the operation of this embodiment will be described. The image forming apparatus 1 of this embodiment improves the image forming processing speed without increasing the circuit scale.

  That is, in the image forming apparatus 1, the controller ASIC 21 of the controller unit 2 does not receive the line synchronization signal LSYNC from the plotter 33, and the line synchronization signal LSYNC issued by the pseudo line synchronization signal generation unit 61 inside the controller ASIC 21. The image data is transferred to the engine unit 3 based on the pseudo line synchronization signal LSYNCa having a cycle substantially the same as the cycle.

  The image forming apparatus 1 performs the necessary image processing on the image data on the hard disk 22 and then stores it in the memory 25, and transfers the image data in the memory 25 to the plotter 33 of the engine unit 3 to form an image. In this image forming operation, the image forming apparatus 1 performs image data transfer processing as shown in FIG.

  That is, the image forming apparatus 1 has parameters (MtoP transfer) necessary for the controller CPU 24 to transfer image data to the controller ASIC 21 by MtoP (memory to plotter) as shown in FIG. Parameter) is set in the engine CPU 32 (S1), and the engine CPU 32 sets the MtoP transfer parameter in the engine ASIC 31 (S2). The controller CPU 24 sets pseudo line synchronization signal cycle data in the register 62 of the controller ASIC 21 (S3), and the engine CPU 32 sets a data reception timing error determination value in the register 46 (S4).

  When the engine CPU 32 completes the setting of necessary parameters and setting values, the engine CPU 32 outputs a trigger for starting MtoP transfer to the engine ASIC 31 (S5). In the controller ASIC 21, when the pseudo line synchronization signal cycle data is set in the register 62 and a predetermined time elapses, the pseudo line synchronization signal generation unit 61 pre-reads the image data by the buffer of the MtoP buffer 42 of the engine ASIC 31. The pseudo line synchronization signal LSYNCa is issued to the output unit 60 (S6). At this time, the controller ASIC 21 reads out a predetermined amount of image data from the memory 25 via the memory arbiter 53 and the system I / F control unit 51 by the image output RDMAC 58 and stores it in the image output buffer 59.

  When the pseudo line synchronization signal LSYNCa is input, the image output unit 60 transfers the pre-read image data of the image output buffer 59 to the engine ASIC 31 via the engine I / F control unit 63 (S7).

  The engine ASIC 31 receives the pre-read image data transferred from the controller ASIC 21 by the controller I / F control unit 41 and stores it in the MtoP buffer 42.

  Thereafter, in the engine unit 3, the plotter 33 issues a frame synchronization signal FSYNC to the engine ASIC 31 (S8), and subsequently issues a line synchronization signal LSYNC (S9).

  On the other hand, in the controller ASIC 21, the pseudo line synchronization signal generator 61 outputs the pseudo line synchronization signal LSYNCa based on the pseudo line synchronization signal period data of the register 62 without depending on the line synchronization signal LSYNC issued by the plotter 33. Issued to the output unit 60 (S10), the image output unit 60 reads out image data for one line from the image output buffer 59 in synchronization with the pseudo line synchronization signal LSYNCa, and passes through the engine I / F control unit 63. To the engine ASIC 31 (S11).

  The engine ASIC 31 temporarily stores the image data transferred from the controller ASIC 21 in the MtoP buffer 42, and then performs necessary image processing by the MtoP image processing unit 43 and passes it to the plotter control unit 44. 33 transfers.

  The image forming apparatus 1 repeatedly performs the transfer process from S9 to S11 between the controller ASIC 21 and the engine ASIC 31. When the transfer of the image data for one page is completed, the image data transfer process ends.

  That is, in the image forming apparatus 1 of this embodiment, the controller ASIC 21 does not depend on the line synchronization signal LSYNC issued by the plotter 33, as shown in FIG. The image data is transferred to the engine ASIC 31 in synchronization with the pseudo line synchronization signal LSYNCa issued by the signal generator 61.

  Therefore, in the image forming apparatus 1 of this embodiment, the delay time t4 from when the line synchronization signal LSYNC is issued by the plotter 33 to when the controller ASIC 21 issues the pseudo line synchronization signal LSYNCa and transmission of image data is started. The total of the image data transfer time t3 is the image data acquisition time required from when the plotter 33 issues the line synchronization signal LSYNC to when the image data is transferred to the plotter 33.

  That is, it is not necessary to request data transfer from the controller ASIC 21 to the engine ASIC 31 from the engine ASIC 31 for each line as compared with the data transfer according to the conventional method shown in FIG. The transfer time of minutes can be reduced.

  As a result, the image data acquisition time can be shortened compared with the conventional technique shown in FIG. 15 without providing a large-capacity memory in the engine unit 3, and the image forming processing speed is improved at a low cost. Can be made.

  However, in the image forming apparatus 1 of this embodiment, the transfer timings between the controller ASIC 21 and the engine ASIC 31 and between the engine ASIC 31 and the plotter 33 are asynchronous. That is, the pseudo line synchronization signal generation unit 61 of the controller ASIC 21 issues the pseudo line synchronization signal LSYNCa based on the pseudo line synchronization signal cycle set to substantially the same cycle as the line synchronization signal LSYNC issued by the plotter 33. The issuance timing of the pseudo line synchronization signal LSYNCa issued each time has no dependency on the line synchronization signal LSYNC issued by the plotter 33. For example, when the plotter 33 is an electrophotographic plotter, the pseudo-line synchronization signal LSYNCa is issued by the independent pseudo-line synchronization signal generation unit 61 that does not depend on the rotation of the polygon. Is done.

  Therefore, the image forming apparatus 1 may have a slight difference between the cycle of the pseudo line synchronization signal LSYNCa and the cycle of the actual line synchronization signal LSYNC issued by the plotter 33. When the image forming apparatus 1 repeatedly transfers the image data for one line in a state in which this period deviation exists, the controller ASIC 21 has a degree that the period deviation accumulates and affects the image quality in the plotter 33. The data transfer timing from is delayed or delayed relative to the actual line synchronization signal LSYNC.

  In this case, for example, when the data transfer timing from the controller ASIC 21 is too early with respect to the actual line synchronization signal LSYNC, the image forming apparatus 1 completes the output of the image data one line before from the MtoP buffer 42 to the plotter 33. The image data of the next line is transferred to the MtoP buffer 42 before. As a result, in the MtoP buffer 42, the image data of the previous line is overwritten with the image data of the next line, and an abnormal image is generated.

  Conversely, when the data transfer timing from the controller ASIC 21 is too late with respect to the actual line synchronization signal LSYNC, the image forming apparatus 1 completes the transfer of the image data of the previous line to the plotter 33 in the MtoP buffer 42. Thus, the data output to the plotter 33 is started before the image data of the next line is stored. As a result, an abnormal image is generated.

  Therefore, in the image forming apparatus 1 of the present embodiment, the data reception timing monitoring unit 45 of the engine ASIC 31 monitors the deviation of the transfer timing of the image data from the controller ASIC 21 with respect to the actual line synchronization signal LSYNC from the plotter 33. Is larger or smaller than the data reception timing error determination value preset in the register 46, a data reception timing error signal is output to the controller ASIC 21 to correct the deviation.

  First, when the data transfer timing from the controller ASIC 21 is too early with respect to the actual line synchronization signal LSYNC, that is, when the cycle of the pseudo line synchronization signal LSYNCa is shorter than the cycle of the actual line synchronization signal LSYNC, FIG. This will be described with reference to FIG. In FIG. 6, the same processing numbers as those in FIG. 4 are assigned the same processing numbers to simplify the description.

  In the image forming apparatus 1, at the image formation timing in FIG. 6, as in the case of FIG. 4, the controller CPU 24 sets the MtoP transfer parameter in the engine CPU 32 (S 1), and the engine CPU 32 sets the MtoP transfer parameter. The engine ASIC 31 is set (S2). The controller CPU 24 sets pseudo line synchronization signal cycle data in the register 62 of the controller ASIC 21 (S3), and the engine CPU 32 sets a data reception timing error determination value in the register 46 (S4).

  Next, the engine CPU 32 outputs an MtoP transfer start trigger to the engine ASIC 31 (S5), and the controller ASIC 21 pre-reads the image data by an amount corresponding to the buffer of the MtoP buffer 42 of the engine ASIC 31, 61 issues a pseudo-line synchronization signal LSYNCa to the image output unit 60 (S6).

  When the pseudo line synchronization signal LSYNCa is input, the image output unit 60 transfers the pre-read image data of the image output buffer 59 to the engine ASIC 31 via the engine I / F control unit 63 (S7).

  The engine ASIC 31 receives the pre-read image data transferred from the controller ASIC 21 by the controller I / F control unit 41 and stores it in the MtoP buffer 42.

  Thereafter, in the engine unit 3, the plotter 33 issues a frame synchronization signal FSYNC to the engine ASIC 31 (S8), and subsequently issues a line synchronization signal LSYNC (S9).

  On the other hand, in the controller ASIC 21, the pseudo line synchronization signal generator 61 outputs the pseudo line synchronization signal LSYNCa based on the pseudo line synchronization signal period data of the register 62 without depending on the line synchronization signal LSYNC issued by the plotter 33. It is issued to the output unit 60 (S10). The image output unit 60 reads image data for one line from the image output buffer 59 in synchronization with the pseudo line synchronization signal LSYNCa, and transfers it to the engine ASIC 31 via the engine I / F control unit 63 (S11). .

  The engine ASIC 31 temporarily stores the image data transferred from the controller ASIC 21 in the MtoP buffer 42, and then performs necessary image processing by the MtoP image processing unit 43 and passes it to the plotter control unit 44. 33 transfers.

  The image forming apparatus 1 repeatedly performs the transfer processing from S9 to S11 between the controller ASIC 21 and the engine ASIC 31 to transfer the image data for one page. However, the cycle of the pseudo line synchronization signal LSYNCa is actually When the period of the line synchronization signal LSYNC is shorter (faster) than the period of the line synchronization signal LSYNC, as shown in FIG. 6, while the image data transfer is performed for each line, the pseudo line synchronization signal LSYNCa and the actual line synchronization signal LSYNC are The amount of timing deviation is smaller than the data reception timing error determination value set in the register 46.

  The data reception timing monitoring unit 45 of the engine ASIC 31 monitors the amount of deviation between the transfer timing of the image data and the actual line synchronization signal LSYNC. When the data reception timing monitoring unit 45 detects that the amount of deviation is smaller than the data reception timing error determination value (S21), the data reception timing monitoring unit 45 sends the data reception timing Under error signal to the controller before transferring the next line image data. The data is transmitted to the ASIC 21 (S22).

  When the pseudo line synchronization signal generation unit 61 of the controller ASIC 21 receives the data reception timing Under error signal from the engine ASIC 31, the pseudo line synchronization signal generation unit 61 performs timing correction to delay the issue timing of the next pseudo line synchronization signal LSYNCa to the image output unit 60 by a predetermined time. The pseudo line synchronization signal LSYNCa is issued (S23, S10).

  That is, as shown in FIG. 7, the image forming apparatus 1 according to the present embodiment performs transfer processing of image data for each line in which the cycle of the pseudo line synchronization signal LSYNCa is shorter than the cycle of the actual line synchronization signal LSYNC. If the amount of deviation between the image transfer timing from the controller ASIC 21 and the actual line synchronization signal LSYNC becomes smaller than the data reception timing error determination value, the data reception timing monitoring unit 45 of the engine ASIC 31 receives the data reception timing Under error. Assert signal.

  When the data reception timing Under error signal is asserted, the pseudo line synchronization signal generation unit 61 of the controller ASIC 21 performs a correction to delay the output timing of the next pseudo line synchronization signal LSYNCa.

  Then, the pseudo line synchronization signal generation unit 61 adjusts the output timing of the pseudo line synchronization signal LSYNCa based on the data reception timing error signal, via the engine I / F control unit 63 and the controller I / F control unit 41. A data reception timing error clear signal is transmitted to the data reception timing monitoring unit 45.

  When receiving the data reception timing error clear signal, the data reception timing monitoring unit 45 negates the data reception timing Under error signal as shown in FIG.

  Therefore, even when the period of the pseudo line synchronization signal LSYNCa is shorter than the period of the actual line synchronization signal LSYNC, the issuance timing of the pseudo line synchronization signal LSYNCa is appropriately adjusted. As a result, the time required for image data acquisition can be shortened compared with the conventional technique shown in FIG. 15 without providing a large-capacity memory in the engine unit 3, and the image forming processing speed can be reduced at a lower cost. Can be improved.

  Next, when the data transfer timing from the controller ASIC 21 is too late with respect to the actual line synchronization signal LSYNC, that is, when the cycle of the pseudo line synchronization signal LSYNCa is longer than the cycle of the actual line synchronization signal LSYNC, FIG. And it demonstrates based on FIG. In FIG. 8, the same processing numbers are assigned to the same processing as in FIG. 4, and the description is simplified.

  In the image forming apparatus 1 in FIG. 8, when the image formation timing comes, the controller CPU 24 sets the MtoP transfer parameter in the engine CPU 32 as in the case of FIG. 4 (S1). The engine CPU 32 sets the MtoP transfer parameter in the engine ASIC 31 (S2). The controller CPU 24 sets pseudo line synchronization signal cycle data in the register 62 of the controller ASIC 21 (S3), and the engine CPU 32 sets a data reception timing error determination value in the register 46 (S4).

  Next, the engine CPU 32 outputs an MtoP transfer start trigger to the engine ASIC 31 (S5), and the controller ASIC 21 pre-reads the image data by an amount corresponding to the buffer of the MtoP buffer 42 of the engine ASIC 31, 61 issues a pseudo-line synchronization signal LSYNCa to the image output unit 60 (S6).

  When the pseudo line synchronization signal LSYNCa is input, the image output unit 60 transfers the pre-read image data of the image output buffer 59 to the engine ASIC 31 via the engine I / F control unit 63 (S7).

  The engine ASIC 31 receives the pre-read image data transferred from the controller ASIC 21 by the controller I / F control unit 41 and stores it in the MtoP buffer 42.

  Thereafter, in the engine unit 3, the plotter 33 issues a frame synchronization signal FSYNC to the engine ASIC 31 (S8), and subsequently issues a line synchronization signal LSYNC (S9).

  On the other hand, in the controller ASIC 21, the pseudo line synchronization signal generator 61 outputs the pseudo line synchronization signal LSYNCa based on the pseudo line synchronization signal period data of the register 62 without depending on the line synchronization signal LSYNC issued by the plotter 33. Issued to the output unit 60 (S10), the image output unit 60 reads out image data for one line from the image output buffer 59 in synchronization with the pseudo line synchronization signal LSYNCa, and passes through the engine I / F control unit 63. To the engine ASIC 31 (S11).

  The engine ASIC 31 temporarily stores the image data transferred from the controller ASIC 21 in the MtoP buffer 42, and then performs necessary image processing by the MtoP image processing unit 43 and passes it to the plotter control unit 44. 33 transfers.

  The image forming apparatus 1 repeatedly performs the transfer processing from S9 to S11 between the controller ASIC 21 and the engine ASIC 31 to transfer the image data for one page. However, the cycle of the pseudo line synchronization signal LSYNCa is actually If the period is longer (slower) than the period of the line synchronization signal LSYNC, as shown in FIG. 8, while the image data transfer is performed for each line, the pseudo line synchronization signal LSYNCa and the actual line synchronization signal LSYNC are The amount of timing deviation is larger than the data reception timing error determination value set in the register 46.

  The data reception timing monitoring unit 45 of the engine ASIC 31 monitors the timing deviation between the pseudo line synchronization signal LSYNCa and the actual line synchronization signal LSYNC, and the deviation amount is larger than the data reception timing error determination value. Is detected (S31), a data reception timing Over error signal is transmitted to the controller ASIC 21 before transfer of the next line image data (S32).

  When the pseudo line synchronization signal generation unit 61 of the controller ASIC 21 receives the data reception timing Over error signal from the engine ASIC 31, the pseudo line synchronization signal generation unit 61 performs timing correction to advance the issuance timing of the next pseudo line synchronization signal LSYNCa to the image output unit 60 by a predetermined time. The pseudo line synchronization signal LSYNCa is issued (S33, S10).

  That is, as shown in FIG. 9, the image forming apparatus 1 according to the present embodiment performs a transfer process of image data for each line in which the cycle of the pseudo line synchronization signal LSYNCa is longer than the cycle of the actual line synchronization signal LSYNC. If the amount of deviation between the image transfer timing from the controller ASIC 21 and the actual line synchronization signal LSYNC becomes larger than the data reception timing error determination value, the data reception timing monitoring unit 45 of the engine ASIC 31 causes the data reception timing over error. Assert signal.

  When the data reception timing Over error signal is asserted, the pseudo line synchronization signal generation unit 61 of the controller ASIC 21 performs correction to advance the output timing of the next pseudo line synchronization signal LSYNCa, as shown by an arrow in FIG.

  Then, when the output timing of the pseudo line synchronization signal LSYNCa is adjusted based on the data reception timing Over error signal, the pseudo line synchronization signal generation unit 61 passes through the engine I / F control unit 63 and the controller I / F control unit 41. Then, a data reception timing error clear signal is transmitted to the data reception timing monitoring unit 45.

  When receiving the data reception timing error clear signal, the data reception timing monitoring unit 45 negates the data reception timing Over error signal as shown in FIG.

  Therefore, the image forming apparatus 1 appropriately adjusts the issuance timing of the pseudo line synchronization signal LSYNCa even when the cycle of the pseudo line synchronization signal LSYNCa is longer than the cycle of the actual line synchronization signal LSYNC. As a result, the image forming apparatus 1 can shorten the time required for image data acquisition without providing a large-capacity memory in the engine unit 3, and can reduce the cost compared to the conventional technique shown in FIG. In addition, the image forming processing speed can be improved.

  In the above description, the case where the image forming apparatus 1 includes only one data transfer channel, for example, a case where monochrome image data is transferred has been described. However, a plurality of data transfer channels such as FIG. As shown in FIG. 11, the same can be applied to the case of transferring color image data with four channels.

  That is, the image forming apparatus 1 transfers image data of four colors C (cyan), M (magenta), Y (yellow), and K (black) from the controller ASIC to the engine ASIC through a 4-channel data transfer path. In this case, an engine ASIC 100 as shown in FIG. 10 and a controller ASIC 110 as shown in FIG. 11 are provided.

  As shown in FIG. 10, the engine ASIC (data output unit) 100 is the same as the engine ASIC 31 described above, but a controller I / F control unit 41, a communication buffer 47, and a CPU I / F control unit that perform processing for four channels. 48 and data transfer / monitoring units 101a to 101d for four channels.

  Each of the data transfer / monitoring units 101a to 101d includes an MtoP buffer 42, an MtoP image processing unit 43, a plotter I / F control unit 44, a data reception timing monitoring unit 45, and a register 46 similar to the engine ASIC 31. The image data transfer corresponding to the channel and the data reception timing are monitored.

  As shown in FIG. 11, the controller ASIC (data providing unit) 110 is the same as the controller ASIC 21, but a system I / F control unit 51, a register control unit 52, a memory arbiter that performs processing for four channels. 53, an image processing WDMAC 54, an image processing RDMAC 55, a controller image processing unit 56, an image processing buffer 57, and an engine I / F control unit 63, and data transfer / adjustment units 110a to 110d for four channels. .

  Each of the data transfer / adjustment units 110a to 110d includes an image output RDMAC 58, an image output buffer 59, an image output unit 60, a pseudo line synchronization signal generation unit 61, and a register 62 similar to those of the controller ASIC 21, and corresponds to each channel. The image data to be transferred is transferred and the transfer timing is adjusted.

  In this manner, even when the image forming apparatus 1 transfers image data of a plurality of colors to form a color image, the transfer speed of the image data is appropriately adjusted without providing a large capacity memory in the engine unit 3. Can be improved.

  Further, in the above description, the image forming apparatus 1 of the present embodiment directly transmits the data reception timing error signal (data reception timing Under error signal, data reception timing Over error signal) and the data reception timing error clear signal to the controller ASIC 21. Transmission / reception is performed between the engine ASIC 31 or between the controller ASIC 110 and the engine ASIC 100. The image forming apparatus 1 is not limited to the case where these data reception timing error signal and data reception timing error clear signal are directly transmitted / received between the controller ASIC 21 and the engine ASIC 31 or between the controller ASIC 110 and the engine ASIC 100. Instead, for example, as shown in FIGS. 12 and 13, the engine ASIC 120 and the controller ASIC 130 may notify via the engine CPU 32 and the controller CPU 24.

  In this case, as shown in FIG. 12, in the engine ASIC (data output unit) 120, the data reception timing monitoring unit (timing signal monitoring unit) 121 determines the timing between the transfer timing of the image data and the actual line synchronization signal LSYNC. Monitor the amount of deviation. When the data reception timing monitoring unit 121 detects that the amount of deviation is larger or smaller than the data reception timing error determination value, the data reception timing error interrupt (data reception timing Under error interrupt, data reception timing Over error) Interrupt) is issued to the engine CPU 32 via the CPU I / F control unit 48.

  When there is a data reception timing error interrupt from the data reception timing monitoring unit 121, the engine CPU 32 transmits a data reception timing error signal (data reception timing Under error signal, data reception timing Over error signal) to the controller CPU 24.

  As shown in FIG. 13, in the controller ASIC (data providing unit) 130, the data reception timing error signal from the controller CPU 24 is input to the pseudo line synchronization signal generation unit 131 via the register control unit 52. The pseudo line synchronization signal generation unit (transfer timing signal generation unit) 131 delays the pseudo line synchronization signal LSYNCa according to the data reception timing error signal (data reception timing Under error signal, data reception timing Over error signal). Correction or timing correction to make it faster is executed.

  In this case, the pseudo line synchronization signal generation unit 131 does not output the data reception timing error clear signal, and the controller CPU 24 transmits it to the engine CPU 32.

  That is, in the case of FIGS. 12 and 13, for example, when the cycle of the pseudo line synchronization signal LSYNCa is shorter than the cycle of the actual line synchronization signal LSYNC, the timing of the pseudo line synchronization signal LSYNCa is adjusted as shown in FIG. . In FIG. 14, the same processing numbers as those in FIG. 4 are given the same processing numbers to simplify the description.

  In the image forming apparatus 1, at the image formation timing in FIG. 14, as in the case of FIG. 4, the controller CPU 24 sets the MtoP transfer parameter in the engine CPU 32 (S 1), and the engine CPU 32 sets the MtoP transfer parameter. The engine ASIC 120 is set (S2). The controller CPU 24 sets pseudo line synchronization signal cycle data in the register 62 of the controller ASIC 130 (S3), and the engine CPU 32 sets a data reception timing error determination value in the register 46 (S4).

  Next, the engine CPU 32 outputs an MtoP transfer start trigger to the engine ASIC 120 (S5), and the controller ASIC 130 pre-reads the image data by an amount corresponding to the buffer of the MtoP buffer 42 of the engine ASIC 120 to generate a pseudo line synchronization signal generator. 131 issues a pseudo line synchronization signal LSYNCa to the image output unit 60 (S6).

  When the pseudo line synchronization signal LSYNCa is input, the image output unit 60 transfers the pre-read image data in the image output buffer 59 to the engine ASIC 120 via the engine I / F control unit 63 (S7).

  The engine ASIC 120 receives the pre-read image data transferred from the controller ASIC 130 by the controller I / F control unit 41 and stores it in the MtoP buffer 42.

  Thereafter, in the engine unit 3, the plotter 33 issues a frame synchronization signal FSYNC to the engine ASIC 120 (S8), and subsequently issues a line synchronization signal LSYNC (S9).

  On the other hand, in the controller ASIC 130, the pseudo line synchronization signal generation unit 131 outputs the pseudo line synchronization signal LSYNCa as an image based on the pseudo line synchronization signal period data in the register 62 without depending on the line synchronization signal LSYNC issued by the plotter 33. It is issued to the output unit 60 (S10). The image output unit 60 reads image data for one line from the image output buffer 59 in synchronization with the pseudo line synchronization signal LSYNCa, and transfers it to the engine ASIC 31 via the engine I / F control unit 63 (S11). .

  The engine ASIC 120 temporarily stores the image data transferred from the controller ASIC 130 in the MtoP buffer 42, and then performs necessary image processing by the MtoP image processing unit 43 and passes it to the plotter control unit 44. 33 transfers.

  The image forming apparatus 1 repeatedly performs the transfer process from S9 to S11 between the controller ASIC 130 and the engine ASIC 120 to transfer image data for one page. When the cycle of the pseudo line synchronization signal LSYNCa is shorter (faster) than the cycle of the actual line synchronization signal LSYNC, the image forming apparatus 1 performs the image data transfer for each line as shown in FIG. The amount of deviation between the transfer timing of the image data and the actual line synchronization signal LSYNC is smaller than the data reception timing error determination value set in the register 46.

  The data reception timing monitoring unit 121 of the engine ASIC 120 monitors the amount of deviation between the image data transfer timing and the actual line synchronization signal LSYNC, and this amount of deviation is smaller than the data reception timing error determination value. When this is detected (S21), before the next line image data is transferred, a data reception timing Under error interrupt is issued to the engine CPU 32 via the CPU I / F control unit 48 (S41).

  When there is a data reception timing Under error interrupt, the engine CPU 32 transmits a data reception timing Under error signal to the controller CPU 24 (S42). When receiving the data reception timing Under error signal, the controller CPU 24 outputs the data reception timing Under error signal to the pseudo line synchronization signal generation unit 131 via the register control unit 52 of the controller ASIC 130 (S43).

  When the pseudo line synchronization signal generation unit 131 receives the data reception timing Under error signal from the controller CPU 24, the pseudo line synchronization signal generation unit 131 performs timing correction to delay the issue timing of the next pseudo line synchronization signal LSYNCa to the image output unit 60 by a predetermined time. A synchronization signal LSYNCa is issued (S43, S10).

  Then, the controller CPU 24 transmits a data reception timing error clear signal to the engine CPU 32 (S44), and the engine CPU 32 sends the data reception timing error clear signal to the data reception timing monitoring unit via the CPU I / F control unit 48 of the engine ASIC 120. It transmits to 121 (S45).

  When receiving the data reception timing error clear signal, the data reception timing monitoring unit 121 stops the data reception timing Under error interrupt.

  In this way, the hardware overhead for transmitting the data reception timing error signal from the engine unit 3 to the controller unit 2 can be reduced, and the circuit configuration can be reduced in size.

  As described above, the image forming apparatus 1 according to the present exemplary embodiment includes a controller ASIC (data providing unit) 21 that transfers and outputs image data (data) stored in the memory (storage unit) 25 by a predetermined unit data amount; A data transfer device (data) that is connected to an engine ASIC (data output unit) 31 that receives image data from the controller ASIC 21 and outputs the image data in response to a line synchronization signal (output timing signal) LSYNC in a predetermined cycle. A controller I / F control unit (data receiving means) 41 for receiving image data transferred from the controller ASIC 21 and one line received by the controller I / F control unit 41. Minute (unit data amount) of image data is output according to the line sync signal LSYNC. The plotter control unit (data output means) 44 and the controller I / F control unit 41 that detect the timing of detecting the timing deviation between the data reception timing when the image data for one line is received and the line synchronization signal LSYNC are detected. When the amount of deviation exceeds a predetermined data reception timing error determination value (allowable range), a data reception timing monitoring unit that transmits a data reception timing error signal (error signal) that notifies the occurrence of timing deviation along with the deviation direction to the controller ASIC 21 ( And a pseudo line synchronization signal generation unit (transfer timing signal) for generating a pseudo line synchronization signal (transfer timing signal) LSYNCa having a transfer cycle substantially the same as the cycle of the line synchronization signal LSYNC. Generating means) 61 and pseudo line synchronization signal LSYNCa When an image output unit (data transfer means) 60 for transferring the image data for one line in the memory 25 to the engine ASIC 31 in synchronization is transmitted from the engine ASIC 31, the pseudo line synchronization signal A pseudo line synchronization signal generation unit (signal timing correction unit) 61 that generates the pseudo line synchronization signal LSYNCa generated by the generation unit 61 by shifting the pseudo line synchronization signal LSYNCa by a predetermined time in the direction of correcting the timing deviation based on the data reception timing error signal. And.

  Therefore, the controller ASIC 21 does not have a large memory in the engine ASIC 31 and transfers the line synchronization signal LSYNC from the engine ASIC 31 to the controller ASIC 21 based on the pseudo line synchronization signal LSYNC having the same cycle as the line synchronization signal LSYNC. The image data can be transferred line by line to the engine ASIC 31 and the data transfer speed can be improved without increasing the circuit scale. As a result, an image with good image quality can be recorded and output at high speed without degrading the plotter performance of the plotter 33.

  Further, the image forming apparatus 1 according to the present embodiment receives a controller ASIC 21 that transfers and outputs data stored in the memory 25 line by line, and receives the data from the controller ASIC 21 to generate a line synchronization signal LSYNC with a predetermined cycle. A data transfer method executed by a data transfer apparatus connected to the engine ASIC 31 that outputs the data in response to the engine ASIC 31, wherein the engine ASIC 31 receives data transferred from the controller ASIC 21. A data output processing step for outputting the data for one line received in the data reception processing step in response to a line synchronization signal LSYNC, and the data for one line is received in the data reception processing step. Timing of data reception and line synchronization signal LSYNC Timing deviation monitoring processing step of detecting a deviation amount and transmitting a data reception timing error signal for notifying the occurrence of timing deviation together with the deviation direction to the controller ASIC 21 when the timing deviation amount exceeds a predetermined data reception timing error determination value. The controller ASIC 21 generates a pseudo line synchronization signal LSYNCa having a transfer cycle substantially the same as the cycle of the line synchronization signal LSYNC, and a transfer timing signal generation processing step in synchronization with the pseudo line synchronization signal LSYNCa. A data transfer processing step for transferring data for one line to the engine ASIC 31, and when a data reception timing error signal is transmitted from the engine ASIC 31, a pseudo line synchronization signal LSYNCa generated in the next transfer timing signal generation processing step. The And a signal timing correction processing step generated by shifting the timing deviation in a direction to correct the timing deviation based on a data reception timing error signal.

  Therefore, the controller ASIC 21 does not have a large memory in the engine ASIC 31 and transfers the line synchronization signal LSYNC from the engine ASIC 31 to the controller ASIC 21 based on the pseudo line synchronization signal LSYNC having the same cycle as the line synchronization signal LSYNC. The image data can be transferred line by line to the engine ASIC 31 and the data transfer speed can be improved without increasing the circuit scale. As a result, an image with good image quality can be recorded and output at high speed without degrading the plotter performance of the plotter 33.

  Further, the image forming apparatus 1 according to the present embodiment receives a controller ASIC 21 that transfers and outputs data stored in the memory 25 for each line, and receives the data from the controller ASIC 21 to generate a line synchronization signal LSYNC with a predetermined cycle. A data transfer program installed in a data transfer device connected to the engine ASIC 31 that outputs the data in response to the control processor, and receives data transferred from the controller ASIC 21 in the engine ASIC 31 Data reception processing, data output processing for outputting data for one line received in the data reception processing in response to a line synchronization signal LSYNC, and data for which the data for one line has been received in the data reception processing Timing of reception and line synchronization signal LSYNC A timing deviation monitoring process for detecting a deviation amount, and when the timing deviation amount exceeds a predetermined data reception timing error determination value, transmitting a data reception timing error signal for notifying the occurrence of the timing deviation together with the deviation direction to the controller ASIC 21; In the controller ASIC 21, a transfer timing signal generation process for generating a pseudo line synchronization signal LSYNCa having a transfer cycle substantially the same as the cycle of the line synchronization signal LSYNC, and one line of the memory 25 in synchronization with the pseudo line synchronization signal LSYNCa When a data transfer timing error signal is transmitted from the engine ASIC 31, the pseudo line synchronization signal LSYNCa generated in the transfer timing signal generation process is then transferred to the data transfer process for transferring the minute data to the engine ASIC 31. Receive timing error A data transfer program for executing a signal timing correction process generated by shifting a predetermined time in the direction of correcting the timing shift based on the signal is mounted.

  Therefore, the controller ASIC 21 does not have a large memory in the engine ASIC 31 and transfers the line synchronization signal LSYNC from the engine ASIC 31 to the controller ASIC 21 based on the pseudo line synchronization signal LSYNC having the same cycle as the line synchronization signal LSYNC. The image data can be transferred line by line to the engine ASIC 31 and the data transfer speed can be improved without increasing the circuit scale. As a result, an image with good image quality can be recorded and output at high speed without degrading the plotter performance of the plotter 33.

  In the image forming apparatus 1 of the present embodiment, the engine ASIC 31 further includes a register (allowable range storage unit) 46 in which a data reception timing error determination value (allowable range) is set and registered, and the data reception timing monitoring unit 45. However, the data reception timing error determination value of the register 46 is compared with the timing deviation amount.

  Accordingly, the data reception timing error determination value can be set as appropriate, and the timing shift is determined based on the data reception timing error determination value set according to the system configuration, the operation mode, etc., and the data transfer is intended by the user. Can be executed with accuracy and speed.

  Further, in the image forming apparatus 1 according to the present embodiment, the controller ASIC 21 further includes a register (transfer cycle storage unit) 62 in which the pseudo line synchronization signal period is set and registered, and the pseudo line synchronization signal generation unit 61 includes the register 62. The pseudo line synchronization signal LSYNCa is generated based on the pseudo line synchronization signal period.

  Therefore, the pseudo line synchronization signal cycle can be set as appropriate, and the pseudo line synchronization signal LSYNCa is generated based on the pseudo line synchronization signal cycle set according to the system configuration, the operation mode, etc. Can be further improved.

  Further, in the image forming apparatus 1 of the present embodiment, when the data reception timing monitoring unit 45 transmits the data reception timing error signal, the timing shift amount detection operation is stopped, and a pseudo line as the signal timing correction unit is provided. When the synchronization signal generation unit 61 completes the correction of the timing shift of the pseudo line synchronization signal LSYNCa, the data reception timing error clear signal (correction completion signal) is transmitted to the engine ASIC 31, and the data reception timing monitoring unit 45 receives the data reception. When the timing error clear signal is transmitted, the timing shift detection operation is resumed.

  Accordingly, the timing shift amount detection operation can be stopped until the data reception timing monitoring unit 45 of the engine ASIC 31 confirms that the timing correction is completed based on the data reception timing error signal in the control ASIC 21. It is possible to prevent the data reception timing error signal from being transmitted by continuously detecting errors until completion.

  Further, in the image forming apparatus 1 of the present embodiment, the engine ASIC 31 is controlled by the engine CPU 32, the controller ASIC 21 is controlled by the controller CPU 24, and the data reception timing monitoring unit 45 controls the engine CPU 32 with respect to the engine CPU 32. A data reception timing error signal is notified by an interrupt to the engine CPU 32. When the engine CPU 32 receives the notification of the data reception timing error signal by an interrupt, the engine CPU 32 transmits the data reception timing error signal to the controller CPU 24. However, when the data reception timing error signal is received, the data reception timing error signal is output to the pseudo line synchronization signal generation unit 61.

  Therefore, the data reception timing error signal can be transmitted via the engine CPU 32 and the controller CPU 24, and the hardware configuration for transmitting the data reception timing error signal directly from the engine ASIC 31 to the controller ASIC 21 can be omitted. Can be miniaturized.

  In the above description, the case where the present invention is applied to the image forming apparatus 1 has been described. However, in general, a device including a data transfer device that transmits and receives data at a predetermined cycle, for example, a scanner device, and image data is transferred to an external device. The present invention can be similarly applied to an image processing apparatus that transfers data in synchronization with the synchronization signal.

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to that described in the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 2 Controller unit 3 Engine unit 21 Controller ASIC
22 Hard disk (HDD)
23 Chipset 24 Controller CPU
25 Memory 31 Engine ASIC
32 engine CPU
33 Plotter 41 Controller I / F control unit 42 MtoP buffer 43 MtoP image processing unit 44 Plotter control unit 45 Data reception timing monitoring unit 46 Register 47 Communication buffer 48 CPU I / F control unit 51 System I / F control unit 52 Register control unit 53 Memory Arbiter 54 Image Processing WDMAC
55 Image Processing RDMAC
56 controller image processing unit 57 image processing buffer 58 image output RDMAC
59 Image output buffer 60 Image output unit 61 Pseudo line synchronization signal generation unit 62 Register 63 Engine I / F control unit 100 Engine ASIC
101a to 101d Data transfer / monitoring unit 110 Controller ASIC
110a to 110d Data transfer / adjustment unit 120 Engine ASIC
121 Data reception timing monitoring unit 130 Controller ASIC
131 Pseudo line synchronization signal generator
FSYNC Frame sync signal
LSYNC Line synchronization signal
LSYNCa Pseudo line sync signal

JP 2011-061736 A

Claims (9)

A data providing unit that transfers and outputs data stored in the storage unit by a predetermined unit data amount, and a data output that receives the data from the data providing unit and outputs the data according to an output timing signal of a predetermined cycle A data transfer device to which the unit is connected,
The data output unit is:
Data receiving means for receiving the data transferred from the data providing unit;
Data output means for outputting the data of the unit data amount received by the data receiving means in accordance with the output timing signal;
When the data receiving means detects a timing shift amount between the data reception timing at which the unit data amount of the data is received and the output timing signal, and the timing shift amount exceeds a predetermined allowable range, along with the shift direction Timing deviation monitoring means for transmitting an error signal notifying of occurrence of timing deviation to the data providing unit;
With
The data providing unit is:
Transfer timing signal generating means for generating a transfer timing signal having a transfer cycle substantially the same as the cycle of the output timing;
Data transfer means for transferring the data of the unit data amount of the storage means to the data output unit in synchronization with the transfer timing signal;
When the error signal is transmitted from the data output unit, the transfer timing signal generated by the transfer timing signal generation means is shifted by a predetermined time in a direction to correct the timing deviation based on the error signal. Signal timing correction means to be generated,
A data transfer device comprising: The data output unit is:
An allowable range storage means in which the allowable range is set and registered;
The timing deviation monitoring means includes:
2. The data transfer apparatus according to claim 1, wherein the allowable range of the allowable range storage means is compared with the timing deviation amount. The data providing unit is:
A transfer cycle storage means for setting and registering the transfer cycle of the transfer timing signal;
The transfer timing signal generating means includes
3. The data transfer apparatus according to claim 1, wherein the transfer timing signal is generated based on the transfer cycle of the transfer cycle storage means. The timing deviation monitoring means includes:
When the error signal is transmitted, the timing shift detection operation is stopped,
The signal timing correction means includes
When the correction of the timing deviation of the transfer timing signal is completed, a correction completion signal is transmitted to the data output unit,
The timing deviation monitoring means includes:
4. The data transfer device according to claim 1, wherein when the correction completion signal is transmitted, the timing shift amount detection operation is resumed. The data output unit is:
Output unit control means for controlling the data output unit,
The data providing unit is:
Providing unit control means for controlling the data providing unit;
The timing deviation monitoring means includes:
Notifying the output unit control means of the error signal by interruption to the output unit control means,
The output unit control means includes
When the error signal notification is received by interruption, the error signal is transmitted to the providing unit control means,
The providing unit control means includes:
5. The data transfer apparatus according to claim 1, wherein when the error signal is received, the error signal is output to the signal timing correction unit. A data providing unit for transferring and outputting image data stored in the storage means by a predetermined unit data amount, and a data output unit for receiving the image data from the data providing unit and outputting it in response to an output timing signal of a predetermined period And an image processing apparatus that is equipped with a data transfer unit that transfers image data and performs image processing on the image data with the data output unit,
An image processing apparatus comprising the data transfer apparatus according to claim 1 as the data transfer unit. A data providing unit for transferring and outputting image data stored in the storage means by a predetermined unit data amount, and receiving the image data from the data providing unit, based on the data in accordance with an output timing signal of a predetermined period An image forming apparatus equipped with a data transfer unit connected to a data output unit for recording and outputting an image by a recording means,
An image forming apparatus comprising the data transfer device according to claim 1 as the data transfer unit. A data providing unit that transfers and outputs data stored in the storage unit by a predetermined unit data amount, and a data output that receives the data from the data providing unit and outputs the data according to an output timing signal of a predetermined cycle A data transfer method executed by a data transfer device to which a unit is connected,
The data output unit is:
A data reception processing step of receiving the data transferred from the data providing unit;
A data output processing step for outputting the data of the unit data amount received in the data reception processing step according to the output timing signal;
In the data reception processing step, the amount of timing deviation between the data reception timing when the data of the unit data amount is received and the output timing signal is detected, and when the amount of timing deviation exceeds a predetermined allowable range, the deviation is detected. A timing deviation monitoring processing step of transmitting an error signal notifying of occurrence of timing deviation together with a direction to the data providing unit;
Have
The data providing unit is:
A transfer timing signal generation processing step for generating a transfer timing signal having a transfer cycle substantially the same as the cycle of the output timing;
A data transfer processing step of transferring the data of the unit data amount of the storage means to the data output unit in synchronization with the transfer timing signal;
When the error signal is transmitted from the data output unit, the transfer timing signal generated in the next transfer timing signal generation processing step is set in a direction for correcting the timing deviation based on the error signal. A signal timing correction processing step to be generated by shifting only,
A data transfer method characterized by comprising: A data providing unit that transfers and outputs data stored in the storage unit by a predetermined unit data amount, and a data output that receives the data from the data providing unit and outputs the data according to an output timing signal of a predetermined cycle A data transfer program installed in the data transfer device to which the unit is connected,
To the control processor,
In the data output unit,
A data receiving process for receiving the data transferred from the data providing unit;
A data output process for outputting the data of the unit data amount received in the data reception process according to the output timing signal;
When the amount of timing difference between the data reception timing when the data of the unit data amount is received in the data reception process and the output timing signal is detected, and the amount of timing deviation exceeds a predetermined allowable range, the direction of deviation Together with a timing deviation monitoring process for transmitting an error signal to notify the occurrence of timing deviation to the data providing unit;
And execute
In the data providing unit,
A transfer timing signal generation process for generating a transfer timing signal having a transfer period substantially the same as the output timing period;
A data transfer process for transferring the unit data amount of the storage means to the data output unit in synchronization with the transfer timing signal;
When the error signal is transmitted from the data output unit, the transfer timing signal generated in the transfer timing signal generation process is then set in a direction for correcting the timing shift based on the error signal for a predetermined time. A signal timing correction process generated by shifting,
A data transfer program characterized in that

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