JP2014067972A - Multilayer wiring board and process of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer wiring board of an arbitrary position interlayer connection structure whose starting material is a four-layer core substrate, whose manufacturing is easy, whose reliability is excellent, and whose price is low, and a process of manufacturing the same.SOLUTION: The multilayer wiring board includes: a four-layer core substrate on which four conductor layers b, c, d, and e are arranged in this order through an insulating layer; a conductor layer disposed on the four-layer core substrate through the insulating layer; a skip via that connects between the conductor layers b to d of the four-layer core substrate and is not connected to the other wiring patterns of the conductor layer c.

Description

  The present invention relates to a multilayer wiring board having an arbitrary position interlayer connection structure that is easy to manufacture and excellent in reliability using a four-layer core board as a starting material.

  In multilayer wiring boards such as portable parts, with higher functionality of electronic parts, higher density and lower height are progressing. However, a wiring board having an arbitrary position interlayer connection structure that can be freely provided at any position and a thin total plate thickness is required. In order to manufacture a wiring board with this structure, it is necessary to realize a full stack structure in which vias are arranged in a row at the same position in all layers, and the core layer must also use a build-up material. A dummy core material (referred to as a support substrate that is used only in the manufacturing process and does not constitute the product multilayer wiring board itself; hereinafter referred to as “dummy core”) without using the core material that constitutes the substrate itself. In addition, a coreless construction method in which layers are formed one by one and a build-up construction method has been conventionally used. In addition, such a multilayer wiring board having no core material constituting the multilayer wiring board itself to be a product is hereinafter referred to as a “coreless build-up wiring board”, and the construction method is hereinafter referred to as a “coreless build-up construction method”. There is.

  However, while electronic parts are highly functional and the number of parts is increased, the final product such as a mobile phone is required to be low in price. Therefore, as the number of parts is increased, there is a large demand for cost reduction per part, and high-density and inexpensive wiring. Since a board is required, an expensive coreless build-up wiring board is no longer meeting the cost requirements of the market.

  As a method for enabling the connection between the conductor layers without using such a coreless buildup method, an electrical process is performed across a plurality of conductor layers from the surface of the wiring board to the inner heat dissipation layer for the purpose of heat dissipation. A method of making a connection and using a skip via is disclosed. (Patent Document 1).

  Further, a method of using a skip via for losing an adhesive layer for the purpose of thinning is disclosed (Patent Document 2).

JP 2011-243767 A JP 2007-115954 A

  However, as disclosed in Patent Documents 1 and 2, a wiring board having a skip via that connects between a plurality of conductor layers has a shorter lead time and a lower manufacturing cost than a coreless build-up wiring board. Since the four-layer core substrate is used as a starting material, there is a problem that it becomes difficult to provide vias for interlayer connection at arbitrary positions.

  The present invention provides a wiring board having an arbitrary position interlayer connection structure that is easy to manufacture and excellent in reliability using a four-layer core substrate as a starting material, and a manufacturing method thereof.

The present invention relates to the following.
1. Multi-layer wiring having a four-layer core substrate in which four conductor layers b, c, d, and e are arranged in this order via an insulating layer, and a conductor layer arranged on the four-layer core substrate via an insulating layer A multilayer wiring board having a skip via which is connected to the conductor layers b-d of the four-layer core board and is not connected to other wiring patterns of the conductor layer c.
2. In item 1, the conductor layer c between the conductor layers b-d of the four-layer core substrate is provided with independent lands that are not connected to other wiring patterns of the conductor layer c, and the conductor layers b-d of the four-layer core substrate. A multilayer wiring board in which skip vias that connect each other are connected to independent lands of the conductor layer c.
3. In item 1, a region having no land is provided in the conductor layer c between the conductor layers b-d of the layer core substrate, and the skip via connecting the conductor layers b-d of the four-layer core substrate is A multilayer wiring board disposed so as to pass through a region having no land of the layer c.
4). 4. The multilayer wiring board according to any one of items 1 to 3, wherein a stack via is disposed immediately above the skip via formed between the conductor layers b-d of the four-layer core board.
5. Item 4. The multilayer wiring having a full stack structure in which vias are arranged immediately above all the conductor layers with a skip via formed between the conductor layers b-d of the four-layer core substrate in between substrate.
6). Item 6. The method for producing a multilayer wiring board according to any one of Items 1 to 5, wherein a four-layer core substrate is formed by arranging four conductor layers b, c, d, e in this order via an insulating layer ( A), a step (B) of forming a skip via that connects the conductor layers b-d of the four-layer core substrate and does not connect to other wiring patterns of the conductor layer c, and on the four-layer core substrate A step (C) of forming a conductor layer disposed via an insulating layer.
7). In the item (6), in the step (C) of forming the conductor layer disposed on the four-layer core substrate via the insulating layer, immediately above the skip via formed between the conductor layers b-d of the four-layer core substrate. A method of manufacturing a multilayer wiring board for forming a stack via.

  According to the present invention, it is possible to provide an inexpensive wiring board having an arbitrary position interlayer connection structure which is easy to manufacture using a four-layer core substrate as a starting material and is excellent in reliability, and a manufacturing method thereof.

It is sectional drawing of the multilayer wiring board which concerns on Embodiment 1 and 2 of this invention. It is sectional drawing for every manufacturing process of the multilayer wiring board which concerns on Embodiment 1 of this invention. It is sectional drawing for every manufacturing process of the multilayer wiring board which concerns on Embodiment 1 of this invention. It is sectional drawing of the conventional coreless buildup wiring board (comparative example).

  A multilayer wiring board and a method for manufacturing the same according to the first and second embodiments of the present invention will be described below with reference to FIGS.

  As shown in FIGS. 1 (1) and (2), the multilayer wiring board according to the first embodiment of the present invention has four conductor layers 6b, c, d, and e arranged in this order via an insulating layer 5. A multilayer wiring board having a four-layer core substrate 4 and a conductor layer 6 disposed on the four-layer core substrate 4 with an insulating layer 5 interposed between the conductor layers 6b-d of the four-layer core substrate 4. And a skip via 3 that is not connected to another wiring pattern (not shown) of the conductor layer 6c. 1 are used to distinguish the conductor layer 6 (the same applies to the following drawings).

  A four-layer core substrate is a copper clad laminate having a four-layer structure and a conductor layer as an inner layer, and any conductor layer does not have an interlayer connection via (hereinafter simply referred to as “via”). Say. The surface copper foil is not desirably a thick copper foil and desirably has a thickness of about 3 μm to 12 μm in order to suppress variations in the conformal mask diameter due to etching for forming an interlayer connection via in a later step. Moreover, when a hole is made from the copper foil surface by the copper direct laser method, the copper foil thickness is preferably about 3 μm to 7 μm. Also, a copper foil with a carrier is desirable in consideration of preventing the surface from being scratched directly. The thickness of one insulating layer of the four-layer core substrate is preferably 60 μm or less in consideration of the aspect ratio of the interlayer connection via, but is preferably as thin as possible in consideration of the aspect ratio with the interlayer connection via. Considering the circuit embedding property of the insulating material, about 35 μm is the best.

A skip via refers to an electrically connected via formed across three or more conductor layers. The drilling method is mainly performed using a CO ₂ laser or a YAG (Yttrium Aluminum Garnet) laser drilling machine, and there is a conformal mask method and copper direct laser processing, but it is not limited to this. . The via diameter is advantageous when the via diameter is large in consideration of plating property and connection reliability. However, when the positional deviation between the via and the land is also taken into consideration, a diameter of about 60 μm to 150 μm is desirable.

  Further, in order to provide a via as a stack structure on the skip via, it is necessary to fill the via in the skip via with a conductive material and make the via surface flat. The conductive material may be plated with copper plating such as filled via plating, filled with conductive paste, or filled with non-conductive ink by hole filling printing after electrolytic copper plating. good. However, in consideration of connection reliability and higher wiring density, it is best to fill the vias with copper as it is.

  Further, the manufacturing cost can be reduced as the number of conductor layers connected by skip vias is three or more. However, when the via depth is increased, plating and connection reliability are deteriorated. The layer to be provided may be the 1-layer surface (a) to the 3-layer surface (c) of the surface of the 6-layer plate, or the 2-layer surface (b) to the 4-layer surface (d) of the inner layer, or the 3-layer surface (c) to the 5-layer surface (e). ) Etc., you can design freely. Also, for example, when connecting a skip via from the second layer surface (b) to the fourth layer surface (d), if the land is provided on the third layer surface (c), the second layer surface (b), the third layer surface (c) and 4 The layer surface (d) and all three layers can be electrically connected. In that case, it is necessary to provide an opening at the drilling position in advance before drilling the skip via on the three-layer surface (c) corresponding to the intermediate layer.

  Moreover, as shown in FIG. 1 (1), the independent land 10 which is not connected with the other wiring pattern of the conductor layer 6c is provided in the conductor layer 6c between the conductor layers 6b-d of the four-layer core substrate 4. The skip via 3 that connects between the conductor layers 6b-d of the four-layer core substrate 4 may be connected to the independent land 10 of the conductor layer 6c. In other words, if it is not desired to connect to the conductor layer 6c, which is an intermediate layer, it is only necessary to provide a land and not connect the wiring. In the case where the land is provided in the conductor layer 6c as the intermediate layer, the opening diameter of the etching is preferably the same as or smaller than the diameter of the skip via 3 in consideration of the positional deviation between the conductor layer 6b and the conductor layer 6c.

  As shown in FIG. 1 (2), the conductor layer 6c between the conductor layers 6b-d of the four-layer core substrate 4 is provided with a region having no land, and the conductor layer 6b- of the four-layer core substrate 4 is provided. The skip vias 3 that connect d may be arranged so as to pass through a region having no land of the conductor layer 6c. That is, it is not necessary to provide a land on the conductor layer 6c which is an intermediate layer.

  Further, when it is desired to connect only the conductor layer c and the conductor layer d, it is not necessary to provide a skip via, and a single layer via that connects two normal layers (via that connects adjacent conductor layers) may be used.

  A stack via may be disposed immediately above the skip via formed between the conductor layers b-d of the four-layer core substrate. The stacked via formed immediately above refers to a structure in which a via is further provided at the same coordinate position on a flat via or a via bottom copper filled with a conductive material in the via. However, even if designed at the same coordinate position, it is difficult to form a via at exactly the same coordinate due to a positional shift of a conformal mask or a laser via processing position in manufacturing, and it is usually less than the size of the via diameter. If it is not, it can be considered that it functions as a stacked via. For example, if the via diameter is 50 μm, it can be said that it is desirable that the positional deviation between the vias in the stack structure directly above is 50 μm or less (within the via diameter range). Also, the filler in the stack via is preferably copper like the skip via, and it is best to perform filled via plating, and the via recess or protrusion is preferably 10 μm or less.

  You may have a full stack structure by which the via | veer was arrange | positioned directly through all the conductor layers on both sides of the skip via formed between the conductor layers b-d of a 4-layer core board | substrate. A full stack structure through all layers is a structure in which vias are provided in the same coordinate position in all six layers of the above-described stack structure if it is a six-layer plate, and a part of them is a skip via. Say. There may be only one skip via or a plurality of skip vias in the full stack structure. In addition, it is only necessary to provide a land in the layer to be electrically connected and connect the wiring to the land, and in a layer not to be connected, it is only necessary to provide only the land and connect the wiring to the land.

  A method for manufacturing the multilayer wiring board according to the first embodiment will be described below with reference to FIGS.

  As shown in FIGS. 2 and 3, the method of manufacturing the multilayer wiring board according to the first embodiment has four layers in which four conductor layers 6 b, c, d, and e are arranged in this order via an insulating layer 5. The step (A) of forming the core substrate 4 and the step of forming the skip via 3 that connects the conductor layers 6b-d of the four-layer core substrate 4 and does not connect to other wiring patterns of the conductor layer 6c (B And a step (C) of forming a conductor layer 6 disposed on the four-layer core substrate 4 with an insulating layer 5 interposed therebetween.

  As shown in FIG. 3, in the step (C) of forming the conductor layer 6 disposed on the four-layer core substrate 4 via the insulating layer 5, it is formed between the conductor layers 6 b-d of the four-layer core substrate 4. A stacked via 2 is formed immediately above the skipped via 3.

  A wiring board having a skip via using a four-layer core board as a starting material and a manufacturing method thereof, such as the present invention, can be manufactured by omitting one interlayer connection via formation and plating process compared to a full-layer build-up board. The lead time can be shortened and the manufacturing cost can be reduced. Also, what is required to reduce the height of the wiring board is a build-up that uses a two-layer core board with a thickness of 30 μm or less as a starting material due to difficulties in handling thin plates in the via formation and plating processes and the occurrence of board clogging. It is difficult to manufacture a substrate, and a coreless construction method of an all-layer buildup substrate in which buildup is performed on one side, which increases manufacturing lead time and cost, is often used. However, according to the wiring substrate and the manufacturing method thereof of the present invention, since the four-layer core substrate is a starting material, there is no need to perform via formation and plating work in a two-layer plate state, and two layers having a thickness of 30 μm or less. A four-layer core substrate can be easily manufactured by only forming a circuit on a plate (copper-clad laminate).

  As mentioned above, the wiring board with a stacked structure with skip vias starting from a 4-layer core board and filled vias is a 6-layer board with a total board thickness of 0.3 mm or less, and design flexibility is low. A high-priced wiring board and a manufacturing method thereof can be provided.

  EXAMPLES Hereinafter, although the suitable Example of this invention is described, this invention is not limited to a following example.

  As shown in FIG. 2 <A-1>, a copper-clad laminate 13 having a plate thickness of 0.03 mm, a workpiece size of 510 mm × 410 mm, and a copper foil thickness of 12 μm (MCL-E-679FG manufactured by Hitachi Chemical Co., Ltd., “MCL”) Is registered trademark), and a dry film SL-1329 (Hitachi Chemical Industry Co., Ltd., trade name) is used to laminate the entire surface of the substrate to form a resist for forming a wiring pattern. A circuit pattern is formed on the resist by a photo method in which the circuit is baked with a direct drawing machine (Paragon 8800 manufactured by Orbotech), and each process of development, etching with iron chloride, and stripping of the resist using an alkaline stripper is performed. An inner layer material was formed. A window hole 7 having an opening diameter of 60 μm was formed at the same time as the patterning in a portion serving as an intermediate layer of the skip via.

  Next, in order to make unevenness on the copper surface of the inner layer material, CZ treatment (MEC etch bond CZ-8100, trade name of “MEC etch bond”, “MEC etch bond” is a registered trademark) is performed, and the surface roughness is 3 to 3. Unevenness of 5 μm was provided. A prepreg with a thickness of 25 μm (GEA-679FG manufactured by Hitachi Chemical Co., Ltd.) and a copper foil with a thickness of 5 μm for wiring (MT18S5DH manufactured by Mitsui Mining & Mining Co., Ltd.) are laminated and integrated on the inner layer material after the treatment. A four-layer core substrate 4 as shown in FIG. 2 <A-2> was produced.

The surface copper foil was opened by removing the surface copper foil by etching at the location where the skip vias or normal vias on the front and back surfaces of the produced 4-layer core substrate were provided, and a conformal mask for laser drilling was formed. The opening diameter was 90 μm for skip vias and 50 μm for normal vias. The copper foil is removed, and the portion of the conformal mask where the resin is exposed is irradiated with a carbon dioxide gas laser (Hitachi Via Mechanics Co., Ltd., laser processing conditions 1000 Hz, pulse width 15 μm, number of cycles 7 or 3). By removing the resin by thermal decomposition, a skip via having a diameter of 90 μm and a normal via having a diameter of 50 μm were simultaneously processed. In the desmear treatment, the swelling part has a swelling dip securigant P (trade name manufactured by Adtech Japan Co., Ltd., “Securigant” is a registered trademark) of about 500 ml / l and caustic soda (manufactured by Shin-Etsu Chemical Co., Ltd.) pH 9.5 to 11 .8, NaMnO ₄ about 60 g / l is used for the etching part, Reduction securigant P (trade name, manufactured by Adtech Japan Co., Ltd.) about 70 ml / l and 98% H ₂ SO ₄ (Furukawa Machine Metal Co., Ltd.) for the reducing part Manufactured by Atotech Co., Ltd. using about 50 ml / l of line speed 1.0 m / min. Then, 2pass processing (processing of passing the processing line twice) was performed.

  Next, a catalyst core is provided on the copper foil and inside the hole for the blind via using HS201B (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a palladium colloid catalyst, and then CUST2000 (manufactured by Hitachi Chemical Co., Ltd.). (Trade name) was used to form a base electroless plating layer having a thickness of 0.5 μm in the hole and on the surface copper foil.

  Next, plating with a thickness of about 30 μm was performed on the base electroless plating layer by electrolytic field plating (Meltex Co., Ltd.). Then, a chemical etching solution (HE-7000Y manufactured by MEC Co., Ltd.) is used to perform half etching with a copper portion thickness of 20 μm, to reduce the copper thickness, and to form a skip via as shown in FIG. 2 <B-1>. A four-layer core substrate was prepared.

  Next, dry film SL-1329 (Hitachi Kasei Kogyo Co., Ltd., trade name) is used for a four-layer core substrate with a flat filled via plating surface, and the entire surface of the substrate is laminated to form a resist for forming a wiring pattern. . A circuit pattern is formed on the resist by a photo method in which the circuit is baked with a direct drawing machine (Paragon 8800 manufactured by Orbotech), and each process of development, etching with iron chloride, and stripping of the resist using an alkaline stripper is performed. A four-layer core substrate 4 as shown in FIG. 2 <B-2> was formed. A window hole 7 having an opening diameter of 60 μm was formed at the same time as the patterning in a portion to be an intermediate layer of the skip via like the two-layer inner layer material.

  As with the two-layer inner layer material, the four-layer inner layer material also has an uneven surface with a surface roughness of 3 to 5 μm by performing CZ treatment (MEC etch bond CZ-8100, trade name, manufactured by MEC Co., Ltd.) to make the copper surface uneven. Was provided. A prepreg with a thickness of 25 μm (GEA-679FG manufactured by Hitachi Chemical Co., Ltd.) and a copper foil with a thickness of 5 μm for wiring (MT18S5DH manufactured by Mitsui Mining & Mining Co., Ltd.) are laminated and integrated on the inner layer material after the treatment. A six-layer substrate as shown in FIG. 3 <C-1> was produced.

The surface copper foil was opened by removing the surface copper foil by etching at the location where the skip vias or normal vias on the front and back surfaces of the produced 6-layer substrate were provided, and a conformal mask for laser drilling was formed. The opening diameter was 90 μm for skip vias and 50 μm for normal vias. The copper foil is removed, and the portion of the conformal mask where the resin is exposed is irradiated with a carbon dioxide gas laser (Hitachi Via Mechanics Co., Ltd., laser processing conditions 1000 Hz, pulse width 15 μm, number of cycles 7 or 3). By removing the resin by thermal decomposition, a skip via having a diameter of 90 μm and a normal via having a diameter of 50 μm were simultaneously processed. The desmear treatment uses about 500 ml / l of swelling dip securigant P (manufactured by Adtech Japan Co., Ltd.) and caustic soda (manufactured by Shin-Etsu Chemical Co., Ltd.) pH 9.5 to 11.8 in the swollen part, and NaMnO _{4 in} the etched part. using 60 g / l, (manufactured by ADTEC Japan) reduction security Gantt P to the reducing unit about 70 ml / l and _98% H 2 SO ₄ (Furukawa Co., Ltd.) by Atotech Co. using about 50 ml / l desmear horizontal line Line speed of 1.0 m / min. Then, 2pass treatment was performed.

  Next, a catalyst core is provided on the copper foil and inside the hole for the blind via using HS201B (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a palladium colloid catalyst, and then CUST2000 (manufactured by Hitachi Chemical Co., Ltd.). , A trade name, “CUST” is a registered trademark), and a base electroless plating layer having a thickness of 0.5 μm was formed in the hole and on the surface copper foil.

  Next, plating with a thickness of about 30 μm was performed on the base electroless plating layer by electrolytic field plating (Meltex Co., Ltd.). Thereafter, a chemical etching solution (HE-7000Y manufactured by MEC Co., Ltd.) is used to perform half etching with a copper portion thickness of 20 μm to reduce the copper thickness, and skip via 3 as shown in FIG. 3 <C-2>. A six-layer substrate having

  Next, using a dry film SL-1329 (Hitachi Chemical Industry Co., Ltd., trade name) on a 6-layer substrate having a flat filled via plating surface, the entire surface of the substrate is laminated to form a resist for forming a wiring pattern. . A circuit pattern is formed on the resist by a photo method in which the circuit is baked with a direct drawing machine (Paragon 8800 manufactured by Orbotech), and each process of development, etching with iron chloride, and stripping of the resist using an alkaline stripper is performed. A 6-layer full stack structure substrate having skip vias 3 as shown in FIG. 3 <C-3> was produced.

The produced 6-layer stack substrate was provided with irregularities having a surface roughness of 1 μm to 2 μm by CZ treatment (MEC etch bond CZ-8100, trade name, manufactured by MEC Co., Ltd.). After applying a solder resist (trade name: PSR3000-AUS308RC manufactured by Taiyo Ink Manufacturing Co., Ltd.) with a roll coater and performing temporary drying at 80 ° C. for 30 minutes, baking is performed at an exposure amount of 550 mJ / cm ² using an automatic exposure machine. Then, a solder resist having a thickness of about 50 μm was formed by a developing machine. Next, the exposed land surface was subjected to nickel plating of about 5 μm, followed by gold plating of about 0.1 μm, and cut into each product substrate by outline processing.

  Table 1 below shows a comparison of each item between the example of the present invention and the conventional coreless buildup method. According to the present invention, it was possible to provide an inexpensive wiring board having an arbitrary position interlayer connection structure that can be applied to a thin plate.

（符号の説明）

(Explanation of symbols)

DESCRIPTION OF SYMBOLS 1 ... Build-up layer 2 ... Stack via 3 ... Skip via 4 ... 4 layer core or 4 layer core board | substrate 5 ... Insulating layer 6 ... Conductive layer 7 ... Etching opening or window hole 8 ... Copper foil 9 ... Normal via or via 10 ... Independent land 11 ... Area 12 having no land ... Multi-layer wiring board 13 ... Copper-clad laminate 15 ... Core material

Claims (7)

Multi-layer wiring having a four-layer core substrate in which four conductor layers b, c, d, and e are arranged in this order via an insulating layer, and a conductor layer arranged on the four-layer core substrate via an insulating layer A substrate,
A multilayer wiring board having skip vias connecting the conductor layers b-d of the four-layer core board and not connected to other wiring patterns of the conductor layer c. In claim 1,
An independent land that is not connected to other wiring patterns of the conductor layer c is provided in the conductor layer c between the conductor layers b-d of the four-layer core substrate,
A multilayer wiring board in which skip vias connecting conductor layers b-d of a four-layer core board are connected to independent lands of the conductor layer c. In claim 1,
A region having no land is provided in the conductor layer c between the conductor layers b-d of the layer core substrate,
A multilayer wiring board in which skip vias connecting conductor layers b-d of a four-layer core board are arranged so as to pass through a region having no land of the conductor layer c.   4. The multilayer wiring board according to claim 1, wherein a stack via is disposed immediately above the skip via formed between the conductor layers b-d of the four-layer core board.   5. The multi-layer structure according to claim 1, wherein the vias are disposed directly above all the conductor layers with the skip via formed between the conductor layers b-d of the four-layer core substrate interposed therebetween. Wiring board. A method for producing a multilayer wiring board according to any one of claims 1 to 5,
A step (A) of forming a four-layer core substrate in which four conductor layers b, c, d, and e are arranged in this order via an insulating layer;
A step (B) of forming a skip via that connects between the conductor layers b-d of the four-layer core substrate and is not connected to other wiring patterns of the conductor layer c;
Forming a conductor layer disposed on the four-layer core substrate via an insulating layer (C);
The manufacturing method of the multilayer wiring board which has this. In claim 6,
In the step (C) of forming a conductor layer disposed on the four-layer core substrate via an insulating layer, a stack via is formed immediately above the skip via formed between the conductor layers b-d of the four-layer core substrate. A method of manufacturing a multilayer wiring board to be formed.

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