JP2014067946A - Manufacturing method of printed wiring board and printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board which includes a plating filled via conductor achieving high connection reliability and can form a fine conductor pattern.SOLUTION: In a manufacturing method of a printed wiring board, a metal layer 53, an electroless plating layer 52, and an electrolytic plating layer 56 are formed on a metal foil 48. Subsequently, the electroless plating layer 52, the electrolytic plating layer 56, and the metal layer 53 are removed to expose the thin metal foil 48 having a uniform thickness and then form conductor patterns 48, 58 by etching. Thus, the manufacturing method of the printed wiring board enables a plating filled via conductor 60 and the thin conductor patterns 48, 58 to be concurrently formed and enables a fine pitch of the printed wiring board.

Description

The present invention relates to a printed wiring board including a filled via formed by plating and filling a via opening of an interlayer resin insulating layer, and a method for manufacturing the printed wiring board.

Currently, printed wiring boards used in portable devices are required to be highly integrated and thin. Here, in order to reduce the thickness of the printed wiring board, it is necessary to reduce the thickness of the conductor pattern.

When a conductor pattern with a layer thickness of 10 μm or less and a plated filling via (filled via) are formed simultaneously by electrolytic plating, the plating of the via conductor cannot be completely completed, and a recess is formed in the center of the outermost surface of the via conductor, and the interlayer resin insulation When the layers are stacked, voids and the like are generated, which causes a decrease in reliability.

In U.S. Pat. No. 2,881,479, a copper foil and a Ni layer are pasted on a core substrate, a via opening is provided with a laser, the inside of the via opening is filled with a plating layer, and then the copper foil is exposed by etching to form a conductor pattern. It is disclosed.

US-B2-8187479

In Patent Document 1, since a via opening is formed by penetrating a copper foil and a Ni layer with a laser, the output of the laser needs to be increased. At this time, it is considered that the dimensional accuracy decreases, such as variations in the size and shape of the via opening, and the copper foil peeling from the insulating layer.

The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a printed wiring board having a filled via with high connection reliability and capable of forming a fine conductor pattern, and the printed wiring board. It is to provide a manufacturing method.

The method for producing the printed wiring board of the present invention is as follows:
Laminating a metal foil on the interlayer resin insulation layer;
Forming a metal layer on the metal foil;
Providing an opening for exposing the metal foil in the metal layer;
Providing a through-hole penetrating the metal foil and the interlayer resin insulating layer by irradiating a laser inside the opening;
Forming an electroless plating layer on the metal layer and on the sidewall of the through hole;
Forming an electrolytic plating layer on the electroless plating layer;
Removing the electroless plating layer and the electrolytic plating layer formed on the metal layer to expose the metal layer;
Removing the metal layer;
Forming a resist having an opening on the metal foil;
Removing the metal foil exposed from the opening to form a conductor pattern;
Stripping the resist;
It has a technical feature.

The printed wiring board of the present invention is
An interlayer resin insulation layer on the core substrate;
A via conductor composed of an electroless plating layer and an electrolytic plating layer penetrating the interlayer resin insulation layer;
And a conductive pattern connected to the via conductor and made of a metal foil formed on the interlayer resin insulation layer.

In the method for producing a printed wiring board of the present invention, after forming a metal layer, an electroless plating layer, and an electrolytic plating layer on a metal foil, the electroless plating layer, the electrolytic plating layer, and the metal layer are removed, and the thickness is uniform. Since the thin metal foil is exposed and then the pattern is formed by etching, a thin conductor pattern having a constant thickness and a plating-filled via conductor can be formed simultaneously, and a fine pitch of the printed wiring board can be achieved. Since an opening is provided in the metal layer using an etching resist formed by exposure and development and the via opening is formed through the opening (metal mask), the positional accuracy of the via opening is high. Compared with the case where metal foil and metal layer are penetrated by laser, only metal foil is penetrated by laser, so that laser can be irradiated with low power, dimensional accuracy of via opening is increased, and connection reliability of via conductor is improved. Rise.

Process drawing which shows the manufacturing method of the printed wiring board based on the Example of this invention. Process drawing which shows the manufacturing method of the printed wiring board of an Example. Process drawing which shows the manufacturing method of the printed wiring board of an Example. Process drawing which shows the manufacturing method of the printed wiring board of an Example. Process drawing which shows the manufacturing method of the printed wiring board of an Example. Process drawing which shows the manufacturing method of the printed wiring board of embodiment. Process drawing which shows the manufacturing method of the printed wiring board of embodiment. The model which shows the stress which arises in the printed wiring board of embodiment. Process drawing which shows the manufacturing method of the printed wiring board of an Example. Process drawing which shows the manufacturing method of the printed wiring board of an Example.

[First embodiment]
The printed wiring board according to the first embodiment of the present invention is shown in FIG.
The printed wiring board 10 of the first embodiment has a core substrate 30. The core substrate includes an insulating substrate 20z having a first surface F and a second surface S opposite to the first surface, a first conductor layer 34F formed on the first surface F of the insulating substrate, and the insulating substrate. It has the 2nd conductor layer 34S formed on the 2nd surface. The core substrate further includes a through-hole conductor 36 that connects the first conductor layer 34F and the second conductor layer 34S. The through hole conductor 36 is formed in the through hole 28 penetrating the insulating substrate 20Z. The shape of the through hole 28 and the shape of the through hole conductor 36 are such that each opening having an opening on each surface of the first surface F and the second surface S of the core substrate 30 is tapered toward the center. Connected hourglass shape. The conductor layer of the core substrate 30 includes a plurality of conductor circuits and through-hole lands formed around the through-hole conductors. The first surface of the core substrate 30 and the first surface of the insulating substrate 20Z are the same surface, and the second surface of the core substrate 30 and the second surface of the insulating substrate 20Z are the same surface.

An interlayer resin insulation layer 50F is formed on the first surface F of the core substrate 30 and the first conductor layer 34F. A conductor layer (uppermost conductor layer) 58F is formed on this interlayer resin insulation layer 50F. The conductor layer 58F is connected to the first conductor layer 34F and the through-hole conductor 36 by a via conductor 60F that penetrates the interlayer resin insulation layer 50F. A buildup layer 55F on the first surface side is formed by the interlayer resin insulation layer 50F, the conductor layer 58F, and the via conductor 60F. In the first embodiment, the build-up layer on the first surface side is a single layer. Note that a plurality of build-up layers on the first surface side can be laminated.

An interlayer resin insulation layer 50S is formed on the second surface S of the core substrate 30 and the second conductor layer 34S. Conductive layer (58S) is formed on interlayer resin insulating layer (50S). The conductor layer 58S and the second conductor layer 34S and the through-hole conductor 36 are connected by a via conductor 60S that penetrates the interlayer resin insulating layer 50S. The interlayer resin insulation layer 50S, the conductor layer 58S, and the via conductor 60S form a buildup layer 55S on the second surface side. In the first embodiment, the build-up layer on the second surface side is one layer. Note that a plurality of build-up layers on the second surface side can be laminated.

A solder resist layer 70F on the first surface side is formed on the buildup layer on the first surface side, and a solder resist layer 70S on the second surface side is formed on the buildup layer on the second surface side. The solder resist layer 70F has an opening 71F that exposes the upper surface of the conductor layer or the via conductor. The solder resist layer 70S has an opening 71S that exposes the upper surface of the conductor layer or the via conductor. A solder bump 76F for mounting an IC chip is formed in the opening 71F of the solder resist layer 70F on the first surface side. BGA solder bumps 76S for mounting on the mother board are formed in the openings 71S of the solder resist layer 70S on the second surface side.

[Description of Embodiment]
With reference to FIG.6 and FIG.7, the manufacturing method of the printed wiring board which concerns on embodiment of this invention is demonstrated.
A metal foil 48 is laminated on an interlayer resin insulation layer 50 having a conductor pattern 34 on the lower surface side. The thickness of the metal foil 48 is preferably in the range of 3 μm to 10 μm. If the thickness of the metal foil 48 is less than 3 μm, the thickness of the conductor pattern formed from this metal foil is less than 3 μm, so that it is not suitable because it is easily affected by impedance. If the thickness of the metal foil 48 exceeds 10 μm, the thickness of the conductor pattern formed from this metal foil exceeds 10 μm, so that the ratio of the metal constituting the substrate is high and the warpage of the entire substrate cannot be suppressed. It seems not. The metal foil 48 is preferably a copper foil or a Cu—W alloy foil. The reason is low electrical resistance and low thermal expansion coefficient.

A metal layer 53 is formed on the metal foil 48 by sputtering. The metal layer 53 is preferably formed by any one of plating, sputtering, and vapor deposition. The thickness of the metal layer is preferably in the range of 0.1 μm to 5 μm. If the thickness of the metal layer is less than 0.1 μm, the laser penetrates easily and cannot be used as a metal mask. If the thickness of the metal layer exceeds 5 μm, it is not suitable because it takes too much etching time for the metal mask opening 53a for via opening and etching removal time for pattern formation. In the present invention, the metal layer 53 is preferably made of a metal material different from the metal foil 48 formed in the conductor pattern. This is because the metal layer 53 is removed by selective etching with a selective etching solution at the time of pattern formation after being used as a metal mask for via opening by laser. The metal layer 53 is preferably made of at least one selected from the group consisting of nickel, chromium and titanium.

An etching resist film is formed on the metal layer 53, exposed through a mask (not shown), developed, and an etching resist 47 having an opening 47a at a via opening forming position is formed (FIG. 6C). An opening 53a is formed in the metal layer 53 by selective etching through the opening 47a of the etching resist 47 (FIG. 6D). The etching resist 47 is peeled off (FIG. 6E). Laser is irradiated through the opening 53a of the metal layer 53, the metal foil 48 and the interlayer resin insulation layer 50 are penetrated, and the via opening 51 is formed in the metal foil 48 and the interlayer resin insulation layer 50 (FIG. 6F). ).

By electroless plating, an electroless plating layer 52 is formed as a seed layer on the inner wall of the via opening 51 and the metal layer 53. Further, by electroplating, the electroless plating layer 52 on the inner wall of the via opening 51 and the metal layer 53 are formed. An electrolytic plating layer 56 is formed on the upper electroless plating layer 52, and the via opening 51 is filled with the electrolytic plating layer 56. At the same time, an electrolytic plating layer 56 is also formed on the metal layer 53 (FIG. 7A). It is desirable to form the metal layer 53 from a material different from the electroless plating layer and the electrolytic plating layer. In the present invention, after filling the via opening with the electroless plating layer and the electroplating layer, the electroless plating layer and the electroplating layer are removed by selective etching with a selective etching solution, thereby providing a via conductor. This is because it is formed. For the electroless plating film, the same metal material as the metal foil is suitable. When the same material is used, the adhesiveness is high and the resistance value can be lowered. Similarly, the same metal material as the electroless plating layer is suitable for the electrolytic plating film. When the same material is used, the adhesiveness is high and the resistance value can be lowered. When the metal foil is a copper foil, an electroless copper plating layer and an electrolytic copper plating layer are suitable.

The electroless plating layer 52 and the electrolytic plating layer 56 on the metal layer 53 are removed by the selective etching solution (FIG. 7B). At the same time, the position of the outermost surface of the via conductor 60 is substantially flush with the surface of the metal layer 53 (FIG. 7B), or from the surface of the metal layer 53 toward the conductor 34. The electroless plating layer and the electrolytic plating layer 56 on the outermost layer of the via conductor are removed so as to be recessed (FIGS. 9A and 10A). The metal layer 53 is removed by selective etching, and the metal foil 48 is exposed (FIG. 7C). An etching resist 54 having a predetermined pattern is formed (FIG. 7D). The metal foil 48 where the etching resist 54 is not formed is removed (FIG. 7E). The etching resist 54 is removed, and a via conductor 60 composed of the electroless plating layer 52 and the electrolytic plating layer 56 and conductor patterns 48 and 58 composed of metal foil are completed (FIG. 7F). By connecting the electroless plating layer 52 constituting the via conductor 60 to the metal foil 48, the via conductor 60 and the conductor pattern 48 are connected.

When the electroless plating layer 52 and the electrolytic plating layer 56 are removed until the position of the outermost surface of the via conductor 60 is substantially flush with the surface of the metal layer 53 (FIG. 7B), the outermost surface of the via conductor 60 is removed. The surface position protrudes from the conductor 34 in the direction of the metal foil 48 by the thickness t1 of the peeled metal layer from the position of the outermost surface of the conductor patterns 48 and 58, and the surface of the metal foil 48 and the via conductor 60 are the outermost positions. A step is provided on the surface (FIG. 7F). Since the via conductor 60 is tapered toward the conductor 34 and has a diameter that is closer to the outermost surface, the interlayer resin insulation layer 150 is laminated on the via conductor 60 and the conductor patterns 48 and 58 (FIG. 8). Adhesion is improved by the anchor effect. Further, when stress is generated, cracks (cracks) C are likely to start from the ridge 60P at the outermost edge of the via conductor 60 as shown in FIG. It seems that the occurrence of disconnection at the connecting portion F between the electrolytic plating layer 52 and the metal foil 48 can be suppressed.

9A and 9B, the electrolytic plating layer 56 and the electroless plating layer 52 are removed, so that the position of the outermost surface of the via conductor 60 is recessed from the surface of the metal layer 53 toward the conductor 34. It corresponds to the position of the outermost surface of the metal foil. After the metal layer 53 is removed with the selective etching solution, the position of the outermost surface of the via conductor 60 becomes substantially the same position as the positions of the outermost surfaces of the conductor patterns 48 and 58. When the interlayer resin insulation layer 150 is laminated on the via conductor 60 and the conductor patterns 48 and 58, it seems that flat lamination is possible.

10A and 10B, the position of the outermost surface of the via conductor 60 is recessed in the direction of the conductor 34 from the surface of the metal layer 53, and from the conductor 34 to the metal foil 48 from the surfaces of the metal foils 48 and 58. It is in a position protruding in the direction of. After removing the metal layer 53 with a selective etching solution, the outermost surface of the via conductor 60 protrudes from the conductor 34 toward the metal foil 48 rather than the outermost surfaces of the conductor patterns 48 and 58. The thickness of the protrusion is not more than the thickness of the peeled metal layer.
Since the via conductor 60 is tapered toward the conductor 34 and becomes closer to the outermost surface, the diameter becomes larger. Therefore, when the interlayer resin insulating layer 150 is laminated on the via conductor 60 and the conductor patterns 48 and 58, the anchor effect is obtained. Improves adhesion. Further, when stress is generated, cracks are likely to occur starting from the ridge 60P at the outermost edge of the via conductor 60, so that the electroless plating layer 52 constituting the via conductor 60 and the metal foil 58 are connected. It seems that the occurrence of disconnection at the part F can be suppressed (see FIG. 8).

In the printed wiring board manufacturing method of the embodiment, after forming the metal layer 53, the electroless plating layer 52, and the electrolytic plating layer 56 on the metal foil 48, the electroless plating layer 52, the electrolytic plating layer 56, and the metal layer 53 are formed. Since the conductive patterns 48 and 58 are formed by etching after removing the metal foil 48 having a uniform thickness and a thin thickness, the thin conductive patterns 48 and 58 having a constant thickness and the plating filled via conductor 60 can be formed at the same time. It seems that the fine pitch of the printed wiring board can be achieved. The via conductor 60 is formed of the electrolytic plating layer 56 so as to be thicker than the designed thickness and so that the outermost surface of the via conductor 60 is higher than the surface of the metal layer 53. Thereafter, the electroless plating layer 52 and the electrolytic plating layer 56 on the metal layer 53 and the electroless copper plating layer and the electrolytic copper plating layer on the outermost surface of the via conductor 60 are removed by selective etching with a selective etching solution. A via conductor 60 is formed in which no recess is formed on the outermost surface portion. When a via conductor is formed immediately above the via conductor 60, the outermost surface of the via conductor 60 is flat, so that it is considered that a via opening is formed with high accuracy and via connection with high connection reliability is possible.

Since the opening 53a is provided in the metal layer 53 using the etching resist 47 formed by exposure / development, and the via opening 51 is formed by the laser through the opening 53a, it is considered that the positional accuracy of the via opening 51 is high. Further, as compared with the case where the metal foil 48 and the metal layer 53 are simultaneously penetrated by the laser, only the metal foil 48 is penetrated by the laser, so that the laser can be irradiated at a low output, and the dimensional accuracy of the via opening 51 is increased. 60 reliability is expected to increase. When the laser output is large, the metal foil 48 is peeled off from the interlayer resin insulation layer 50, and the space between the peeled metal foil 48 and the interlayer resin insulation layer 50 is plated and filled. It is thought that there will be a failure to connect.

[Method for Manufacturing Printed Wiring Board of First Embodiment]
A method of manufacturing the printed wiring board 10 of the first embodiment is shown in FIGS. 1 to 4. (1) An insulating substrate 20 z having a first surface F and a second surface S opposite to the first surface, and both surfaces thereof A double-sided copper clad laminate 20 composed of laminated copper foils 22 and 22 is prepared (FIG. 1A). ELC4785TH-G manufactured by Sumitomo Bakelite Co., Ltd. can be used as the double-sided copper-clad laminate. Copper foils 22 and 22 are laminated on the first surface F and the second surface S of the insulating substrate, respectively.

(2) The double-sided copper-clad laminate is processed to complete the core substrate 30 including the through-hole conductor 36, the first conductor layer 34F, and the second conductor layer 34S (FIG. 1B). The first surface of the core substrate and the first surface of the insulating substrate are the same surface, and the second surface of the core substrate and the second surface of the insulating substrate are the same surface. The core substrate 30 is manufactured by the method disclosed in US77786390.

(3) On the first surface F and the second surface S of the core substrate 30, a prepreg containing inorganic fibers, inorganic particles such as silica, and a thermosetting resin such as epoxy, and a copper foil 48 having a thickness of 7 μm are sequentially laminated. The Thereafter, the interlayer resin insulation layer 50F and the interlayer resin insulation layer 50S are formed from the prepreg by heating press, and the copper foil 48 is bonded to the interlayer resin insulation layer (FIG. 1C). Here, an interlayer resin insulation layer including inorganic fibers is laminated, but an interlayer resin insulation layer not including a core material can also be used.

(4) Next, a nickel layer 53 of 2 μm is formed on the copper foil 48 by plating (FIG. 1D). An etching resist film is coated on the nickel layer 53, exposed through a mask (not shown), developed, and an etching resist 47 having an opening 47a at a via opening forming position is formed (FIG. 1E).

(5) An opening 53a is formed in the nickel layer 53 by selective etching with a selective etching solution through the opening 47a of the etching resist 47 (FIG. 2A). The etching resist 47 is peeled off (FIG. 2B). The CO2 gas laser is irradiated through the opening 53a of the nickel layer 53, the copper foil 48 and the interlayer resin insulation layer are penetrated, the via opening 51F is formed in the interlayer resin insulation layer 50F, and the via opening 51S is formed in the interlayer resin insulation layer 50S. (FIG. 2C).

(6) An electroless copper plating layer 52 is formed by electroless copper plating. Further, an electrolytic copper plating layer 56 is formed by electrolytic copper plating using the electroless copper plating layer 52 as a seed layer, and via openings 51F and 51S are formed. Filled with an electrolytic copper plating layer 56. At the same time, an electrolytic copper plating layer 56 is also formed on the electroless copper plating layer on the nickel layer 53 (FIG. 2D).

(7) The electroless copper plating layer 52 and the electrolytic copper plating layer 56 on the nickel layer 53 are removed by selective etching so that the position of the outermost surface of the via conductor 60 is substantially flush with the surface of the nickel layer 53. (FIG. 2E). The nickel layer 53 is removed by selective etching, and the copper foil 48 is exposed (FIG. 3A). At this time, the outermost surface of the via conductor 60 is at a position where a thickness of 2 μm corresponding to the thickness of the nickel layer protrudes from the conductor 34 toward the copper foil 48. An etching resist 54 having a predetermined pattern is formed (FIG. 3B). The copper foil 48 in the portion where the etching resist 54 is not formed is removed (FIG. 3C). Etching resist 54 is removed, and via conductors 60F and 60S made of electroless copper plating layer 52 and electrolytic copper plating layer 56, and conductor patterns 48, 58F and 58S made of 7 μm copper foil are completed (FIG. 3D). . Build-up layers 55F and 55S on the first surface side and the second surface side are formed.

(8) The first surface side solder resist layer 70F having the opening 71F on the first surface side buildup layer is formed, and the first surface side solder having the opening 71S on the first surface side buildup layer. A resist layer 70S is formed (FIG. 4A).

(9) The nickel plating layer 72 is formed in the openings 71F and 71S of the solder resist layers 70F and 70S, and the gold plating layer 74 is further formed on the nickel plating layer 72 (FIG. 4B). A nickel-palladium-gold layer may be formed instead of the nickel-gold layer.

(10) The solder ball 76f is mounted on the opening 71F of the solder resist layer 70F, the solder ball 76s is mounted on the opening 71S of the solder resist layer 70S (FIG. 4C), and the solder bump 76F is opened on the opening 71F by reflow. BGA bumps 76F are formed on 71S. The printed wiring board 10 is completed (FIG. 5).

In the above-described embodiment, the buildup layer composed of one layer of the interlayer resin insulation layer is formed. However, the configuration of the present invention is a buildup layer composed of two or more layers of the interlayer resin insulation layer. Applicable.

30 Core substrate 47 Etching resist 47a Opening 48 Copper foil 50 Interlayer resin insulation layer 51 Via opening 52 Electroless copper plating layer 53 Nickel layer 53a Opening 56 Electrolytic copper plating layer 58 Conductor pattern 60 Via conductor

Claims (15)

Laminating a metal foil on the interlayer resin insulation layer;
Forming a metal layer on the metal foil;
Providing an opening for exposing the metal foil in the metal layer;
Providing a through-hole penetrating the metal foil and the interlayer resin insulating layer by irradiating a laser inside the opening;
Forming an electroless plating layer on the metal layer and on the sidewall of the through hole;
Forming an electrolytic plating layer on the electroless plating layer;
Removing the electroless plating layer and the electrolytic plating layer formed on the metal layer to expose the metal layer;
Removing the metal layer;
Forming a resist having an opening on the metal foil;
Removing the metal foil exposed from the opening to form a conductor pattern;
Stripping the resist;
The manufacturing method of the printed wiring board which has this. In the manufacturing method of the printed wiring board of Claim 1,
The metal layer is formed from a material different from that of the metal foil. In the manufacturing method of the printed wiring board of Claim 1 or Claim 2:
The metal layer is formed from a material different from the electroless plating layer and the electrolytic plating layer. In the manufacturing method of the printed wiring board of any one of Claims 1-3.
When the metal layer is removed, the surface of the metal foil and the surface of the electrolytic plating layer in the through hole are positioned on substantially the same plane. In the manufacturing method of the printed wiring board of any one of Claims 1-3.
When the metal layer is removed, a step is provided between the surface of the metal foil and the surface of the electrolytic plating layer in the through hole. In the manufacturing method of the printed wiring board of Claim 5,
When the metal layer is removed, the position of the surface of the electrolytic plating layer in the through hole is protruded to the upper interlayer resin insulation layer side from the position of the surface of the metal foil. In the manufacturing method of the printed wiring board of any one of Claims 1-6:
The metal foil is selected from either a copper foil or a Cu—W alloy foil. In the manufacturing method of the printed wiring board of any one of Claims 1-7,
The metal layer is made of at least one selected from the group consisting of nickel, chromium and titanium. In the manufacturing method of the printed wiring board of any one of Claims 1-8,
The metal layer is formed by plating, sputtering, or vapor deposition. In the manufacturing method of the printed wiring board of any one of Claims 1-9,
The metal layer has a thickness in the range of 0.1 μm to 5 μm. In the manufacturing method of the printed wiring board of any one of Claims 1-10,
The thickness of the metal foil is in the range of 3 μm to 10 μm. An interlayer resin insulation layer on the core substrate;
A via conductor composed of an electroless plating layer and an electrolytic plating layer penetrating the interlayer resin insulation layer;
A conductor pattern connected to the via conductor and composed of a metal foil formed on the interlayer resin insulation layer;
A printed wiring board having: In the printed wiring board of Claim 12,
The via conductor and the conductor pattern are characterized in that the electroless plating layer constituting the via conductor and the metal foil constituting the conductor pattern are joined. In the printed wiring board of Claim 12 or Claim 13,
The surface of the metal foil and the surface of the electrolytic plating layer in the through hole are located on substantially the same plane. In the printed wiring board of Claim 12 or Claim 13,
The position of the surface of the electrolytic plating layer in the through hole protrudes toward the upper interlayer resin insulation layer from the position of the surface of the metal foil.

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