JP2014063785A - Metal contamination evaluation method for semiconductor substrate, and method of manufacturing semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide means for performing metal contamination evaluation of a semiconductor substrate by the DLTS method with a high sensitivity.SOLUTION: A metal contamination evaluation method for a semiconductor substrate includes: producing a diode by forming a semiconductor junction on one surface of an evaluation target semiconductor substrate and forming an ohmic layer on the other surface; performing DLTS measurement of the produced diode; evaluating presence or absence of metal contamination of the evaluation target semiconductor substrate, or a degree of metal contamination, or the presence or absence and the degree of the metal contamination, on the basis of measurement results. Before the production of the diode, the following processing 1 or 2 is performed. Processing 1: Heat treatment performed on such a condition that a thermal donor is formed or activated in a case where the evaluation target semiconductor substrate is an epitaxial wafer or an annealing wafer or a part of the same. Processing 2: Thinning processing for thinning a thickness of the semiconductor substrate from a surface on a side where the ohmic layer is formed.

Description

The present invention relates to a method for evaluating metal contamination of a semiconductor substrate, and more particularly to a method for evaluating metal contamination that enables evaluation of a small amount of metal contamination of a semiconductor substrate by a DLTS method (Deep-Level Transient Spectroscopy). .
Furthermore, the present invention relates to a method for manufacturing a semiconductor substrate that provides a product substrate that is quality-controlled based on the evaluation results obtained by the method.

  Metal contamination of the semiconductor substrate adversely affects the device characteristics of the product. For example, when a heavy metal such as Fe or Ni enters Si, it forms a deep level in the band gap and acts as a carrier capture center or recombination center, which causes pn junction leakage in the device and a decrease in lifetime. Therefore, in order to provide a high-quality semiconductor substrate with little metal contamination, a method for evaluating the metal contamination of the semiconductor substrate with high reliability is required.

  Various methods have been proposed and put into practical use as methods for evaluating metal contamination of semiconductor substrates. Among them, the DLTS method is highly sensitive, so it is frequently used especially in recent years with the cleaning of silicon wafers. (For example, refer to Patent Document 1).

JP 2008-258544 A

In the DLTS method, a semiconductor junction (Schottky junction or pn junction) is formed on one surface of a semiconductor substrate to be evaluated, and an ohmic layer is formed on the other surface to produce a diode. ) And measure the transient response by applying voltage periodically while sweeping the temperature. The contamination metal species can be specified by the peak position of the DLTS spectrum obtained by plotting the DLTS signal against the temperature, and the metal contamination can be quantitatively evaluated from the peak height.
This point will be further described. By taking the inverse 1 / T of the peak position (temperature) T of the DLTS spectrum on the horizontal axis and e / T ² on the vertical axis and taking a so-called Arrhenius plot, the slope of the plot (y intercept) ) To obtain a deep level energy level. Also, Arrhenius plot library based on DLTS measurement results introduced in past literatures and papers, and Arrhenius created by accumulating DLTS measurement results on semiconductor substrates intentionally introduced with defects and metal contamination By comparing with the library of plots, the identity of the deep level (contaminated metal species) detected in this measurement can be identified.

When the amount of contaminating metals contained in the semiconductor substrate is large, the DLTS signal from the deep level is sufficiently large, and the influence of baseline waviness and noise is sufficiently small and negligible, making it easy to detect peaks. . However, in recent years, with the improvement in performance of semiconductor devices, the cleaning of semiconductor substrates such as silicon wafers (reduction of metal impurity concentration) has been promoted. There is a need for higher sensitivity.
However, in a clean semiconductor substrate, the DLTS signal is extremely weak because there is a small amount of metal impurities that can cause deep levels. In such a case, the swell component of the baseline that is unrelated to the carrier emission from the deep level and the magnitude of the noise become so large that they cannot be ignored compared to the intensity of the true DLTS signal due to the deep level. This hinders accurate detection of the height.

  As described above, higher sensitivity is required for metal contamination evaluation of a semiconductor substrate by the DLTS method.

  Accordingly, an object of the present invention is to provide means for performing metal contamination evaluation of a semiconductor substrate with high sensitivity by the DLTS method.

The inventors of the present invention have made extensive studies in order to achieve the above-described object, and the fact that the semiconductor substrate to be evaluated increases the series resistance of the DLTS measurement diode causes undulation in the baseline of the DLTS spectrum, It came to be considered that it is a cause of generation of a pseudo signal (noise) not caused by the position.
In addition, as a result of further studies, the inventors of the present invention performed a process for lowering the substrate resistance of the semiconductor substrate to be evaluated before lowering the diode to lower the series resistance of the diode. It was found that (so-called medium / long period noise) can be reduced.
However, if the resistivity in the vicinity of the surface to be measured is greatly reduced by reducing the substrate resistance, the ratio (S / N ratio) between the noise (N) and the signal (S) with a very short period is reduced. As a result, the detection sensitivity decreases.
Based on the above knowledge, the present inventors increase the detection sensitivity of the metal contamination evaluation by the DLTS method by performing a process of lowering the substrate resistance of other portions without greatly reducing the resistivity in the vicinity of the surface to be measured. As a result, the present invention was completed.

That is, the above object has been achieved by the following means.
[1] A method for evaluating metal contamination of a semiconductor substrate,
Forming a semiconductor junction on one surface of a semiconductor substrate to be evaluated and forming an ohmic layer on the other surface to produce a diode;
Performing DLTS measurement of the fabricated diode,
Evaluating the presence or absence of metal contamination, the degree of metal contamination, or the presence and extent of metal contamination based on the measurement results,
Including
The evaluation method according to claim 1, wherein the following treatment 1 or 2 is performed before manufacturing the diode.
Process 1: Heat treatment performed under conditions for forming or activating a thermal donor when the semiconductor substrate to be evaluated is an epitaxial wafer, an annealed wafer, or a part thereof.
Process 2: Thinning process for reducing the thickness of the semiconductor substrate from the surface on the side where the ohmic layer is formed.
[2] The evaluation method according to [1], wherein the semiconductor substrate is a silicon epitaxial wafer or a part thereof.
[3] The evaluation method according to [2], wherein the silicon epitaxial wafer has an N-type epitaxial layer on an N-type silicon single crystal substrate obtained from a silicon single crystal ingot grown by the MCZ method or the CZ method.
[4] preparing a lot of semiconductor substrates comprising a plurality of semiconductor substrates;
Extracting at least one semiconductor substrate from the lot;
A step of evaluating metal contamination of the extracted semiconductor substrate;
As a result of the evaluation, a process of shipping another semiconductor substrate in the same lot as the semiconductor substrate in which the metal contamination is determined to be below an allowable level as a product substrate,
A method of manufacturing a semiconductor substrate comprising:
The said manufacturing method characterized by performing metal contamination evaluation of the said extracted semiconductor substrate by the method in any one of [1]-[3].

  According to the present invention, it is possible to increase the sensitivity of metal contamination evaluation by the DLTS method.

It is explanatory drawing of the outline | summary of DLTS method. It is explanatory drawing of the outline | summary of DLTS method. It is explanatory drawing of the outline | summary of DLTS method. It is explanatory drawing of the outline | summary of DLTS method. The difference of the DLTS spectrum by the presence or absence of the process 1 is shown.

The present invention relates to a method for evaluating metal contamination of a semiconductor substrate by a DLTS method (hereinafter also referred to as “the evaluation method of the present invention”).
The evaluation method of the present invention is:
Forming a semiconductor junction on one surface of a semiconductor substrate to be evaluated and forming an ohmic layer on the other surface to produce a diode;
Performing DLTS measurement of the fabricated diode,
Evaluating the presence or absence of metal contamination, the degree of metal contamination, or the presence and extent of metal contamination based on the measurement results,
The following treatment 1 or 2 is performed before manufacturing the diode.
Process 1: Heat treatment performed under conditions for forming or activating a thermal donor when the semiconductor substrate to be evaluated is an epitaxial wafer, an annealed wafer, or a part thereof.
Process 2: Thinning process for reducing the thickness of the semiconductor substrate from the surface on the side where the ohmic layer is formed.
Hereinafter, the evaluation method of the present invention will be described in more detail.

Both of the above processes 1 and 2 are processes for lowering the substrate resistance of other portions without greatly reducing the resistivity in the vicinity of the surface to be measured (surface on which the semiconductor junction is formed) with respect to the semiconductor substrate to be evaluated. It is. The reason why the target semiconductor substrate is specified as the epitaxial wafer, the annealed wafer, or a part thereof in the process 1 is as follows.
An epitaxial wafer is obtained by vapor-phase growth (epitaxial growth) of an epitaxial layer on a polished wafer (hereinafter also referred to as “substrate”), and oxygen diffuses from the polished wafer to the epitaxial growth layer during epitaxial growth. However, since this diffusion is limited to a region close to the interface between the epitaxial layer and the polished wafer, that is, a deep region of the epitaxial layer, the region evaluated by the DLTS method (the depth at which the depletion layer of the diode spreads) has a low oxygen concentration. . An annealed wafer is a wafer in which a polished wafer is subjected to high-temperature heat treatment (annealing) in an atmosphere of hydrogen, argon, etc. to improve crystal integrity on the wafer surface, and the oxygen concentration in the vicinity of the surface layer due to outward diffusion during annealing. Is going down. If these wafers have a low oxygen concentration in the vicinity of the surface layer, the original resistivity is maintained in the surface layer region to be evaluated by the DLTS method even if heat treatment is performed under conditions where a thermal donor is formed or activated. If it is, if it is a board | substrate and an annealed wafer, only the resistivity of the deep area | region of a wafer can be reduced.
On the other hand, polished wafers that have only been sliced from an ingot and polished will not only reduce the resistivity deep in the wafer but also the resistivity of the surface layer region evaluated by the DTLS method, and thus the substrate resistance will decrease. As a result, even if the medium / long period noise is reduced, the detection sensitivity is decreased due to a decrease in the S / N ratio of a very short period.
For the above reasons, the target of the process 1 is specified to the epitaxial wafer and the annealed wafer. A semiconductor substrate suitable for application of the treatment 1 is an epitaxial wafer in which an N-type epitaxial layer is formed on an N-type silicon single crystal substrate obtained from a silicon single crystal ingot grown by the MCZ method or the CZ method, and An annealed wafer obtained by annealing the N-type silicon single crystal substrate. The interstitial oxygen concentration of the N-type silicon single crystal substrate is usually about 5.0 × 10 ^{17 to} 1.5 × 10 ¹⁸ atoms / cm ^{3 in} terms of old ASTM.

  On the other hand, since the process 2 does not affect the resistivity in the vicinity of the surface to be measured, it can be applied to various wafers such as an epitaxial wafer, an annealed wafer, and a polished wafer regardless of the type of wafer. The conductivity type may be N-type or P-type.

  Hereinafter, details of the processes 1 and 2 will be sequentially described.

Process 1 is a heat treatment performed on a semiconductor substrate to be evaluated under conditions for forming or activating a thermal donor. When the heat treatment is performed after the diode is formed, the barrier height of the semiconductor junction is lowered. Therefore, the heat treatment is performed before the diode is formed.
Since the thermal donor is usually formed or activated at a temperature of 400 ° C. or higher, the treatment 1 is preferably performed at a temperature of 400 ° C. or higher. When the heat treatment temperature exceeds 600 ° C., for example, phenomena such as decomposition of thermal donors and generation of oxygen precipitates occur. Therefore, the heat treatment temperature is preferably 400 ° C. to 600 ° C., preferably 400 ° C. to 500 ° C. It is more preferable to set the temperature within the range. In the present invention, the temperature related to heat treatment refers to the ambient temperature at which heat treatment is performed. The heat treatment can be performed, for example, in a clean room atmosphere, in purified nitrogen, oxygen, or an atmosphere in which purified nitrogen and oxygen are mixed.
The heat treatment time is preferably such a time that the substrate resistance is sufficiently lowered by the formation or activation of the thermal donor, and is usually about 1 to 100 hours. Moreover, contamination from a heat treatment furnace or oven can be prevented by sandwiching the semiconductor substrate to be evaluated between two dummy wafers having high cleanliness in a sandwich shape and performing heat treatment. As the dummy wafer, it is preferable to use a silicon wafer whose surface is cleaned to have a heavy metal concentration of Fe, Cu, Ni, Cr, W or the like of less than 1E9 / cm ² . If the semiconductor substrate subjected to the treatment 1 is stored or handled at a temperature of less than 400 ° C., the concentration of the thermal donor formed by the treatment 1 is stable without increasing or decreasing.

  Process 2 is a thinning process for reducing the thickness of the semiconductor substrate from the surface on which the ohmic layer is formed (hereinafter also referred to as “back surface”). Thinning from the back surface can be performed by a known method such as cutting with a grinder or chemical-mechanical polishing (CMP). The greater the amount removed by the thinning process, the lower the substrate resistance, which is advantageous for reducing medium and long period noise. However, as the removal amount increases, it becomes more difficult to manufacture a diode for DLTS measurement. Therefore, considering the ease of manufacturing the diode, the substrate thickness after the thinning process is preferably 200 μm or more.

The evaluation method of the present invention can be performed in the same manner as the metal contamination evaluation by the normal DLTS method, except that the treatment 1 or the treatment 2 is performed before the production of the diode.
Below, the outline | summary of a general DLTS method is demonstrated. The drawings referred to below show an example in which a 1 mm ² Schottky diode is formed on p-type CZ silicon.

1) Reverse voltage (V _R ) for forming a depletion layer at a semiconductor junction (Schottky junction or pn junction) formed on a semiconductor sample to be evaluated and a weak voltage near 0 V for trapping carriers in the depletion layer (V ₁ ) is alternately and periodically applied (the condition of voltage application to the diode as a sample is shown in the upper diagram of FIG. 1. In the figure, V _R = + 5 V and V ₁ = + 1 V).
2) The transient response of the capacitance (capacitance) of the diode generated corresponding to the voltage is measured (see the lower diagram in FIG. 1).
3) The voltage application and the capacity measurement in the above 1) and 2) are performed while sweeping the sample temperature within a predetermined temperature range. In the case of silicon, a temperature sweep in the range of 30 to 300K is generally performed. This capacitance transient response is temperature dependent. A schematic diagram of temperature dependence is shown in FIG.
At this time, the DLTS signal (ΔC) is usually defined as follows.
ΔC = C (t1) −C (t2) (1)
In the above formula (1), C (t1) is a capacity at a time t1 when a predetermined period has elapsed from the voltage application, and C (t2) is a capacity at a time t2 after a predetermined period has elapsed since the C (t1) measurement. In recent years, a method of using a lock-in amplifier to obtain a DLTS signal by taking the difference between the integrated values of the first half and the second half of the transient response (lock-in type) is often used. In addition, since the DLTS signal ΔC is a minute signal, the measured value ΔC is usually taken into a computer and an average value is obtained for each temperature. However, the temperature sweep is linearly performed, and T ± 0.5 to 1 [ In many cases, the average value of ΔC acquired in the range of K] is ΔC at the temperature T [K].

When a deep level exists in a depletion layer formed by applying a reverse voltage (V _R ), a DLTS spectrum as shown in FIG. 3 can be obtained by plotting the DLTS signal ΔC in relation to temperature. FIG. 3 shows DLTS spectra obtained by measuring p-type CZ silicon under two conditions of measurement frequencies e = 54.25 / s and e = 542.5 / s. The reason why a spectrum having a shape as shown in FIG. 3 is obtained is that the speed of carrier emission depends on temperature as follows.
Low temperature: ΔC≈0 due to slow release of carriers from deep levels
High temperature: carrier emission from a deep level is fast, and almost carrier emission has ended before t = t1, and as a result, ΔC≈0
From such a relationship, a peak of ΔC appears at a predetermined temperature depending on the deep level characteristics (activation energy Ea, carrier capture cross section σ) and measurement conditions. In FIG. 3, since the data processing according to the above formula (1) is performed, the peak is downward (convex downward), but data processing may be performed as ΔC = C (t2) −C (t1). In the case, the signal due to the deep level becomes convex upward.

From the peak height in the DLTS spectrum obtained as described above, for example, the deep level concentration (N _T ) can be calculated by the following equation (2).
N _T ≈ 2 * N _D * ΔC _MAX / C _∞ (/ cm ³ ) (2)
Here, N _D is a dopant concentration, [Delta] C _MAX is the depletion layer capacitance after the release was almost completed carrier from DLTS intensity of the signal, after the C _∞ is V _R applied, the deep level at the peak position temperature. Therefore, C _∞ = C (V = V _R , t = ∞).

Further, when DLTS measurement is performed while changing the ratio of t ₁ / t ₂ , the DLTS peak position is shifted accordingly.
At this time, the carrier emission rate e can be calculated from the following formulas (3) and (4) according to the measurement conditions t1 and t2.
τ = (t ₂ −t ₁ ) / log (t ₂ / t ₁ ) (3)
e = 1 / τ (4)

Furthermore, by taking the reciprocal 1 / T of the peak position (temperature) T on the horizontal axis and e / T ² on the vertical axis and taking a so-called Arrhenius plot, the energy level of the deep level from the slope (y intercept) of the plot (E _T ) can be obtained. This is because the relationship of the following formula (5) is established between various characteristic values.
ln (e / T ² ) = ln (γσ) · E _act / kT (5)
Here, k is a Boltzmann constant, and γ and E _act are as follows.
In the case of an n-type substrate (majority carriers are electrons): γ = 1.9E20 [cm ⁻² s ⁻¹ K ⁻² ]
E _act = E _C −E _T [eV]
In the case of a p-type substrate (majority carriers are holes): γ = 1.8E21 [cm ⁻² s ⁻¹ K ⁻² ]
E _act = E _T −E _V [eV]
(In the above, E _C is the lower end of the conduction band and E _V is the upper end of the valence band.)

Also, Arrhenius plot library based on DLTS measurement results introduced in past literatures and papers, and Arrhenius created by accumulating DLTS measurement results on semiconductor substrates intentionally introduced with defects and metal contamination By comparing with a library of plots, it is possible to identify the identity of the deep level (contaminated metal species) detected in this measurement. For example, in FIG. 3, the peak of the DLTS signal was detected at the positions of 52k and 60k, respectively, under two conditions where the measurement frequencies e = 54.25 / s and e = 542.5 / s. FIG. 4 is a result of Arrhenius plotting the relationship between the peak position (temperature) and e obtained by the measurement of FIG. 3 and collating it with a library built in the measuring instrument. FIG. 4 shows that the DLTS signal detected in FIG. 3 is likely to be due to the Fe—B pair. From this result, the contaminating metal species can be identified as Fe.
Thus, in specifying the contaminated metal species, the medium / long-period noise hinders accurate detection of the peak position and height. This phenomenon is a factor that greatly reduces the accuracy of evaluation particularly when the amount of metal contamination is small and the DLTS signal is weak. On the other hand, according to the present invention, the medium / long-period noise can be reduced by performing the process 1 or 2 described above on the semiconductor substrate to be evaluated before manufacturing the diode, thereby reducing the DLTS method. This can improve the sensitivity of metal contamination evaluation.

  The present invention further includes a step of preparing a lot of semiconductor substrates composed of a plurality of semiconductor substrates, a step of extracting at least one semiconductor substrate from the lot, a step of evaluating metal contamination of the extracted semiconductor substrate, A semiconductor substrate manufacturing method (hereinafter referred to as “the manufacturing method of the present invention”) including a step of shipping, as a product substrate, another semiconductor substrate in the same lot as the semiconductor substrate in which the metal contamination is determined to be an allowable level or less as a result of the evaluation "). In the manufacturing method of the present invention, the metal contamination evaluation of the extracted semiconductor substrate is performed by the evaluation method of the present invention.

  As described above, according to the evaluation method of the present invention, metal contamination of a semiconductor substrate such as a silicon wafer can be measured with high sensitivity even if the substrate is cleaned and the amount of contamination is small. Therefore, by such an evaluation method, a semiconductor substrate in which metal contamination is determined to be below an allowable level, for example, a semiconductor substrate in the same lot as a non-defective semiconductor substrate determined to be free from contamination by a predetermined metal or to have a small amount of contamination. By shipping as a product substrate, a high-quality product substrate can be provided with high reliability. In addition, the standard (allowable level of metal contamination) for determining a non-defective product can be set in consideration of physical properties required for the substrate according to the use of the substrate. The number of substrates included in one lot and the number of substrates to be extracted may be set as appropriate.

  Hereinafter, the present invention will be further described based on examples. However, this invention is not limited to the aspect shown in the Example. The following steps and treatments were performed at room temperature unless otherwise specified.

An N-type silicon wafer sliced from a silicon single crystal ingot grown by the CZ method and having an interstitial oxygen concentration of 1.2 × 10 ¹⁸ atoms / cm ³ and having a resistivity of about 15 Ω · cm has a resistivity. An epitaxial wafer was prepared by vapor-phase-growing an epitaxial layer having a thickness of 10 Ω · cm and a thickness of 7 μm. Here, the interstitial oxygen concentration was measured by the FT-IR method, and the old ASTM conversion coefficient was used for conversion from the FT-IR signal intensity to the interstitial oxygen concentration.

The silicon wafer was divided into two, and one of them formed a Schottky diode (hereinafter referred to as “non-heat-treated diode”) by a conventional procedure.
That is,
(A) Oxide film removal with HF aqueous solution + pure water rinse + drying (B) Schottky electrode formation by vacuum deposition (electrode area is 1 mm ² )
(C) Backside ohmic contact formation by gallium rubbing was performed.
The series resistance of the diode determined from the forward current-voltage characteristics of the Schottky diode was about 110Ω.

A diode (hereinafter referred to as “diode with heat treatment”) was formed in the order of the following steps on the other part divided into two.
(1) A sample is sandwiched between two dummy wafers that have been confirmed to have a heavy metal concentration of less than 1E9 / cm ² such as Fe, Cu, Ni, Cr, W, etc. on the surface, and a heat treatment furnace (furnace atmosphere: To clean room atmosphere). Heat treatment was performed at 450 ° C. for 4 hours.
(2) Oxide film removal with HF aqueous solution + pure water rinse + drying (3) Schottky electrode formation by vacuum deposition (electrode area is 1 mm ² )
(4) Backside ohmic contact formation by gallium rubbing The series resistance of the diode determined from the forward current-voltage characteristics of the Schottky diode was about 60Ω. It is considered that the interstitial oxygen in the substrate was activated as a thermal donor by the heat treatment at 450 ° C., so that the resistivity of the substrate was lowered and the series resistance of the diode was reduced as compared with the diode without heat treatment.
In the above (3), the Schottky electrode is formed by vacuum deposition, but it can also be formed by sputtering. In the above (4), gallium is used, but backside ohmic contact formation may be performed by aluminum vapor deposition.

FIG. 5 shows the result of DLTS measurement performed on the above-mentioned diode without heat treatment and the diode with heat treatment. Here, a lock-in DLTS measuring device was used, and the reverse voltage was −3 V, the pulse voltage was 0 V, the pulse width was 50 μs, and the pulse frequency was 25 Hz.
As shown in FIG. 5, in the diode without heat treatment, a broad signal having a peak of about 150 k appeared in the range of 100 to 200K. In the case of a single impurity level that forms a peak at 150K, the full width at half maximum should be about 20K, and the broad signal that appears here is not due to a single impurity, but because the series resistance is too high. There is a strong suspicion of the resulting pseudo signal.
On the other hand, in the diode with heat treatment, no broad signal appeared, and a signal with a single energy level having a half width of about 20K was detected at a position of 150K. This signal is presumed to be due to Mo contamination from a known library.
From the above results, the series resistance of the Schottky diode can be reduced by the above heat treatment, so that high sensitivity can be obtained even with a minute amount of metal contamination without being disturbed by the undulation of the DLTS pseudo signal / baseline. It has been shown that it can be detected. The application of the present invention is particularly effective when the substrate resistance is, for example, 10 Ω · cm or more and the series resistance of the diode is high, but also when the substrate resistance is less than 10 Ω · cm, the resistivity of the surface to be measured By performing the process of reducing the series resistance of the diode without greatly reducing the noise, it is possible to reduce medium / long-period noise and increase the detection sensitivity.

Although the aspect using the process 1 which reduces the series resistance of a diode by heat processing was described above, the same effect can be acquired also by reducing the series resistance of a diode by the process 2.
The thickness of the substrate after thinning to reduce the series resistance of the diode to the same level as in the processing 1 becomes a value shown in the following Table 1 by known calculation.

  The present invention is useful for quality control and process control in the field of manufacturing semiconductor substrates.

Claims (4)

A method for evaluating metal contamination of a semiconductor substrate,
Forming a semiconductor junction on one surface of a semiconductor substrate to be evaluated and forming an ohmic layer on the other surface to produce a diode;
Performing DLTS measurement of the fabricated diode,
Evaluating the presence or absence of metal contamination, the degree of metal contamination, or the presence and extent of metal contamination based on the measurement results,
Including
The evaluation method according to claim 1, wherein the following treatment 1 or 2 is performed before manufacturing the diode.
Process 1: Heat treatment performed under conditions for forming or activating a thermal donor when the semiconductor substrate to be evaluated is an epitaxial wafer, an annealed wafer, or a part thereof.
Process 2: Thinning process for reducing the thickness of the semiconductor substrate from the surface on the side where the ohmic layer is formed. The evaluation method according to claim 1, wherein the semiconductor substrate is a silicon epitaxial wafer or a part thereof. The evaluation method according to claim 2, wherein the silicon epitaxial wafer has an N-type epitaxial layer on an N-type silicon single crystal substrate obtained from a silicon single crystal ingot grown by the MCZ method or the CZ method. Preparing a lot of semiconductor substrates comprising a plurality of semiconductor substrates;
Extracting at least one semiconductor substrate from the lot;
A step of evaluating metal contamination of the extracted semiconductor substrate;
As a result of the evaluation, a process of shipping another semiconductor substrate in the same lot as the semiconductor substrate in which the metal contamination is determined to be below an allowable level as a product substrate,
A method of manufacturing a semiconductor substrate comprising:
The said manufacturing method characterized by performing the metal contamination evaluation of the said extracted semiconductor substrate by the method of any one of Claims 1-3.