JP2014060345A - Power semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power semiconductor device having low on-resistance and high avalanche resistance.SOLUTION: A power semiconductor device includes a first semiconductor layer 1 of a first conductivity type, a second semiconductor layer 2 of the first conductivity type, a third semiconductor layer 3 of a second conductivity type, a fourth semiconductor layer 4 of the first conductivity type, a fifth semiconductor layer 5 of the first conductivity type, a gate electrode, a first electrode, and a second electrode. The second semiconductor layer extends in the first semiconductor layer along a first direction perpendicular to a first surface of the first semiconductor layer and a second direction parallel to the first surface. The third semiconductor layer extends in the second semiconductor layer along the first direction and the second direction. The fourth semiconductor layer extends in the third semiconductor layer along the first direction and the second direction. The fifth semiconductor layer extends on a surface of the second semiconductor layer along the second direction, and is adjacent to the first semiconductor layer in a third direction perpendicular to the first direction and the second direction. The gate electrode extends from within the fourth semiconductor layer through the third semiconductor layer to within the second semiconductor layer along the third direction.

Description

  Embodiments described herein relate generally to a power semiconductor device.

As a power semiconductor device, an insulated gate transistor such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) is used. These power semiconductor devices are required to have low power consumption by low on-resistance. In an insulated gate transistor having a medium to high withstand voltage of about several tens of V to 300 V, the on-resistance R _on is governed by the density of the channel layer. For example, in the case of MOSFET, the channel layer is formed in a region facing the gate electrode through the gate insulating film on the surface of the base layer between the source layer and the drift layer. The distance between the source layer and the drift layer is called a channel length, which is the length of a path through which current flows. The width of the channel layer perpendicular to the channel length is called the channel width and corresponds to the cross section of the current path. As the channel width is increased in the same chip, the resistance of the channel layer can be lowered. Therefore, although the on-resistance of the insulated gate transistor has been reduced by miniaturization, there is a limit to further lowering the on-resistance by miniaturization.

  Thus, an insulated gate transistor has been developed in which the direction in which the channel width extends is not in the direction horizontal to the chip but in the direction perpendicular to the chip. In such an insulated gate transistor, a source layer, a base layer, a drift layer, a drain layer, and a gate electrode are provided so that the channel width extends in the vertical direction of the chip and the channel length extends in the horizontal direction of the chip. It is done. As the channel width increases, further reduction in on-resistance can be expected.

  However, the length in the direction perpendicular to the chip from the bottom of the base layer to the source electrode increases as the channel width increases. When an avalanche breakdown occurs at the pn junction between the base layer and the drift layer at the bottom of the base layer, holes generated by the avalanche breakdown travel in the direction perpendicular to the chip from the bottom of the base layer to the base layer. , And discharged to the source electrode at the upper end of the base layer. For this reason, as the channel width increases, the voltage drop due to current when holes generated by avalanche breakdown are discharged to the source electrode increases. The potential at the bottom of the base layer rises with respect to the source layer, and the parasitic transistor constituted by the source layer, the base layer, and the drift layer is likely to be turned on. When the parasitic transistor is turned on, a large current flows through the power semiconductor device, and as a result, the power semiconductor device is destroyed. That is, in a power semiconductor device in which the channel width extends in the direction perpendicular to the chip, the avalanche resistance may decrease as the channel width is increased by increasing the depth in the direction perpendicular to the chip of the base layer. A power semiconductor device with low on-resistance and high avalanche resistance is desired.

JP 2007-103459 A

  Providing power semiconductor devices with low on-resistance and high avalanche resistance.

  A power semiconductor device according to an embodiment of the present invention includes a first conductivity type first semiconductor layer, a first conductivity type second semiconductor layer, a second conductivity type third semiconductor layer, A fourth semiconductor layer of one conductivity type, a fifth semiconductor layer of the first conductivity type, a gate electrode, a first electrode, and a second electrode are provided.

  The first semiconductor layer of the first conductivity type has a first surface and a second surface opposite to the first surface. The second semiconductor layer of the first conductivity type extends in the first semiconductor layer from the first surface of the first semiconductor layer along a first direction perpendicular to the first surface, and the first semiconductor layer The first semiconductor layer is stretched along a second direction parallel to the first surface. The second conductivity layer of the first conductivity type has a lower first conductivity type impurity concentration than the first semiconductor layer. The third semiconductor layer of the second conductivity type extends from the surface of the second semiconductor layer in the second semiconductor layer along the first direction, and extends along the second direction. Stretch inside. The fourth semiconductor layer of the first conductivity type extends in the third semiconductor layer along the first direction from the surface of the third semiconductor layer, and the third semiconductor layer along the second direction. The inside is stretched and the first conductivity type impurity concentration is higher than that of the second semiconductor layer. The fifth semiconductor layer of the first conductivity type is provided on the surface of the second semiconductor layer so as to extend along the second direction and to be in contact with the first semiconductor layer and the second semiconductor layer. The first conductivity type impurity concentration is higher than that of the second semiconductor layer.

  The gate electrode extends from the fourth semiconductor layer through the third semiconductor layer along the third direction into the second semiconductor layer, and extends along the first direction into the second semiconductor layer. The gate insulating film is provided in the third semiconductor layer and in the gate trench extending in the second semiconductor layer. The first electrode is electrically connected to the third semiconductor layer and the fourth semiconductor layer. The second electrode is electrically connected to the second surface of the first semiconductor layer.

The principal part model perspective view of the semiconductor device for electric power which concerns on 1st Embodiment. The figure which abbreviate | omitted the upper part from the AA plane in FIG. The principal part schematic perspective view of the semiconductor device for electric power which concerns on the modification of 1st Embodiment. The principal part schematic perspective view of the semiconductor device for electric power which concerns on 2nd Embodiment. The principal part schematic perspective view of the semiconductor device for electric power which concerns on 3rd Embodiment. The principal part schematic perspective view of the semiconductor device for electric power which concerns on 4th Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings used in the description in the embodiments are schematic for ease of description, and the shape, size, magnitude relationship, etc. of each element in the drawings are not necessarily shown in the drawings in actual implementation. The present invention is not limited to the above, and can be appropriately changed within a range in which the effect of the present invention can be obtained. Although the first conductivity type is described as n-type and the second conductivity type is described as p-type, the opposite conductivity types may be used. As a semiconductor, silicon will be described as an example, but it can also be applied to a compound semiconductor such as silicon carbide (SiC) or nitride semiconductor (AlGaN). As the insulating film, silicon oxide is described as an example, but other insulators such as silicon nitride, silicon oxynitride, and alumina can be used. When n-type conductivity is expressed by n ⁺ , n, and n ⁻ , the n-type impurity concentration is assumed to be lower in this order. Similarly, in the p-type, the p-type impurity concentration is low in the order of p ⁺ , p, and p ⁻ .

(First embodiment)
A power semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2. The power semiconductor device will be described by taking a MOSFET as an example, but can also be applied to an IGBT. The same applies to the following embodiments. FIG. 1 is a schematic perspective view of a main part of the power semiconductor device according to the first embodiment. FIG. 2 is a schematic perspective view of a main part in which an upper part is omitted from the plane AA in FIG. 1. Note that the source electrode and the drain electrode are not shown in the perspective view of FIG.

As shown in FIGS. 1 and 2, the power semiconductor device according to the first embodiment of the present invention includes an n ⁺ -type drain layer 1 (a first semiconductor layer of a first conductivity type), an n ⁻ -type, and Drift layer 2 (first conductivity type second semiconductor layer), p-type base layer 3 (second conductivity type third semiconductor layer), and n ^{+ -type} source layer 4 (first conductivity type fourth semiconductor layer). Semiconductor layer), an n ^{+ type} semiconductor layer 8 (first conductivity type fifth semiconductor layer), a p ^{+ type} contact layer 9 (second conductivity type sixth semiconductor layer), a gate electrode 7, And a source electrode (first electrode) and a drain electrode (second electrode). The n ⁺ -type drain layer 1, the n ⁻ -type drift layer 2, the p-type base layer 3, the n ^{+ -type} source layer 4, the n ^{+ -type} semiconductor layer 8, and the p ^{+ -type} contact layer 9 are, for example, semiconductor layers made of silicon. It is. The n-type impurity is, for example, phosphorus (P). The p-type impurity is, for example, boron (B).

The n ⁺ -type drain layer 1 has a first surface and a second surface opposite to the first surface. The n ^{+ -type} drain layer 1 has an n-type impurity concentration of 1 × 10 ¹⁹ / cm ³ or more.

The n ⁻ -type drift layer 2 extends from the first surface of the n ⁺ -type drain layer 1 along the Z direction (first direction) perpendicular to the first surface, and extends in the n ⁺ -type drain layer. The n ⁺ -type drain layer 1 is extended along the Y direction (second direction) parallel to the surface of 1. The n ⁻ -type drift layer 2 has a lower n-type impurity concentration than the n ⁺ -type drain layer 1. The n-type impurity concentration of the n ⁻ -type drift layer 2 is, for example, 1 × 10 ¹⁷ / cm ³ or less. Further, the thickness of the n ⁻ -type drift layer 2 in the Z direction is, for example, 10 to 50 μm. The thickness of the n ⁻ -type drift layer 2 in the Z direction is set according to the channel width formed along the Z direction.

p-type base layer 3, n ^- along the surface of the form the drift layer 2 in the Z-direction n ^- stretching the shape drift layer 2 medium, and n along the Y-direction ^- stretching the shape drift layer 2 medium. The p-type impurity concentration of the p-type base layer 3 is, for example, 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm ³ . The thickness in the Z direction of the portion (bottom) of the n ^{− type} drift layer 2 sandwiched between the p type base layer 3 and the n ^{+ type} drain layer 1 in the Z direction is, for example, 3 μm. The thickness in the X direction of the portion (side portion) of the n ^{− type} drift layer 2 sandwiched between the p type base layer 3 and the n ^{+ type} drain layer 1 in the X direction perpendicular to the Z direction and the Y direction is n ^- similar to the bottom of the form the drift layer 2, a 3 [mu] m.

n ⁺ -type source layer 4, stretching the p-type base layer 3 medium along the surface of the p-type base layer 3 in the Z direction, and stretching the p-type base layer 3 medium along the Y-direction, n ^- form The n-type impurity concentration is higher than that of the drift layer 2. The n type impurity concentration of the n ^{+ type} source layer 4 is, for example, 1 × 10 ¹⁹ / cm ³ or more. The thickness in the Z direction of the portion (bottom) of the p-type base layer 3 sandwiched between the n ^{+ -type} source layer 4 and the n ⁻ -type drift layer 2 in the Z direction is, for example, 0.2 to 1.0 μm. In addition, the thickness in the X direction of the portion (side portion) of the p-type base layer 3 sandwiched between the n ^{+ -type} source layer 4 and the n ⁻ -type drift layer 2 in the X direction is the same as the bottom of the p-type base layer. 0.2 to 1.0 μm. The thickness of the n ^{+ -type} source layer 4 in the X direction is, for example, 1.0 to 2.0 μm.

The n ^{+ -type} semiconductor layer 8 is provided on the surface of the n ⁻ -type drift layer 2 so as to extend along the Y direction, is adjacent to the n ⁺ -type drain layer in the X direction, and is more n than the n ⁻ -type drift layer 2. High impurity concentration. The n type impurity concentration of the n ^{+ type} semiconductor layer 8 is, for example, 1 × 10 ¹⁹ / cm ³ or more. n-type impurity concentration of the n ⁺ -type semiconductor layer 8, if you like even more n-type impurity concentration of the n ⁺ -type drain layer 1, may be less than or equal to n-type impurity concentration of the n ⁺ -type drain layer 1. The n ^{+ type} semiconductor layer 8 extends along the X direction.

The p ^{+ -type} contact layer 9 extends along the Y direction on the surface of the p-type base layer 3 and is adjacent to the n ^{+ -type} source layer 4 in the X direction. The p ^{+ -type} contact layer 9 has a higher p-type impurity concentration than the p-type base layer 3. The p type impurity concentration of the p ^{+ type} contact layer 9 is, for example, 1 × 10 ¹⁸ / cm ³ or more. The p ^{+ -type} contact layer 9 is separated from the n ⁻ -type drift layer 2 via the p-type base layer 3 in the X direction. In the present embodiment, the p ^{+ -type} contact layer 9 is adjacent to the n ^{+ -type} source layer 4 in the X direction. However, the p ^{+ -type} contact layer 9 may be separated from the n ^{+ -type} source layer 4 via the p-type base layer 3 as long as the contact with the source electrode described later is good.

A gate trench 5 extends from the n ^{+ -type} source layer 4 along the X direction through the p-type base layer 3 and into the n ⁻ -type drift layer 2, and extends along the Z direction in the n ^{+ -type} source layer 4, the p-type base layer 3, and the n ⁻ -type drift layer 2 are stretched. The gate trench 5 passes through the p ^{+ -type} contact layer 9 along the X direction. A plurality of gate trenches 5 are provided along the Y direction. The p ^{+ -type} contact layer 9 is adjacent to the gate trench 5 at both ends in the Y direction. That is, the p ^{+ -type} contact layer 9 is exposed on the side wall of the gate trench 5.

The bottom of the gate trench 5 may be in the n ^{+ -type} source layer 4 in the bottom of the p-type base layer 3 or above the bottom of the p-type base layer 3 in the Z direction. If the bottom of the gate trench 5 is too shallow, the channel width is reduced. Conversely, if the depth is too deep, electric field concentration occurs around the bottom of the gate trench 5 and avalanche breakdown is likely to occur.

  A gate insulating film 6 is provided so as to cover the entire side wall and the entire bottom surface of the gate trench 5. The gate insulating film 6 is, for example, silicon oxide. Instead of silicon oxide, silicon oxynitride or silicon nitride may be used.

  The gate electrode 7 is provided in the gate trench 5 via the gate insulating film 6. The gate electrode may be any conductive material, for example, conductive polysilicon.

The first interlayer insulating film 10 is formed on the n ⁺ -type drain layer 1, the n ⁻ -type drift layer 2, the p-type base layer 3, the n ^{+ -type} source layer 4, the n ^{+ -type} semiconductor layer 8, and the p ^{Provided on the + -type} contact layer 9. The first interlayer insulating film 10 is, for example, silicon oxide. Instead of silicon oxide, silicon nitride, silicon oxynitride, or the like can be used.

  The gate wiring layer 11 has a predetermined pattern, is provided on the first interlayer insulating film 10, and is electrically connected to the gate electrode 7 through the opening of the first interlayer insulating film 10. The gate wiring layer 11 connects each gate electrode to a gate pad (not shown).

  A second interlayer insulating film 12 is provided on the first interlayer insulating film so as to cover the gate wiring layer 11. The second interlayer insulating film 12 is, for example, silicon oxide. Instead of silicon oxide, silicon nitride or silicon oxynitride may be used.

A source contact opening 13 penetrating the second interlayer insulating film 12 and the first interlayer insulating film 10 is provided. A source electrode (not shown) is provided on the second interlayer insulating film 12 and is electrically connected to the n ^{+ -type} source layer 4 and the p ^{+ -type} contact layer 9 through the source contact opening 13. The source electrode is electrically connected to the p-type base layer 3 through the p ^{+ -type} contact layer 9. A drain electrode (not shown) is electrically connected to the second surface of the n ⁺ -type drain layer 1. The source electrode and the drain electrode are typically used as semiconductor electrodes, such as copper or aluminum.

  Next, the operation and characteristics of the power semiconductor device according to this embodiment will be described. When a voltage exceeding a threshold value is applied to the gate electrode 7 with respect to the source electrode, a channel layer with an inversion distribution is formed on the surface of the p-type base layer 3 joined to the gate insulating film 6, and the power semiconductor device is turned on. become. The width of the channel layer in the X direction is the channel length, and the width of the channel layer in the Z direction is the channel width.

When a positive voltage is applied to the drain electrode relative to the source electrode, electrons supplied from the source electrode to the n ^{+ -type} source layer 4 are transferred from the n ^{+ -type} source layer 4 to the p-type base layer along the X direction. 3 channel layer and n ⁻ -type drift layer 2, and then flows to n ⁺ -type drain layer 1. As a result, current flows from the drain electrode toward the source electrode. When the voltage applied to the gate electrode falls below the threshold value, the channel layer disappears and the power semiconductor device is turned off. The drain-source current is cut off, and the drain-source voltage rises. At the same time, the depletion layer starts to spread from the pn junction between the p-type base layer 3 and the n ⁻ -type drift layer 2 toward the n ⁻ -type drift layer.

In the power semiconductor device in which the channel width extends in the direction perpendicular to the chip, the p-type base layer 3 generally has a corner portion at the bottom. For this reason, the depletion layer hardly extends from the pn junction between the p-type base layer 3 and the n ⁻ -type drift layer 2 at the corner portion, and electric field concentration occurs. Due to this electric field concentration, the breakdown voltage between the n ⁺ -type drain layer 1 and the p-type base layer 3 is lower in the corner portion than in other portions, and avalanche breakdown occurs.

Holes generated by this avalanche breakdown flow through the p-type base layer 3 along the Z direction and are discharged to the source electrode. Due to the voltage drop due to the hole current, the potential of the p-type base layer 3 rises with respect to the n ^{+ -type} source layer 4. The voltage drop increases as the channel width is increased to reduce the on-resistance. As a result, the parasitic transistor formed by the n ^{+ -type} source layer 4, the p-type base layer 3, and the n ⁻ -type drift layer 2 is turned on, a large current flows between the drain and the source, and the power semiconductor device is destroyed. Is done.

However, in the power semiconductor device according to this embodiment, n ^- in the form drift layer 2 of the surface (upper surface) extending in the Y direction, the n ⁺ -type semiconductor layer 8 adjacent in the X direction and n ⁺ -type drain layer 1 Prepare. The n ^{+ -type} semiconductor layer 8 further extends from the n ⁺ -type drain layer 1 toward the p-type base layer 3 on the surface of the p-type base layer 3. That is, the width in the X direction of the n ^{− type} drift layer 2 on the surface of the n ^{− type} drift layer 2 can be adjusted by changing the width in the X direction of the n ^{+ type} semiconductor layer 8.

As the width of the n ⁻ -type drift layer 2 in the X direction is reduced, the breakdown voltage at this portion is reduced. Therefore, the presence of the n ^{+ -type} semiconductor layer 8 on the surface of the n ⁻ -type drift layer 2 can lower the breakdown voltage on the surface of the p-type base layer 3 than the bottom of the p-type base layer 3. That is, in the X direction, the p-type base layer 3, the n− type drift layer 2, and the n ^{+ type} semiconductor layer 8 constitute a clamp diode.

  For this reason, in the power semiconductor device according to the present embodiment, since avalanche breakdown occurs on the surface of the p-type base layer 3, holes generated by avalanche breakdown are efficiently discharged to the source electrode, that is, positive The discharge resistance of holes is very small. As a result, the parasitic transistor can be prevented from being turned on, so that the avalanche resistance is improved in the power semiconductor device according to the present embodiment.

As another method of reducing the width of the n ^{− type} drift layer 2 in the X direction on the surface of the n ^{− type} drift layer 2 without using the n ^{+ type} semiconductor layer 8, the surface of the p type base layer 3 ( There is a method of protruding the p ^{+ -type} contact layer 9 provided on the upper surface) from the p-type base 3 to the n ⁻ -type drift layer (comparative example). That is, the p ^{+ -type} contact layer 9, the n ⁻ -type drift layer 2, and the n ⁺ -type drain layer 1 constitute a clamp diode. In the power semiconductor device according to this comparative example, the diffusion of n-type impurities from the n ⁺ -type drain layer 1 to the n ⁻ -type drift layer 2 is a problem.

The manufacturing process of the power semiconductor device includes a process having a high-temperature process such as an epitaxial growth process of the n ⁻ -type drift layer 2, the p-type base layer 3, and the n ⁺ -type source layer 4 or an oxide film process. In such a high temperature process, n-type impurities are thermally diffused from the n ⁺ -type drain layer 1 to the n ⁻ -type drift layer 2. The thermal diffusion of this n-type impurity varies greatly. For this reason, in the power semiconductor device according to the comparative example, the width of the n ^{− type} drift layer 2 sandwiched between the p ^{+ type} contact layer 9 and the n ^{+ type} drain layer 1 in the X direction has a large variation. Variation in pressure resistance increases.

On the other hand, in the power semiconductor device according to the present embodiment, the n ^{+ type} semiconductor is larger than the maximum distance in which the n type impurity diffuses from the n ^{+ type} drain layer 1 to the n ^{− type} drift layer 2 in the X direction. The n ^{+ -type} semiconductor layer 8 is formed so that the width of the layer 8 in the X direction is sufficiently large. Since the n ^{+ -type} semiconductor layer 8 is formed by ion implantation and subsequent heat treatment, the variation in the width of the n ^{+ -type} semiconductor layer 8 in the X direction is from the n ⁺ -type drain layer 1 to the n ⁻ -type drift layer 2. It can be made smaller than the variation in which n-type impurities are diffused. As a result, in the power semiconductor device according to this embodiment, variations in breakdown voltage are reduced as compared with the power semiconductor device according to the comparative example.

(Second Embodiment)
A power semiconductor device according to the second embodiment will be described with reference to FIG. FIG. 3 is a schematic perspective view of a main part corresponding to FIG. 2 of the power semiconductor device according to the second embodiment. Note that the same reference numerals or symbols are used for portions having the same configurations as those described in the first embodiment, and description thereof is omitted. Differences from the first embodiment will be mainly described.

In the power semiconductor device according to the present embodiment, as shown in FIG. 3, the p ^{+ -type} contact layer 9 has both ends in the Y direction via the p-type base layer 3 and the gate insulating film 6. Separate. Although not shown, the power semiconductor device according to this embodiment includes a first interlayer insulating film 10, a gate wiring layer 11, a second interlayer insulating film 12, and a source contact opening 13 similar to those in FIG. Is provided. Here, the p ^{+ -type} contact layer 9 is ion-implanted and implanted into the surfaces of the p-type base layer 3 and the n ^{+ -type} source layer 4 exposed in the source contact opening 13 using the second interlayer insulating film 12 as a mask. It is formed by performing a subsequent heat treatment. The p type impurity concentration of the p ^{+ type} contact layer 9 is, for example, 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ . The p-type impurity is also implanted into the surface of the n ^{+ -type} source layer 4 by ion implantation. The n-type impurity concentration of the n ^{+ -type} source layer 4 is 1 × 10 ¹⁹ / cm ³ or more. The p ^{+ -type} contact layer 9 is formed so that the n-type impurity concentration becomes 1 × 10 ¹⁹ / cm ³ or more even after impurity compensation.

The power semiconductor device according to the present embodiment is different from the power semiconductor device according to the first embodiment in the above points. In the power semiconductor device according to this embodiment, by providing the p ⁺ -type contact layer 9, it is possible to omit the lithographic step for the p ⁺ -type contact layer 9 formed. That is, in the step of forming the p ^{+ -type} contact layer 9 of the power semiconductor device according to the first embodiment, a mask having an opening extending in a stripe shape in the Y direction is formed by a lithography step, and then an ion An injection is performed. In contrast, in the step of forming the p ^{+ -type} contact layer 9 of the power semiconductor device according to the present embodiment, the first interlayer insulating film 10, the gate wiring layer 11, and the second interlayer insulating film 12 are A p-type impurity is implanted by ion implantation through the source contact opening 13 functioning as a mask. Thereby, in the power semiconductor device according to the present embodiment, the process of forming a mask by lithography is reduced as compared with the power semiconductor device according to the first embodiment.

Also in the power semiconductor device according to the present embodiment, the n ^{+ -type} semiconductor layer 8 is present on the surface of the n ⁻ -type drift layer 2, as in the power semiconductor device according to the first embodiment. The breakdown voltage on the surface of the p-type base layer 3 can be made lower than the bottom of the base layer 3. For this reason, avalanche tolerance improves. In addition, variations in the breakdown voltage are reduced.

(Third embodiment)
A power semiconductor device according to a third embodiment will be described with reference to FIG. FIG. 4 is a schematic perspective view of a main part corresponding to FIG. 2 of the power semiconductor device according to the third embodiment. Note that the same reference numerals or symbols are used for portions having the same configurations as those described in the first embodiment, and description thereof is omitted. Differences from the first embodiment will be mainly described.

As shown in FIG. 4, the power semiconductor device according to the present embodiment includes an n-type semiconductor layer 14 between the n ^{+ -type} semiconductor layer 8 and the n ⁻ -type drift layer 2. The n-type semiconductor layer 14 extends the surface (upper surface) of the n ⁻ -type drift layer 2 along the Y direction, and is adjacent to the n ⁺ -type drain layer 1 in the X direction. The n-type semiconductor layer 14 extends the surface of the n ⁻ -type drift layer 2 along the X direction. The width of the n-type semiconductor layer in the X direction is larger than the width of the n ^{+ -type} semiconductor layer in the X direction. The n-type impurity concentration of the n-type semiconductor layer 14 is lower than the n-type impurity concentration of the n ^{+ -type} semiconductor layer 8 and higher than the n-type impurity concentration of the n ⁻ -type drift layer 2. The n-type impurity concentration of the n-type semiconductor layer 14 is, for example, 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm ³ .

The n-type semiconductor layer 14 is formed, for example, by ion-implanting n-type impurities into the surface of the n ⁻ -type drift layer 2 and then performing a heat treatment. The n ^{+ -type} semiconductor layer 8 is formed by further ion-implanting n-type impurities into the surface of the n-type semiconductor layer 14 and then performing a heat treatment.

In the power semiconductor device according to the first embodiment, in the profile of the n-type impurity concentration along the X direction on the surface of the n ⁻ -type drift layer 2, the n-type impurity concentration is the impurity concentration of the n ^{+ -type} semiconductor layer 8. To the n-type impurity concentration of the n ⁻ -type drift layer 2. On the other hand, in the power semiconductor device according to the present embodiment, the n-type impurity concentration is once changed from the impurity concentration of the n ^{+ -type} semiconductor layer 8 to the n-type impurity concentration of the n-type semiconductor layer 14 and then n ^−. The n-type impurity concentration of the drift layer 4 is changed. That is, in the power semiconductor device according to the present embodiment, on the surface of the n ⁻ -type drift layer 2, the n-type impurity concentration is changed from the n-type impurity concentration of the n ^{+ -type} semiconductor layer 8 to n of the n ⁻ -type drift layer 2. The impurity concentration decreases in two steps.

The power semiconductor device according to the present embodiment is different from the power semiconductor device according to the first embodiment in the above points. In the power semiconductor device according to the first embodiment, when an avalanche breakdown occurs in the clamp diode and a large current flows, a phenomenon (snapback) occurs in which the holding voltage of the element decreases and returns to the original voltage. This becomes remarkable when the difference between the n-type impurity concentration of the n ^{+ -type} semiconductor layer 8 of the clamp diode and the n-type impurity concentration of the n ⁻ -type drift layer 4 is large.

In the power semiconductor device according to the present embodiment, an n-type semiconductor layer 14 having an n-type impurity concentration between the n ⁺ -type impurity concentration between the n ^{+ -type} semiconductor layer 8 and the n ⁻ -type drift layer 2 is provided. Prepare. As a result, in the power semiconductor device according to the present embodiment, the n-type impurity concentration of the n ^{+ -type} semiconductor layer 8 is reduced in two steps from the n-type impurity concentration of the n ⁻ -type drift layer 2, so that snapback is suppressed. The

Also in the power semiconductor device according to the present embodiment, the n ^{+ -type} semiconductor layer 8 is present on the surface of the n ⁻ -type drift layer 2, as in the power semiconductor device according to the first embodiment. The breakdown voltage on the surface of the p-type base layer 3 can be made lower than the bottom of the base layer 3. For this reason, avalanche tolerance improves. In addition, variations in the breakdown voltage are reduced.

(Fourth embodiment)
A power semiconductor device according to a fourth embodiment will be described with reference to FIG. FIG. 5 is a schematic perspective view of a main part of a power semiconductor device according to the fourth embodiment. Note that the same reference numerals or symbols are used for portions having the same configurations as those described in the first embodiment, and description thereof is omitted. Differences from the first embodiment will be mainly described.

Power semiconductor device according to this embodiment, n between the gate electrode 7 and the n ⁺ -type drain layer 1 in the X direction ^- the form drift layer 2 medium in the field trench 15 extending along the Z-direction, the field A field electrode 17 is further provided via an insulating film 16. The field insulating film 16 is, for example, silicon oxide and is thicker than the gate insulating film 6. Instead of silicon oxide, silicon nitride or silicon oxynitride may be used. The field electrode 17 may be any conductive material, and is, for example, conductive polysilicon. Bottom field trench 15, in this embodiment, reach into the n ⁺ -type drain layer 1, than the bottom of the gate trenches 5, it has reached the second surface side of the n ⁺ -type drain layer 1.

As described above, the field plate electrode 17 is provided between the gate electrode 7 and the n ⁺ -type drain layer 1 in the X direction. The field plate electrode 17 is formed deeper in the n ⁻ -type drift layer than the gate electrode 7. The plurality of field plate electrodes 17 are arranged in the n ⁻ -type drift layer 2 along the Y direction while adjoining the gate electrode 7 in the X direction.

Similar to the power semiconductor device according to the first embodiment, the first interlayer insulating film 10 is formed on the n ⁺ -type drain layer 1, the n ⁻ -type drift layer 2, the p-type base layer 3, and the n ^{+ -type} source. Provided on the layer 4, the n ^{+ -type} semiconductor layer 8, and the p ^{+ -type} contact layer 9. Field plate wiring layer 18 has a predetermined pattern, is provided on first interlayer insulating film 10, and is electrically connected to field plate electrode 17 through the opening of first interlayer insulating film 10. . The field plate wiring layer 18 is electrically connected to the source electrode in a region not shown. As a result, the field plate electrode is held at the source potential.

  The second interlayer insulating film 12 is provided on the first interlayer insulating film 12 so as to cover the field plate wiring layer 18. The gate wiring layer 11 has a predetermined pattern, is provided on the second interlayer insulating film 12, and is electrically connected to the gate electrode 7 through the opening of the second interlayer insulating film 12.

A third interlayer insulating film 19 is provided on the second interlayer insulating film so as to cover the gate wiring layer 11. A source contact opening 13 penetrating the third interlayer insulating film 19, the second interlayer insulating film 12, and the first interlayer insulating film 10 is provided. A source electrode (not shown) is provided on the third interlayer insulating film 19 and is electrically connected to the n ^{+ -type} source layer 4 and the p ^{+ -type} contact layer 9 through the source contact opening 13. The source electrode is electrically connected to the p-type base layer 3 through the p ^{+ -type} contact layer 9. A drain electrode (not shown) is electrically connected to the second surface of the n ⁺ -type drain layer 1.

In the power semiconductor device according to the present embodiment, the field plate electrode 17 is provided between the gate electrode 7 and the n ⁺ -type drain layer 1. By reducing the distance between adjacent field plate electrodes 17 along the Y direction, a depletion layer extending from each of the adjacent field plate electrodes 17 in the Y direction into the n ⁻ -type drift layer 1 is coupled in the OFF state. Therefore, the n ⁻ -type drift layer 1 is easily and fully depleted. As a result, the n-type impurity concentration of the n ⁻ -type drift layer 1 can be increased without causing a decrease in the breakdown voltage of the power semiconductor device. As a result, the on-resistance of the power semiconductor device is reduced.

Further, the gate electrode 7 is shielded from the n ⁺ -type drain layer 1 by the field plate electrode 17 of the source potential. For this reason, the gate-drain capacitance _CGD is greatly reduced.

Also in the power semiconductor device according to the present embodiment, the n ^{+ -type} semiconductor layer 8 is present on the surface of the n ⁻ -type drift layer 2, as in the power semiconductor device according to the first embodiment. The breakdown voltage on the surface of the p-type base layer 3 can be made lower than the bottom of the base layer 3. For this reason, avalanche tolerance improves. In addition, variations in the breakdown voltage are reduced.

(Fifth embodiment)
A power semiconductor device according to a fifth embodiment will be described with reference to FIG. FIG. 6 is a schematic perspective view of a main part of a power semiconductor device according to the fifth embodiment. Note that the same reference numerals or symbols are used for portions having the same configurations as those described in the fourth embodiment, and description thereof is omitted. Differences from the fourth embodiment will be mainly described.

In the power semiconductor device according to the present embodiment, an n ^{− type} electric field relaxation layer 20 is further provided between the n ^{− type} drift layer 2 and the n ^{+ type} drain layer 1 in the Z direction. The n ^{− type} electric field relaxation layer 20 is a semiconductor layer made of silicon. n ^- n-type impurity concentration of the form field relaxation layer 20, n ^- lower than the n-type impurity concentration in the form drift layer 2. p-type base layer 3, n ^- reaching form electric field relaxation layer 20 ^- the form drift layer 2 through the Z-direction n. Field plate trench 15, n ^- form drift layer 2 and the n ^- through the form field relaxation layer 20 reaches the ^{n +} -type drain layer 1.

  In the above point, the power semiconductor device according to the present embodiment is different from the power semiconductor device according to the fourth embodiment.

In the power semiconductor device according to the present embodiment, n ^- n-type impurity concentration of the form field relaxation layer 20, n ^- lower than the n-type impurity concentration in the form drift layer 2. For this reason, the depletion layer becomes easier to extend from the p-type base layer 3 to the n ⁻ -type electric field relaxation layer 20, so that the n ⁻ -type electric field relaxation layer 20 is more fully depleted than the n ⁻ -type drift layer 2. It becomes easy. Therefore, the breakdown voltage of the pn junction between the p-type base layer 3 and the n ⁻ -type electric field relaxation layer 20 at the bottom of the p-type base layer 3 is p-type base layer 3 and n ^{− at} the side of the p-type base layer 3. The breakdown voltage of the pn junction with the drift layer 2 is higher. As a result, in the power semiconductor device according to the present embodiment, since the occurrence of avalanche breakdown at the bottom of the p-type base layer 3 is further suppressed, the avalanche withstand capability is further increased as compared with the power semiconductor device according to the fourth embodiment. high.

Also in the power semiconductor device according to the present embodiment, the n ^{+ -type} semiconductor layer 8 is present on the surface of the n ⁻ -type drift layer 2, as in the power semiconductor device according to the first embodiment. The breakdown voltage on the surface of the p-type base layer 3 can be made lower than the bottom of the base layer 3. For this reason, avalanche tolerance improves. In addition, variations in the breakdown voltage are reduced.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1 n ^{+ type} drain layer 2 n ^{− type} drift layer 3 p type base layer 4 n ^{+ type} source layer 5 gate trench 6 gate insulating film 7 gate electrode 8 n ^{+ type} semiconductor layer 9 p ^{+ type} contact layer 10 first layer Insulating film 11 Gate wiring layer 12 Second interlayer insulating film 13 Source contact opening 14 n-type semiconductor layer 15 Field plate trench 16 Field plate insulating film 17 Field plate electrode 18 Field plate wiring layer 19 Third interlayer insulating film 20 n ⁻ Type electric field relaxation layer

Claims (12)

A first semiconductor layer of a first conductivity type having a first surface and a second surface opposite to the first surface;
A second semiconductor layer extending from the first surface of the first semiconductor layer in the first semiconductor layer along a first direction perpendicular to the first surface and parallel to the first surface; A first conductivity type second semiconductor layer having a first conductivity type impurity concentration lower than that of the first semiconductor layer, extending in the first semiconductor layer along the direction of
Second conductivity extending from the surface of the second semiconductor layer in the second semiconductor layer along the first direction and extending in the second semiconductor layer along the second direction. A third semiconductor layer of the shape;
Extending from the surface of the third semiconductor layer in the third semiconductor layer along the first direction and extending in the third semiconductor layer along the second direction; A first conductivity type fourth semiconductor layer having a first conductivity type impurity concentration higher than that of the second semiconductor layer;
The second semiconductor layer is provided on the surface of the second semiconductor layer so as to extend along the second direction and in contact with the first semiconductor layer and the second semiconductor layer. A fifth semiconductor layer of a first conductivity type having a higher first conductivity type impurity concentration;
Along the third direction, the fourth semiconductor layer extends through the third semiconductor layer and into the second semiconductor layer, and the fourth direction extends along the first direction. A gate electrode provided through a gate insulating film in a gate trench extending in the semiconductor layer, in the third semiconductor layer, and in the second semiconductor layer;
A first electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer;
A second electrode electrically connected to the second surface of the first semiconductor layer;
A sixth semiconductor layer of a second conductivity type extending along the second direction on the surface of the third semiconductor layer and having a second conductivity type impurity concentration higher than that of the third semiconductor layer;
A seventh semiconductor layer of a first conductivity type provided between the second semiconductor layer and the fifth semiconductor layer and extending along the second direction;
In the first direction, an eighth of the first conductivity type provided between the first semiconductor layer and the second semiconductor layer and having a first conductivity type impurity concentration lower than that of the second semiconductor layer. A semiconductor layer of
The second semiconductor layer extends in the first direction, and in the third direction, a field plate trench provided between the gate electrode and the first semiconductor layer has a field. A field plate electrode provided via a plate insulating film;
With
The sixth semiconductor layer is spaced apart from the gate insulating film via the third semiconductor layer in the second direction;
The sixth semiconductor layer is spaced apart from the second semiconductor layer via the third semiconductor layer in the third direction;
The seventh semiconductor layer has a higher impurity concentration of the first conductivity type than the second semiconductor layer, and a lower impurity concentration of the first conductivity type than the fifth semiconductor layer,
The field plate electrode is electrically connected to the first electrode;
The field plate electrode extends to the second surface side of the first semiconductor layer from the gate electrode,
The power semiconductor device, wherein the field plate electrode extends into the first semiconductor layer. A first semiconductor layer of a first conductivity type having a first surface and a second surface opposite to the first surface;
A second semiconductor layer extending from the first surface of the first semiconductor layer in the first semiconductor layer along a first direction perpendicular to the first surface and parallel to the first surface; A first conductivity type second semiconductor layer having a first conductivity type impurity concentration lower than that of the first semiconductor layer, extending in the first semiconductor layer along the direction of
Second conductivity extending from the surface of the second semiconductor layer in the second semiconductor layer along the first direction and extending in the second semiconductor layer along the second direction. A third semiconductor layer of the shape;
Extending from the surface of the third semiconductor layer in the third semiconductor layer along the first direction and extending in the third semiconductor layer along the second direction; A first conductivity type fourth semiconductor layer having a first conductivity type impurity concentration higher than that of the second semiconductor layer;
The second semiconductor layer is provided on the surface of the second semiconductor layer so as to extend along the second direction and in contact with the first semiconductor layer and the second semiconductor layer. A fifth semiconductor layer of a first conductivity type having a higher first conductivity type impurity concentration;
Along the third direction, the fourth semiconductor layer extends through the third semiconductor layer and into the second semiconductor layer, and the fourth direction extends along the first direction. A gate electrode provided through a gate insulating film in a gate trench extending in the semiconductor layer, in the third semiconductor layer, and in the second semiconductor layer;
A first electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer;
A second electrode electrically connected to the second surface of the first semiconductor layer;
A power semiconductor device comprising:   A sixth semiconductor layer of a second conductivity type extending along the second direction on the surface of the third semiconductor layer and having a second conductivity type impurity concentration higher than that of the third semiconductor layer; The power semiconductor device according to claim 2.   4. The power semiconductor device according to claim 3, wherein the sixth semiconductor layer is separated from the gate insulating film via the third semiconductor layer in the second direction.   The power semiconductor device according to claim 3, wherein the sixth semiconductor layer is adjacent to the gate insulating film in the second direction.   The power semiconductor device according to claim 3, wherein the sixth semiconductor layer is separated from the second semiconductor layer via the third semiconductor layer in the third direction. . A seventh semiconductor layer of a first conductivity type provided between the second semiconductor layer and the fifth semiconductor layer and extending along the second direction;
7. The semiconductor device according to claim 2, wherein the seventh semiconductor layer has a higher impurity concentration of the first conductivity type than that of the second semiconductor layer and a lower impurity concentration of the first conductivity type than that of the fifth semiconductor layer. The power semiconductor device according to claim 1.   In the first direction, an eighth semiconductor of the first conductivity type having a first conductivity type impurity concentration lower than that of the second semiconductor layer between the first semiconductor layer and the second semiconductor layer. The power semiconductor device according to claim 2, further comprising a layer.   The second semiconductor layer extends in the first direction, and in the third direction, a field plate trench provided between the gate electrode and the first semiconductor layer has a field. The power semiconductor device according to any one of claims 2 to 8, further comprising a field plate electrode provided via a plate insulating film.   The power semiconductor device according to claim 9, wherein the field plate electrode is electrically connected to the first electrode.   11. The power semiconductor device according to claim 9, wherein the field plate electrode extends to the second surface side of the first semiconductor layer from the gate electrode.   The power semiconductor device according to claim 11, wherein the field plate electrode reaches the first semiconductor layer.

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