JP2014056991A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which controls a tapered shape of an inlet port of a via hole.SOLUTION: A semiconductor device manufacturing method comprises: forming an insulator layer 20 on a conductive layer 18 on a substrate; forming a via hole 22 which pierces the insulator layer 20; forming a resist 32 in the via hole 22; forming a mask 33 on the insulator layer 20 and the on the resist 32; forming a resist 34 on the mask 33; patterning an opening for forming a wiring groove in the resist 34, that is, patterning the resist 34 so as to form a correction pattern 34a near a position right above the via hole 22; etching the mask 33 by using the resist 34 as a mask; etching the insulator layer 20 by using the mask 33 as a mask halfway down a depth to form a wiring groove; removing the resist 32 in the via hole 22; and embedding a conductor in the via hole 22 and in the wiring groove to form embedded wiring connected to the conductive layer 18.

Description

  The present invention relates to a method for forming a semiconductor device manufacturing method.

  Conventionally, miniaturization techniques have been used to improve the integration density of elements in a semiconductor device. With the miniaturization of semiconductor elements, the wiring that connects the elements is also miniaturized.

  In addition, semiconductor devices are required to have a low dielectric constant between wirings in order to improve integration density and reduce power consumption and speed.

  As a method for forming a wiring that meets such requirements, a damascene method is used in which a conductor is embedded in a groove formed of a low dielectric constant material, and an extra conductor is chemically mechanically polished to form a buried wiring. . In particular, a dual damascene method in which a via hole and a buried wiring trench are formed together has attracted attention from the viewpoint of simplifying the manufacturing process.

JP 2009-16619 A

  In the dual damascene method, a via hole is formed in an insulator layer, and then the insulator layer is etched to form a wiring groove. Then, the entrance portion of the via hole exposed in the wiring trench is shaved by etching to form a taper.

  The tapered shape of the via hole affects the ease of embedding a conductor in the via hole or the stress migration characteristics of the conductor embedded in the via hole.

  Therefore, when forming the wiring trench by etching, it is preferable that the taper at the entrance portion of the via hole can be controlled so as to be formed in a desired shape.

  An object of the present specification is to provide a method of manufacturing a semiconductor device capable of controlling the tapered shape of the via hole entrance.

  According to one embodiment of a method for manufacturing a semiconductor device disclosed in this specification, a step of forming an insulator layer on a conductive layer formed on a semiconductor substrate, and a step of forming a via hole penetrating the insulator layer Forming a first resist layer inside the via hole, forming a mask layer on the insulator layer and the first resist layer, and forming a second resist layer on the mask layer And a step of patterning an opening for forming a wiring groove in the second resist layer, wherein the second resist layer is formed so as to form a correction pattern close to a position directly above the via hole. A step of patterning, a step of etching the mask layer using the second resist layer as a mask, a step of removing the second resist layer, and the insulator using the mask layer as a mask Are etched halfway in the depth direction to form the wiring trench, to remove the first resist layer inside the via hole, and to embed a conductor in the via hole and the wiring trench, Forming a buried wiring connected to the conductive layer.

  According to one embodiment of the method for manufacturing a semiconductor device disclosed in this specification, the tapered shape of the via hole entrance can be controlled.

  The objects and advantages of the invention will be realized and obtained by means of the elements and combinations particularly pointed out in the appended claims.

  Both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention as claimed.

It is a figure which shows an example of the semiconductor device formed using one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 1) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 2) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 3) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 4) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 5) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 6) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 7) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 8) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 9) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 10) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 11) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the process (the 12) of one Embodiment of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the modification 1 of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the modification 2 of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the modification 3 of the manufacturing method of the semiconductor device disclosed to this specification. It is a figure which shows the modification 4 of the manufacturing method of the semiconductor device disclosed to this specification. (A) is a figure which shows the semiconductor device formed using the modification 5 of the manufacturing method of the semiconductor device disclosed to this specification, (B) is a figure which shows the correction pattern used for formation of wiring. It is.

  In the method for manufacturing a semiconductor device disclosed in this specification, a via hole and a wiring trench are formed together by using a dual damascene method.

  In the dual damascene method, a via hole is formed in an insulator layer, and then the insulator layer is etched to form a wiring groove. Then, the entrance portion of the via hole exposed in the wiring trench is shaved by etching to form a taper.

  Therefore, the tapered shape of the via hole entrance is affected by the etching conditions of the wiring trench.

  On the other hand, the wiring groove includes, for example, a wiring groove that forms a thin wiring for transmitting a signal and a wiring groove that forms a wiring having a large width for supplying power. Here, the width of the wiring means a dimension in a direction orthogonal to the longitudinal direction in which the wiring extends.

  When the wiring groove is dry-etched, for example, the opening is wide in the wide wiring groove, and the amount of etching gas supplied to the surface to be etched is large, so that the etching rate is increased. On the other hand, since the opening is narrow in the narrow wiring groove, the amount of etching gas supplied to the surface to be etched is relatively small, so that the etching rate is slow.

  In general, the etching conditions for simultaneously etching a narrow wiring groove and a thick wiring groove can be selected so that a narrow wiring groove can be formed with high accuracy.

  When the etching conditions are selected so that narrow wiring grooves can be formed with high precision, the portion of the via hole entrance exposed in the thick wiring grooves is etched, so the taper is large. Will be formed.

  Therefore, even when the etching condition is selected so that a narrow wiring groove can be formed with high accuracy, it is required to prevent the taper at the entrance of the via hole exposed in the thick wiring groove from being formed.

  The method for manufacturing a semiconductor device disclosed in this specification provides a method for solving such a problem.

  Hereinafter, a preferred embodiment of a method for manufacturing a semiconductor device disclosed in this specification will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the invention described in the claims and equivalents thereof.

  FIG. 1 is a diagram illustrating an example of a semiconductor device formed using an embodiment of a method for manufacturing a semiconductor device disclosed in this specification.

  The semiconductor device 10 includes a semiconductor substrate 11 and element layers 12 a and 12 b formed on the substrate 11. For example, a silicon wafer can be used as the substrate 11. The element layers 12a and 12b include elements such as transistors and diodes, for example.

  A first insulator layer 13 is disposed on the element layers 12a and 12b so as to cover the substrate 11.

  On the 1st insulator layer 13, the 2nd insulator layer 16 and the 3rd insulator layer 17 are arrange | positioned through the metal diffusion prevention layer 15. FIG. The second insulator layer 16 is made of, for example, a low-k material having a low dielectric constant.

  A plug 14 is disposed on the element layer 12a. The plug 14 is disposed in the first insulator layer 13. A first wiring layer 18 that is a conductive layer is disposed on the plug 14. The plug 14 electrically connects the first wiring layer 18 and the element layer 12a. The first wiring layer 18 is disposed in the second insulator layer 16 and the third insulator layer 17.

  A fourth insulator layer 20 and a fifth insulator layer 21 are disposed on the third insulator layer 17 with a metal diffusion prevention layer 19 interposed therebetween. For example, the fourth insulator layer 20 is formed of a low-k material having a low dielectric constant.

  A second wiring layer 26 is disposed on the first wiring layer 18 via a via contact 25. The via contact 25 and the second wiring layer 26 are electrically connected in the via hole 22 formed in the fourth insulator layer 20 and in the wiring groove 23 formed in the fourth insulator layer 20 and the fifth insulator layer 21. The body 24 is formed by being embedded. The cross section of the via hole 22 has a circular shape.

  The second wiring layer 26 is electrically connected to the first wiring layer 18 via the via contact 25.

  The via hole 22 has a taper portion 22 a at the coupling portion with the wiring groove 23. The shape of the tapered portion 22 a affects the ease of introduction when the conductor 24 is introduced into the via hole 22 when the via contact 25 is formed. Further, the shape of the tapered portion 22 a affects the stress migration characteristic of the via contact 25.

  Accordingly, the tapered portion 22a is preferably formed to have a desired shape from the viewpoint described above.

  In addition, as described above, when the etching conditions for forming the wiring groove are selected so that the narrow wiring groove can be formed with high accuracy, the portion of the entrance of the via hole exposed in the thick wiring groove is Since the amount to be etched increases, the taper is formed large.

  The second wiring layer 26 shown in FIG. 1 is an example of a thick wiring. In this specification, a thick wiring means a wiring whose wiring width is twice or more the diameter of the via hole, and a thin wiring means a wiring whose wiring width is less than twice the diameter of the via hole. To do.

  The semiconductor device 10 has a narrow wiring layer (not shown) formed on the fourth insulator layer 20 and the fifth insulator layer 21. This thin wiring layer (not shown) is formed using the dual damascene method together with the second wiring layer 26. When forming the second wiring layer 26 which is a thick wiring, the wiring groove 23 is formed using etching conditions selected so that a narrow wiring groove can be formed with high accuracy.

  In the manufacturing method of the semiconductor device disclosed in this specification, the etching condition of the entrance portion of the via hole exposed in the wide wiring groove is devised so as to be close to the thin wiring groove, and the taper portion is formed. Reduce the amount etched. As will be described in detail later, in FIG. 1, the convex portion 20a located in the vicinity of the entrance of the via hole 22 is devised so that the etching condition of the entrance portion of the via hole 22 is close to that of the narrow wiring groove. As a result.

  Next, with respect to the semiconductor device having the wiring shown in FIG. 1, an embodiment of a method for manufacturing a semiconductor device disclosed in this specification will be described below with reference to the drawings.

First, as shown in FIG. 2, a structure including element layers 12 a and 12 b, a plug 14, and a first wiring layer 18 is formed on a substrate 11. The first insulator layer 13 is formed by, for example, SiO _2. The metal diffusion preventing layer 15 is formed of SiC with a thickness of 30 nm, for example. The second insulator layer 16 is formed of SiOC with a thickness of 200 nm, for example. The third insulator layer 17 is formed of, for example, SiO ₂ with a thickness of 100 nm. The plug 14 is made of, for example, tungsten. The first wiring layer 18 is made of, for example, copper.

  Next, as shown in FIG. 3, on the first wiring layer 18 and the third insulator layer 17, a metal diffusion prevention layer 19, a fourth insulator layer 20, a fifth insulator layer 21, and a BARC ( Bottom Anti Reflective Coating) layer 30 is formed in order.

  Each layer is formed using, for example, a plasma CVD method.

The metal diffusion preventing layer 19 is made of SiC, for example, with a thickness of 50 nm. For example, the fourth insulator layer 20 is formed of SiOC with a thickness of 400 nm. For example, the fifth insulator layer 21 is formed of SiO ₂ with a thickness of 100 nm. The BARC layer 30 is made of SiN with a thickness of 50 nm, for example.

  Next, as shown in FIG. 4, a first resist layer 31 is formed on the BARC layer 30. Then, the first resist layer 31 is patterned to form a via hole using a photolithography method.

  Next, as shown in FIG. 5, the fourth insulator layer 20, the fifth insulator layer 21, and the BARC layer 30 are etched using the patterned first resist layer 31, so that the fourth insulator layer 20 A via hole 22 penetrating the fifth insulator layer 21 and the BARC layer 30 is formed. As this etching condition, it is preferable to use a condition that has a higher etching rate for etching the fourth insulator layer 20 than the metal diffusion preventing layer 19. The metal diffusion preventing layer 19 is exposed at the bottom of the via hole 22. Then, the first resist layer 31 is removed.

  Next, as shown in FIG. 6, a second resist layer 32 is embedded in the via hole 22 and formed on the BARC layer 30. The second resist layer 32 is formed of a resin using, for example, a spin coat method. The thickness of the second resist layer 32 on the BARC layer 30 can be set to 100 nm, for example.

Then, a mask layer 33 is formed on the second resist layer 32. The mask layer 33 is formed using, for example, a plasma CVD method. The mask layer 33 is formed of SiO ₂ with a thickness of 100 nm, for example.

  Then, the third resist layer 34 is formed on the mask layer 33.

  Next, as shown in FIG. 7, the third resist layer 34 is patterned in accordance with the position of the via hole 22 using a photolithography method, and an opening 35 for forming a wiring groove is formed in the third resist layer 34. Formed. The patterned third resist layer 34 has a wiring pattern 34 b of the second wiring layer 26.

  Here, as shown in FIG. 8, the third resist layer 34 is patterned so that a correction pattern 34 a close to the position directly above the via hole 22 is formed. The correction pattern 34 a is formed in the third resist layer 34 in the vicinity of the position P of the mask layer 33 corresponding to the via hole 22. 7 is a cross-sectional view taken along line XX in FIG.

  In the future, when the fourth insulator layer 20 is etched to form the wiring groove 23, the portion of the fourth insulator layer 20 located under the correction pattern 34a remains as a protrusion. This suppresses the diffusion of the etching gas to the portion where the via hole 22 is located. As a result, the etching conditions at the entrance of the via hole 22 can be brought into a state close to that of a narrow wiring trench.

  The width W of the correction pattern 34a is preferably 0.5 to 1.2 times, particularly 0.7 to 0.9 times, more preferably about 0.8 times the diameter of the via hole 22. Here, the width of the correction pattern 34a means the dimension in the radial direction R of the via hole 22 in the correction pattern 34a.

  If the width of the correction pattern 34a is smaller than 0.5 times the diameter of the via hole 22, the amount of the portion of the fourth insulator layer 20 located under the correction pattern 34a remaining as a convex portion is reduced, and the via hole 22 is reduced. The diffusion of the etching gas cannot be sufficiently suppressed with respect to the portion where is located.

  On the other hand, when the width of the correction pattern 34a is larger than 1.2 times the diameter of the via hole 22, the amount of the portion of the fourth insulator layer 20 located under the correction pattern 34a remaining as a convex portion increases. The second wiring layer 26 may be disconnected.

  The distance L between the correction pattern 34 a and the position P of the mask layer 33 corresponding to the position immediately above the via hole 22 is preferably less than or equal to half the diameter of the via hole 22. If the distance L between the correction pattern 34a and the position P is larger than half the diameter of the via hole 22, there is a possibility that the diffusion of the etching gas cannot be sufficiently suppressed with respect to the portion where the via hole 22 is located. The correction pattern 34a may be formed adjacent to the position P.

  Since the wiring pattern 34b is a pattern for forming a thick wiring groove, the wiring pattern 34b has a size larger than that in the case of forming a thin wiring groove. Therefore, the correction pattern 34a is formed when the size of the wiring groove 23, that is, the size of the wiring pattern 34b is equal to or larger than a predetermined dimension. Further, the dimension or shape of the correction pattern 34a can be set according to the dimension of the wiring pattern 34b. On the other hand, in the case of a wiring pattern that forms a thin wiring groove, a correction pattern is not formed.

  Next, as shown in FIG. 9, the mask layer 33 is etched using the patterned third resist layer 34 as a mask, and the second resist layer 32 is exposed. Then, the third resist layer 34 is removed. The portion of the mask layer 33 located under the correction pattern 34a remains on the second resist layer 32 as a convex portion 33a.

Next, as shown in FIG. 10, the second resist layer 32 is etched using the etched mask layer 33 as a mask, and the BARC layer 30 is exposed in the opening 35. As the etching gas, for example, O ₂ gas can be used. The second resist layer 32 is preferably etched so that a part of the second resist layer 32 remains in the via hole 22. The thickness of the second resist layer 32 remaining in the via hole 22 can be set to 200 nm, for example. In the opening 35, the portion 32a of the second resist layer 32 located under the convex portion 33a remains on the BARC layer 30.

  Next, as shown in FIGS. 11 and 12, using the etched mask layer 33 as a mask, the BARC layer 30 and the fifth insulator layer 21 are etched, and the fourth insulator layer 20 is halfway in the depth direction. Etched until. The depth to which the fourth insulator layer 20 is etched is determined according to the thickness of the second wiring layer 26. The depth at which the fourth insulator layer 20 is etched can be, for example, 200 nm.

  FIG. 12 shows a state in which the fourth insulator layer 20 is etched to a predetermined depth. FIG. 11 shows a state in the middle of etching the fourth insulator layer 20 to a predetermined depth.

  As shown in FIG. 11, the convex portion 33a that is the portion of the mask layer 33 located under the correction pattern 34a and the portion 32a of the second resist layer 32 that is located under the convex portion 33a are etched. Removed. However, the convex portion 33a and the portion 32a of the second resist layer 32 located under the convex portion 33a delay the etching of the portion of the fourth insulator layer 20 located under the convex portion 33a. Accordingly, the portion of the fourth insulator layer 20 located under the correction pattern 34a is etched shallower than the portion of the fourth insulator layer 20 not located under the correction pattern 34a. A projecting portion 20 a that projects into 35 is formed.

  In the opening portion 35, the entrance portion of the via hole 22 is surrounded by the convex portion 20 a and one wall surface of the opening portion 35, and is in the same state as being exposed in the narrow wiring groove. . The convex portion 20 a suppresses the diffusion of the etching gas to the entrance portion of the via hole 22. As a result, the etching rate of the entrance portion of the via hole 22 can be reduced as compared with the case where there is no protrusion 20a. Therefore, by adjusting the size or shape of the correction pattern 34a, the shape of the tapered portion 22a at the entrance of the via hole 22 can be controlled without changing the etching conditions.

  As shown in FIG. 12, as the etching of the opening 35 proceeds, the convex portion 20a is also etched, and the height of the convex portion 20a is lowered. Therefore, when the conductor is embedded in the wiring groove 23, the convex portion 20a does not disturb the conductivity of the wiring layer. The mask layer 33 is removed by this etching.

Next, as shown in FIG. 13, the second resist layer 32 on the BARC layer 30 and the second resist layer 32 inside the via hole 22 are removed by etching. For this etching, plasma etching using O ₂ and CF ₄ gas can be used. When the mask layer 33 remains on the second resist layer 32, the mask layer 33 is removed by this etching.

  Subsequently, the BARC layer 30 on the fifth insulator layer 21 and the portion of the metal diffusion prevention layer 19 exposed in the via hole 22 are removed by etching to form a wiring groove 23.

A seed layer (not shown) is formed in the via hole 22 and the wiring groove 23. The seed layer is formed using, for example, Ta having a thickness of 25 nm and a thickness of 100 nm. In addition, before forming the seed layer, the via hole 22 and the wiring groove 23 may be pretreated using H ₂ plasma or H ₂ annealing.

  Next, a conductor 24 is embedded in the via hole 22 and the wiring groove 23. To embed the conductor 24, for example, an electroplating method can be used. As the conductor 24, for example, copper, aluminum, silver or the like can be used. Then, by using a chemical mechanical polishing method, the excess conductor 24 is polished until the fifth insulator layer 21 is exposed, and a second wiring layer 26 that is an embedded wiring connected to the first wiring layer 18 is formed. The In this way, the semiconductor device 10 having the second wiring layer 26 is formed as shown in FIG.

  According to the manufacturing method of the semiconductor device of the present embodiment described above, the shape or shape of the tapered portion 22a at the entrance of the via hole 22 is controlled without changing the etching conditions by adjusting the size or shape of the correction pattern 34a. Can do.

  Next, a modified example of the manufacturing method of the semiconductor device of the present embodiment described above will be described below with reference to the drawings.

  FIG. 14 is a diagram illustrating a first modification of the method for manufacturing a semiconductor device disclosed in this specification.

  As shown in FIG. 14, in the process shown in FIG. 8 of the first modification, the correction pattern 34 a is formed so as to continuously surround the position P of the mask layer 33 corresponding to the position directly above the via hole 22.

  In the process shown in FIGS. 11 and 12 of the modified example 1, since the convex portion 20a formed by the correction pattern 34a is formed so as to surround the entrance of the via hole 22, etching is performed on the entrance portion of the via hole 22. Gas diffusion can be further suppressed.

  FIG. 15 is a diagram illustrating a second modification example of the method for manufacturing a semiconductor device disclosed in this specification.

  As shown in FIG. 15, in the process shown in FIG. 8 of the modified example 2, four correction patterns 34 a are formed so as to surround the four sides of the position P of the mask layer 33 corresponding to the position directly above the via hole 22. .

  Modification 2 also has the same effect as Modification 1 described above.

  FIG. 16 is a diagram illustrating a third modification of the method for manufacturing a semiconductor device disclosed in this specification.

  In the process shown in FIG. 5 of the modified example 3, three via holes 22 are formed.

  Then, as shown in FIG. 16, in the process shown in FIG. 8 of the modified example 3, the correction pattern 34 a continuously surrounds the position P of the mask layer 33 corresponding to the position immediately above the three via holes 22. Formed.

  11 and 12 of the modified example 3, the convex portion 20a formed by the correction pattern 34a is formed so as to surround the entrances of the three via holes 22. Accordingly, the entrance portions of the three via holes 22 are close to being exposed in the narrow wiring grooves, so that the diffusion of the etching gas can be suppressed with respect to the entrance portions of the via holes 22.

  Thus, when a plurality of via holes are arranged, the correction pattern 34 a may be formed so as to surround the position P of the mask layer 33 corresponding to the position directly above the plurality of via holes 22.

  FIG. 17 is a diagram illustrating a fourth modification of the method for manufacturing a semiconductor device disclosed in this specification.

  In the process shown in FIG. 5 of Modification Example 4, a plurality of via holes 22 are formed.

  Then, as shown in FIG. 17, in the process shown in FIG. 8 of Modification Example 4, the correction pattern 34 a is formed close to each position P of the mask layer 33 corresponding to the position directly above the plurality of via holes 22. The Further, in the step shown in FIG. 8 of the modified example 4, as shown in FIG. 17, a plurality of correction patterns 34a are periodically formed in addition to the position of the mask layer 33 corresponding to the position directly above the via hole 22. Is done.

  In the process shown in FIGS. 11 and 12 of the modified example 4, since the convex portion 20a formed by the correction pattern 34a is formed close to the entrance of the via hole 22, the etching gas is applied to the entrance portion of the via hole 22. Diffusion can be further suppressed.

  Further, in the process shown in FIGS. 11 and 12 of the modified example 4, the etching of the region sandwiched between the convex portions 20a and the convex portions 20a formed by the periodically arranged correction patterns 34a is performed with a narrow wiring width. It approaches the etching state in the groove. Therefore, the entire wiring trench is etched under the etching conditions in the narrow wiring trench.

  In this way, by forming the correction pattern 34a other than the position of the mask layer 33 corresponding to the position directly above the via hole 22, the etching conditions in the wiring trench can be controlled locally or entirely.

  FIG. 18A is a diagram illustrating a semiconductor device formed by using Modification Example 5 of the semiconductor device manufacturing method disclosed in this specification, and FIG. 18B is a diagram illustrating a correction used for forming a wiring. It is a figure which shows a pattern.

  A semiconductor device 50 shown in FIG. 18A includes three first wiring layers 18a, 18b, and 18c. The three first wiring layers 18 a, 18 b and 18 c are arranged in the second insulator layer 16 and the third insulator layer 17 with a space therebetween.

  The first wiring layer 18a is electrically connected to the second wiring layer 26 via the via contact 25 as in the above-described embodiment.

  The first wiring layer 18 c is electrically connected to the second wiring layer 26 via the via contact 28. The first wiring layer 18c is electrically connected to the element layer 12b through the plug 14b.

  Here, when the tapered portion 22a of the via hole 22 is formed large as shown by the solid line T in FIG. 18A, the distance between the via contact 25 and the first wiring layer 18b becomes closer, and thus a short circuit may occur. is there. Here, it is assumed that the first wiring layer 18a and the first wiring layer 18b are used at different potentials.

  Therefore, as shown in FIG. 18B, in the step shown in FIG. 5 of the modified example 5, the position P is close to the position P of the mask layer 33 corresponding to the position directly above the via hole 22. A correction pattern 34a is formed in a portion on the one wiring layer 18b side.

  In the process shown in FIGS. 11 and 12 of the modified example 5, the convex portion 20a formed by the correction pattern 34a suppresses the diffusion of the etching gas and prevents the tapered portion 22a of the via hole 22 from being formed large. .

  Here, in order to prevent a short circuit between the via contact 25 and the first wiring layer 18b, the distance between the via hole 22 and the first wiring layer 18b is used as a criterion for determining the necessity of forming the correction pattern 34a. Can be used.

  As shown in FIG. 18B, the distance between the via hole 22 and the first wiring layer 18b is L1 in plan view. When the distance L1 is smaller than a predetermined reference value, it is determined that the correction pattern 34a is formed.

  On the other hand, as shown in FIG. 18B, when the distance L2 between the via hole 27 and the first wiring layer 18b is larger than a predetermined reference value, the mask layer 33 corresponding to the position directly above the via hole 27. It is determined that it is not necessary to form a correction pattern in a portion on the first wiring layer 18b side with respect to the position Q in the vicinity of the position Q.

  In the present invention, the wiring and the semiconductor device manufacturing method of the above-described embodiments can be appropriately changed without departing from the gist of the present invention. In addition, the configuration requirements of one embodiment can be applied to other embodiments as appropriate.

  All examples and conditional words mentioned herein are intended for educational purposes to help the reader deepen and understand the inventions and concepts contributed by the inventor. All examples and conditional words mentioned herein are to be construed without limitation to such specifically stated examples and conditions. Also, such exemplary mechanisms in the specification are not related to showing the superiority and inferiority of the present invention. While embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions or modifications can be made without departing from the spirit and scope of the invention.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Board | substrate 12a, 12b Element layer 13 1st insulator layer 14 Plug 15 Metal diffusion prevention layer 16 2nd insulator layer 17 3rd insulator layer 18 1st wiring layer 19 Metal diffusion prevention layer 20 4th insulator Layer 20a Convex part 21 Fifth insulator layer 21a Convex part 22 Via hole (via)
22a taper portion 23 wiring groove 24 conductor 25 via contact 26 second wiring layer 30 BARC layer 31 first resist layer 32 second resist layer (first resist layer)
33 mask layer 33a convex portion 34 third resist layer (second resist layer)
34a Correction pattern 34b Wiring pattern 35 Opening

Claims (9)

Forming an insulator layer on a conductive layer formed on a semiconductor substrate;
Forming a via hole penetrating the insulator layer;
Forming a first resist layer inside the via hole;
Forming a mask layer on the insulator layer and the first resist layer;
Forming a second resist layer on the mask layer;
Patterning an opening for forming a wiring groove in the second resist layer, patterning the second resist layer so as to form a correction pattern close to a position directly above the via hole; ,
Etching the mask layer using the second resist layer as a mask;
Removing the second resist layer;
Etching the insulator layer halfway in the depth direction using the mask layer as a mask to form the wiring groove;
Removing the first resist layer inside the via hole;
A step of burying a conductor in the via hole and the wiring groove to form a buried wiring connected to the conductive layer;
A method for manufacturing a semiconductor device, comprising: The step of patterning the second resist layer is characterized by patterning the second resist layer so as to form the correction pattern when the size of the opening of the second resist layer is a predetermined dimension or more. A method for manufacturing a semiconductor device according to claim 1. The step of forming the wiring groove includes
The portion of the mask layer located under the correction pattern is removed, and the portion of the insulator layer located under the correction pattern is not located under the correction pattern. 3. The method of manufacturing a semiconductor device for wiring according to claim 1, wherein etching is performed shallower than a portion of the insulator layer.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the width of the correction pattern is 0.5 to 1.2 times the diameter of the via.   5. The method of manufacturing a semiconductor device according to claim 1, wherein a distance between the correction pattern and a position directly above the via hole is equal to or less than a half of a diameter of the via hole.   6. The method of manufacturing a semiconductor device according to claim 1, wherein in the patterning of the second resist layer, the correction pattern is formed so as to surround a position immediately above the via hole. Method. The step of forming the via hole forms a plurality of the via holes,
The method of manufacturing a semiconductor device according to claim 1, wherein in the patterning of the second resist layer, the correction pattern is formed so as to surround positions directly above the plurality of via holes.   The method of manufacturing a semiconductor device according to claim 1, wherein in the patterning of the second resist layer, the correction pattern is formed in addition to a position close to a position immediately above the via hole. .   The method of manufacturing a semiconductor device according to claim 8, wherein the correction pattern is periodically formed.

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