JP2014056908A - Bonding tool and semiconductor device manufacturing method using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bonding tool which enabled mounting without voids when using a bonding tool larger than an area of a semiconductor chip, and provide a semiconductor device manufacturing method.SOLUTION: A bonding tool comprises a semiconductor chip sucking surface which includes a center part having thermal conductivity of not less than 50 W/mK and not more than 1000 W/mK and a peripheral part having thermal conductivity of less than 50 W/mK, in which the thermal conductivity of the center part is larger than thermal conductivity of the peripheral part by 50 W/mK and over. And provided is a semiconductor device manufacturing method using the bonding tool.

Description

  The present invention relates to a bonding tool used when thermocompression bonding a semiconductor chip and a circuit board and a method for manufacturing a semiconductor device using the bonding tool.

  In recent years, with the miniaturization and high density of semiconductor devices, flip chip mounting as a method of mounting a semiconductor chip on a circuit board, and further three-dimensional stack mounting in which three-dimensional stacking is performed by through electrodes penetrating the chip are rapidly performed. It is spreading. As a method for ensuring the connection reliability of the joining portion of the semiconductor chip, after bonding the bump formed on the semiconductor chip and the electrode pad of the circuit board, the liquid sealing adhesion is performed in the gap between the semiconductor chip and the circuit board. It has been a common method to inject and cure the agent.

  Recently, in order to improve the connection reliability of the joint portion, bonding is performed by interposing a thermosetting adhesive paste or adhesive film between the bump formed on the semiconductor chip and the pad electrode of the wiring board. It is being considered. Adhesive films are superior in terms of controlling the amount of adhesive, minimizing the mounting area by controlling the amount of fillets, and removing voids that impair reliability. As a mounting method using such an adhesive film, after temporarily bonding an adhesive sheet to a semiconductor wafer with bumps, the semiconductor wafer is made into a semiconductor chip with an adhesive film by dicing, and this semiconductor chip is flip-chip connected to a circuit board, A method of performing electrical bonding and resin sealing at the same time, or a method of bonding a semiconductor chip by thermocompression bonding after adhering an adhesive film to a wiring board is used (see Patent Documents 1 and 2). Further, in such a mounting method, use of a bonding tool larger than that of the semiconductor chip has been studied for the purpose of flattening the upper surface of the fillet at the outer peripheral portion of the semiconductor chip (see Patent Document 3).

Japanese Patent No. 3995022 JP 2007-305812 A JP 2012-44071 A

  However, when using a bonding tool that is larger than the semiconductor chip, the adhesive that protrudes outside the semiconductor chip is cured by the heat of the bonding tool and the flow path is blocked, so that voids generated at the bottom of the semiconductor chip during bonding In some cases, it may be difficult to eliminate the excess adhesive film.

  In the present invention, the adsorption surface of the semiconductor chip is composed of a central part having a thermal conductivity of 50 W / mK or more and 1000 W / mK or less, and an outer peripheral part having a thermal conductivity of less than 50 W / mK, and the thermal conductivity of the central part. Is a bonding tool characterized in that is larger than the thermal conductivity of the outer peripheral portion by 50 W / mK or more, and a method of manufacturing a semiconductor device using the same.

  By using the bonding tool of the present invention, it becomes possible to manufacture a semiconductor device without voids at a high yield.

Illustration of the bonding tool of the present invention Explanatory drawing of thermocompression bonding process using a general bonding tool Explanatory drawing of the thermocompression bonding process using the bonding tool of the present invention Explanatory drawing of the bonding tool used in Examples 1-4 Illustration of bonding tool used in Comparative Examples 1 and 2

  In the bonding tool of the present invention, the suction surface of the semiconductor chip is composed of a central portion having a thermal conductivity of 50 W / mK or more and 1000 W / mK or less, and an outer peripheral portion having a thermal conductivity of less than 50 W / mK, The thermal conductivity is 50 W / mK or more larger than the thermal conductivity of the outer peripheral portion.

  FIG. 1 is an explanatory example of the bonding tool of the present invention. 1a is a plan view of the bonding tool viewed from the suction surface of the semiconductor chip, and 1b is a cross-sectional view of the bonding tool taken along line A. FIG. It has a semiconductor chip suction surface 12 and a mounting surface 13 to a bonding head equipped with a heater or the like. The bonding tool of the present invention is made of a material in which the adsorption surface of the semiconductor chip has two types of thermal conductivity, the central portion 11 has a thermal conductivity of 50 W / mK to 1000 W / mK, and the outer peripheral portion 12 has a thermal conductivity of 50 W / mK. And the thermal conductivity of the central portion is 50 W / mK or greater than the thermal conductivity of the outer peripheral portion. By setting it as such a structure, a temperature difference arises in the center part and outer peripheral part of a semiconductor chip adsorption surface, and the temperature of an outer peripheral part becomes low. For this reason, as shown in FIG. 3, the adhesive that protrudes to the outside of the semiconductor chip is hard to be cured, and voids are easily removed to the outside of the semiconductor chip. On the other hand, the semiconductor chip can be sufficiently heated, and melting and joining of the solder progresses and a good mounting state is obtained. When a general bonding tool is used, the adhesive protruding outside the semiconductor chip is cured by the heat of the bonding tool, so that the void cannot move to the outside of the semiconductor chip and tends to stay below the chip (FIG. 2). ).

  The shape of the central portion 11 is generally a rectangle that is similar to a semiconductor chip to be bonded, but is arbitrarily designed depending on the arrangement of bumps. The length of each side of the central portion 11 is not particularly limited, but is generally 90% or more and less than 100% of the length of each side corresponding to the semiconductor chip. Although it depends on the arrangement of the bumps, if it is 90% or more, heat can be sufficiently transferred to and connected to the bumps at the end of the chip. Moreover, by setting it to less than 100%, the adhesive protruding outside the semiconductor chip is hardly cured by the heat of the bonding tool, and voids are easily removed.

  For the central portion 11, a known material having a thermal conductivity of 50 W / mK or more and 1000 W / mK or less can be used. The higher the thermal conductivity of the central portion 11, the better. However, a general solid material that can be used for the application is 1000 W / mK or less in terms of cost and ease of processing. Examples include, but are not limited to, silicon carbide, aluminum nitride, cemented carbide (WC-Co alloy), and the like. The thermal conductivity is more preferably 100 W / mK or more from the viewpoint of bonding reliability.

  The outer peripheral part 12 is generally arranged so as to surround the central part 11, and the width x is generally about 0.1 mm to 5 mm.

  A known material having a thermal conductivity of less than 50 W / mK can be used for the outer peripheral portion 12. Examples include stainless steel, zirconia, silicon nitride, polytetrafluoroethylene (hereinafter referred to as PTFE), tetrafluoroethylene / perfluoroalkyl vinyl ether copolymer (hereinafter referred to as PFA), polyvinylidene fluoride (hereinafter referred to as PTFE). , PVDF.) And the like, but not limited thereto. The thermal conductivity of the outer peripheral portion 12 is more preferably 5 W / mK or less from the viewpoint of void removal. In addition, the use of a fluororesin is more preferable because adhesion of the adhesive to the bonding tool can be prevented.

  By using a material having low thermal conductivity for the outer peripheral portion 12, the tool temperature of the outer peripheral portion can be lowered with respect to the central portion. This prevents the adhesive that protrudes from the outside of the semiconductor chip from being cured by the heat of the bonding tool, and ensures the fluidity of the adhesive and voids, resulting in voids generated between the semiconductor chip and the circuit board, Excess adhesive is removed out of the semiconductor chip.

  You may fix the member of the outer peripheral part 12 to a bonding tool by methods, such as screwing.

  Hereinafter, a method for manufacturing a semiconductor device using the bonding tool of the present invention will be described.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a circuit board having electrodes and a semiconductor chip having bumps are thermocompression bonded, and is applied to the electrode part of the circuit board and / or the bump part of the semiconductor chip. Have solder,
(A) Laminating a thermosetting adhesive film on the surface of the circuit board having the electrodes,
(B) Using the bonding tool described above, a step of thermocompression bonding the bump side surface of the semiconductor chip with the electrode side surface of the circuit board, and solder bonding and curing of the adhesive film;
In this order in a semiconductor device manufacturing method.

  In the method of manufacturing a semiconductor device according to the present invention, the electrode portion of the circuit board and / or the bump portion of the semiconductor chip has solder, whereby the electrode portion of the circuit board and the bump portion of the semiconductor chip are electrically connected. The

  Next, (A) the process of laminating a thermosetting adhesive film on the surface of the circuit board having electrodes will be described. As a laminating method, a thermosetting adhesive film is formed on a plastic film to form a laminate, which is cut into a desired shape and size, placed at a desired location on a circuit board, and then laminated. Just do it. The thermosetting adhesive film can be formed into a desired shape and size by punching with a punch mold or cutting with a pinnacle blade, a Thomson blade or the like. Moreover, the well-known method described in Unexamined-Japanese-Patent No. 2010-251652, Unexamined-Japanese-Patent No. 2010-251346, etc. can also be used. In order to completely cover the mounting position of the semiconductor chip, the pasting size of the thermosetting adhesive film is preferably equal to or larger than the size of the semiconductor chip. It is preferable to laminate so as not to generate a void between the thermosetting adhesive film and the circuit board, and it is preferable to laminate in a vacuum. As an apparatus capable of laminating in a vacuum, for example, there is a vacuum pressure laminator (manufactured by Nichigo Morton, CVP300, etc.). The laminating temperature is preferably 60 ° C. or higher from the viewpoint of the ability to follow the unevenness of the bonded surface. Moreover, in order to prevent hardening of the adhesive film at the time of affixing, it is preferable that affixing temperature shall be 100 degrees C or less. The pressure at the time of attachment is preferably 0.1 MPa or more so as to follow the unevenness of the substrate. Finally, the plastic film is peeled off to obtain a circuit board on which the thermosetting adhesive film is laminated.

  Next, (B) using the above-described bonding tool, the process of solder bonding and curing of the adhesive film by thermocompression bonding the bump-side surface of the semiconductor chip with the electrode-side surface of the circuit board will be described. To do.

  In the thermocompression bonding process, it is common to use a bonding apparatus such as a flip chip bonder. The thermocompression bonding process may be performed separately in a temporary crimping process in which temporary fixing is performed at a temperature equal to or lower than the solder melting point and a final crimping process in a temperature equal to or higher than the solder melting point, or only the final crimping process may be performed. . Moreover, when performing the temporary press-bonding process and the main press-bonding process separately, the temporary press-bonding process and the main press-bonding process may be performed continuously, or after the temporary press-bonding process is performed, the temperature is returned to room temperature. You may go.

  The temperature in the temporary press bonding step is preferably in the temperature range of 80 to 180 ° C. Moreover, the pressure at the time of temporary pressure bonding has the preferable range of 0.01-10 MPa. The time is preferably 0.1 seconds to several minutes. Temporary pressure bonding may be performed under normal pressure, or may be performed in a vacuum in order to prevent entrapment of bubbles and the like.

  In the main press-bonding step, a temperature of 200 ° C. to 400 ° C. is applied to make the insulating resin composition a cured film, and the solder bumps are melted to perform bonding. This heat treatment is performed by selecting a temperature and raising the temperature stepwise, or selecting a certain temperature range and continuously raising the temperature for 1 second to several minutes. As an example, the temperature is raised from 100 ° C. to 250 ° C. in 5 seconds, and heat treatment is performed at 250 ° C. for 20 seconds. Alternatively, a method such as linearly raising the temperature from room temperature to 300 ° C. over 30 seconds can be mentioned. At this time, the heating temperature is preferably 200 ° C. or higher and 350 ° C. or lower, and more preferably 220 ° C. or higher and 280 ° C. or lower. Moreover, the pressure at the time of this press-fit has the preferable range of 0.01-10 MPa. The heat treatment may be performed under normal pressure or in a vacuum. Moreover, in order to prevent the oxidative deterioration by air, you may implement in nitrogen atmosphere.

  In the thermocompression bonding process, after confirming the alignment mark formed on the semiconductor chip and the alignment mark on the substrate so that the connection positions of the bumps on the semiconductor chip and the electrode pads on the circuit board match, the mounting position is mechanically corrected. Crimp.

  The semiconductor device referred to in the present invention refers to all devices that can function by utilizing the characteristics of semiconductor elements. An electro-optical device in which a semiconductor chip is connected to a substrate, a semiconductor circuit substrate, and electronic components including these are all semiconductor devices. include. Further, a semiconductor device includes a semiconductor chip in which semiconductor chips in which connection terminals such as pads and bumps are formed on both sides of silicon having through electrodes TSV (through silicon vias) are three-dimensionally stacked.

  Examples of the semiconductor chip used in the method for manufacturing a semiconductor device of the present invention include an integrated circuit, a large-scale integrated circuit, a transistor, a thyristor, and a diode, and are not particularly limited. Semiconductors such as silicon (Si) and germanium (Ge), and compound semiconductor chips such as gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), and silicon carbide (SiC) can also be used. Bumps are formed on the semiconductor chip used in the manufacturing method of the present invention. Copper, gold, nickel, solder or the like is used for the bump. In order to achieve both the narrow pitch of the bump and the reliability, a metal pillar, particularly a bump in which solder is formed on a copper pillar is preferable. The material of the solder is not particularly limited, but it is preferable to use a lead-free solder such as SnAgCu-based, SnCu-based, SnAg-based, SnAgCuBi-based, SnZnBi-based, SnAgInBi-based from the viewpoint of influence on the human body and the environment. Moreover, it is preferable that the shape of the solder is hemispherical from the viewpoint that the resin or filler is difficult to bite between the bump and the pad.

  It is preferable that the bumps on the semiconductor chip have all the same height, and the variation in the bump height is preferably 2 μm or less.

  As a substrate used in the method for manufacturing a semiconductor device of the present invention, a silicon substrate, a semiconductor chip or semiconductor wafer having a TSV structure, ceramics, a compound semiconductor, an organic circuit substrate, an inorganic circuit substrate, and a circuit on these substrates are used. The one in which the constituent materials are arranged. Examples of organic circuit boards include glass-based copper-clad laminates such as glass cloth / epoxy copper-clad laminates, composite copper-clad laminates such as glass nonwoven fabrics / epoxy copper-clad laminates, polyetherimide resin substrates, Examples include heat-resistant / thermoplastic substrates such as ether ketone resin substrates and polysulfone resin substrates, polyester copper-clad film substrates, and polyimide copper-clad film substrates. Examples of the inorganic circuit board include ceramic substrates such as an alumina substrate, an aluminum nitride substrate, and a silicon carbide substrate, and metal substrates such as an aluminum base substrate and an iron base substrate.

  Examples of circuit constituent materials include conductors containing metals such as silver, gold, copper, and aluminum, resistors containing inorganic oxides, low dielectrics and resins containing glass materials and / or resins, etc. And high dielectric materials containing high dielectric constant inorganic particles, insulators containing glass-based materials, and the like.

  The substrate used in the method for manufacturing a semiconductor device of the present invention has electrode pads corresponding to the positions of the bumps of the semiconductor chip. The electrode pad may be flat or may be a so-called pillar-shaped (columnar) protrusion. Moreover, any of polygons, such as a circle, a rectangle, and an octagon, may be sufficient. There are no particular restrictions on the material of the electrode pad, and metals that can be generally used in semiconductor devices such as aluminum, copper, titanium, tungsten, chromium, nickel, gold, tin, solder, and alloys using them can be used. A plurality of metals can be laminated. As with the bump, the electrode pad preferably has a height variation of 2 μm or less.

  The thermosetting adhesive film used in the present invention may be composed only of an insulating resin, or may contain other components in the insulating resin. A plurality of types of insulating resins may be mixed. As the insulating resin, a polyimide resin, an epoxy resin, an acrylic resin, a phenoxy resin, a polyethersulfone resin, or the like can be used, but is not limited thereto. You may further contain hardening agents, such as an epoxy resin, hardening accelerators, such as imidazole and an acid anhydride. A well-known thing can be used as a hardening | curing agent and a hardening accelerator.

  The thermosetting adhesive film preferably contains an insulating inorganic filler from the viewpoint of insulation reliability and reliability with respect to temperature cycles. As the insulating inorganic filler, silica, silicon nitride, alumina, aluminum nitride, titanium oxide, titanium nitride, barium titanate, or the like can be used.

  Moreover, a crosslinking agent, surfactant, a dispersing agent, etc. may be contained in the thermosetting adhesive film as needed. The thermosetting adhesive film may have photosensitivity. In the case of having photosensitivity, after forming a film or attaching a sheet, pattern processing can be performed by exposure and development to open a necessary portion such as a bump forming portion.

  Examples of the thermosetting adhesive film used in the present invention include those disclosed in Japanese Patent Application Laid-Open No. 2004-319823, Japanese Patent Application Laid-Open No. 2008-94870, Japanese Patent No. 3995022, Japanese Patent Application Laid-Open No. 2009-262227, and the like. An agent resin composition can be used.

  The thickness of the thermosetting adhesive film is not limited and can be arbitrarily adjusted according to the specifications of the semiconductor device to be manufactured, but is generally about 5 μm to 100 μm.

  In the method for manufacturing a semiconductor device of the present invention, the shape of the center portion of the bonding tool is rectangular, and the length of each side of the center portion is 90% or more of the length of each corresponding side of the semiconductor chip, Preferably it is less than 100%. Although it depends on the arrangement of the bumps, if it is 90% or more, heat can be sufficiently transferred to and connected to the bumps at the end of the chip. Moreover, by setting it to less than 100%, the adhesive protruding outside the semiconductor chip is hardly cured by the heat of the bonding tool, and voids are easily removed.

  Moreover, in order to prevent adhesion of the adhesive to the bonding tool, a deposition film may be used. Although there is no restriction | limiting in particular in a deposition film, Metal foil, such as heat resistant resin films, such as a fluororesin film and a polyimide film, aluminum foil, copper foil, etc. can be used.

  In the method for manufacturing a semiconductor device of the present invention, additional curing may be performed after the above steps. The conditions for the additional curing can be arbitrarily set according to the characteristics of the thermosetting adhesive film to be used.

  Hereinafter, although the bonding tool of this invention and the manufacturing method of a semiconductor device using the same are demonstrated more concretely, this invention is not limited to these.

  Hereinafter, the present invention will be described with reference to examples and the like, but the present invention is not limited to these examples. The materials and evaluation methods used in Examples 1 to 4 and Comparative Examples 1 and 2 are shown below.

<Bonding tool>
The bonding tools 1 and 2 of the present invention shown in FIG. 4 and the general bonding tool 3 shown in FIG. 5 were used. In FIGS. 4 and 5, the upper part of each figure shows a cross-sectional view, and the lower part of each figure shows a plan view. The thermal conductivity of the stainless steel SUS304 used for the bonding tool 1 is 16.7 W / mK, the thermal conductivity of the fluororesin (PTFE) used for the bonding tool 2 is 0.25 W / mK, and the bonding tools 1 to 3 The thermal conductivity of aluminum nitride is 170 W / mK.

<Semiconductor chip structure>
An aluminum wiring having a thickness of 1 μm is formed on an oxide film on a silicon substrate, chromium is formed in an opening of a silicon nitride insulating film having a thickness of 1 μm formed thereon, a post having a height of 10 μm and a copper of 5 μm. A semiconductor chip on which the solder (SnAg) was formed was produced. The bump diameter is 25, 30, 35, 40 μm, and the bump pitch is 75, 80, 85, 90 μm for each bump diameter. Further, 138, 150, 162, and 174 bumps are formed for each pitch. The aluminum wiring is patterned so that the connection resistance can be measured for each bump structure after mounting on the substrate. The chip size is 7 mm × 7 mm, and the chip thickness is 100 μm.

<Board>
As a substrate, an aluminum wiring having a thickness of 1 μm is formed on an oxide film of a silicon substrate (thickness of 100 μm), and chromium is formed in an opening of a silicon nitride insulating film having a thickness of 1 μm formed thereon. A chip having an electrode pad in which nickel and gold (film thickness: 1 μm) were formed on copper (film thickness: 5 μm) formed on was prepared. The electrode pads are all formed so as to correspond to the bumps of the semiconductor chip, and the electrode pads have the same diameter. By mounting the semiconductor chip, a daisy chain is formed, and the junction resistance between the bump and the electrode pad can be measured through the lead electrode. The substrate size is 12 mm × 12 mm, the substrate thickness is 100 μm, and a 2 mm square lead electrode pad for measuring the conduction resistance of the daisy chain is formed in a region where no chip is mounted.

<Thermosetting adhesive film>
Synthesis Example 1 Synthesis of Organic Solvent-Soluble Polyimide Under a nitrogen stream, 2,2-bis (3-amino-4-hydroxyphenyl) hexafluoropropane (hereinafter referred to as BAHF) 24.54 g (0.067 mol), 1 , 3-bis (3-aminopropyl) tetramethyldisiloxane (hereinafter referred to as SiDA) 4.97 g (0.02 mol), and 1.86 g (0.02 mol) of aniline as an end-capping agent were added N- It was dissolved in 80 g of methylpyrrolidone (hereinafter referred to as NMP). Here, 31.02 g (0.1 mol) of bis (3,4-dicarboxyphenyl) ether dianhydride (hereinafter referred to as ODPA) was added together with 20 g of NMP and reacted at 20 ° C. for 1 hour, and then at 50 ° C. Stir for 4 hours. Thereafter, 15 g of xylene was added, and the mixture was stirred at 180 ° C. for 5 hours while water was azeotroped with xylene. After the stirring was completed, the solution was poured into 3 L of water to obtain a white precipitated polymer. The precipitate was collected by filtration, washed with water three times, and then dried at 80 ° C. for 20 hours using a vacuum dryer. When the resulting measuring the infrared absorption spectrum of the polymer solids, 1780 cm around ^-1, absorption peaks of an imide structure caused by a polyimide was detected near 1377 cm ^-1. In this way, an organic solvent-soluble polyimide was obtained.

<Solid epoxy compound>
157S70 (trade name, manufactured by Mitsubishi Chemical Corporation)
EP1032H60 (trade name, manufactured by Mitsubishi Chemical Corporation)
<Liquid epoxy compound>
EP828 (trade name, manufactured by Mitsubishi Chemical Corporation)
<Curing accelerator>
Imidazole-based curing accelerator Curesol 2PHZ (trade name, manufactured by Shikoku Kasei Kogyo Co., Ltd.)
Microcapsule type curing accelerator NovaCure HX-3792 (trade name, manufactured by Asahi Kasei E-Materials Co., Ltd.) NovaCure HX-3792 is a ratio of weight ratio of microcapsule type curing accelerator / liquid bisphenol A type epoxy compound to 1/2. Contains.

<Filler>
SO-E2 (trade name, manufactured by Admatechs Co., Ltd., spherical silica particles, average particle size 0.5 μm)
SE6050 (trade name, manufactured by Admatechs Co., Ltd., spherical silica particles, average particle size 2 μm)
<Other resins and additives>
Phenoxy resin FX293 (trade name, manufactured by Toto Kasei Co., Ltd.)
Preparation of thermosetting adhesive film laminate A 25 g of organic solvent-soluble polyimide obtained in Synthesis Example 1, 20 g of solid epoxy compound 157S70, 45 g of curing accelerator HX-3792, 90 g of filler SO-E2, solvent methyl 80 g of isobutyl ketone was prepared, and a filler and curing accelerator particles were dispersed using a ball mill. The obtained resin composition varnish was peeled off using a slit die coater (coating machine), and a 75 μm thick polyethylene terephthalate film, Therapy HP2 (U) (trade name, manufactured by Toray Film Processing Co., Ltd.) , Non-silicone, heavy release grade), and dried at 80 ° C. for 10 minutes to obtain a laminate A. The thickness of the thermosetting adhesive film after drying was 25 μm.

Preparation of thermosetting adhesive film laminate B 25 parts by weight of phenoxy resin FX293, 30 parts by weight of solid polyfunctional epoxy resin EP1032H60 and 45 parts by weight of liquid bisphenol A type epoxy resin EP828 as an epoxy compound, as a curing accelerator 3 parts by weight of Curazole 2PHZ and 100 parts by weight of SE6050 as a spherical silica filler were prepared in a toluene-ethyl acetate solvent so that the solid concentration was 60% by weight. Distributed processing was performed. The obtained resin composition varnish was peeled off using a slit die coater (coating machine), and a 75 μm thick polyethylene terephthalate film, Therapy HP2 (U) (trade name, manufactured by Toray Film Processing Co., Ltd.) , Non-silicone, heavy release grade), and dried at 80 ° C. for 10 minutes to obtain a laminate B. The thickness of the mounting adhesive sheet after drying was 25 μm.

<Lamination of thermosetting adhesive film to substrate>
The obtained laminate was punched out using a pinnacle blade to obtain a laminate of a 7.5 mm square mounting adhesive sheet and a base film.

  This laminated body is set at the mounting position of the semiconductor chip so that the mounting adhesive sheet surface is in contact with the wiring board, and is vacuum laminated with a vacuum pressure laminator (manufactured by Nichigo Morton Co., Ltd., CVP300). The base film was peeled off to obtain a wiring board with an adhesive sheet for mounting. The lamination temperature was 80 ° C., the degree of vacuum during lamination was 100 Pa or less, and the pressure during application was 0.3 MPa.

<Bonding>
Using a bonding apparatus (Toray Engineering Co., Ltd., FC3000S), alignment was performed so that the bumps of the semiconductor chip and the electrode pads on the substrate overlapped with predetermined positions, and then thermocompression bonding was performed to prepare a bonding sample. . The bonding tools used in each example and comparative example are listed in Table 1. The substrate stage temperature is 80 ° C., the temperature is 140 ° C., pressure 30 N / chip, and pre-bonded for 2 seconds. A bonding sample was obtained. For bonding tools 1 and 3, a 15 μm-thick fluororesin (PTFE) deposition film was used in order to prevent the adhesive sample from adhering to the bonding tool and making it impossible to remove the bonding sample. A hole for chip adsorption was made in the adhesion-preventing film, and it was sandwiched between the bonding tool and the semiconductor chip without wrinkles.

<Mountability evaluation>
The voids, continuity, and bonding cross section of the mounting sample were evaluated by the following procedure.

1. Void Evaluation In the void evaluation, each sample was polished in parallel from the semiconductor chip surface to scrape the semiconductor chip, and the number of voids was counted by observing the thermosetting adhesive film with an optical microscope. Five bonding samples under the same conditions were judged as ◎ when the average number of voids was 1 or less, ◯ when 5 or less, and × when 6 or more.

2. Conductivity evaluation The semiconductor chip and the substrate used in the evaluation of each example are designed to be electrically connected to each bump pitch via connecting portions of 138, 150, 162, and 174, respectively. Has been. If there is a portion where even one bump and electrode pad are not in contact with each other, connection failure occurs. Here, the measurement terminal of DIGITAL VOLMETER (made by HEWLETT PACKARD, 3455A) was connected, and the resistance value was measured. The resistance value includes not only the connection portion between the bump and the electrode pad but also the resistance inside the semiconductor chip and the value of the lead electrode. It was determined whether or not all measured resistance values were less than 100 kΩ for each bump pitch daisy chain. For all five bonding samples under the same conditions, ◎ when the resistance value of all 5 samples is less than 100 kΩ, ◎ when the resistance value of daisy chain is 100 kΩ or more is less than 2 samples The case where the resistance value of the daisy chain was 100 kΩ or more was 3 or more was determined as x.

10 Central part 11 having a thermal conductivity of 50 W / mK or more and 1000 W / mK or less 11 An outer peripheral part 12 having a thermal conductivity of less than 50 W / mK 12 A suction surface 13 of a semiconductor chip 14 A mounting face 14 to a bonding head A chip suction hole 15 A semiconductor chip 16 Thermosetting Adhesive film 17 Circuit board 18 Void 19 Aluminum nitride 20 Stainless steel (SUS304)
21 Fluororesin (PTFE)

Claims (5)

The adsorption surface of the semiconductor chip is composed of a central part with a thermal conductivity of 50 W / mK or more and 1000 W / mK or less and an outer peripheral part with a thermal conductivity of less than 50 W / mK, and the thermal conductivity of the central part is that of the outer peripheral part. A bonding tool characterized by being 50 W / mK or more larger than thermal conductivity. The bonding tool according to claim 1, wherein the outer peripheral portion has a thermal conductivity of 5 W / mK or less. The bonding tool according to claim 1, wherein a fluororesin is used for the outer peripheral portion. A method of manufacturing a semiconductor device in which a circuit board having an electrode and a semiconductor chip having a bump are thermocompression bonded, the electrode part of the circuit board and / or the bump part of the semiconductor chip having solder,
(A) Laminating a thermosetting adhesive film on the surface of the circuit board having the electrodes,
(B) Using the bonding tool according to any one of claims 1 to 3, the bump-side surface of the semiconductor chip is thermocompression-bonded with the electrode-side surface of the circuit board, and solder bonding and adhesive film A step of curing,
In this order, a method for manufacturing a semiconductor device. The shape of the center portion of the bonding tool is a rectangle, and the length of each side of the center portion is 90% or more and less than 100% of the length of each corresponding side of the semiconductor chip. Item 5. A method for manufacturing a semiconductor device according to Item 4.

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