JP2014048955A - Data transfer device, and data transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer device in which DMA data transfer by a plurality of programs is made possible with an appropriate buffer capacity.SOLUTION: Data transfer from a memory storing data to a DMA device, having a buffer and a plurality of registers each storing a maximum beat number corresponding to each program, by a plurality of programs is performed as follows: A transfer command is read out by using a storage address set in a counter on the basis of a data transfer request from the DMA device, and DMA data transfer from a memory to a DMA device is performed. At this occasion, data, a counter identifier of a counter, in which a storage address for an executed transfer command, and a maximum beat number of a program executing the transfer command are output to a DMA device. On the other hand, the DMA device controls allocation of the buffer and DMA data transfer in accordance with a maximum beat number corresponding to the counter identifier.

Description

  The present invention relates to a data transfer apparatus and a data transfer method, and more particularly to a data transfer apparatus and a data transfer method for performing DMA data transfer.

  In order to transfer data without imposing a load on the CPU, a device employing direct memory access (DMA) has been proposed. For example, the data transfer device disclosed in Patent Document 1 includes three program counters (PC) 3-1, 3-2, and 3-3 and three addresses stored in these as shown in FIG. A PC selection unit 4 for selecting either one is provided. The instruction stored at the address selected by the PC selection unit 4 is once stored in the instruction memory 5, and the instruction decoding unit 6 decodes the instruction. Based on the command, the data transfer execution unit 7 transfers data to the DMA device 1-1 or 1-2 via the DMA port 7-1 or 7-2.

JP 2005-352594 A

  When performing high-speed transfer in DMA data transfer, a data reception buffer may be provided due to the data processing performance of the DMA device. In the case of an apparatus having a plurality of processing modes, the continuous transfer amount (hereinafter, the number of beats) may differ depending on the mode for one DMA device. In this case, each DMA device needs to have a capacity that does not cause a buffer shortage regardless of which mode is selected.

  However, in the conventional example disclosed in Patent Document 1, since the number of beats in DMA transfer is not known, it is necessary to secure a large buffer capacity for safety. Therefore, a buffer with a limited capacity cannot be used effectively, which is inefficient.

  The present invention has been made in view of the above conventional example, and an object thereof is to provide a data transfer apparatus and a data transfer method capable of transferring DMA data by a plurality of programs with an appropriate buffer capacity.

  In order to achieve the above object, a data transfer apparatus of the present invention has the following configuration.

  That is, a data transfer device for controlling DMA data transfer by a plurality of programs, a memory for storing data, storage means for storing a data transfer instruction instructed by the CPU, and data corresponding to each of the plurality of programs A plurality of counters in which addresses of the storage means storing transfer instructions are set; a plurality of first registers for storing information indicating the maximum number of beats corresponding to each of the plurality of programs; and a buffer. Based on a data transfer request from the DMA device and the DMA device, the storage unit is accessed by using the addresses set in the plurality of counters, and the stored data transfer instruction is read out from the memory. When executing DMA data transfer to the data, the data and the data transfer to be executed are performed. Data transfer means for outputting a counter identifier of a counter for storing an instruction address to the DMA device, the DMA device assigning the buffer and transferring the DMA data according to the maximum number of beats of a program corresponding to the counter identifier It is characterized by controlling.

  Therefore, according to the present invention, when data is transferred according to a plurality of programs, the maximum number of beats for each program can be stored, and buffer allocation and DMA data transfer can be controlled based on the maximum number of beats. Thus, for example, even when there are a plurality of processing modes and the number of beats for each mode differs for each program, the buffer capacity can be appropriately managed, and the buffer capacity is not increased unnecessarily.

It is a block diagram which shows the structure of the data processing apparatus containing the data transfer part which is embodiment of this invention. It is a block diagram which shows the detailed structure of a data transfer part. It is a flowchart which shows the operation | movement outline | summary of a data transfer part. It is a figure explaining a structure and operation | movement of a DMA device. It is a timing chart which shows the signal protocol between a data transfer part and a DMA device. It is a figure which shows the transfer data format from a DMA data port. It is a block diagram which shows the structure of the data transfer apparatus according to a prior art.

  Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

  In this specification, “recording” (hereinafter also referred to as “printing”) is not only for forming significant information such as characters and figures, but also for images on a wide range of recording media, regardless of significance. A case where a pattern, a pattern, or the like is formed or a medium is processed is also expressed. It does not matter whether it has been made obvious so that humans can perceive it visually.

  “Recording medium” refers not only to paper used in general recording apparatuses but also widely to cloth, plastic film, metal plate, glass, ceramics, wood, leather, and the like that can accept ink. Shall.

  FIG. 1 is a block diagram of a data processing apparatus 101 including a data transfer unit according to an embodiment of the present invention.

  In FIG. 1, a CPU 102 operates as an arithmetic circuit that performs data processing according to a program stored in a built-in ROM (not shown). The data transfer unit 105 controls DMA data transfer between the memory 104 and the DMA device 106 according to a program stored in a built-in memory (not shown). The CPU 102 is also connected to the data transfer unit 105, and transfers messages such as data transfer start and end and a program to the data transfer unit 105.

  The data transfer unit 105 transfers different data while switching programs (threads) in predetermined units. As a result, a plurality of different data are apparently processed in parallel. When transferring data to be processed, the data transfer unit 105 transfers information (PGNum) for identifying a program (thread) corresponding to the data in synchronization with the transfer of the data.

  The DMA device 106 is connected to the data transfer unit 105 via two DMA ports 105a and 105b. The DMA device 106 has a function of receiving data and a command from the data transfer unit 105 and transferring the received data to the IP_A 107, IP_B 108, and IP_C 109 based on the command information.

  IP_A 107, IP_B 108, and IP_C 109 are processors (Image Processors) that execute predetermined image processing, and are functional blocks (processing units) that can execute different image processing. The DMA device 106 knows which program corresponds to the received data by the PGNum sent together with the data to be processed, and transfers the data to the corresponding IP. Further, the DMA device 106 performs data transfer and buffer control according to the maximum number of beats for each program by a beat number command transmitted together with PGNum.

  The two DMA ports are a DMA data port 105a that transmits data to be processed and a DMA command port 105b that transmits a command indicating the number of beats.

  The data processing apparatus 101 is applied to, for example, a recording apparatus equipped with an inkjet recording head. The recording apparatus includes an engine unit that reciprocally scans a carriage on which an inkjet recording head is mounted and ejects ink onto a recording medium; a print control unit that receives image data by connecting to a host and performs image processing and recording control; Prepare. The print control unit includes an interface with a CPU, a memory, and a host. However, DMA transfer is used for inputting / outputting data to / from the memory to increase the processing speed. A data processing apparatus 101 is incorporated in the print control unit to speed up data transfer. In particular, when a large-sized recording sheet having a recording medium size of A0, B0 or the like is used, the amount of image data handled by the recording apparatus becomes enormous, and a data processing apparatus that executes DMA transfer as described here is applied. By doing so, the effect is remarkable in terms of speeding up the processing. This data processing apparatus can also be applied to office and personal inkjet recording apparatuses having a recording medium size of A4 or B4.

  Note that the recording apparatus to be applied covers not only the ink jet recording apparatus having the above-described configuration, but also a wide variety of recording apparatuses to which other recording systems such as an electrophotographic system, a sublimation system, and a thermal transfer system are applied.

  FIG. 2 is a block diagram showing a detailed configuration of the data transfer unit 105. Here, in particular, output transfer to the DMA device 106 is illustrated as an example.

  In FIG. 2, the addresses set in the program counters (PC) 201, 202, 203 by the program counter (PC) update unit 200 indicate the addresses of transfer instructions stored in the memory 206. A program counter (PC) selection unit 204 selects any one of the program counters 201, 202, and 203 based on a control signal from the data transfer execution unit 208.

  An address (adr) selection unit 205 switches an access address to the memory 206. When there is a write access from the CPU 102, an address from the CPU 102 is selected, a sequence for writing data to the memory 206 is generated (not shown), and the data is written to a desired address. The instruction decoding unit 207 decodes the data transfer instruction read from the memory 206 and determines the data transfer direction, the data transfer destination, the data transfer source, and the like.

  The data transfer execution unit 208 drives the DMA data port 105 a or the CPU bus 210 in accordance with the data transfer instruction decoded by the instruction decoding unit 207 and executes data transfer between the memory 104 and the DMA device 106. The DMA command port 105b notifies the DMA device 106 of the number of beats of each program. The data transfer execution unit 208 also manages the program counter number of the data transfer unit 105. When the DMA device 106 asserts a data transfer request (DMA_Req) signal, data transfer between the two DMA ports 105 a and 105 b and the DMA device 106 is started.

  Next, the actual operation of the data transfer unit will be described with reference to a flowchart.

  FIG. 3 is a flowchart showing an outline of the operation of the data transfer unit 105.

  First, in step S301, the CPU 102 writes three types of data transfer programs in the memory 206 of the data transfer unit 105. In step S302, the CPU 102 sets the data transfer execution unit 208 to start the program.

  In step S303, the data transfer execution unit 208 issues a control signal to the program counter selection unit 204 to instruct the program counter 201 to be selected. As a result, the instruction data stored at the address of the memory 206 indicated by the value of the program counter 201 is read and passed to the instruction decoding unit 207. In step S304, the received data is decoded and transmitted to the data transfer execution unit 208 as a data transfer command.

  In step S305, the data transfer execution unit 208 makes a read request to the memory 104 in accordance with the received data transfer command. In step S306, in response to this, the processing target data read from the memory 104 is transferred to the DMA device 106 via the DMA data port 105a together with PGNum information for identifying which program the data conforms to. Alternatively, the processing target data read from the memory 104 is transferred to the DMA device 106 via the DMA command port 105b along with the PGNum information and the beat number command.

  Note that steps S303 to S306 are executed by a pipeline operation. For example, in step S303, the currently executed program counter is sequentially selected such that the program counter 201 is first selected, the program counter 202 is then selected, and then the program counter 203 is selected. Then, the process proceeds while switching the program to be processed for each predetermined unit. When the program is executed to the end, program counters excluding the program counter are sequentially selected and continued until all programs are executed to the end.

  Similarly for the instruction decoding in step S304, the instructions stored at the address of the program counter selected in step S303 are sequentially decoded. Steps S303 and S304 can be temporarily stopped according to the operation status of the data transfer execution unit 208. That is, by performing pipeline operations in step S303 and step S304, it is possible to reduce the waiting time for instruction execution in step S305.

  In step S307, it is confirmed whether all programs have been executed and data has been transferred. If the transfer is not completed, the process returns to step S303. If it is determined that the transfer is completed, an interrupt is asserted to the CPU 102 to notify that the data transfer is completed and the process ends.

  Here, the configuration and operation of the DMA device 106 will be described in detail.

  FIG. 4 is a diagram for explaining the configuration and operation of the DMA device 106.

  As can be seen from FIG. 1, the DMA device 106 is connected to the IP_A 107, IP_B 108, and IP_C 109, and the address spaces of the IPs 107 to 109 are mapped so as to be separated.

  As shown in FIG. 4A, the DMA device 106 has registers (second registers) 110, 111, and 112 that manage addresses for each program counter number and registers (first registers) that manage the maximum number of beats. Register) 115, 116, 117. Then, the address value and the maximum number of beats corresponding to each IP 107 to 109 are written from the CPU 102 or the DMA command port 105b. Addresses A, B, and C are set in the registers 110, 111, and 112, respectively, and the maximum beat number A, the maximum beat number B, and the maximum beat number C are set in the registers 115, 116, and 117, respectively.

  The values of the program counters 201 to 203 (PGNum = # 1, PGNum = # 2, PGNum = # 3) are associated with the addresses (address A, address B, address C) set in the registers 110 to 112. ing. The values of the program counters 201 to 203 (PGNum = # 1, PGNum = # 2, PGNum = # 3) also correspond to the maximum beat number A, the maximum beat number B, and the maximum beat number C set in the registers 115 to 117. It is attached.

  The DMA device 106 includes a buffer 118 divided into eight storage areas, and holds data received from the DMA data port 105a for eight receptions. The control unit 119 controls the DMA_Req signal to the data port 105a based on the capacity of the buffer 118 and information on the maximum number of beats A, B, and C stored in the registers 115 to 117. Further, the control unit 119 stores the data received from the data port 105 a and the value of the program counter number in the buffer 118. The data output unit 120 refers to the value of the address stored in the registers 110 to 112 associated with the data 402 stored in the buffer 118 based on the program counter number, and executes output to each IP. The DMA device 106 outputs the address value and the data received from the data transfer unit to a bus (IP bus) connected to the IPs 107 to 109. The address value used in this data transfer is incremented to indicate the next address and used at the next data transfer.

  FIG. 4B shows a data format of a command transferred from the DMA command port 105b. As shown in FIG. 4B, this transfer command designates an address (address) of a register existing in the DMA device 106 at the upper level and data (data) to be stored at that address at the lower level. Commands are written to the registers of the DMA device 106 using such a format.

  FIG. 4C shows registers and register values in a state where the number of beats of PGNum # 1 to # 3 is set.

  The DMA device 106 asserts the DMA_Req signal of the DMA data port 105a when the following condition is satisfied. The condition is that if the maximum number of beats is 2 or more and the maximum number of beats a, the maximum number of beats b, and the maximum number of beats c, buffer free space> maximum number of beats a + maximum number of beats b + maximum number of beats c It is. That is, the buffer free capacity is monitored, and as a result, if the buffer free capacity is larger than the sum of all the maximum beat numbers, the DMA_Req signal is asserted.

  FIG. 5 is a timing chart for explaining a protocol between the DMA data port 105 a and the DMA command port 105 b of the data transfer execution unit 208 and the DMA device 106.

  In FIG. 5, CLK 401 is a clock signal used by the data transfer execution unit 208 and the DMA device 106, and is composed of a synchronous circuit using a rising edge. Data 402 is data used by the data transfer execution unit 208 for data transfer, and PGNum 403 is a program counter number indicating which program of the program counters 201 to 203 is used for data transfer. DMA_Req 404 is a data request signal for the data transfer unit 105 of the DMA device 106, and DMA_Ack 405 is a data output confirmation signal indicating that the data transfer execution unit 208 is outputting data to the DMA data port 105a. Further, the BUF 406 indicates the state of the buffer 118, that is, the free capacity of the buffer 118.

  Here, the control of the data transfer request signal 404 (DMA_Req signal) according to the free space of the buffer 118 will be described.

  The example shown in FIG. 5 is an example in which three programs are operating simultaneously. The number of beats of each program is PGNum # 1 = 1, PGNum # 2 = 1, PGNum # 3 = 4, PGNum # 1 and PGNum # 2 are transferred twice, and PGNum # 3 is executed four beats once. Shows the case. Before starting the data transfer, each program notifies the DMA device 106 of the maximum number of beats that can be transmitted from now on as a data (Data) signal of the DMA command port 105b. These data are stored in the registers 115 to 117 of the DMA device as the maximum beat number A, the maximum beat number B, and the maximum beat number C.

  Next, the DMA processing flow will be described with reference to the timing chart shown in FIG.

  In clock cycle 2 (CLK2), the DMA device 106 asserts DMA_Req 404 (data request signal). The data transfer execution unit 208 attempts to output transfer data after the next cycle (after CLK3). According to FIG. 5, since the output data is not ready in clock cycles 3 and 4 (CLK3 and 4), DMA_Ack 405 (data output confirmation signal) outputs a deasserted state. Since the preparation of output data is completed in clock cycle 5 (CLK5), DMA_Ack405 (data output confirmation signal) is asserted. At the same time, # 1 is output to Data 402 (data) and PGNum 403 (program counter number) of Data 402 (data).

  In this embodiment, program counter numbers # 1, # 2, and # 3 correspond to the values of the program counters 201 to 203, respectively.

  In clock cycle 6 (CLK6), the DMA device 106 confirms that DMA_Ack (data output confirmation signal) is asserted. At the same time, Data 402 (data) and PGNum 403 (program counter number) are received, and the data is stored in the buffer 118. At this timing, the free capacity of the buffer 118 stores data for one reception, so it decreases by one from “8” to “7”.

  In this way, Data 402 (data) and PGNum 403 (program counter number) in the clock cycle in which DMA_Req 404 (data request signal) and DMA_Ack 405 (data output confirmation signal) are simultaneously asserted can be handled as valid data.

  Thereafter, processing is similarly performed until clock cycle 10 (CLK10). In clock cycle 8 (CLK8), 4-beat transfer of PGNum # 3 is started. As shown in FIG. 3, since the data transfer is executed sequentially when the program is being executed, the first beat (# 3-1) of the 4-beat transfer is transferred. In clock cycle 9 (CLK9), transfer of the next program is started.

  In clock cycle 11 (CLK11), DMA_Req 404 and DMA_Ack 405 are asserted and the value of BUF 406 is 3. For this reason, in clock cycle 11 (CLK11), the value of BUF 406 becomes smaller than the maximum number of beats of PGNum # 3. At this point in time, there is a possibility that the transfer of PGNum # 3 is 1 to 4 beats, so DMA_Req 404 is negated in consideration of the case of 4-beat transfer. DMA_Req 404 is negated in clock cycle 12 (CLK12), but since the start of 4-beat transfer of PGNum # 3 is already permitted in clock cycle 8 (CLK8), the second beat (# 3-2) Perform the transfer. Also in clock cycles 13 and 14 (CLK13 and 14), the third beat (# 3-3) and fourth beat (# 3-4) of PGNum # 3 are transferred.

  As described above, according to this embodiment, even when a plurality of programs share a single DMA port, the DMA device can recognize the maximum number of beats for each program at any time and control the buffer. Thus, data transfer can be performed at an arbitrary timing with an arbitrary number of beats equal to or less than the maximum number of beats.

  In the embodiment described above, the transfer data format may be changed from the DMA data port 105a when the number of beats is 1 (single transfer mode) and when the number of beats is 2 or more (multiple beat transfer mode). .

  FIG. 6 is a diagram showing a transfer data format from the DMA data port.

  A program for performing high-speed data transfer sets the number of beats to 2 or more, and the DMA data port 105a transfers only data as shown in FIG. On the other hand, as shown in FIG. 6, the 1-beat (single transfer) program assigns bits with the upper address as the address and the lower address as the data.

  When the DMA device 106 receives the data 402, the DMA device 106 can determine whether the received data format is a multi-beat transfer or a single transfer by referring to the PGNum 403 to be simultaneously received and the preset maximum number of beats. With such a configuration, it is easy to create a program that frequently transmits register settings by a program and a program that transfers a large amount of data at high speed.

  As described above, the program counter number is transferred from the data transfer unit to the DMA device in synchronization with the data, and the data request signal can be controlled based on the beat number information for each program and the buffer capacity of the DMA device. . As a result, the DMA device can determine the program that performed the data transfer without overhead.

  In the embodiment described above, the case where three programs are operated simultaneously has been described as an example. However, the present invention can be applied to the case where two programs operate simultaneously with the same configuration. In this case, since the number of buffers of the DMA device is 8, for example, the number of program beats can be set to 4 beats.

  In addition, even if a plurality of programs are not operated in parallel but are sequentially operated one by one, it is possible to set a buffer according to the program to be operated. At this time, the processing efficiency can be improved by using the buffer area not used for other purposes. In the present embodiment, the transfer destination according to the program is set to IP. However, the transfer destination is not limited to this, and can be replaced with another processing unit. In this way, even with the same configuration, arbitrary transfer can be performed for each program using a single DMA port, so that it is possible to realize optimum setting of the buffer capacity and high-speed and high-flexibility data transfer.

  In the above-described embodiment, the program counter is described using three examples, but the present invention is not limited to this. Other numbers of program counters may be provided. Further, identifiers other than numerals (for example, counter identifiers) may be used for program identification. Further, the above-described example is only one example of signals exchanged between the data transfer unit and the DMA device, and other protocols can be applied to the present invention.

Claims (7)

A data transfer apparatus for controlling DMA data transfer by a plurality of programs,
Memory to store data,
Storage means for storing a data transfer instruction instructed by the CPU;
A plurality of counters set with addresses of the storage means storing data transfer instructions corresponding to the plurality of programs;
A DMA device comprising a plurality of first registers for storing information indicating the maximum number of beats corresponding to each of the plurality of programs, and a buffer;
Based on the data transfer request from the DMA device, the storage unit is accessed by using the addresses set in the plurality of counters to read the stored data transfer command, and the DMA data from the memory to the DMA device is read. Data transfer means for outputting to the DMA device a counter identifier of a counter that stores the data and the address of the data transfer instruction to be executed when executing the transfer;
The DMA device controls the buffer allocation and DMA data transfer according to the maximum number of beats of a program corresponding to the counter identifier.   The DMA device monitors the free capacity of the buffer, and transmits the data transfer request when the free capacity is larger than the sum of the maximum number of beats corresponding to the output counter identifier. The data transfer apparatus according to 1. The DMA device further includes a plurality of second registers for storing addresses corresponding to the counter identifiers of the plurality of counters,
The DMA device refers to an address stored in a second register corresponding to the output counter identifier and outputs the received data to a processing unit corresponding to the address. Or the data transfer apparatus of 2. Selection means for selecting any of the plurality of counters according to a control signal from the data transfer means;
4. The apparatus according to claim 1, further comprising decoding means for accessing the storage means using an address set in the counter selected by the selection means and reading and decoding the stored data transfer instruction. The data transfer device according to any one of the above.   The data transfer means corresponds to each of the plurality of programs, the selection means sequentially selects one of the plurality of counters, and uses the address set in the selected counter to store in the storage means. 5. The data transfer apparatus according to claim 1, wherein the data transfer instructions accessed and stored are sequentially executed.   6. The data transfer according to claim 1, wherein a data format of data transfer to the DMA device is changed according to whether the maximum beat number is 1 or 2 or more. apparatus. A data transfer method for controlling data transfer from a memory storing data to a DMA device by a plurality of programs,
The DMA device includes a plurality of registers for storing a maximum number of beats corresponding to each of the plurality of programs, and a buffer.
A storage step of storing in the storage means a data transfer instruction instructed by the CPU;
A setting step of setting addresses of the storage means in which data transfer instructions corresponding to the plurality of programs are stored in a plurality of counters;
Based on the data transfer request from the DMA device, the storage unit is accessed by using the addresses set in the plurality of counters to read the stored data transfer command, and the DMA data from the memory to the DMA device is read. A data transfer step of outputting to the DMA device a counter identifier of a counter that stores the data and the address of the data transfer instruction to be executed when executing the transfer;
The data transfer method, wherein the DMA device controls allocation of the buffer and DMA data transfer according to a maximum number of beats of a program corresponding to the counter identifier.

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