JP2014048954A - Data transfer device, and data transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer device in which while suppressing increase in a circuit size or wiring, DMA transfer executed by a plurality of programs in a concurrent and parallel manner is performed.SOLUTION: Data transfer between a memory storing data and a DMA device is performed by a plurality of programs as follows: A data transfer command instructed from the CPU is stored in a storage medium, and addresses of the storage means, in which data transfer commands respectively corresponding to a plurality of programs are stored, are set in a plurality of counters. While changing over a plurality of counters on the basis of a data transfer request from a DMA device, DMA data transfer between a memory and the DMA device is performed in accordance with the data transfer command stored in the storage means by using addresses set in the plurality of counters. At this occasion, a counter identifier of a counter storing an address of a data transfer command to be executed is output to the DMA device.

Description

  The present invention relates to a data transfer apparatus and a data transfer method, and more particularly to a data transfer apparatus and a data transfer method for performing DMA data transfer.

  In order to transfer data without imposing a load on the CPU, a device employing direct memory access (DMA) has been proposed. For example, the data transfer device disclosed in Patent Document 1 includes three program counters (PC) 3-1, 3-2, and 3-3 and three addresses stored in these as shown in FIG. A PC selection unit 4 for selecting either one is provided. The instruction stored at the address selected by the PC selection unit 4 is once stored in the instruction memory 5, and the instruction decoding unit 6 decodes the instruction. Based on the command, the data transfer execution unit 7 transfers data to the DMA device 1-1 or 1-2 via the DMA port 7-1 or 7-2.

  In this configuration, by using a plurality of PCs and a plurality of DMA ports corresponding to the plurality of PCs, a plurality of programs can be executed in parallel and data transfer according to the programs can be performed.

JP 2005-352594 A

  However, in the conventional example as disclosed in Patent Document 1, since data transfer is performed in parallel by a plurality of programs, it is necessary to use a plurality of DMA ports assigned to each program. In addition, when a plurality of DMA ports are provided, wiring to the DMA devices and a control circuit are required when connecting the DMA devices connected to the DMA ports to the common bus. Thus, the increase in the DMA port has a problem that the circuit scale and wiring increase.

  The present invention has been made in view of the above-described conventional example, and provides a data transfer apparatus and a data transfer method capable of simultaneous DMA data transfer by a plurality of programs while suppressing an increase in circuit scale and wiring. Objective.

  In order to achieve the above object, a data transfer apparatus of the present invention has the following configuration.

  That is, a data transfer device for controlling DMA data transfer by a plurality of programs, which is a memory for storing data, storage means for storing a data transfer instruction instructed by a CPU, and data corresponding to each of the plurality of programs A DMA device having a plurality of counters in which addresses of the storage means storing transfer instructions are set; a plurality of registers for storing addresses corresponding to the counter identifiers of the plurality of counters; and the DMA device In accordance with a data transfer request from the memory device and the DMA device according to a data transfer instruction stored in the storage means using addresses set in the plurality of counters while switching the plurality of counters. The DMA data transfer is executed and the data transfer to be executed is executed. And having a running means for outputting the counter identifier for the counter that stores the address of the instruction to the DMA device.

  Therefore, according to the present invention, when data according to a plurality of programs is transferred, the data can be transferred to the DMA device via a common port. Therefore, the plurality of programs are obeyed while suppressing an increase in circuit scale and wiring. Simultaneous data transfer can be performed.

It is a block diagram which shows the structure of the data processing apparatus containing the data transfer part which is embodiment of this invention. It is a block diagram which shows the structure of a data transfer part. It is a flowchart which shows the operation | movement procedure of a data transfer part. It is a timing chart which shows the signal protocol between a data transfer part and a DMA device. It is a flowchart which shows the operation | movement procedure of the data transfer part at the time of the data transfer from a DMA device. It is a flowchart which shows the operation | movement procedure of the DMA device at the time of the data transfer from a DMA device. It is a block diagram which shows the structure of the data transfer apparatus according to a prior art.

  Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

  In this specification, “recording” (hereinafter also referred to as “printing”) is not only for forming significant information such as characters and figures, but also for images on a wide range of recording media, regardless of significance. A case where a pattern, a pattern, or the like is formed or a medium is processed is also expressed. It does not matter whether it has been made obvious so that humans can perceive it visually.

  “Recording medium” refers not only to paper used in general recording apparatuses but also widely to cloth, plastic film, metal plate, glass, ceramics, wood, leather, and the like that can accept ink. Shall.

  FIG. 1 is a block diagram of a data processing apparatus 101 including a data transfer unit according to an embodiment of the present invention.

  In FIG. 1, a CPU 102 operates as an arithmetic circuit that performs data processing according to a program stored in a built-in ROM (not shown). The data transfer unit 105 controls DMA data transfer between the memory 104 and the DMA device 106 according to a program stored in a built-in memory (not shown). The CPU 102 is also connected to the data transfer unit 105, and transfers messages such as data transfer start and end and a program to the data transfer unit 105.

  The data transfer unit 105 transfers different data while switching programs (threads) in predetermined units. As a result, a plurality of different data are apparently processed in parallel. When transferring data to be processed, the data transfer unit 105 transfers information (PGNum) for identifying a program (thread) corresponding to the data in synchronization with the transfer of the data.

  The DMA device 106 has a function of receiving data and PGNum from the data transfer unit 105 and transferring the received data to IP_A 107, IP_B 108, and IP_C 109 according to PGNum. IP_A 107, IP_B 108, and IP_C 109 are processors (Image Processors) that execute predetermined image processing, and are functional blocks (processing units) that can execute different image processing.

  Here, the operation of the DMA device 106 will be described.

  The DMA device 106 is connected to IP_A 107, IP_B 108, and IP_C 109, and the address spaces of IP 107 to 109 are mapped so as to be separated. The DMA device 106 includes registers 110, 111, and 112 for managing addresses for each program counter number, and addresses corresponding to the IPs 107 to 109 are written by the CPU 102. Addresses A, B, and C are set in the registers 110, 111, and 112, respectively. The DMA device 106 knows which program corresponds to the received data by the PGNum sent together with the data to be processed, and transfers the data to the corresponding IP.

  The data processing apparatus 101 is applied to, for example, a recording apparatus equipped with an inkjet recording head. The recording apparatus includes an engine unit that reciprocally scans a carriage on which an inkjet recording head is mounted and ejects ink onto a recording medium; a print control unit that receives image data by connecting to a host and performs image processing and recording control; Prepare. The print control unit includes an interface with a CPU, a memory, and a host. However, DMA transfer is used for inputting / outputting data to / from the memory to increase the processing speed. A data processing apparatus 101 is incorporated in the print control unit to speed up data transfer. In particular, when a large-sized recording sheet having a recording medium size of A0, B0 or the like is used, the amount of image data handled by the recording apparatus becomes enormous, and a data processing apparatus that executes DMA transfer as described here is applied. By doing so, the effect is remarkable in terms of speeding up the processing. This data processing apparatus can also be applied to office and personal inkjet recording apparatuses having a recording medium size of A4 or B4.

  Note that the recording apparatus to be applied covers not only the ink jet recording apparatus having the above-described configuration, but also a wide variety of recording apparatuses to which other recording systems such as an electrophotographic system, a sublimation system, and a thermal transfer system are applied.

  FIG. 2 is a block diagram showing a detailed configuration of the data transfer unit 105. Here, in particular, output transfer to the DMA device 106 is illustrated as an example.

  In FIG. 2, the addresses set in the program counters (PC) 201, 202, 203 by the program counter (PC) update unit 200 indicate the addresses of transfer instructions stored in the memory 206. A program counter (PC) selection unit 204 selects any one of the program counters 201, 202, and 203 based on a control signal from the data transfer execution unit 208.

  The values of the program counters 201 to 203 (PGNum = # 1, PGNum = # 2, PGNum = # 3) are associated with the addresses (address A, address B, address C) set in the registers 110 to 112. ing. That is, when PGNum = # 1, IP 107 is selected, when PGNum = # 2, IP 108 is selected, and when PGNum = # 3, IP 109 is selected. Then, the image data is transferred to the IP selected by PGNum, and image processing is executed.

  An address (adr) selection unit 205 switches an access address to the memory 206. When there is a write access from the CPU 102, an address from the CPU 102 is selected, a sequence for writing data to the memory 206 is generated (not shown), and the data is written to a desired address. The instruction decoding unit 207 decodes the data transfer instruction read from the memory 206 and determines the data transfer direction, the data transfer destination, the data transfer source, and the like.

  The data transfer execution unit 208 drives the DMA port 209 or the CPU bus 210 according to the data transfer instruction decoded by the instruction decoding unit 207 and executes data transfer between the memory 104 and the DMA device 106. The data transfer execution unit 208 also manages the program counter number of the data transfer unit 105. The DMA port 209 is shared for data transfer according to a plurality of programs.

  Note that when the DMA device 106 asserts a data transfer request (DMA_Req) signal, data transfer between the DMA port 209 and the DMA device 106 is started.

  Next, the actual operation of the data transfer unit will be described with reference to a flowchart.

  FIG. 3 is a flowchart showing an outline of the operation of the data transfer unit 105.

  First, in step S301, the CPU 102 writes three types of data transfer programs in the memory 206 of the data transfer unit 105. In step S302, the CPU 102 sets the data transfer execution unit 208 to start the program.

  In step S303, the data transfer execution unit 208 issues a control signal to the program counter selection unit 204 to instruct the program counter 201 to be selected. As a result, the instruction data stored at the address of the memory 206 indicated by the value of the program counter 201 is read and passed to the instruction decoding unit 207. In step S304, the received data is decoded and transmitted to the data transfer execution unit 208 as a data transfer command.

  In step S305, the data transfer execution unit 208 makes a read request to the memory 104 in accordance with the received data transfer command. In step S306, in response to this, the processing target data read from the memory 104 is transferred to the DMA device 106 via the DMA port 209 together with the PGNum information for identifying the data according to which program.

  Note that steps S303 to S306 are executed by a pipeline operation. For example, in step S303, the currently executed program counter is sequentially selected such that the program counter 201 is first selected, the program counter 202 is then selected, and then the program counter 203 is selected. Then, the process proceeds while switching the program to be processed for each predetermined unit. When the program is executed to the end, program counters excluding the program counter are sequentially selected and continued until all programs are executed to the end.

  Similarly for the instruction decoding in step S304, the instructions stored at the address of the program counter selected in step S303 are sequentially decoded. Steps S303 and S304 can be temporarily stopped according to the operation status of the data transfer execution unit 208. That is, by performing pipeline operations in step S303 and step S304, it is possible to reduce the waiting time for instruction execution in step S305.

  In step S307, it is confirmed whether all programs have been executed and data has been transferred. If the transfer is not completed, the process returns to step S303. If it is determined that the transfer is completed, an interrupt is asserted to the CPU 102 to notify that the data transfer is completed and the process ends.

  FIG. 4 is a timing chart illustrating a protocol between the DMA port 209 and the DMA device 106 of the data transfer execution unit 208.

  In FIG. 4, CLK 401 is a clock signal used by the data transfer execution unit 208 and the DMA device 106, and is composed of a synchronous circuit using a rising edge. Data 402 is data used by the data transfer execution unit 208 for data transfer, and PGNum 403 is a program counter number indicating which program of the program counters 201 to 203 is used for data transfer. DMA_Req 404 is a data request signal for the data transfer unit 105 of the DMA device 106, and DMA_Ack 405 is a data output signal indicating that the data transfer execution unit 208 is outputting data to the DMA port 209.

  Here, the DMA processing flow will be described with reference to the timing chart shown in FIG.

  In clock cycle 2 (CLK2), the DMA device 106 asserts DMA_Req 404 (data request signal). The data transfer execution unit 208 attempts to output transfer data after the next cycle (after CLK3).

  According to FIG. 4, since the output data is not ready in clock cycles 3 and 4 (CLK 3 and 4), DMA_Ack 405 (data output signal) outputs a deasserted state. Since the preparation of output data is completed in clock cycle 5 (CLK5), DMA_Ack405 (data output signal) is asserted and # 1 is output to PGNum 403 (program counter number) of Data 402 (data) and Data 402 (data).

  In this embodiment, program counter numbers # 1, # 2, and # 3 correspond to the values of the program counters 201 to 203, respectively. When the DMA device 106 confirms that DMA_Ack (data output signal) is asserted at clock cycle 6 (CLK6), it receives Data 402 (data) and PGNum 403 (program counter number).

  In this way, Data 402 (data) and PGNum 403 (program counter number) in the clock cycle in which DMA_Req 404 (data request signal) and DMA_Ack 405 (data output signal) are simultaneously asserted can be handled as valid data.

  Next, the data transfer execution unit 208 outputs the data of the program counter 202 at clock cycle 8 (CLK8), and the DMA device 106 receives the data and the program counter number at clock cycle 9 (CLK9). Similarly, the DMA device 106 receives the data and the program counter number output from the data transfer execution unit 208 in clock cycle 9 (CLK9) in clock cycle 10 (CLK10).

  Further, the operation of the DMA device 106 will be described with reference to FIG.

  The DMA device 106 receives Data 402 (data) and PGNum 403 (program counter number) at clock cycle 6 (CLK6). Since the received program counter number is # 1, the value of the address A stored in the register 110 is referred to. The DMA device 106 outputs the address value and Data (data) received from the data transfer unit 105 to a bus (IP bus) connected to the IPs 107, 108, and 109. Similarly, since the data received in clock cycle 9 (CLK9) has the program counter number # 2, the value of address B stored in register 111 is referred to and output to the IP bus. Similarly, received data in clock cycle 10 (CLK10) is also output to the IP bus with reference to the value of address C stored in register 112.

  When data is transferred from the DMA device to the data transfer unit, the processing operation in the data transfer unit 105 is as follows.

  FIG. 5 is a flowchart showing an outline of operation in the data transfer unit 105 at the time of data transfer from the DMA device to the data transfer unit. In FIG. 5, the same processing steps as those already described with reference to FIG. 3 are denoted by the same step reference numerals, and the description thereof is omitted. As can be seen by comparing FIG. 3 and FIG. 5, the overall operation is basically the same as that shown in FIG. 3, but the data transfer direction after the process of decoding the received data in step S304 is different. ing.

  Specifically, in step S305a, data is read from the DMA device 106, and in step S306a, the data read in step S305a is transferred to the memory 104.

  Next, the operation of the DMA device during data transfer from the DMA device to the data transfer unit will be described.

  FIG. 6 is a flowchart showing an outline of the operation in the DMA device 106 during data transfer from the DMA device to the data transfer unit.

  In step S <b> 601, the CPU 102 writes the start address and the transfer data amount of data to be transferred from the IPs 107 to 109 to the data transfer unit 105 via the DMA device 106 in the DMA device 106. In step S602, the DMA device 106 sequentially reads and stores data in a buffer that stores data read from the IPs 107 to 109, based on the address information and the amount of transfer data written from each IP.

  In step S603, it is confirmed whether the IP buffer during data transfer is not empty, and if it is empty, it is determined that data preparation is completed. In step S604, DMA Req 404 (data request signal) is asserted to the data transfer unit 105.

  In step S605, the data transfer unit 105 asserts DMA_Ack405 (data output signal) together with the program counter number. The DMA device 106 reads out data stored in the IP buffer corresponding to the address number stored in the register of the DMA device 106 as Data 402 (data) according to RGNum 403 and DMA_Ack 405. In this way, data corresponding to the program counter number is transferred.

  In step S606, it is confirmed whether there is an IP for which transfer of the transfer data amount set in step S601 has been completed. If there is an IP that has been completed, the process proceeds to step S607. Since there is no problem even if the buffer of the IP is empty, the IP is excluded from the targets for the subsequent data preparation completion determination. On the other hand, if there is no IP that has been transferred for the amount of transfer data set in step S601, the process skips step S607. In step S608, it is confirmed whether all IPs have been transferred for the amount of transfer data set in step S601. If all have not been completed, the process returns to step S602 and data transfer continues. If all have been completed, the data transfer process is terminated.

  Therefore, according to the embodiment described above, by transmitting the program counter number from the data transfer unit to the DMA device in synchronization with the data, the DMA device can determine the program that has transferred the data without overhead. . In addition, as shown in FIG. 1, a data transfer unit is realized with one DMA port for data transfer, one DMA device, and an interface with one CPU for a plurality of IPs (three in this embodiment). it can.

  Therefore, an increase in the circuit scale and the number of signal wirings can be suppressed as compared with those using DMA ports according to the number of programs. In addition, if a plurality of DMA ports are used and one DMA port is shared by a plurality of programs, the number of DMA ports can be made smaller than the number of programs to be used. The increase in the number can be suppressed. In the present embodiment, the transfer destination according to the program is set to IP. However, the transfer destination is not limited to this, and can be replaced with another processing unit.

  In the above-described embodiment, the program counter is described using three examples, but the present invention is not limited to this. Other numbers of program counters may be provided. Further, identifiers other than numerals (for example, counter identifiers) may be used for program identification. Further, the above-described example is only one example of signals exchanged between the data transfer unit and the DMA device, and other protocols can be applied to the present invention.

Claims (5)

A data transfer device for controlling DMA data transfer by a plurality of programs,
Memory to store data,
Storage means for storing a data transfer instruction instructed by the CPU;
A plurality of counters set with addresses of the storage means storing data transfer instructions corresponding to the plurality of programs;
A DMA device comprising a plurality of registers for storing addresses, each corresponding to a counter identifier of the plurality of counters;
Based on a data transfer request from the DMA device, the memory, the DMA device, and the DMA device are switched according to a data transfer command stored in the storage unit using addresses set in the plurality of counters while switching the plurality of counters. A data transfer apparatus comprising: execution means for executing DMA data transfer between the two and outputting a counter identifier of a counter for storing an address of the data transfer instruction to be executed to the DMA device.   At the time of data transfer to the DMA device, the DMA device receives the counter identifier and data, refers to the address stored in the register corresponding to the received counter identifier, and corresponds the received data to the address The data transfer apparatus according to claim 1, wherein the data transfer apparatus outputs the data to a processing unit.   At the time of data transfer from the DMA device, the DMA device receives the counter identifier, refers to the address stored in the register corresponding to the received counter identifier, and stores the data stored in the buffer of the processing unit. 3. The data transfer apparatus according to claim 1, wherein the data transfer apparatus reads and transfers the data. Selection means for selecting one of the plurality of counters according to a control signal from the execution means;
4. The apparatus according to claim 1, further comprising decoding means for accessing the storage means using an address set in the counter selected by the selection means and reading and decoding the stored data transfer instruction. The data transfer device according to any one of the above. A data transfer method for controlling DMA data transfer between a memory for storing data and a DMA device by a plurality of programs,
A storage step of storing in the storage means a data transfer instruction instructed by the CPU;
A setting step of setting addresses of the storage means in which data transfer instructions corresponding to the plurality of programs are stored in a plurality of counters;
Based on a data transfer request from the DMA device, the memory and the DMA device are switched according to a data transfer instruction stored in the storage means using addresses set in the plurality of counters while switching the plurality of counters. A data transfer method comprising: executing a DMA data transfer between the first and second DMAs and outputting a counter identifier of a counter for storing an address of the data transfer command to be executed to the DMA device.

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