JP2014045050A - Simulation device of drain current and simulation program of drain current - Google Patents

Abstract

PROBLEM TO BE SOLVED: To calculate a drain current at high speed with high accuracy, for a storage type thin film transistor containing a defect of capturing a carrier in a semiconductor film.SOLUTION: A simulation device 1 includes Fermi level calculation means 11 for calculating the Fermi level under flat band conditions based on electrical neutrality conditions, electrical charge carrier density calculation means 12 for calculating the electrical charge carrier density under flat band conditions, potential distribution calculation means 14 for calculating the potential distribution in the depth direction of a semiconductor film from a one-dimensional Poisson equation while taking account of electron density, hole density, donor density, and the density of acceptor type defect and donor type defect, as the density of electric charges, carrier density distribution calculation means 15 for calculating the carrier density distribution in the depth direction, carrier plane density calculation means 16 for calculating the carrier plane density, and drain current calculation means 17 for calculating the drain current by using the carrier plane density and the surface potential at more than one position in the channel length direction.

Description

  The present invention relates to a simulation apparatus for calculating a drain current and a program for the storage type thin film transistor including a defect that traps carriers in a semiconductor.

In the structural design of a semiconductor transistor, it is necessary to determine values of device parameters such as a gate insulating film thickness and a semiconductor film thickness. In addition, when development target values are set for important performance indicators such as a subthreshold coefficient (S value) and threshold voltage (V _th ), the performance indicators and targets should be satisfied. In addition, the value of the device parameter must be determined. In general, a simulation technique is used for the structural design of such a transistor. In order to determine device parameter values efficiently, high-speed and high-accuracy simulation of drain current characteristics is required, and usually a commercially available two-dimensional device simulator (for example, two-dimensional device simulator “ATLAS” manufactured by SILVACO). Is used.

As a specific structure design method, first, drain current characteristics are calculated by simulation, and transistor performance indicators such as a subthreshold coefficient (S value) and a threshold voltage (V _th ) are obtained therefrom. If they do not satisfy the preset conditions, the device parameter values are changed and the simulation is performed again. By repeating this, the value of the device parameter can be determined so that the drain current characteristic satisfies the condition. By such a method, the number of trials of actual elements for transistor structure design can be reduced, and the transistor development period and cost can be reduced.

  On the other hand, an oxide semiconductor such as amorphous InGaZnO (IGZO; indium gallium zinc oxide) is used because of its high mobility compared to amorphous silicon TFTs and high uniformity compared to polycrystalline silicon TFTs. TFTs are currently attracting attention. Also in the development of such an oxide semiconductor TFT, as described above, calculation of drain current characteristics using a simulation technique is important.

  In recent years, examples of calculating drain current characteristics of IGZO-TFT using a commercially available two-dimensional device simulator have been reported (see Non-Patent Documents 1 and 2).

Hsing-Hung Hsieh, Toshio Kamiya, Kenji Nomura, Hideo Hosono, and Chung-Chih Wu, Appl. Phys. Lett. 92, 133503 (2008) Tze-Ching Fung, Chiao-Shun Chuang, Charlene Chen, Katsumi Abe, Robert Cottle, Mark Townsend, Hideya Kumomi, and Jerzy Kanicki, J. Appl.Phys. 106, 084511 (2009)

  However, in the calculation using the two-dimensional device simulator as described above, the drain current characteristic can be obtained with high accuracy under a wide range of conditions. On the other hand, the simulation takes a long time, and a high specification is required to execute the simulation. There is a problem that a computer is necessary.

  A TFT using an oxide semiconductor is an accumulation-type transistor using a majority carrier that includes a defect of trapping carriers in a semiconductor film. For this reason, a conventional simulation method used for an amorphous silicon TFT or a polycrystalline silicon TFT cannot be directly applied to such a TFT.

  Therefore, the present invention can be applied to a storage type TFT including a defect that traps carriers in a semiconductor film, such as an oxide semiconductor TFT, and can simulate a drain current at high speed. An object is to provide a simulation program.

  In order to solve the above-described problem, a drain current simulation apparatus according to claim 1 (hereinafter referred to as a simulation apparatus as appropriate) is a storage-type thin film transistor including a defect that traps carriers in a semiconductor film, and includes a semiconductor A drain current simulation device for calculating a drain current, which is a current between a drain electrode and a source electrode, for a field effect thin film transistor having a structure in which a film, an insulating film, and a gate electrode are stacked in this order, A potential distribution calculation unit, a carrier density distribution calculation unit, a carrier surface density calculation unit, and a drain current calculation unit are included.

  According to such a configuration, the simulation apparatus uses the potential distribution calculation means to accept the electron defect, the hole density, the donor density, and the acceptor type defect and the donor having an exponential state density in the band gap as the charge density of the semiconductor film. In consideration of the density of mold defects, the potential distribution in the depth direction in the semiconductor film is calculated by solving the one-dimensional Poisson equation. Thereby, the simulation apparatus calculates the potential distribution at high speed.

Next, the simulation apparatus calculates the carrier density distribution in the depth direction in the semiconductor film by using the potential distribution calculated by the potential distribution calculating means by the carrier density distribution calculating means. Next, the simulation apparatus calculates the carrier surface density in the semiconductor film by integrating the carrier density distribution calculated by the carrier density distribution calculating unit over the entire range in the depth direction of the semiconductor film by the carrier surface density calculating unit. Then, for the two or more positions in the channel length direction, the simulation apparatus calculates the carrier surface charge density obtained by multiplying the carrier surface density calculated by the carrier surface density calculating unit by the elementary charge and the semiconductor film and gate calculated by the potential distribution calculating unit. The drain current is calculated by the drain current calculation means using the potential at the interface with the insulating film.
Accordingly, the simulation apparatus calculates the drain current using a one-dimensional potential distribution that can be calculated at high speed.

The simulation apparatus according to claim 2 is the simulation apparatus according to claim 1, further comprising Fermi level calculation means and charge carrier density calculation means.
According to such a configuration, the simulation apparatus calculates the Fermi level under the flat band condition of the semiconductor film from the equation (18), which is an equation for the Fermi level, by the Fermi level calculation means. Next, the simulation apparatus calculates the Fermi level calculated by the Fermi level calculation means by the charge carrier density calculation means by using the expressions (5), (6), (A9), (B10), and (C9). ), The hole density, the electron density, the density of positively charged donor-type defects in the deep state (Deep state), and the deep state of negatively-charged acceptor-type defects (in the flat band condition of the semiconductor film) The density in the deep state and the density in the tail state of the negatively charged acceptor type defect are calculated as the charge carrier density.

  Next, the simulation apparatus differentiates Equation (1), which is a one-dimensional Poisson equation, by the potential distribution calculation means, and the gate-source voltage, which is a voltage between the gate electrode and the source electrode, is flat with the potential at the gate electrode. The potential distribution is calculated by numerical analysis with the boundary condition being equal to the difference from the band voltage. Further, when calculating the potential distribution, the charge carrier density in the flat band condition of the semiconductor film calculated by the charge carrier density calculating means is used.

Next, the simulation apparatus calculates the carrier density distribution from the equation (19) by the carrier density distribution calculating unit, and further calculates the carrier density distribution by the equation (20) by the carrier surface density calculating unit. And a simulation apparatus calculates drain current by Formula (30) by a drain current calculating means.
Here, Formula (18) is as follows.

  Moreover, Formula (5), Formula (6), Formula (A9), Formula (B10), and Formula (C9) are as follows.

  Moreover, Formula (1) is as follows.

Here, the charge density ρ of the semiconductor film is expressed by the formula (2), and further, the hole density p, the electron density n of the semiconductor film, the density N _dd ⁺ in the deep state of the positively charged donor type defect, and negative density _{N at} the and tail states negatively charged acceptor-type defects ^{- -} charged acceptor-type defect density _{N ad} in deep state in each formula (3), the formula (4-2), formula (10) And (13-2) and (16-2). In addition, since Formula (10), Formula (13-2), and Formula (16-2) are approximate formulas, they contribute to speeding up of potential calculation.

  Moreover, Formula (19) and Formula (20) are given as follows.

  Further, equation (30) is given as follows.

In the above, β = q / kT, γ _d = q / E _dd , and γ _a = q / E _ad .
K is a Boltzmann constant, T is an absolute temperature, and q is an elementary electric quantity.
Furthermore, ρ is the charge density of the semiconductor film, p ₀ is the hole density in the flat band condition of the semiconductor film, n ₀ is the electron density in the flat band condition of the semiconductor film, and N _dd0 ⁺ is positively charged in the flat band condition of the semiconductor film. The density of donor-type defects in the deep state, N _ad0 ⁻ is the density of negatively charged acceptor-type defects in the flat band condition of the semiconductor film, and N _at0 ⁻ is the negatively charged acceptor in the flat band condition of the semiconductor film. Density in the tail state of the type defect, g _dd0 is the density of states in the deep state of the donor type defect at the upper end of the valence band of the semiconductor film, and g _ad0 is the density of states in the deep state of the acceptor type defect in the lower end of the conduction band of the semiconductor film. , _Gat0 is the value at the bottom of the conduction band of the semiconductor film. State density at the tail state of Kuseputa type defects, E _v is the valence band upper end of the energy of the semiconductor film, E _c is the conduction band minimum energy of the semiconductor film, E _f is the Fermi level of a flat band condition of the semiconductor film, E _dd is the reciprocal of the slope of the state density distribution in the deep state of the donor-type defect of the semiconductor film, E _ad is the reciprocal of the slope of the state density distribution in the deep state of the acceptor-type defect of the semiconductor film, and E _at is the acceptor type of the semiconductor film. The reciprocal of the slope of the state density distribution in the defect tail state, n _i is the intrinsic carrier density of the semiconductor film, E _i is the intrinsic Fermi level of the semiconductor film, ε _sc is the dielectric constant of the semiconductor film, and t _sc is the film of the semiconductor film thickness, phi is the potential, φ (x) is the potential distribution, n (x) is the carrier density distribution, n is the carrier surface density, n _d is the semiconductor An effective donors density.

Further, x indicates the position in the thickness direction of the semiconductor film, and the interface between the semiconductor film and the insulating film is 0, and the interface between the semiconductor film and the source electrode and the drain electrode is t _sc . Further, y indicates the position of the semiconductor film in the channel length direction, and the end of the source electrode on the drain electrode side is 0, and the end of the drain electrode on the source electrode side is L.
L is the channel length of the semiconductor film, W is the channel width of the semiconductor film, μ is the mobility of electrons in the semiconductor film, V _ds is the drain-source voltage, and φ _n is the pseudo-Fermi potential of the electrons. , Φ _n (y) is a pseudo-Fermi potential of electrons at the position y in the channel length direction, and φ _n (0) = 0 and φ _n (L) = V _ds .
Further, I _d is the drain current, Q is the carrier surface charge density, Q ₀ is the carrier surface charge density at the position y = 0 in the carrier length direction of the semiconductor film, and Q _L is the position y = of the semiconductor film in the carrier length direction. The carrier surface charge density at L, φ _s is the potential at the position x = 0 in the thickness direction of the semiconductor film, φ _s0 is the position x = 0 in the thickness direction of the semiconductor film, and the channel length direction of the semiconductor film The potential at position y = 0, φ _sL is the potential at position x = 0 in the thickness direction of the semiconductor film and at position y = L in the channel length direction of the semiconductor film.

  The simulation apparatus according to claim 3 is the simulation apparatus according to claim 2, wherein the drain current calculation unit calculates the drain current by an expression (35) instead of the expression (30), and Formula (35) is as follows.

  According to such a configuration, the simulation apparatus has a carrier surface charge density at two positions of the source electrode end and the drain electrode end, which are both ends in the channel length direction of the semiconductor film, and an interface between the semiconductor film and the gate insulating film. Using the surface potential which is the potential, the drain current is calculated by the approximate expression shown in Expression (35). Note that the carrier surface charge density and the surface potential at the both ends in the channel length direction of the semiconductor film are calculated based on the one-dimensional potential distribution at the both ends in the channel length direction as described above.

A simulation apparatus according to a fourth aspect is the simulation apparatus according to the second or third aspect, further comprising calculation range setting means.
According to such a configuration, the simulation apparatus sequentially sets a plurality of drain-source voltages and / or gate-source voltages in a predetermined range as potential distribution calculation conditions in the potential distribution calculation means by the calculation range setting means. To do. Next, the simulation apparatus calculates the potential distribution in the drain-source voltage and / or the gate-source voltage by the potential distribution calculation means. Then, the simulation apparatus calculates the drain current by the drain current calculation means described above. Further, the simulation apparatus sequentially changes the drain-source voltage and / or the gate-source voltage in a predetermined range by the calculation range setting means, and the drain-source sequentially set by the drain current calculation means. A drain current corresponding to the inter-voltage and / or the gate-source voltage is calculated. As a result, the simulation apparatus determines the drain current dependency on the drain voltage, which correlates the drain current with the drain-source voltage and / or the gate-source voltage as the calculation condition of the potential distribution on which the calculation is based. And / or calculate gate voltage dependence.

  The drain current simulation apparatus according to the first aspect of the present invention includes hardware resources such as a CPU (central processing unit), a memory, and a hard disk included in a general computer, potential distribution calculation means, carrier density distribution, and the like. It can also be realized by a drain current simulation program according to claim 5 for functioning as a calculation means, a carrier surface density calculation means, and a drain current calculation means. This program may be distributed via a communication line, or may be recorded and distributed on a recording medium such as a CD-ROM or a flash memory.

According to the first or fifth aspect of the present invention, in the accumulation type TFT including the defect that traps carriers in the semiconductor film, the depth direction of the semiconductor film at two or more positions in the channel length direction of the semiconductor film. Since the drain distribution is calculated based on the one-dimensional potential distribution, the drain current can be calculated at high speed and with high accuracy without using a high-spec computer.
According to the second aspect of the present invention, the density in the deep state of the donor-type defect having an exponential state density in the band gap, the density in the deep state of the acceptor-type defect, and the tail state of the acceptor-type defect The potential distribution is calculated by numerical analysis of the one-dimensional Poisson equation considering the pseudo-Fermi potential of the electron including the density, and the drain current is calculated based on the one-dimensional potential distribution at two or more positions in the channel length direction. Since the calculation is performed, the drain current for a wide range of drain-source voltages can be calculated at high speed and with high accuracy for a storage type TFT including a defect that traps carriers in a semiconductor film.
According to the third aspect of the present invention, since the drain current is calculated based on the one-dimensional potential distribution at both ends in the channel length direction, the storage type TFT including a defect that traps carriers in the semiconductor film. The basic characteristics of the drain current can be calculated at high speed and with high accuracy.
According to the fourth aspect of the present invention, the drain voltage dependency characteristic and / or the gate voltage dependency characteristic of the drain current can be calculated for a storage type TFT including a defect that traps carriers in the semiconductor film.

It is typical sectional drawing which shows the structure of TFT which is calculation object in embodiment of this invention. It is a figure which shows the state density distribution in the band gap of the defect of the semiconductor film in TFT which is calculation object in embodiment of this invention. It is a figure for demonstrating flat band conditions about TFT which is the calculation object in embodiment of this invention. It is a figure for demonstrating the boundary condition at the time of solving a Poisson equation about TFT which is a calculation object in embodiment of this invention. It is a figure for demonstrating the influence of parasitic resistance about TFT which is the calculation object in embodiment of this invention. It is a block diagram which shows the structure of the simulation apparatus of the drain current in embodiment of this invention. It is a flowchart which shows the flow of a process of the simulation apparatus of the drain current in embodiment of this invention. It is a figure which shows the Example of calculation of the drain current characteristic using the simulation apparatus of the drain current which concerns on this invention, and shows the result of having calculated the gate voltage dependence of drain current by changing the density of a defect variously. It is a figure which shows the Example of calculation of the drain current characteristic using the simulation apparatus of the drain current which concerns on this invention, The drain voltage is changed variously, The result and the measured value which calculated the gate voltage dependence of the drain current are shown. Show. It is a figure which shows the Example of the calculation of the drain current using the simulation apparatus of the drain current which concerns on this invention, and shows the result of having calculated the drain voltage dependence of the drain current by changing gate voltage variously, and an actual measurement value . It is a figure which shows the Example of calculation of the drain current characteristic using the simulation apparatus of the drain current which concerns on this invention, the result of having calculated the gate voltage dependence of drain current by changing the thickness of a gate insulating film, and an actual value It shows.

  Embodiments of the present invention will be described below with reference to the drawings as appropriate. Here, an n-type storage TFT will be described. In this embodiment, a drain current calculation method will be described first, and then a drain current simulation apparatus using the calculation method will be described.

[Drain current calculation method]
First, a method for calculating the drain current will be described.
FIG. 1 schematically shows a cross section of a TFT for explaining a drain current calculation method in the present invention. In the TFT, a source electrode S and a drain electrode D are provided at both ends in the left-right direction of the semiconductor film SC in the drawing, respectively. In the drawing, a gate electrode G is formed below the semiconductor film SC with a gate insulating film IN interposed therebetween. This is a bottom-gate, top-contact type field effect transistor (FET) provided. In this embodiment, a bottom gate and top contact type TFT will be described as an example. However, a TFT to which the present invention can be applied is not limited to this structure.

_{Here, t sc} is the thickness of the semiconductor film SC, L is the channel length of the semiconductor film _{SC, t in} is the thickness of the gate insulating film IN. In the coordinate system, the vertical direction of the drawing, which is the thickness direction (also referred to as the depth direction) of the semiconductor film SC, is the x direction, and the horizontal direction of the drawing, which is the channel length direction, is the y direction. The coordinates in the x direction are x = 0 at the interface between the semiconductor film SC and the gate insulating film IN, and x = _tsc at the upper end surface. The coordinates in the y direction are y = 0 when the semiconductor film SC is in contact with the right end of the source electrode S and y = L when the semiconductor film SC is in contact with the left end of the drain electrode D.

[Poisson equation]
Here, when the channel length L is not extremely short with respect to the thickness of the gate insulating film IN, the Poisson equation in the semiconductor film SC is one-dimensional as shown in the equation (1) from the gradual channel approximation. It can be expressed by an equation. Here, the case where the channel length L is not extremely short with respect to the thickness t _in of the gate insulating film IN is, for example, when the thickness t _in of the gate insulating film IN is set to 100 [nm]. Gradual channel approximation can be performed when L is about 5 μm or more. The gradual channel approximation is an approximation in which the electric field in the y direction is ignored because the change in the channel length direction (y direction) of the drain-source voltage is gentle.

In Expression (1), φ is an electrostatic potential (hereinafter simply referred to as “potential” as appropriate), x is a position in the thickness direction of the semiconductor film SC, ρ is a charge density, and ε _sc is a dielectric constant of the semiconductor film SC. It is. At this time, the charge density ρ in the semiconductor film SC including a defect that captures carriers is given by Expression (2) in consideration of the density of defects that capture carriers.

Here, q is the elementary charge, p is the hole density, n is the electron density, N _d is the effective donor density derived from oxygen deficiency, impurity hydrogen, etc., and N _dd ⁺ is the deep _depth of the positively charged donor type defect. The density in the state (Deep state), N _ad ⁻ is the density in the deep state of the negatively charged acceptor type defect, and N _at ⁻ is the density in the tail state of the negatively charged acceptor type defect. is there. In addition, since the influence of the tail state of the donor-type defect on the drain current characteristics is small, the related item is ignored here. Note that N _dd ⁺ is a density in a deep state of a positively charged donor type defect or the like, and “N _dd ⁺ is a density of a positively charged donor type defect (Deep state)” as appropriate. .
Further, “Deep state” and “Tail state” will be described later.

Here, the hole density p and the electron density n are given as shown in equations (3) and (4-1), respectively. Furthermore, in this embodiment, the density n of electrons, which are majority carriers in the n-type TFT, is a system in which the drain-source voltage _Vds is high and cannot be approximated as being in a thermal equilibrium state, that is, thermally non- In order to be applicable to an equilibrium system, an electron pseudo-Fermi potential φ _n is introduced, and instead of the potential φ in the equation (4-1), (φ−φ _n ) Formula (4-2) is used.
In the case of calculating for the p-type TFT, the electron density n and the acceptor-type defect density N _ad ⁻ , N _at ⁻ (formula (13-2) and formula (16) will be described later in the calculation for the n-type TFT. -2) refer) to instead of introducing a quasi-Fermi potential phi _n electronic introduces density n _dd ⁺ the quasi-Fermi potential phi _p of holes hole density p and the donor-type defects (formula (3) and In equation (10), φ is replaced with (φ−φ _p )). In this case, it is not necessary to introduce the electron pseudo-Fermi potential φ _{n to} the electron density n and the acceptor-type defect densities N _ad ⁻ and N _at ⁻ .

Here, p ₀ and n ₀ are the hole density and electron density of the semiconductor film SC under flat band conditions, respectively, and β is the reciprocal of the thermal voltage. Here, β = q / kT, k is a Boltzmann constant, and T is an absolute temperature. Also, quasi-Fermi potential phi _n electrons in the source edge _{(y = 0), φ n} = 0, at the drain end (y = L), the φ _n = _{V ds.}
However, as will be described later, when the influence of the parasitic resistance cannot be ignored, φ _n = V _ds-eff at the drain end (y = L). Here, V _ds-eff is an effective drain-source voltage in consideration of the effect of voltage drop due to parasitic resistance. A detailed description of the effective drain-source voltage _Vds-eff will be given later.

Further, the hole density p ₀ and the electron density n ₀ of the semiconductor film SC under the flat band condition are given by the equations (5) and (6), respectively.

Here, n _i is the intrinsic carrier density, E _i is the intrinsic Fermi level, and E _f is the Fermi level under flat band conditions.

In the calculation method according to the present embodiment, the effective donor density N _d derived from oxygen deficiency, impurity hydrogen, or the like does not depend on the potential φ, and the heat treatment temperature or heat treatment atmosphere (for example, a nitrogen gas atmosphere, Approximate to take a predetermined value determined by the manufacturing process such as air). As this predetermined value, an empirical value determined based on an experimental result can be used as a specific parameter.

Next, the density of defects that capture carriers will be described in detail. FIG. 2 is a diagram showing the density of states of a donor type defect (Deep state) and an acceptor type defect (Deep state, Tail state) in the band gap. The “Deep state” refers to the energy state at the center in the energy state between the energy E _{v at the} upper end of the valence band and the energy E _{c at the} lower end of the conduction band. Further, the "Tail state", among the above-mentioned energy, is intended to refer to energy state in the vicinity of the energy E _c of the near or bottom of the conduction band energy E _v of the valence band upper end.

Here, the state density g _dd of the donor-type defect (Deep state) is given as a function of the energy E in the band gap as shown in Expression (7).

Here, g _dd0 is the density of states of the donor type defects in the energy E _v of the valence band maximum (Deep state). Further, E _dd is the reciprocal of the gradient of the state density distribution of the donor type defect (Deep state), and “E _dd > kT”. Note that kT is 26 meV at room temperature.

Further, the density N _dd ⁺ of the positively charged donor-type defect (Deep state) is expressed by (1-) in Equation (7), where f (E) is the defect level occupation probability, as shown in Equation (8). multiplied by f (E)), it can be determined by integrating the energy E _v of the valence band upper end to the energy E _c of the conduction band. The defect level occupation probability f (E) is given by equation (9).

Here, E _fe is the Fermi level.
Next, the integral calculation of Expression (8) needs to be performed numerically, but an analytical approximate solution can be obtained by considering that “E _dd > kT”. Derivation of this approximate solution will be described.

First, Expression (7) and Expression (9) are substituted into Expression (8), and the upper end of the integration range is changed from the energy E _{c at the} lower end of the conduction band to infinity, thereby obtaining Expression (A1) which is an approximate expression. It is done.

  Here, when z and α are set as in the formula (A2), the formula (A1) can be expressed as in the formula (A3) and further approximated as in the formula (A4).

Here, when α> 1 (E _dd > kT), since the relationship of the equation (A5) is established, the equation (A4) becomes the equation (A6).

  Here, the formula (A8) is obtained by substituting the relational expression shown in the formula (A7) into the formula (A6).

Further, as shown in the formula (A9), in the formula (A8), when the potential φ = 0, the density N _dd0 of the positively charged donor-type defect (Deep state) under the flat band condition of the semiconductor film SC. ⁺ .

Therefore, by using the formula (A9), the formula (A8) can be expressed as the formula (10). In this embodiment, Expression (10) is used as an approximate expression of the density N _dd ⁺ of the positively charged donor-type defect (Deep state) shown in Expression (8).

Further, the state density g _ad of the acceptor type defect (Deep state) is given by the equation (11).

Here, g _ad0 is the state density of the acceptor type defect (Deep state) at the energy E _c at the lower end of the conduction band, E _ad is the reciprocal of the slope of the state density distribution of the acceptor type defect (Deep state), and “E _ad > KT ”.

Further, the density N _ad ⁻ of acceptor defects (Deep state) charged negatively is obtained by multiplying the equation (11) by the defect level occupation probability f (E) as shown in the equation (12). it can be determined by integrating the energy E _v band upper end to the energy E _c of the conduction band.

Similar to the integral calculation shown in equation (8), the integral calculation in equation (12) also needs to be performed numerically, but by considering that “E _ad > kT”, an analytical approximate solution Can be obtained. Derivation of this approximate solution will be described.

First, by substituting Equation (9) and Equation (11) into Equation (12), Equation (B1) is obtained, and further, the lower end of the integration range is changed from the energy E _{v at the} upper end of the valence band to minus infinity. By changing, the approximate expression (B2) is obtained.

  Here, as shown in Expression (B3), when z and α are set, Expression (B2) can be expressed as Expression (B4), and further, by changing the upper end of the integration range to infinity. Then, an approximate expression (B5) is obtained. Note that z and α in the formula (B3) are different from z and α in the formula (A2).

Here, when α> 1 (E _ad > kT), since the relationship of the equation (B6) is established, the equation (B5) becomes the equation (B7).

  Here, the formula (B9) is obtained by substituting the relational expression shown in the formula (B8) into the formula (B7).

Further, as shown in the formula (B10), in the formula (B9), when the potential φ = 0, the density N _ad0 of the negatively charged acceptor type defect (Deep state) under the flat band condition of the semiconductor film SC. ^- .

Therefore, by using the formula (B10), the formula (B9) can be expressed as the formula (13-1). Furthermore, in the present embodiment, in order to be applicable to a system in a thermally non-equilibrium state, similarly to the electron density n shown in the equation (4-2), the electron pseudo-Fermi potential φ _n is considered, Equation (13-2) in which the potential φ in Equation (13-1) is replaced by (φ−φ _n ) is replaced by the density N _ad ^{− of} the negatively charged acceptor type defect (Deep state) shown in Equation (12). It is used as an approximate expression.

Further, the state density _{g at} the acceptor-type defects (Tail state) is given by equation (14).

Here, g _at0 is the state density of the acceptor type defect (Tail state) at the lower end of the conduction band, E _at is the reciprocal of the slope of the state density distribution of the acceptor type defect (Tail state), and “E _at <kT” is there.

Further, the density N _at ⁻ of the negatively charged acceptor type defect (Tail state) is expressed by the equation (14), the occupation probability f () of the defect level shown in the equation (9), as shown in the equation (15). E) the multiplied, it can be determined by integrating the energy E _v of the valence band upper end to the energy E _c of the conduction band.

Similar to the integral calculation shown in equations (8) and (12), the integral calculation in equation (15) also needs to be done numerically, but by considering that “E _at <kT”, An analytical approximate solution can be obtained. Derivation of this approximate solution will be described.

First, formula (C1) is obtained by substituting equation (9) and (14) into equation (15), further changes to minus infinity to the lower end of the integration range from the energy E _v of the valence band maximum Thus, an expression (C2) that is an approximate expression is obtained.

Here, since the state density of the tail state of the acceptor type defect takes a high value only near the energy E _{c at} the lower end of the conduction band, the integration of the equation (C2) is expressed by the equation (9). Occupancy probability f (E) can be approximated as shown in equation (3).

  Therefore, the equation (C2) can be further approximated as shown in the equation (C4), and as a result, the equation (C5) is obtained.

  Here, by substituting the relational expression of the formula (C6) into the formula (C5), the formula (C7) is obtained, and further transformed, the formula (C8) is obtained.

Further, as shown in the formula (C9), in the formula (C8), when the potential φ = 0, the density N _at0 of the negatively charged acceptor type defect (Tail state) under the flat band condition of the semiconductor film SC. ^- .

Therefore, by using the formula (C9), the formula (C8) can be expressed as the formula (16-1). Furthermore, in the present embodiment, in order to be applicable to a system in a thermally non-equilibrium state, similarly to the electron density n shown in the equation (4-2), the electron pseudo-Fermi potential φ _n is considered, The equation (16-2) in which the potential φ in the equation (16-1) is replaced with (φ−φ _n ) is replaced by the density N _at ^{− of} the negatively charged acceptor type defect (Tail state) shown in the equation (15). It is used as an approximate expression.

[Calculation of Fermi level under flat band condition]
Next, a process for calculating the Fermi level E _f under the flat band condition based on the electrical neutral condition of the semiconductor film SC will be described.

Here, the flat band condition will be described with reference to FIG. As shown in FIG. 3, the flat band condition is a condition in which the energy band in the semiconductor film SC does not bend and becomes flat in the TFT energy band diagram. When the work function of the metal that is the gate electrode G is equal to the work function of the semiconductor film SC and no electric charge is present in the gate insulating film IN, the Fermi level of the metal that is the gate electrode G is obtained under flat band conditions. E _fm is equal to the Fermi rank E _fs of the semiconductor film SC.

Further, when there is a difference between the work function of the metal that is the gate electrode G and the work function of the semiconductor film SC, or when there is a charge in the gate insulating film IN, the energy band in the semiconductor film SC that is generated by these. bending to compensate for the gate voltage V _g necessary for the energy band in the flat is flat band voltage V _fb.

The process of calculating the Fermi level E _f will be continued.
Substituting Equation (3), Equation (4-2), Equation (10), Equation (13-2), and Equation (16-2) into Equation (2), the flat band condition “φ = 0” By setting “ρ = 0” and “φ _n = 0”, which are electrical neutral conditions in the semiconductor film SC, Expression (17) is obtained.

  Then, when Expression (5), Expression (6), Expression (A9), Expression (B10), and Expression (C9) are substituted into Expression (17), Expression (18) is obtained.

Here, the state density g _{dd0 of} the donor type defect (Deep state) at the energy E _v at the upper end of the valence band, the reciprocal number E _dd of the state density distribution of the donor type defect (Deep state), and the energy E at the lower end of the conduction band the state density g _ad0 of the acceptor-type defects in the _c (Deep _state), the acceptor-type defects (Deep state) inverse of the slope E _ad state density _{distribution,} the acceptor-type defects in the energy E _c of the conduction band minimum (Tail state) State density g _at0 , acceptor type defect (Tail state) state density distribution reciprocal number E _at , effective donor density N _d , intrinsic carrier density n _i , intrinsic Fermi level E _i , top of valence band The energy E _v and the energy E _{c at the} lower end of the conduction band are given as device parameters that are design values of the device or intrinsic parameters specific to the material used. The absolute temperature T can be set to an arbitrary value (for example, 300K). Therefore, in Equation (18), the only unknown is the Fermi level E _f .

Therefore, by performing numerical analysis on the equation (18), which is an equation of the Fermi level E _f , for example, by a known method such as Newton method or bisection method, which is a root finding algorithm using iterative calculation, under flat band conditions The Fermi level E _f of can be calculated.

[Calculation of charge carrier density under flat band conditions]
Next, by substituting the Fermi level E _f calculated from the equation (18) into the equations (5), (6), (A9), (B10), and (C9), the semiconductor film SC As the charge carrier density under the flat band condition, the hole density p ₀ , the electron density n ₀ , the positively charged donor type defect (Deep state) density N _dd0 ⁺ , the negatively charged acceptor type defect (Deep state) Density N _ad0 ⁻ and negatively charged acceptor type defect (Tail state) density N _at0 ⁻ are obtained. The potential distribution is calculated using these charge carrier densities.

[Calculation of potential distribution]
The Poisson equation shown in the equation (1) is differentiated, and the solution is obtained by numerical analysis using a known method such as a Gaussian elimination method that is a direct method or a Jacobian method that is an iterative method. Can be sought. Thereby, the potential distribution in the x direction (depth direction) can be calculated.

Here, in order to make a difference, when performing numerical analysis in the semiconductor film SC, for example, assuming an equally spaced mesh, the mesh width is Δx, and the potential distribution φ (x) is discretized in units of Δx. Will be treated as a numerical function. As a result, the potential distribution φ (x) is calculated as a numerical function (sequence) of {φ (0), φ (Δx), φ (2Δx),..., Φ (t _sc )} by numerical analysis. The

Here, with reference to FIG. 4, the boundary condition at the time of solving a Poisson equation is demonstrated.
First, the potential φ at the gate electrode G is defined as a difference “V _gs −V _fb ” between the gate-source voltage V _gs and the flat band voltage V _fb . In addition, the electric flux density is made continuous at the interface (x = 0) between the gate insulating film IN and the semiconductor film SC. Furthermore, assuming that there is a sufficiently thick insulating film layer in a region where “x> t _sc ”, that is, the upper surface side of the semiconductor film SC (see FIG. 1), the electric field E is almost zero at x = t _sc . To be.

[Calculation of carrier density distribution]
The carrier density distribution in the semiconductor film SC can be calculated from the potential distribution obtained by solving the Poisson equation.
In Expression (4-2), when the potential at the position x is φ (x), the carrier density (electron density) n (x) at the position x is given by Expression (19).

[Calculation of carrier surface density]
The carrier surface density N can be calculated by integrating the carrier density n (x) from x = 0 to x = _tsc in the thickness direction, as shown in Expression (20).

  Actually, since the potential distribution is obtained by numerical calculation, the integration in Expression (20) cannot be performed analytically. Therefore, in the semiconductor film SC, assuming an equally spaced mesh when performing numerical calculation, and assuming that the mesh width is Δx, the surface density N of carriers can be calculated as shown in Equation (21).

[Calculation of drain current]
The drain current I _d is given as the sum of the diffusion current component I _diff and the drift current component I _drift as shown in Expression (23). Here, in the y direction which is the channel length direction, if the source end is set to y = 0, the drain end is set to y = L, and the electric field in the y direction is approximated in the x direction (depth direction), the diffusion current is approximated. The component I _diff and the drift current component I _drift can be expressed as Equation (24) and Equation (25), respectively.
In Expression (24), N (y) is the surface density of carriers at the position y in the channel length direction. In Expression (25), φ _s (y) is the relationship between the gate insulating film IN and the semiconductor film SC at the position y. This is the potential (surface potential) at the interface (x = 0).

First, when the diffusion current component I _diff shown in Expression (24) is integrated with respect to y, Expression (26) is obtained. Here, N _L is the carrier surface density at y = L, and N ₀ is the carrier surface density at y = 0. The diffusion current component I _diff is given as shown in Expression (27).
In Expression (27), Q _L and Q ₀ are carrier surface charge densities at y = L and y = 0, respectively, and a relationship of Q ₀ = −qN ₀ and Q _L = −qN _L is established.

Next, when the drift current component I _drift shown in Expression (25) is integrated with respect to y, Expression (28) is obtained. Here, φ _sL and φ _s0 are potentials at the interface (x = 0) between the gate insulating film IN and the semiconductor film SC at y = L and y = 0, respectively. The drift current component I _drift is given by the equation (29).
At this time, the relationship of Q = −qN was used.

By substituting Equation (27) and Equation (29) into Equation (23), the drain current I _d can be expressed as Equation (30). In Expression (30), the first term on the right side represents the diffusion current component, and the second term represents the drift current.

Specifically, the integral calculation of the second term in the equation (30) is performed by the equation (31). In other words, the carrier surface charge density Q and the potential φ _s are replaced with functions discretized in the y direction, respectively, and a product-sum operation between the carrier surface charge density Q and the difference between the potential φ _s as shown in Expression (31). By performing the above, the integral value can be calculated.
In the formula (31), m _y is a positive integer, the drain when discretizing function in the y direction - indicating the division number of the voltage V _ds between source. The more the m _y to a large value, the interval of discretized function is reduced, since it more faithfully represent the original continuous function, it is possible to increase the calculation accuracy.

In the equation (31), the discretized carrier surface charge density Q _r and surface potential φ _{sr at} the r-th position in the y-direction are first expressed as a pseudo-Fermi potential φ _n (r) at the r-th position in the y-direction. Is set according to the equation (32), and the calculation is performed using the potential φ _r (x) obtained by solving the Poisson equation shown in the equation (1). A specific example of calculation will be described later. In Expression (32), ΔV _ds is a calculation interval (width) given by Expression (33) and corresponding to discretization in the y direction. Further, 0-th position is the position of y = 0 (source end), m _y-th position is the position of y = L (drain terminal).

Next, a specific example of the calculation of Expression (31) will be described. First, according to the equation (33), for example, when V _ds = 10 [V] and ΔV _ds = 0.2 [V], the division number m _y = 50, and the drain current at a certain gate voltage V _g In order to calculate I _d , 51 conditions including the starting point (φ _n (r) = 0, 0.2, 0.4, 0.6,..., 9.6, 9.8, 10 [V ]) To solve the Poisson equation. In the case of this example, by solving the Poisson equation under 51 conditions, the one-dimensional potential φ at 51 positions in the y direction is converted into a discrete function φ _r (x) (r is from 0 to 50). X is a discrete value determined by the interval Δx from 0 to t _sc .

Next, by substituting the potential distribution φ _r (x) and the pseudo-Fermi potential φ _n (r) into φ (x) and φ _n in the equation (19), respectively, the carrier density n at the r-th position in the y direction. _r (x) is obtained. Then, as an integration calculation in which the carrier density n _r (x) is substituted into n (x) of the equation (20), the product surface density at the r-th position in the y direction is obtained by performing the product-sum operation of the equation (21). _Nr is obtained. Further, the carrier surface charge density Q _{r at} the r-th position in the y direction is obtained by multiplying the carrier surface density N _r by the negative elementary charge (−q).

for the position r = 0 to m _y in the y-direction, the carrier surface charge density _{Q r,} and the potential phi _r (0) is a potential phi _sr at x = 0 calculated previously, by substituting the equation (31) , The integral value of the second term on the right side of Equation (30) can be obtained.
It should be noted that the carrier surface charge densities Q ₀ and Q _L in the first term on the right side of the equation (30) are the carrier surface charge densities Q _r for the integral calculation in the second term, where r = 0 and r = 50, respectively. The value calculated as the carrier surface charge density in this case can be used.
Through the above calculation process, the drain current I _d can be calculated with respect to the drain-source voltage V _ds of an arbitrary magnitude.

In addition, by changing the value of the gate voltage V _g set when calculating the drain current I _d in various _ways and calculating the corresponding drain current I _d , the gate voltage dependence of the drain current I _d (drain Current characteristics) can be calculated. Similarly, the value of the drain voltage V _d variously changed, it is also possible to calculate the drain voltage dependence of the drain current I _d.
Here, the value of the gate voltage V _g is the drain current calculation process, used to define the boundary conditions for calculating a potential distribution φ (x). That is, it is used to calculate the potential φ = V _gs −V _fb = (V _g −V _s ) −V _fb at the gate electrode G.

When the drain-source voltage V _ds is small (about 1 to several [V] or less), the carrier density distribution can be regarded as gradually changing with respect to the y direction which is the channel length direction. The relational expression (34) can be used. Then, by using the relational expression of Expression (34), Expression (30) can be approximated as Expression (35).

The range of application of Equation (35) is that the drain-source voltage V _ds is limited to a voltage of about 1 to several [V] or less, but for calculating the drain current I _d at a certain gate voltage V _g . _Can solve the Poisson equation only under the two conditions of the source end (y = 0, φ _n = 0) and the drain end (y = L, φ _n = V _ds ). That is, the one-dimensional potential φ at two locations of the source end and the drain end, which are both ends in the channel length direction of the semiconductor film SC, may be calculated. Therefore, the drain current I _d when the drain-source voltage V _ds is the above-described low voltage can be calculated in a shorter time compared to the case where the equation (30) is used.

Further, the approximation is further advanced, and there are relationships shown in the equations (36) and (37) with respect to the carrier surface charge densities Q ₀ and Q _L and the surface potentials φ _s0 and φ _sL at the source end and the drain end, respectively. Shall. By substituting these relational expressions into Expression (35), an approximate expression of Expression (38) can be obtained.

Here, when the carrier surface density at the source end (y = 0) is N ₀ , the relationship of Expression (39) is established. Then, by substituting equation (39) into equation (38), an approximate equation of equation (40) can be obtained.

When the drain current I _d is calculated using the approximate expression shown in the equation (40), in order to calculate the carrier surface density N ₀ at the source end, at the source end (y = 0, φ _n = 0). Only solve the Poisson equation. That is, a one-dimensional potential φ at the source end may be calculated. Therefore, as compared with the case of using the equation (35) can calculate the drain current I _d in a shorter time.

(Influence of parasitic resistance)
Further, as shown in FIG. 5, if there is a parasitic resistance in the transistor, that is, when it is impossible to ignore the influence of the parasitic resistance, it is necessary to calculate the drain current I _d in consideration of the influence. In the example shown in FIG. 5, it is assumed that the source electrode side and the drain electrode side have parasitic resistances having the same resistance value R.

Since the drain current _Id flows through the parasitic resistance R, a voltage drop occurs. Therefore, the voltage actually applied between the drain and source of the transistor is the drain electrode D and the source electrode S (see FIG. 1) between the terminals. It becomes smaller than the voltage ( _Vds ) applied between. Here, assuming that the drain-source voltage actually applied to the transistor is V _{ds -eff} and the magnitude of the parasitic resistance is R, the relationship of Expression (41) is established as can be seen from FIG.
Further, in consideration of the influence of the parasitic resistance in the calculation formula of the drain current I _d shown in the formula (40), the formula (40) shows that the drain-source voltage V _ds is an effective drain-source voltage V _ds-. Instead of _eff , it can be expressed as in equation (42).
Then, by substituting Equation (41) into Equation (42) and rearranging, Equation (43) showing the relationship between the drain-source voltage _Vds and the effective drain-source voltage _Vds-eff. Is obtained.

When considering the influence of the parasitic resistance, when calculating the pseudo-Fermi potential φ _n (r) using the equations (32) and (33), the drain-source voltage V _ds is calculated using the equation (43). The calculation is performed by replacing the calculated effective drain-source voltage V _ds-eff . Then, by solving the Poisson equation using this pseudo-Fermi potential φ _n (r), the influence of the parasitic resistance can be taken into the calculation of the potential distribution.

  Next, referring to FIG. 6 (refer to FIG. 1 as appropriate), a drain current simulation apparatus (hereinafter referred to as a simulation apparatus as appropriate) that performs drain current simulation using the drain current calculation method of the present invention described above. explain.

[Configuration of simulation device]
As shown in FIG. 6, the simulation apparatus (drain current simulation apparatus) 1 in this embodiment includes a device parameter input means 10, a Fermi level calculation means 11, a charge carrier density calculation means 12, a calculation range setting means 13, a potential. A distribution calculating means 14, a carrier density distribution calculating means 15, a carrier surface density calculating means 16, a drain current calculating means 17, a parameter storing means 18, a charge carrier density storing means 19 and a drain current storing means 20 are provided.

The simulation apparatus 1 can be configured by dedicated hardware, but a program (drain current) that realizes the above-described means for calculating the drain current in a general computer such as a personal computer (personal computer). This can be realized by executing the simulation program. In the present embodiment, a drain current simulation apparatus 1 is realized by causing a personal computer to execute a drain current simulation program.
Hereinafter, each means will be described in detail.

Device parameter input means 10, via an input means such as a keyboard (not shown), and inputs the device parameters is a parameter indicating the structure and characteristic values of the devices required for the calculation of the drain current I _d. The device parameter input unit 10 stores the input device parameters in the parameter storage unit 18.

The device parameters to be input, the thickness t _sc of the semiconductor film _SC, the gate thickness t _in the insulating film _IN, the channel length L, the channel width W, the donor type defects (Deep state of the energy E _v of the valence band maximum ) State density g _dd0 , donor-type defect (Deep state) state density distribution reciprocal E _dd , acceptor-type defect state density g _ad0 at the conduction band bottom energy E _c , acceptor-type defect (Deep state) inverse of the slope E _ad state density distribution of _the slope of the density of states distribution in the density of states of the acceptor-type defects in the energy E _c of the conduction band minimum (Tail state) g _at0, the acceptor-type defects (Tail state) inverse _{E at} the include flat band voltage _{V fb} and effective donor density _{N d.}

In the present embodiment, the intrinsic Fermi level E _i , intrinsic carrier density n _i , valence band upper end energy E _v , conduction band lower end energy E _c , mobility μ, dielectric constant ε _sc for the semiconductor film SC. The dielectric constant ε _in of the gate insulating film IN is stored in advance in the parameter storage means 18 as a unique parameter unique to the material used. Further, for the source voltage V _s which is one of the calculation conditions, for example, a predetermined value (for example, 0 [V]) is stored in the parameter storage unit 18.
Hereinafter, the device parameters, unique parameters, and the like are collectively referred to as “device parameters”.

  The device parameter input means 10 may input device parameters via a storage medium such as an optical disk, a magnetic disk, or a flash memory in addition to the keyboard described above, or a LAN (Local Area Network) or the like. You may make it input via a communication line.

The Fermi level calculation means 11 calculates the Fermi level E _f under the flat band condition of the semiconductor film SC using the device parameters and the like stored in the parameter storage means 18, and uses the calculated Fermi level E _f This is output to the charge carrier density calculating means 12.

Specifically, the Fermi level calculation means 11 substitutes device parameters and the like into the above equation (18), and numerically analyzes the equation (18) by the Newton method, the bisection method, or the like, thereby obtaining the Fermi level of the semiconductor film SC. The level E _f is calculated.

The charge carrier density calculating means 12 uses the Fermi level E _f input from the Fermi level calculating means 11, and the density N _dd0 ⁺ of a positively charged donor-type defect (Deep state) in the flat band condition of the semiconductor film SC. The negatively charged acceptor type defect (Deep state) density N _ad0 ⁻ , the negatively charged acceptor type defect (Tail state) density N _at0 ⁻ , the hole density p ₀ and the electron density n ₀ were calculated. These charge carrier densities are stored in the charge carrier density storage means 19.

Specifically, the charge carrier density calculating means 12 substitutes the Fermi level E _f into the above-described equations (5), (6), (A9), (B10), and (C9). In the flat band condition of the semiconductor film SC, the hole density p ₀ , the electron density n ₀ , the positively charged donor-type defect (Deep state) density N _dd0 ⁺ , and the negatively charged acceptor-type defect (Deep state), respectively. Density N _ad0 ⁻ and negatively charged acceptor type defect (Tail state) density N _at0 ⁻ are calculated. When device parameters or the like are required for calculating these charge carrier densities, the charge carrier density calculation unit 12 refers to the device parameters stored in the parameter storage unit 18 as appropriate.

Calculation range setting means 13, when calculating a potential distribution by solving the Poisson equation, the range of the gate voltage V _g was entered via a keyboard (not shown), in calculating the potential distribution, entered the gate voltage Various gate voltages _Vg and drain voltages _{Vd in} the range of _Vg and drain voltage _Vd are set as calculation conditions. The calculation range setting unit 13 sets the gate voltage _Vg and the drain voltage _Vd in the potential distribution calculation unit 14 as calculation conditions.

Specifically, calculation range setting unit 13, as the setting range of the gate voltage V _g, the input initial value V _g0 of the gate voltage, and the maximum value V _gmax of the gate voltage, and a distance [Delta] V _g varying the gate voltage To do. Then, the calculation range setting means 13 sequentially _selects V _g0 , V _g0 + ΔV _g , V _g0 + 2 × ΔV _g ,... Based on the input initial value V _g0 , maximum value V _gmax , and interval ΔV _{g. ..} , V _gmax is set in the potential distribution calculating means 14 as the gate voltage V _g .
Similarly, the drain voltage _{V d,} as the setting range of the drain voltage _{V d,} and inputs the initial value _{V d0} of the drain voltage, and the maximum value _{V dmax} of the drain voltage, and a distance [Delta] V _d for varying the drain voltage. Then, the calculation range setting means 13 sequentially _selects V _d0 , V _d0 + ΔV _d , V _d0 + 2 × ΔV _d ,... Based on the input initial value V _d0 , maximum value V _dmax , and interval ΔV _{d. ..} , V _dmax , and set in the potential distribution calculation means 14 as the drain voltage V _d .

The potential distribution calculation unit 14 is configured to determine the gate voltage V set by the calculation range setting unit 13 based on the charge carrier density stored in the charge carrier density storage unit 19 and the device parameters stored in the parameter storage unit 18. The potential distribution φ (x) in the depth direction of the semiconductor film SC at _g and the drain voltage V _d is calculated, and the calculated potential distribution φ (x) is output to the carrier density distribution calculating means 15.

Specifically, the potential distribution calculating means 14 has a positive charge donor density (Deep state) density N _dd0 ⁺ as a charge carrier density, a negative charge acceptor type defect (Deep state) density N _ad0 ⁻ , The density N _at0 ^{− of} negatively charged acceptor type defects (Tail state), the hole density p ₀ and the electron density n ₀ , the necessary device parameters, etc., and the gate voltage V _g and the drain voltage V _{d as} calculation conditions To calculate equation (1). At this time, Formula (2), Formula (3), Formula (4-2), Formula (10), Formula (13-2), and Formula (16-2) are also used. Further, the Poisson equation shown in the equation (1) is differentiated, and the potential distribution φ (x) is calculated by numerically analyzing the differentiated Poisson equation by the Gaussian elimination method, the Jacobian method, or the like.

Here, the potential distribution calculation means 14 indicates that the potential φ (−t _in ) at the gate electrode G is the difference between the gate-source voltage V _gs (V _gs = V _g −V _s ) and the flat band voltage V _fb ( The potential distribution φ (x) is calculated with a boundary condition equal to V _gs −V _fb ).

The carrier density distribution calculating unit 15 stores the potential distribution φ (x) input from the potential distribution calculating unit 14, the electron density n ₀ stored in the charge carrier density storing unit 19, and the parameter storing unit 18 in Expression (19). By substituting the stored device parameters and the like, the carrier density distribution (electron density distribution) n (x) is calculated.
The carrier density distribution calculating unit 15 outputs the calculated carrier density distribution n (x) to the carrier surface density calculating unit 16.

The carrier surface density calculating unit 16 calculates the carrier density n (x) input from the carrier density distribution calculating unit 15 from the lower end (x = 0) that is the entire range in the depth direction of the semiconductor film SC according to the equation (20). The carrier surface density N is calculated by integrating up to the upper end (x = t _sc ).

Specifically, the carrier surface density calculating unit 16 calculates the carrier surface density N by numerical integration with the mesh width as Δx, as shown in Expression (21).
The carrier surface density calculating unit 16 outputs the calculated carrier surface density N to the drain current calculating unit 17.

The drain current calculation means 17 substitutes the carrier surface density N input from the carrier surface density calculation means 16 and the device parameters stored in the parameter storage means 18 into the equation (30) or the equation (35), The drain current _Id is calculated.

The drain current calculation unit 17 stores the calculated drain current I _d in the drain current storage unit 20 in association with the gate voltage V _g and the drain voltage V _d which are calculation conditions.
The drain current calculation unit 17, the drain current I _d, instead of the gate voltage V _g, the gate - may be in association with the source voltage V _gs is stored in the drain current storage means 20. The drain current calculation means 17, the drain current I _d, instead of the drain voltage V _d, the drain - may be in association with the source voltage V _ds is stored in the drain current storage means 20.

Parameter storage means 18, the device parameter input unit 10 is a device parameters entered semiconductor film SC thickness t _sc, the thickness t _in the gate insulating film _IN, the channel length L, the channel width W, of the valence band maximum The state density g _{dd0 of} the donor type defect (Deep state) at the energy E _v , the reciprocal E _dd of the state density distribution of the donor type defect (Deep state), and the acceptor type defect (Deep) at the energy E _c at the bottom of the conduction band state density g _ad0 , acceptor-type defect (Deep state) state density distribution reciprocal number E _ad , acceptor-type defect (Tail state) state density g _at0 , acceptor-type _energy density E _c It stores the reciprocal number E _at of the state density distribution of the defect (Tail state), the flat band voltage V _fb, and the effective donor density N _d .

Further, the parameter storage means 18 includes intrinsic Fermi level E _i , intrinsic carrier density n _i , valence band upper end energy E _v , conduction band lower end energy E _c , mobility of the semiconductor film SC as other parameters. It is assumed that μ, the dielectric constant ε _sc, and the dielectric constant ε _in of the gate insulating film IN are stored in advance as eigenvalues specific to the material to be used.

The parameter storage unit 18 stores in advance predetermined values as the source voltage V _s and the absolute temperature T, which are other calculation conditions. Furthermore, a Boltzmann constant k and an electric elementary quantity q, which are constants, are stored in advance.

  The device parameters and the like stored in the parameter storage means 18 are Fermi level calculation means 11, charge carrier density calculation means 12, potential distribution calculation means 14, carrier density distribution calculation means 15, carrier surface density calculation means 16, and drain current. Referenced by the arithmetic means 17 as appropriate.

The charge carrier density storage means 19 is a charge carrier density calculated by the charge carrier density calculation means 12, which is a positively charged donor type defect (Deep state) density N _dd0 ⁺ , a negatively charged acceptor type defect (Deep). state) density N _ad0 ⁻ , negatively charged acceptor type defect (Tail state) density N _at0 ⁻ , hole density p _0, and electron density n ₀ are stored. These data are referred to by the potential distribution calculation means 14 and the carrier density distribution calculation means 15.

Drain current storage means 20, the drain current I _d calculated by the drain current calculation unit 17 is configured to store in association with the drain current I gate voltage is calculated condition _d V _g and the drain voltage V _d.

The drain current I _d which are stored in the drain current storage means 20, for example, the threshold voltage V _th and the sub-threshold coefficient which is a characteristic value of the TFT (S value) is utilized for the calculation of such. In addition, the graph drawing means (not shown) can be output to display means or printing means connected to the computer and displayed as a graph of drain current characteristics (see, for example, FIGS. 8 to 11).

  In the present embodiment, the device parameters input by the device parameter input means 10 are temporarily stored in the parameter storage means 18 and read out as appropriate by calculation means such as the Fermi level calculation means 11. The means 10 may output the input device parameters directly to the necessary calculation means.

The unique parameter may be input by the device parameter input unit 10 together with the device parameter. Furthermore, the source voltage V _s, which is one of the calculation conditions, may be input by the device parameter input unit 10 or the calculation range setting unit 13.

In the present embodiment, the charge carrier density such as the density N _dd0 ^{+ of} the positively charged donor-type defect (Deep state) calculated by the charge carrier density calculating unit 12 is temporarily stored in the charge carrier density storage unit 19. However, the charge carrier density calculating means 12 may output the calculated charge carrier density directly to the potential distribution calculating means 14 or the like.

  The drain current simulation apparatus according to the present invention includes hardware resources such as a CPU (Central Processing Unit), a memory, and a hard disk included in a general computer, and each means of the device parameter input means 10 to the drain current storage means 20. It can also be realized by a drain current simulation program for functioning as This program may be distributed via a communication line, or may be recorded and distributed on a recording medium such as a CD-ROM or a flash memory.

[Operation of simulation device]
Next, referring to FIG. 7 (refer to FIGS. 1 and 6 as appropriate), the operation of the drain current simulation apparatus 1 in this embodiment will be described.

  First, the simulation apparatus 1 inputs device parameters for a TFT to be simulated by the device parameter input unit 10 and stores the device parameters in the parameter storage unit 18 (step S10).

Next, the simulation apparatus 1 uses the device parameters stored in the parameter storage unit 18 by the Fermi level calculation unit 11 to calculate the Fermi level of the semiconductor film SC under the flat band condition according to the equation (18). E _f is calculated, and the calculated Fermi level E _f is output to the charge carrier density calculating means 12 (step S11).

Next, the simulation apparatus 1 uses the Fermi level E _f calculated by the Fermi level calculation unit 11 and the device parameters stored in the parameter storage unit 18 by the charge carrier density calculation unit 12 and the formula ( 5), Formula (6), Formula (A9), Formula (B10), and Formula (C9), the charge carrier density in the flat band condition of the semiconductor film SC is the hole density p ₀ , electron density n ₀ , positive the density of charged donor-type defect density _{N dd0} ^+, negatively charged acceptor type defects (Deep state) (Deep state) in _{N ad0} ^- and density _{N at0} negatively charged acceptor-type defects (Tail state) ^- a The calculated values are stored in the charge carrier density storage means 19 (step S12).

Next, the simulation apparatus 1 uses the calculation range setting means 13 as data for determining the setting range of the drain voltage V _d when calculating the potential distribution φ (x), and the drain voltage initial value V _d0 and the drain voltage. and the maximum value _{V dmax} of the distance [Delta] V _d for varying the drain voltage, entered from the keyboard (not shown), sets the initial value _{V d0} in the potential distribution calculating unit 14 as the drain voltage _{V d} (step S13).

Next, the simulation apparatus 1 uses the calculation range setting means 13 as data for determining the setting range of the gate voltage V _g when calculating the potential distribution φ (x), and the gate voltage initial value V _g0 and the gate voltage. and the maximum value _{V gmax} of the interval [Delta] V _g varying the gate voltage, entered from the keyboard (not shown), sets the initial value _{V g0} to the potential distribution calculating means 14 as the gate voltage _{V g} (step S14).

Next, the simulation apparatus 1 uses the potential distribution calculation unit 14 to store the positively charged donor-type defect ( _Neep state) density N _dd0 ⁺ stored in the charge carrier density storage unit 19 and the negatively charged acceptor-type defect. (Deep state) density N _ad0 ⁻ , negatively charged acceptor type defect (Tail state) density N _at0 ⁻ , hole density p ₀ , electron density n ₀ , device parameters stored in parameter storage means 18, etc. , The Poisson equation shown in the equation (1) is differentiated to calculate the potential distribution φ (x) at the gate voltage V _g and the drain voltage V _d set by the calculation range setting means 13, and the calculated potential The distribution φ (x) is output to the carrier density distribution calculating means 15 (step S15).

  Next, the simulation apparatus 1 uses the carrier density distribution calculation means 15 to calculate the potential distribution φ (x) calculated by the potential distribution calculation means 14, the charge carrier density and parameter storage means 18 stored in the charge carrier density storage means 19. Is used to calculate the carrier density distribution n (x) according to the equation (19), and outputs the calculated carrier density distribution n (x) to the carrier surface density calculating means 16 ( Step S16).

  Next, the simulation apparatus 1 uses the carrier surface density calculation unit 16 to calculate the equation using the carrier density distribution n (x) calculated by the carrier density distribution calculation unit 15 and the device parameters stored in the parameter storage unit 18. The carrier surface density N is calculated by (20), and the calculated carrier surface density N is output to the drain current calculation means 17 (step S17).

Next, the simulation apparatus 1 uses the drain current calculation unit 17 to calculate the equation (30) or the carrier surface density N calculated by the carrier surface density calculation unit 16 and the device parameter stored in the parameter storage unit 18. The drain current I _d is calculated by the equation (35), and the calculated drain current I _d is stored in the drain current storage unit 20 in association with the gate voltage V _g and the drain voltage V _d which are the calculation conditions (step S35). S18).

Then, the simulator 1, the computation range setting unit 13, the calculation conditions, in order to change the gate voltage V _g at the time of calculating the next drain current I _d, the previous gate voltage V _g, the calculated adding the interval [Delta] V _g, to set the potential distribution calculating unit 14 (step S19).

Then, the simulator 1, the computation range setting means 13, the gate voltage _{V g} was condition change in step S19 is to determine if the maximum value _{V gmax} is greater than the calculated range (step S20), the condition in step S19 When the changed gate voltage V _g is equal to or lower than the maximum value V _gmax of the calculation range (No in step S20), the simulation apparatus 1 returns to step S15 and calculates the potential distribution for the gate voltage V _g set in step S19. The calculation of the potential distribution φ (x) by means 14 is repeated.
On the other hand, if it is larger the process proceeds to step S21 for changing the (Yes in step S20), the condition of the drain voltage _{V d.}

In step S21, the simulator 1, the computation range setting unit 13, the calculation conditions, in order to change the drain voltage V _d when calculating the next drain current I _d, the last time of the drain voltage V _d, calculated adding the interval [Delta] V _d, it is set to the potential distribution calculating unit 14 (step S21).

Next, the simulation apparatus 1 determines whether or not the drain voltage V _d whose condition has been changed in step S21 is greater than the maximum value V _dmax of the calculation range by the calculation range setting unit 13 (step S22). When the changed drain voltage V _d is equal to or lower than the maximum value V _dmax of the calculation range (No in step S22), the simulation apparatus 1 returns to step S14 and returns the condition of the gate voltage V _g to the initial value V _g0. And the calculation of the potential distribution φ (x) by the potential distribution calculation means 14 is repeated for the drain voltage V _d set in step S21.
On the other hand, if it is larger (Yes in step S22), and because the calculation of the drain current I _d finished in a predetermined calculation range, the simulator 1, the process ends.

The obtained drain current characteristics can be displayed in a graph on a display device (not shown), for example (see, for example, FIGS. 8 to 11). Then, whether the drain current characteristic is desired properties, for example, to calculate the threshold voltage V _th and S value check, if the desired properties, such as the gate insulating film thickness t _in and the semiconductor film thickness t _sc The device parameters are changed, the above procedure is repeated, the drain current characteristics are calculated, the device parameters are determined so as to obtain a desired drain current, and the device structure of the TFT can be determined.

Incidentally, those in the present embodiment, the drain voltage V _d is set previously, the drain current V _d, but so as to calculate the drain current I _d by changing the gate voltage V _g, which is limited to is not. The gate voltage V _g is set previously, the gate voltage V _g, may be calculated drain current I _d by changing the drain current V _d. Also, one of the voltage of the drain voltage V _d or the gate voltage V _g is a fixed value, by varying the other of the voltage to calculate the drain current I _d, so as to calculate the dependence on the other voltage of the drain current It may be.

Next, an example of the drain current simulation apparatus according to the embodiment of the present invention will be described.
As simulation conditions in this example, the semiconductor film was IGZO, and the gate insulating film was SiO ₂ . The channel length L was 80 [μm], and the channel width W was 130 [μm].

FIG. 8 shows the gate voltage dependence of the drain current of the TFT, which was calculated by varying the defect density parameter ( _gad0 ). In this calculation, the gate insulating film thickness t _in = 100 [nm] and the semiconductor film thickness t _sc = 30 [nm]. The vertical axis indicates the drain current _Id on a logarithmic scale, and the horizontal axis indicates the gate-source voltage _Vgs .
In addition, as a parameter of defect density, acceptor type defect (Deep state) state density g _ad0 at energy E _c at the bottom of the conduction band is _set to 0 × 2 × 10 ¹⁹ [cm ⁻³ eV ⁻¹ ] to 5 × 10 ^18. It is set at intervals of [cm ⁻³ eV ⁻¹ ], the reciprocal number E _ad of the state density distribution of the acceptor type defect (Deep state) is 0.1 [eV], and the drain-source voltage V _ds is 1 [V]. It was.

As shown in FIG. 8, as the defect density increases, the increase in the drain current I _d with respect to the increase in the gate voltage V _g (gate-source voltage V _gs ) becomes moderate. This is because carrier capture increases as the defect density increases. From this, it is understood that the influence of the defect is correctly taken into account in the calculation by the simulation apparatus.

Next, FIGS. 9 and 10 show a comparison between the calculation result (solid line) and the actual measurement value (◯) of the drain current characteristic of the TFT. 9, the gate voltage of the drain current I _d - represents a (gate-source voltage) dependent, the vertical axis represents the drain current I _d, a logarithmic scale on the left shows a linear scale on the right. The horizontal axis indicates the gate-source voltage _Vgs . Further, FIG. 10, the drain voltage of the drain current I _d - represents a (drain-source voltage) dependent, the vertical axis represents the drain current I _d in a linear scale, the horizontal axis is the drain - source voltage V _ds is shown. In these calculations, the gate insulating film thickness t _in = 100 [nm] and the semiconductor film thickness t _sc = 30 [nm]. In the calculations shown in FIG. 9 and FIG. 10, the drain current is calculated using the equation (30) with the common device parameters.

In FIG. 9, the results when the gate-source voltage V _gs is changed when the drain-source voltage V _ds is fixed to 1, 3, and 10 [V] are graphed. In FIG. 10, when the gate-source voltage V _gs is fixed to 0, 5, 10, 15 [V], the results when the drain-source voltage V _ds is changed are graphed.
As shown in FIG. 9 and FIG. 10, the calculation results reproduce the actual measurement values in a wide range of gate voltage V _g (gate-source voltage V _gs ) and drain voltage V _d (drain-source voltage V _ds ). The effectiveness of this simulation device is shown.

Next, in FIG. 11, two types of _TFT gate insulating film thickness _{t in} different (t in = 10 [nm] and _{t in = 100 [nm])} , the calculation result of the drain current characteristic (solid line) and measured values A comparison of (○) is shown. Further, the semiconductor film thickness t _sc = 30 [nm], and the drain-source voltage V _ds is 1 [V]. The calculation of the drain current _{I d} is using Equation (35), the gate insulating film thickness _{t in} the two different TFT, and using a common device parameters. The vertical axis represents the drain current _Id on a logarithmic scale, and the horizontal axis represents the gate-source voltage _Vgs .

As shown in FIG. 11, when the gate insulating film thickness is thin (t _in = 10 [nm]), the drain current characteristic has a steep rise. On the other hand, when the gate insulating film is thick (t _in = 100 [nm]), the drain current characteristic has a gentle rise. It can be seen that such a change in drain current characteristics depending on the gate insulating film thickness can be reproduced with high accuracy by this simulation apparatus. Thus, it is shown that this simulation apparatus is effective for the structural design (determination of device parameters) of the TFT.

When the calculation is performed using a general desktop computer (CPU (Central Processing Unit) Intel Core 2 Duo E8400 3.00 GHz installed by Intel), the calculation time in the simulation apparatus of the present invention is as follows. It is.
In the calculation of the gate voltage dependence of the drain current I _d of the TFT having the semiconductor film thickness t _sc = 30 [nm] shown in FIG. 9 using the equation (30), the drain-source voltage V _ds = 10 [V]. A numerical analysis software library LAPACK (Linear Algebra) which is an open software provided with a BSD license (Berkeley Software Distribution License) for numerical calculation is set to Δx = 0.5 [nm] in the semiconductor film SC. when using PACKage), the time required to calculate the gate voltage V _g of 200 points was about 20 seconds.
Further, in the calculation of the gate voltage dependence of the drain current I _d of the TFT having the semiconductor film thickness t _sc = 30 [nm] shown in FIG. 11 using the formula (35), the drain-source voltage V _ds = 1 [ and V], the size of mesh [Delta] x = 0.5 and [nm] in the semiconductor film SC, in the case of using the numerical analysis software library LAPACK numerical calculation, required to calculate the gate voltage _{V g} of 200 points The time was about 0.5 seconds.

Usually, the calculation time of drain current characteristics when using a commercially available two-dimensional device simulator (for example, two-dimensional device simulator “ATLAS” manufactured by SILVACO) is several minutes to several tens of minutes. It can be seen that the calculation by is sufficiently fast and accurate.
From the above, it can be seen that the simulation apparatus of the present invention realizes high-speed and high-accuracy calculation of the drain current I _{d in} a storage-type TFT including defects that trap carriers in the semiconductor film SC.

1 Drain current simulation device (simulation device)
DESCRIPTION OF SYMBOLS 10 Device parameter input means 11 Fermi level calculation means 12 Charge carrier density calculation means 13 Calculation range setting means 14 Potential distribution calculation means 15 Carrier density distribution calculation means 16 Carrier surface density calculation means 17 Drain current calculation means 18 Parameter storage means 19 Charge Carrier density storage means 20 Drain current storage means S Source electrode D Drain electrode G Gate electrode SC Semiconductor film IN Gate insulating film

Claims (5)

The field effect type thin film transistor having a structure in which the object of simulation is a storage type thin film transistor including defects that trap carriers in the semiconductor film, and the semiconductor film, the insulating film, and the gate electrode are stacked in this order. A drain current simulation device for calculating a drain current that is a current between a drain electrode and a source electrode,
Taking into account the electron density, hole density, donor density, and the density of acceptor-type defects and donor-type defects having an exponential density of states in the band gap as the charge density of the semiconductor film, the one-dimensional Poisson equation is solved. A potential distribution calculating means for calculating a potential distribution in the depth direction in the semiconductor film,
Carrier density distribution calculating means for calculating a carrier density distribution in the depth direction in the semiconductor film using the potential distribution calculated by the potential distribution calculating means;
A carrier surface density calculating unit that calculates the carrier surface density in the semiconductor film by integrating the carrier density distribution calculated by the carrier density distribution calculating unit over the entire range in the depth direction of the semiconductor film;
In two or more positions in the channel length direction of the semiconductor film, in the carrier surface charge density obtained by multiplying the carrier surface density calculated by the carrier surface density calculating means by the elementary charge and the potential distribution calculated by the potential distribution calculating means. Drain current calculation means for calculating the drain current using the potential at the interface between the semiconductor film and the insulating film;
A drain current simulation apparatus comprising: Fermi level calculation means for calculating the Fermi level of the semiconductor film under a flat band condition from Equation (18) which is an equation for the Fermi level;
By substituting the Fermi level calculated by the Fermi level calculation means into Equation (5), Equation (6), Equation (A9), Equation (B10), and Equation (C9), the flat band condition of the semiconductor film Hole density, electron density, density of positively charged donor-type defects in deep state, density of negatively-charged acceptor-type defects in deep state, and negatively-charged acceptor type A charge carrier density calculating means for calculating a density in a tail state of the defect as a charge carrier density;
The potential distribution calculation means differentiates the equation (1) which is the one-dimensional Poisson equation, and a gate-source voltage and a flat band voltage in which a potential at the gate electrode is a voltage between the gate electrode and the source electrode. It is calculated by numerical analysis with the boundary condition being equal to the difference between
The carrier distribution density calculating means calculates the carrier density distribution from the equation (19),
The carrier surface density calculating means calculates the carrier surface density distribution by equation (20),
The drain current calculation means calculates the drain current by the equation (30),
Formula (18) is

And
Here, Formula (5), Formula (6), Formula (A9), Formula (B10), and Formula (C9) are

And
The formula (1) is

And
here,

And
The formula (19) is

And
Formula (20) is

And
The formula (30) is

And
here,
β = q / kT,
γ _d = q / E _dd ,
γ _a = q / E _ad ,
And
k is the Boltzmann constant,
T is the absolute temperature,
q is the elementary charge,
ρ is the charge density of the semiconductor film,
p is the hole density of the semiconductor film,
n is the electron density of the semiconductor film,
N _dd ⁺ is the density in the deep state of positively charged donor-type defects in the semiconductor film,
N _ad ⁻ is the density in the deep state of the negatively charged acceptor type defect of the semiconductor film,
N _at ⁻ is the density in the tail state of the negatively charged acceptor type defect of the semiconductor film,
p ₀ is the hole density in the flat band condition of the semiconductor film,
n ₀ is the electron density in the flat band condition of the semiconductor film,
N _dd0 ⁺ is the density in the deep state of positively charged donor-type defects in the flat band condition of the semiconductor film,
N _ad0 ⁻ is the density in the deep state of the negatively charged acceptor type defect in the flat band condition of the semiconductor film,
N _at0 ⁻ is the density in the tail state of the negatively charged acceptor type defect in the flat band condition of the semiconductor film,
g _dd0 is the density of states in the deep state of the donor-type defect at the top of the valence band of the semiconductor film,
g _ad0 is the density of states in the deep state of the acceptor type defect at the lower end of the conduction band of the semiconductor film,
g _at0 is the density of states in the tail state of the acceptor type defect at the lower end of the conduction band of the semiconductor film,
_Ev is the energy at the top of the valence band of the semiconductor film,
E _c is the energy at the lower end of the conduction band of the semiconductor film,
E _f is the Fermi level under the flat band condition of the semiconductor film,
E _dd is the reciprocal of the gradient of the state density distribution in the deep state of the donor-type defect of the semiconductor film,
E _ad is the reciprocal of the slope of the state density distribution in the deep state of the acceptor type defect of the semiconductor film,
E _at is the reciprocal of the slope of the state density distribution in the tail state of the acceptor type defect of the semiconductor film,
n _i is the intrinsic carrier density of the semiconductor film,
E _i is the intrinsic Fermi level of the semiconductor film,
ε _sc is the dielectric constant of the semiconductor film,
t _sc is the film thickness of the semiconductor film,
φ is potential,
φ (x) is the potential distribution,
n (x) is the carrier density distribution,
N is the carrier surface density,
N _d is the effective donor density of the semiconductor film,
x is a position in the thickness direction of the semiconductor film (the interface between the semiconductor film and the insulating film is 0, and the interface between the semiconductor film, the source electrode and the drain electrode is t _sc ),
y is the position in the channel length direction of the semiconductor film (the end of the source electrode on the drain electrode side is 0, and the end of the drain electrode on the source electrode side is L),
L is the channel length of the semiconductor film,
W is the channel width of the semiconductor film,
μ is the mobility of electrons in the semiconductor film,
V _ds is the drain-source voltage,
φ _n is the pseudo-Fermi potential of the electron,
φ _n (y) is the quasi-Fermi potential of the electron at the position y in the channel length direction, and φ _n (0) = 0, φ _n (L) = V _ds ,
I _d is the drain current,
Q is the carrier surface charge density,
Q ₀ is the carrier surface charge density at the position y = 0 in the carrier length direction of the semiconductor film,
Q _L is a carrier surface charge density at a position y = L in the carrier length direction of the semiconductor film,
φ _s is a potential at a position x = 0 in the thickness direction of the semiconductor film,
φ _s0 is a potential at a position x = 0 in the thickness direction of the semiconductor film and a position y = 0 in the channel length direction of the semiconductor film,
φ _sL is a potential at a position x = 0 in the thickness direction of the semiconductor film and a position y = L in the channel length direction of the semiconductor film,
The drain current simulation apparatus according to claim 1, wherein: The drain current calculation means calculates the drain current by an equation (35) instead of the equation (30),
The equation (35) is

The drain current simulation apparatus according to claim 2, wherein: A calculation range setting means for sequentially setting a plurality of the drain-source voltages and / or the gate-source voltages in a predetermined range in the potential distribution calculation means as the potential distribution calculation conditions;
A drain voltage dependency of the drain current in which the drain current calculated based on the potential distribution is associated with the drain-source voltage and / or the gate-source voltage as the calculation condition of the potential distribution, and 4. The drain current simulation apparatus according to claim 2, wherein gate voltage dependency is calculated. The field effect type thin film transistor having a structure in which the object of simulation is a storage type thin film transistor including defects that trap carriers in the semiconductor film, and the semiconductor film, the insulating film, and the gate electrode are stacked in this order. In order to calculate the drain current, which is the current between the drain electrode and the source electrode,
Taking into account the electron density, hole density, donor density, and the density of acceptor-type defects and donor-type defects having an exponential density of states in the band gap as the charge density of the semiconductor film, the one-dimensional Poisson equation is solved. A potential distribution calculating means for calculating a potential distribution in the depth direction in the semiconductor film,
A carrier density distribution calculating means for calculating a carrier density distribution in the depth direction in the semiconductor film using the potential distribution calculated by the potential distribution calculating means;
A carrier surface density calculating unit that calculates the carrier surface density in the semiconductor film by integrating the carrier density distribution calculated by the carrier density distribution calculating unit over the entire range in the depth direction of the semiconductor film;
In two or more positions in the channel length direction of the semiconductor film, in the carrier surface charge density obtained by multiplying the carrier surface density calculated by the carrier surface density calculating means by the elementary charge and the potential distribution calculated by the potential distribution calculating means. Drain current calculation means for calculating the drain current using the potential at the interface between the semiconductor film and the insulating film;
Drain current simulation program to function as

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