JP5906079B2 - Drain current simulation apparatus and drain current simulation program - Google Patents

Description

  The present invention relates to a simulation apparatus for calculating a drain current and a program for the storage type thin film transistor including a defect that traps carriers in a semiconductor.

In the structural design of a semiconductor transistor, it is necessary to determine values of device parameters such as a gate insulating film thickness and a semiconductor film thickness. In addition, when development target values are set for important performance indicators such as a subthreshold coefficient (S value) and threshold voltage (V _th ), the performance indicators and targets should be satisfied. In addition, the value of the device parameter must be determined. In general, a simulation technique is used for the structural design of such a transistor. In order to determine device parameter values efficiently, high-speed and high-accuracy simulation of drain current characteristics is required, and usually a commercially available two-dimensional device simulator (for example, two-dimensional device simulator “ATLAS” manufactured by SILVACO). Is used.

As a specific structure design method, first, drain current characteristics are calculated by simulation, and transistor performance indicators such as a subthreshold coefficient (S value) and a threshold voltage (V _th ) are obtained therefrom. If they do not satisfy the preset conditions, the device parameter values are changed and the simulation is performed again. By repeating this, the value of the device parameter can be determined so that the drain current characteristic satisfies the condition. By such a method, the number of trials of actual elements for transistor structure design can be reduced, and the transistor development period and cost can be reduced.

  On the other hand, an oxide semiconductor such as amorphous InGaZnO (IGZO; indium gallium zinc oxide) is used because of its high mobility compared to amorphous silicon TFT and high uniformity compared to polycrystalline silicon TFT. TFTs are currently attracting attention. Also in the development of such an oxide semiconductor TFT, as described above, calculation of drain current characteristics using a simulation technique is important.

  In recent years, examples of calculating drain current characteristics of IGZO-TFT using a commercially available two-dimensional device simulator have been reported (see Non-Patent Documents 1 and 2).

Hsing-Hung Hsieh, Toshio Kamiya, Kenji Nomura, Hideo Hosono, and Chung-Chih Wu, Appl. Phys. Lett. 92, 133503 (2008) Tze-Ching Fung, Chiao-Shun Chuang, Charlene Chen, Katsumi Abe, Robert Cottle, Mark Townsend, Hideya Kumomi, and Jerzy Kanicki, J. Appl.Phys. 106, 084511 (2009)

  However, in the calculation using the two-dimensional device simulator as described above, the drain current characteristic can be obtained with high accuracy under a wide range of conditions. On the other hand, the simulation takes a long time, and a high specification is required to execute the simulation. There is a problem that a computer is necessary.

  A TFT using an oxide semiconductor is an accumulation-type transistor using a majority carrier that includes a defect of trapping carriers in a semiconductor film. For this reason, a conventional simulation method used for an amorphous silicon TFT or a polycrystalline silicon TFT cannot be directly applied to such a TFT.

  Therefore, the present invention can be applied to a storage type TFT including a defect that traps carriers in a semiconductor film, such as an oxide semiconductor TFT, and can simulate a drain current at high speed. An object is to provide a simulation program.

In order to solve the above-described problem, a drain current simulation apparatus according to claim 1 (hereinafter, referred to as a simulation apparatus as appropriate) is a storage-type thin film transistor including a defect that traps carriers in a semiconductor film, and includes a semiconductor In a field effect thin film transistor having a structure in which a film, an insulating film, and a gate electrode are stacked in this order, when the drain-source voltage, which is the voltage between the drain electrode and the source electrode, is low, the drain electrode and the source A drain current simulation device for calculating a drain current which is a current between electrodes, a potential distribution calculation unit, a carrier density distribution calculation unit, a carrier surface density calculation unit, a drain current calculation unit, a Fermi quasi A position calculating means and a charge carrier density calculating means are provided .

  According to such a configuration, the simulation apparatus uses the potential distribution calculation means to accept the electron defect, the hole density, the donor density, and the acceptor type defect and the donor having an exponential state density in the band gap as the charge density of the semiconductor film. Considering the density of mold defects, the potential distribution in the depth direction in the semiconductor film is calculated by solving the one-dimensional Poisson equation. Thereby, the simulation apparatus calculates the potential distribution at high speed.

Next, the simulation apparatus calculates the carrier density distribution in the depth direction in the semiconductor film by using the potential distribution calculated by the potential distribution calculating means by the carrier density distribution calculating means. Next, the simulation apparatus calculates the carrier surface density in the semiconductor film by integrating the carrier density distribution calculated by the carrier density distribution calculating unit over the entire range in the depth direction of the semiconductor film by the carrier surface density calculating unit. The simulation apparatus multiplies the carrier surface density calculated by the carrier surface density calculating unit by the drain current calculating unit by the mobility, the elementary charge, the drain-source voltage, and the ratio of the channel width and the channel length. Calculate the drain current.
As a result, the simulation apparatus calculates the potential distribution at high speed, and as a result, calculates the drain current at high speed.

Further , the simulation apparatus calculates the Fermi level under the flat band condition of the semiconductor film from the equation (18) which is an equation for the Fermi level by the Fermi level calculation means. Next, the simulation apparatus calculates the Fermi level calculated by the Fermi level calculation means by the charge carrier density calculation means by using the expressions (5), (6), (A9), (B10), and (C9). ), The hole density, the electron density, the density of positively charged donor-type defects in the deep state (Deep state), and the deep state of negatively-charged acceptor-type defects (in the flat band condition of the semiconductor film) The density in the deep state and the density in the tail state of the negatively charged acceptor type defect are calculated as the charge carrier density.

  Next, the simulation apparatus differentiates Equation (1), which is a one-dimensional Poisson equation, by the potential distribution calculation means, and the potential at the gate electrode is equal to the difference between the voltage between the gate electrode and the source electrode and the flat band voltage. With this as a boundary condition, the potential distribution is calculated by numerical analysis. Further, when calculating the potential distribution, the charge carrier density in the flat band condition of the semiconductor film calculated by the charge carrier density calculating means is used.

  Next, the simulation apparatus calculates the carrier density distribution from the equation (19) by the carrier density distribution calculating unit, and further calculates the carrier density distribution by the equation (20) by the carrier surface density calculating unit. The simulation apparatus calculates the drain current by the drain current calculation means.

  Here, the equation (18) is

である。

It is.

  Moreover, Formula (5), Formula (6), Formula (A9), Formula (B10), and Formula (C9) are:

である。

It is.

  Moreover, Formula (1) is

It is. Here, the charge density ρ of the semiconductor film is expressed by the formula (2), and further, the hole density p, the electron density n of the semiconductor film, the density N _dd ⁺ in the deep state of the positively charged donor type defect, and negative The density N _ad ⁻ in the deep state of the acceptor type defect charged in the negative state and the density N _at ⁻ in the tail state of the acceptor type defect negatively charged are respectively expressed by the equations (3), (4), (10), and (13) and equation (16). In addition, since Formula (10), Formula (13), and Formula (16) are approximate formulas, they contribute to speeding up of potential calculation.

  Moreover, Formula (19) and Formula (20) are given as follows.

In the above, β = q / kT, γ _d = q / E _dd , and γ _a = q / E _ad .
K is a Boltzmann constant, T is an absolute temperature, and q is an elementary electric quantity.
Furthermore, ρ is the charge density of the semiconductor film, p ₀ is the hole density in the flat band condition of the semiconductor film, n ₀ is the electron density in the flat band condition of the semiconductor film, and N _dd0 ⁺ is positively charged in the flat band condition of the semiconductor film. The density of donor-type defects in the deep state, N _ad0 ⁻ is the density of negatively charged acceptor-type defects in the flat band condition of the semiconductor film, and N _at0 ⁻ is the negatively charged acceptor in the flat band condition of the semiconductor film. Density in the tail state of the type defect, g _dd0 is the density of states in the deep state of the donor type defect at the upper end of the valence band of the semiconductor film, and g _ad0 is the density of states in the deep state of the acceptor type defect in the lower end of the conduction band of the semiconductor film. , _Gat0 is the value at the bottom of the conduction band of the semiconductor film. State density at the tail state of Kuseputa type defects, E _v is the valence band upper end of the energy of the semiconductor film, E _c is the conduction band minimum energy of the semiconductor film, E _f is the Fermi level of a flat band condition of the semiconductor film, E _dd is the reciprocal of the slope of the state density distribution in the deep state of the donor-type defect of the semiconductor film, E _ad is the reciprocal of the slope of the state density distribution in the deep state of the acceptor-type defect of the semiconductor film, and E _at is the acceptor type of the semiconductor film. The reciprocal of the slope of the state density distribution in the defect tail state, n _i is the intrinsic carrier density of the semiconductor film, E _i is the intrinsic Fermi level of the semiconductor film, ε _sc is the dielectric constant of the semiconductor film, and t _sc is the film of the semiconductor film thickness, phi is the potential, φ (x) is the potential distribution, n (x) is the carrier density distribution, n is the carrier surface density, n _d is the semiconductor An effective donors density. X indicates the position in the thickness direction of the semiconductor film.

A simulation apparatus according to a second aspect is the simulation apparatus according to the first aspect , further comprising calculation range setting means.

  According to such a configuration, the simulation apparatus sequentially sets a plurality of gate voltages in a predetermined range as potential distribution calculation conditions in the potential distribution calculation unit by the calculation range setting unit. Next, the simulation apparatus calculates a potential distribution at the gate voltage by the potential distribution calculation means. Then, the simulation apparatus calculates the drain current by the drain current calculation means described above. The simulation apparatus sequentially changes the gate voltage in a predetermined range by the calculation range setting means, and calculates the drain current corresponding to the sequentially set gate voltage by the drain current calculation means. Thus, the simulation apparatus calculates the gate voltage dependency of the drain current in which the drain current is associated with the gate voltage as the calculation condition of the potential distribution that is the basis of the calculation.

Simulation program of the drain current according to claim 3, a computer, a program to function as the simulation apparatus according to claim 1 or claim 2.

According to the first or third aspect of the present invention, the potential distribution in the depth direction of the semiconductor film is calculated for the storage type TFT including the defect that traps carriers in the semiconductor film, and the one-dimensional potential is calculated. Since the drain current is calculated based on the distribution, the basic characteristics of the drain current can be calculated at high speed and with high accuracy without using a high-spec computer. Furthermore , one-dimensional including the density of donor-type defects with exponential state density in the band gap in the deep state, the density of acceptor-type defects in the deep state, and the density of acceptor-type defects in the tail state Since the potential distribution was calculated by numerical analysis of the Poisson equation and the drain current was calculated using the result, the basic characteristics of the drain current for the storage type TFT including defects that trap carriers in the semiconductor film were obtained. It is possible to calculate with high speed and high accuracy.
According to the invention described in claim 2 or claim 3 , the gate voltage dependence characteristic of the drain current can be calculated for the accumulation type TFT including the defect that traps carriers in the semiconductor film.

It is typical sectional drawing which shows the structure of TFT which is calculation object in embodiment of this invention. It is a figure which shows the state density distribution in the band gap of the defect of the semiconductor film in TFT which is calculation object in embodiment of this invention. It is a figure for demonstrating flat band conditions about TFT which is the calculation object in embodiment of this invention. It is a figure for demonstrating the boundary condition at the time of solving a Poisson equation about TFT which is a calculation object in embodiment of this invention. It is a block diagram which shows the structure of the simulation apparatus of the drain current in embodiment of this invention. It is a flowchart which shows the flow of a process of the simulation apparatus of the drain current in embodiment of this invention. It is a figure which shows an example of the calculation result of a drain current characteristic using the simulation apparatus of the drain current in embodiment of this invention, and an actual value, (a) And (b) was calculated using different device parameters, respectively. It is an example. It is a figure which shows the other example of the calculation result of the drain current characteristic using the simulation apparatus of the drain current in embodiment of this invention, (a) and (b) are the examples calculated using different device parameters, respectively. is there.

  Embodiments of the present invention will be described below with reference to the drawings as appropriate. Here, an n-type storage TFT will be described.

[Drain current calculation method]
First, a method for calculating the drain current will be described.
FIG. 1 schematically shows a cross section of a TFT for explaining a drain current calculation method in the present invention. In the TFT, a source electrode S and a drain electrode D are provided at both ends in the left-right direction of the semiconductor film SC in the drawing, respectively. In the drawing, a gate electrode G is formed below the semiconductor film SC with a gate insulating film IN interposed therebetween. This is a bottom-gate, top-contact type field effect transistor (FET) provided. In this embodiment, a bottom gate and top contact type TFT will be described as an example. However, a TFT to which the present invention can be applied is not limited to this structure.

_{Here, t sc} is the thickness of the semiconductor film SC, L is the channel length of the semiconductor film _{SC, t in} is the thickness of the gate insulating film IN. In the coordinate system, the vertical direction of the drawing, which is the thickness direction (also referred to as the depth direction) of the semiconductor film SC, is the x direction, and the horizontal direction of the drawing, which is the channel length direction, is the y direction. The coordinates in the x direction are x = 0 at the interface between the semiconductor film SC and the gate insulating film IN, and x = _tsc at the upper end surface. The coordinates in the y direction are y = 0 when the semiconductor film SC is in contact with the right end of the source electrode S and y = L when the semiconductor film SC is in contact with the left end of the drain electrode D.

[Poisson equation]
Here, the Poisson equation in the semiconductor film SC can be represented by a one-dimensional equation as shown in Equation (1).

In Expression (1), φ is an electrostatic potential (hereinafter simply referred to as “potential” as appropriate), x is a position in the thickness direction of the semiconductor film SC, ρ is a charge density, and ε _sc is a dielectric constant of the semiconductor film SC. It is.

Here, the use of a one-dimensional Poisson equation will be described.
By evaluating the basic characteristics (threshold voltage _Vth and S value) of the TFT, the amount of defects present in the interface between the gate insulating film IN and the semiconductor film SC, the semiconductor film SC, the amount of fixed charges, etc. Can be estimated. Therefore, evaluation of basic characteristics is extremely important when developing TFTs.

However, in a TFT having a short channel length L, when the drain voltage _Vds, which is the voltage between the drain electrode D and the source electrode S, increases, the influence causes the threshold voltage _Vth to decrease or the S value to increase. Phenomenon occurs. When such a phenomenon occurs, the threshold voltage V _th and S value observed there are strongly influenced by the drain voltage V _ds , and the threshold voltage V _th and S value reflecting the original basic characteristics of the TFT are obtained. Will be different.

Accordingly, as the basic characteristics of the TFT, without greatly influenced by the difference of the drain voltage V _ds, and stable in order to evaluate the threshold voltage V _th and S value is, the condition drain voltage V _ds is low, the drain current It is necessary to evaluate the characteristics. The evaluation of the basic characteristics of the TFT is useful for determining the device parameters of the TFT.

Therefore, the present invention calculates the drain current I _d at high speed and with high accuracy under the condition that the drain voltage V _ds is small (for example, about 1 (V) to several V) in order to calculate the basic characteristics of the TFT. A simulation model was used. Here, when the drain voltage _Vds is as low as about 1 (V), it is not necessary to consider the change in the channel length direction (y direction in FIG. 1). Therefore, a good simulation model can be constructed using the one-dimensional Poisson equation in the thickness direction (x direction in FIG. 1).

The description of Expression (1) will be continued.
In the equation (1), the charge density ρ in the semiconductor film SC including a defect that captures carriers is given by the equation (2) in consideration of the density of defects that capture carriers.

Here, q is the elementary charge, p is the hole density, n is the electron density, N _d is the effective donor density derived from oxygen deficiency, impurity hydrogen, etc., and N _dd ⁺ is the deep _depth of the positively charged donor type defect. The density in the state (Deep state), N _ad ⁻ is the density in the deep state of the negatively charged acceptor type defect, and N _at ⁻ is the density in the tail state of the negatively charged acceptor type defect. is there. In addition, since the influence of the tail state of the donor-type defect on the drain current characteristics is small, the related item is ignored here. Note that N _dd ⁺ is a density in a deep state of a positively charged donor type defect or the like, and “N _dd ⁺ is a density of a positively charged donor type defect (Deep state)” as appropriate. .
Further, “Deep state” and “Tail state” will be described later.

  Here, the hole density p and the electron density n are given by the equations (3) and (4), respectively.

Here, p ₀ and n ₀ are the hole density and electron density of the semiconductor film SC under flat band conditions, respectively, and β is the reciprocal of the thermal voltage. Here, β = q / kT, k is a Boltzmann constant, and T is an absolute temperature.
Further, the hole density p ₀ and the electron density n ₀ of the semiconductor film SC under the flat band condition are given by the equations (5) and (6), respectively.

Here, n _i is the intrinsic carrier density, E _i is the intrinsic Fermi level, and E _f is the Fermi level under flat band conditions.

In the calculation method according to the present embodiment, the effective donor density N _d derived from oxygen deficiency, impurity hydrogen, or the like does not depend on the potential φ, and the heat treatment temperature or heat treatment atmosphere (for example, a nitrogen gas atmosphere, Approximate to take a predetermined value determined by the manufacturing process such as air). As this predetermined value, an empirical value determined based on an experimental result can be used as a specific parameter.

Next, the density of defects that capture carriers will be described in detail. FIG. 2 is a diagram showing the density of states of a donor type defect (Deep state) and an acceptor type defect (Deep state, Tail state) in the band gap. The “Deep state” refers to the energy state at the center in the energy state between the energy E _{v at the} upper end of the valence band and the energy E _{c at the} lower end of the conduction band. Further, the "Tail state", among the above-mentioned energy, is intended to refer to energy state in the vicinity of the energy E _c of the near or bottom of the conduction band energy E _v of the valence band upper end.

Here, the state density g _dd of the donor-type defect (Deep state) is given as a function of the energy E in the band gap as shown in Expression (7).

Here, g _dd0 is the density of states of the donor type defects in the energy E _v of the valence band maximum (Deep state). Further, E _dd is the reciprocal of the gradient of the state density distribution of the donor type defect (Deep state), and “E _dd > kT”. Note that kT is 26 meV at room temperature.

Further, the density N _dd ⁺ of the positively charged donor-type defect (Deep state) is expressed by (1-) in Equation (7), where f (E) is the defect level occupation probability, as shown in Equation (8). multiplied by f (E)), it can be determined by integrating the energy E _v of the valence band upper end to the energy E _c of the conduction band. The defect level occupation probability f (E) is given by equation (9).

Here, E _fe is the Fermi level.
Next, the integral calculation of Expression (8) needs to be performed numerically, but an analytical approximate solution can be obtained by considering that “E _dd > kT”. Derivation of this approximate solution will be described.

First, Expression (7) and Expression (9) are substituted into Expression (8), and the upper end of the integration range is changed from the energy E _{c at the} lower end of the conduction band to infinity, thereby obtaining Expression (A1) which is an approximate expression. It is done.

  Here, when z and α are set as in the formula (A2), the formula (A1) can be expressed as in the formula (A3) and further approximated as in the formula (A4).

Here, when α> 1 (E _dd > kT), since the relationship of the equation (A5) is established, the equation (A4) becomes the equation (A6).

  Here, the formula (A8) is obtained by substituting the relational expression shown in the formula (A7) into the formula (A6).

Further, as shown in the formula (A9), in the formula (A8), when the potential φ = 0, the density N _dd0 of the positively charged donor-type defect (Deep state) under the flat band condition of the semiconductor film SC. ⁺ .

Therefore, by using the formula (A9), the formula (A8) can be expressed as the formula (10). In this embodiment, Expression (10) is used as an approximate expression of the density N _dd ⁺ of the positively charged donor-type defect (Deep state) shown in Expression (8).

Further, the state density g _ad of the acceptor type defect (Deep state) is given by the equation (11).

Here, g _ad0 is the state density of the acceptor type defect (Deep state) at the energy E _c at the lower end of the conduction band, E _ad is the reciprocal of the slope of the state density distribution of the acceptor type defect (Deep state), and “E _ad > KT ”.

Further, the density N _ad ⁻ of acceptor defects (Deep state) charged negatively is obtained by multiplying the equation (11) by the defect level occupation probability f (E) as shown in the equation (12). it can be determined by integrating the energy E _v band upper end to the energy E _c of the conduction band.

Similar to the integral calculation shown in equation (8), the integral calculation in equation (12) also needs to be performed numerically, but by considering that “E _ad > kT”, an analytical approximate solution Can be obtained. Derivation of this approximate solution will be described.

First, by substituting Equation (9) and Equation (11) into Equation (12), Equation (B1) is obtained, and further, the lower end of the integration range is changed from the energy E _{v at the} upper end of the valence band to minus infinity. By changing, the approximate expression (B2) is obtained.

  Here, as shown in Expression (B3), when z and α are set, Expression (B2) can be expressed as Expression (B4), and further, by changing the upper end of the integration range to infinity. Then, an approximate expression (B5) is obtained. Note that z and α in the formula (B3) are different from z and α in the formula (A2).

Here, when α> 1 (E _ad > kT), since the relationship of the equation (B6) is established, the equation (B5) becomes the equation (B7).

  Here, the formula (B9) is obtained by substituting the relational expression shown in the formula (B8) into the formula (B7).

Further, as shown in the formula (B10), in the formula (B9), when the potential φ = 0, the density N _ad0 of the negatively charged acceptor type defect (Deep state) under the flat band condition of the semiconductor film SC. ^- .

Therefore, by using the formula (B10), the formula (B9) can be expressed as the formula (13). In this embodiment, Expression (13) is used as an approximate expression of the density N _ad ⁻ of the negatively charged acceptor type defect (Deep state) shown in Expression (12).

Further, the state density _{g at} the acceptor-type defects (Tail state) is given by equation (14).

Here, g _at0 is the state density of the acceptor type defect (Tail state) at the lower end of the conduction band, E _at is the reciprocal of the slope of the state density distribution of the acceptor type defect (Tail state), and “E _at <kT” is there.

Further, the density N _at ⁻ of the negatively charged acceptor type defect (Tail state) is expressed by the equation (14), the occupation probability f () of the defect level shown in the equation (9), as shown in the equation (15). E) the multiplied, it can be determined by integrating the energy E _v of the valence band upper end to the energy E _c of the conduction band.

Similar to the integral calculation shown in equations (8) and (12), the integral calculation in equation (15) also needs to be done numerically, but by considering that “E _at <kT”, An analytical approximate solution can be obtained. Derivation of this approximate solution will be described.

First, formula (C1) is obtained by substituting equation (9) and (14) into equation (15), further changes to minus infinity to the lower end of the integration range from the energy E _v of the valence band maximum Thus, an expression (C2) that is an approximate expression is obtained.

Here, since the state density of the tail state of the acceptor type defect takes a high value only near the energy E _{c at} the bottom of the conduction band, when the integration of the equation (C2) is performed, the occupation represented by the equation (9) Probability f (E) can be approximated as in equation (C3).

  Therefore, the equation (C2) can be further approximated as shown in the equation (C4), and as a result, the equation (C5) is obtained.

  Here, by substituting the relational expression of the formula (C6) into the formula (C5), the formula (C7) is obtained, and further transformed, the formula (C8) is obtained.

Further, as shown in the formula (C9), in the formula (C8), when the potential φ = 0, the density N _at0 of the negatively charged acceptor type defect (Tail state) under the flat band condition of the semiconductor film SC. ^- .

Therefore, by using the formula (C9), the formula (C8) can be expressed as the formula (16). In the present embodiment, Expression (16) is used as an approximate expression of the density N _at ⁻ of the negatively charged acceptor type defect (Tail state) shown in Expression (15).

[Calculation of Fermi level under flat band condition]
Next, a process for calculating the Fermi level E _f under the flat band condition based on the electrical neutral condition of the semiconductor film SC will be described.

Here, the flat band condition will be described with reference to FIG. As shown in FIG. 3, the flat band condition is a condition in which the energy band in the semiconductor film SC does not bend and becomes flat in the TFT energy band diagram. When the work function of the metal that is the gate electrode G is equal to the work function of the semiconductor film SC and no electric charge is present in the gate insulating film IN, the Fermi level of the metal that is the gate electrode G is obtained under flat band conditions. E _fm is equal to the Fermi rank E _fs of the semiconductor film SC.

Further, when there is a difference between the work function of the metal that is the gate electrode G and the work function of the semiconductor film SC, or when there is a charge in the gate insulating film IN, the energy band in the semiconductor film SC that is generated by these. bending to compensate for the gate voltage V _g necessary for the energy band in the flat is flat band voltage V _fb.

The process of calculating the Fermi level E _f will be continued.
By substituting Equation (3), Equation (4), Equation (10), Equation (13), and Equation (16) into Equation (2), the electric current in the semiconductor film SC is obtained under the flat band condition “φ = 0”. By setting “ρ = 0” which is a neutral condition, Expression (17) is obtained.

  Then, when Expression (5), Expression (6), Expression (A9), Expression (B10), and Expression (C9) are substituted into Expression (17), Expression (18) is obtained.

Here, the state density g _{dd0 of} the donor type defect (Deep state) at the energy E _v at the upper end of the valence band, the reciprocal number E _dd of the state density distribution of the donor type defect (Deep state), and the energy E at the lower end of the conduction band the state density g _ad0 of the acceptor-type defects in the _c (Deep _state), the acceptor-type defects (Deep state) inverse of the slope E _ad state density _{distribution,} the acceptor-type defects in the energy E _c of the conduction band minimum (Tail state) State density g _at0 , acceptor type defect (Tail state) state density distribution reciprocal number E _at , effective donor density N _d , intrinsic carrier density n _i , intrinsic Fermi level E _i , top of valence band The energy E _v and the energy E _{c at the} lower end of the conduction band are given as device parameters that are design values of the device or intrinsic parameters specific to the material used. The absolute temperature T can be set to an arbitrary value (for example, 300K). Therefore, in Equation (18), the only unknown is the Fermi level E _f .

Therefore, by performing numerical analysis on the equation (18), which is an equation of the Fermi level E _f , for example, by a known method such as Newton method or bisection method, which is a root finding algorithm using iterative calculation, under flat band conditions The Fermi level E _f of can be calculated.

[Calculation of charge carrier density under flat band conditions]
Next, by substituting the Fermi level E _f calculated from the equation (18) into the equations (5), (6), (A9), (B10), and (C9), the semiconductor film SC As the charge carrier density under the flat band condition, the hole density p ₀ , the electron density n ₀ , the positively charged donor type defect (Deep state) density N _dd0 ⁺ , the negatively charged acceptor type defect (Deep state) Density N _ad0 ⁻ and negatively charged acceptor type defect (Tail state) density N _at0 ⁻ are obtained. The potential distribution is calculated using these charge carrier densities.

[Calculation of potential distribution]
The Poisson equation shown in the equation (1) is differentiated, and the solution is obtained by numerical analysis using a known method such as a Gaussian elimination method that is a direct method or a Jacobian method that is an iterative method. Can be sought. Thereby, the potential distribution in the x direction (depth direction) can be calculated.

Here, in order to make a difference, when performing numerical analysis in the semiconductor film SC, for example, assuming an equally spaced mesh, the mesh width is Δx, and the potential distribution φ (x) is discretized in units of Δx. Will be treated as a numerical function. As a result, the potential distribution φ (x) is calculated as a numerical function (sequence) of {φ (0), φ (Δx), φ (2Δx),..., Φ (t _sc )} by numerical analysis. The

Here, with reference to FIG. 4, the boundary condition at the time of solving a Poisson equation is demonstrated.
First, the potential φ at the gate electrode G is defined as a difference “V _gs −V _fb ” between the gate-source voltage V _gs and the flat band voltage V _fb . In addition, the electric flux density is made continuous at the interface (x = 0) between the gate insulating film IN and the semiconductor film SC. Furthermore, assuming that there is a sufficiently thick insulating film layer in a region where “x> t _sc ”, that is, the upper surface side of the semiconductor film SC (see FIG. 1), the electric field E is almost zero at x = t _sc . To be.

[Calculation of carrier density distribution]
The carrier density distribution in the semiconductor film SC can be calculated from the potential distribution obtained by solving the Poisson equation.
In the equation (4), when the potential at the position x is φ (x), the carrier density (electron density) n (x) at the position x is given by the equation (19).

[Calculation of carrier surface density]
The carrier surface density N can be calculated by integrating the carrier density n (x) from x = 0 to x = _tsc in the thickness direction, as shown in Expression (20).

  Actually, since the potential distribution is obtained by numerical calculation, the integration in Expression (20) cannot be performed analytically. Therefore, in the semiconductor film SC, assuming an equally spaced mesh when performing numerical calculation, and assuming that the mesh width is Δx, the surface density N of carriers can be calculated as shown in Equation (21).

[Calculation of drain current]
When the channel length L is long and the drain-source voltage _Vds is small, it can be approximated that the carrier density distribution in the channel direction (y direction) is constant. Therefore, the drain current I _d is obtained by using the carrier surface density N calculated by the equation (20) (or the equation (21)), the carrier surface density N, the mobility μ, It can be calculated by multiplying the element q, the drain-source voltage _Vds, and the ratio (W / L) of the channel width W to the channel length L.

By the above calculation process, it is possible to calculate the drain current I _d.

In addition, by changing the value of the gate voltage V _g set when calculating the drain current I _d in various _ways and calculating the corresponding drain current I _d , the gate voltage dependence of the drain current I _d (drain Current characteristics) can be calculated.
Note that the value of the gate voltage Vg is used to determine a boundary condition when calculating the potential distribution φ (x) in the drain current calculation process. That is, it is used to calculate the potential φ = V _gs −V _fb = (V _g −V _s ) −V _fb at the gate electrode G.

  Next, referring to FIG. 5 (refer to FIG. 1 as appropriate), a drain current simulation apparatus (hereinafter referred to as a simulation apparatus as appropriate) that performs drain current simulation using the drain current calculation method of the present invention described above. explain.

[Configuration of simulation device]
As shown in FIG. 5, a simulation apparatus (drain current simulation apparatus) 1 in this embodiment includes a device parameter input means 10, a Fermi level calculation means 11, a charge carrier density calculation means 12, a calculation range setting means 13, a potential. A distribution calculating means 14, a carrier density distribution calculating means 15, a carrier surface density calculating means 16, a drain current calculating means 17, a parameter storing means 18, a charge carrier density storing means 19 and a drain current storing means 20 are provided.

The simulation apparatus 1 can be configured by dedicated hardware, but a program (drain current) that realizes the above-described means for calculating the drain current in a general computer such as a personal computer (personal computer). This can be realized by executing the simulation program. In the present embodiment, a drain current simulation apparatus 1 is realized by causing a personal computer to execute a drain current simulation program.
Hereinafter, each means will be described in detail.

Device parameter input means 10, via an input means such as a keyboard (not shown), and inputs the device parameters is a parameter indicating the structure and characteristic values of the devices required for the calculation of the drain current I _d. The device parameter input unit 10 stores the input device parameters in the parameter storage unit 18.

The device parameters to be input, the thickness t _sc of the semiconductor film _SC, the gate thickness t _in the insulating film _IN, the channel length L, the channel width W, the donor type defects (Deep state of the energy E _v of the valence band maximum ) State density g _dd0 , donor-type defect (Deep state) state density distribution reciprocal E _dd , acceptor-type defect state density g _ad0 at the conduction band bottom energy E _c , acceptor-type defect (Deep state) inverse of the slope E _ad state density distribution of _the slope of the density of states distribution in the density of states of the acceptor-type defects in the energy E _c of the conduction band minimum (Tail state) g _at0, the acceptor-type defects (Tail state) inverse _{E at} the include flat band voltage _{V fb} and effective donor density _{N d.}

In the present embodiment, the intrinsic Fermi level E _i , intrinsic carrier density n _i , valence band upper end energy E _v , conduction band lower end energy E _c , mobility μ, dielectric constant ε _sc for the semiconductor film SC. The dielectric constant ε _in of the gate insulating film IN is stored in advance in the parameter storage means 18 as a unique parameter unique to the material used. Further, for the source voltage V _s which is one of the calculation conditions, for example, a predetermined value (for example, 0 [V]) is stored in the parameter storage unit 18. Furthermore, for the source voltage V _d (or the drain-source voltage V _ds ) used for the calculation of the drain current I _d , for example, a predetermined value (for example, 1 [V]) is stored in the parameter storage unit 18. Remember.
Hereinafter, the device parameters, unique parameters, and the like are collectively referred to as “device parameters”.

  The device parameter input means 10 may input device parameters via a storage medium such as an optical disk, a magnetic disk, or a flash memory in addition to the keyboard described above, or a LAN (Local Area Network) or the like. You may make it input via a communication line.

The Fermi level calculation means 11 calculates the Fermi level E _f under the flat band condition of the semiconductor film SC using the device parameters and the like stored in the parameter storage means 18, and uses the calculated Fermi level E _f This is output to the charge carrier density calculating means 19.

Specifically, the Fermi level calculation means 11 substitutes device parameters and the like into the above equation (18), and numerically analyzes the equation (18) by the Newton method, the bisection method, or the like, thereby obtaining the Fermi level of the semiconductor film SC. The level E _f is calculated.

The charge carrier density calculating means 12 uses the Fermi level E _f input from the Fermi level calculating means 11, and the density N _dd0 ⁺ of a positively charged donor-type defect (Deep state) in the flat band condition of the semiconductor film SC. The negatively charged acceptor type defect (Deep state) density N _ad0 ⁻ , the negatively charged acceptor type defect (Tail state) density N _at0 ⁻ , the hole density p ₀ and the electron density n ₀ were calculated. These charge carrier densities are stored in the charge carrier density storage means 19.

Specifically, the charge carrier density calculating means 12 substitutes the Fermi level E _f into the above-described formula (5), formula (6), formula (A9), formula (B10), and formula (C9). In the flat band condition of the semiconductor film SC, the hole density p ₀ , the electron density n ₀ , the positively charged donor-type defect (Deep state) density N _dd0 ⁺ , and the negatively charged acceptor-type defect (Deep state), respectively. Density N _ad0 ⁻ and negatively charged acceptor type defect (Tail state) density N _at0 ⁻ are calculated. When device parameters or the like are required for calculating these charge carrier densities, the charge carrier density calculation unit 12 refers to the device parameters stored in the parameter storage unit 18 as appropriate.

Calculation range setting means 13, when calculating a potential distribution by solving the Poisson equation, the range of the gate voltage V _g was entered via a keyboard (not shown), in calculating the potential distribution, entered the gate voltage They are for setting various gate voltage V _g in the range of V _g as calculation conditions. The calculation range setting unit 13 sets the gate voltage _Vg in the potential distribution calculation unit 14 as a calculation condition.

Specifically, the calculation range setting means 13 inputs the initial value V ₀ of the gate voltage, the maximum value V _max of the gate voltage, and the interval ΔV for changing the gate voltage as the setting range of the gate voltage V _g. . Then, the calculation range setting means 13 sequentially V ₀ , V ₀ + ΔV, V ₀ + 2 × ΔV,..., V based on the input initial value V ₀ , maximum value V _max , and interval ΔV. _max setting the potential distribution calculating means 14 as the gate voltage _{V g.}

The potential distribution calculation unit 14 is configured to determine the gate voltage V set by the calculation range setting unit 13 based on the charge carrier density stored in the charge carrier density storage unit 19 and the device parameters stored in the parameter storage unit 18. The potential distribution φ (x) in the depth direction of the semiconductor film SC at _g is calculated, and the calculated potential distribution φ (x) is output to the carrier density distribution calculating means 15.

Specifically, the potential distribution calculating means 14 has a positive charge donor density (Deep state) density N _dd0 ⁺ as a charge carrier density, a negative charge acceptor type defect (Deep state) density N _ad0 ⁻ , Using the density N _at0 ⁻ , the hole density p ₀ and the electron density n _{0 of the} negatively charged acceptor type defect (Tail state), necessary device parameters, and the gate voltage V _g which is a calculation condition, the equation (1 ). At this time, equations (2) to (4), (10), (13), and (16) are also used. Further, the Poisson equation shown in the equation (1) is differentiated, and the potential distribution φ (x) is calculated by numerically analyzing the differentiated Poisson equation by the Gaussian elimination method, the Jacobian method, or the like.

Here, the potential distribution calculation means 14 indicates that the potential φ (−t _in ) at the gate electrode G is the difference between the gate-source voltage V _gs (V _gs = V _g −V _s ) and the flat band voltage V _fb ( The potential distribution φ (x) is calculated with a boundary condition equal to V _gs −V _fb ).

The carrier density distribution calculating unit 15 stores the potential distribution φ (x) input from the potential distribution calculating unit 14, the electron density n ₀ stored in the charge carrier density storing unit 19, and the parameter storing unit 18 in Expression (19). By substituting the stored device parameters and the like, the carrier density distribution (electron density distribution) n (x) is calculated.
The carrier density distribution calculating unit 15 outputs the calculated carrier density distribution n (x) to the carrier surface density calculating unit 16.

The carrier surface density calculating unit 16 uses the carrier surface density n (x) input from the carrier density distribution calculating unit 15 as the lower end (x = 0) that is the entire range in the depth direction of the semiconductor film SC according to the equation (20). To the upper end (x = t _sc ) to calculate the carrier surface density N.

Specifically, the carrier surface density calculating unit 16 calculates the carrier surface density N by numerical integration with the mesh width as Δx, as shown in Expression (21).
The carrier surface density calculating unit 16 outputs the calculated carrier surface density N to the drain current calculating unit 17.

The drain current calculation means 17 substitutes the carrier surface density N input from the carrier surface density calculation means 16 and the device parameters stored in the parameter storage means 18 into the equation (23), and calculates the drain current I _d . calculate.

The drain current calculation unit 17 stores the calculated drain current I _d in the drain current storage unit 20 in association with the gate voltage V _g which is a calculation condition.
The drain current calculation unit 17, the drain current I _d, instead of the gate voltage V _g, the gate - may be in association with the source voltage V _gs is stored in the drain current storage means 20.

Parameter storage means 18, the device parameter input unit 10 is a device parameters entered semiconductor film SC thickness t _sc, the thickness t _in the gate insulating film _IN, the channel length L, the channel width W, of the valence band maximum The state density g _{dd0 of} the donor type defect (Deep state) at the energy E _v , the reciprocal E _dd of the state density distribution of the donor type defect (Deep state), and the acceptor type defect (Deep) at the energy E _c at the bottom of the conduction band state density g _ad0 , acceptor-type defect (Deep state) state density distribution reciprocal number E _ad , acceptor-type defect (Tail state) state density g _at0 , acceptor-type _energy density E _c It stores the reciprocal number E _at of the state density distribution of the defect (Tail state), the flat band voltage V _fb, and the effective donor density N _d .

Further, the parameter storage means 18 includes intrinsic Fermi level E _i , intrinsic carrier density n _i , valence band upper end energy E _v , conduction band lower end energy E _c , mobility of the semiconductor film SC as other parameters. It is assumed that μ, the dielectric constant ε _sc, and the dielectric constant ε _in of the gate insulating film IN are stored in advance as eigenvalues specific to the material to be used.

The parameter storage unit 18 stores in advance predetermined values as the source voltage V _s and the absolute temperature T, which are other calculation conditions. Furthermore, a Boltzmann constant k and an electric elementary quantity q which are constants are stored in advance.

  The device parameters and the like stored in the parameter storage means 18 are Fermi level calculation means 11, charge carrier density calculation means 12, potential distribution calculation means 14, carrier density distribution calculation means 15, carrier surface density calculation means 16, and drain current. Referenced by the arithmetic means 17 as appropriate.

The charge carrier density storage means 19 is a charge carrier density calculated by the charge carrier density calculation means 12, which is a positively charged donor type defect (Deep state) density N _dd0 ⁺ , a negatively charged acceptor type defect (Deep). state) density N _ad0 ⁻ , negatively charged acceptor type defect (Tail state) density N _at0 ⁻ , hole density p _0, and electron density n ₀ are stored. These data are referred to by the potential distribution calculation means 14 and the carrier density distribution calculation means 15.

Drain current storage means 20, the drain current I _d calculated by the drain current calculation unit 17 is configured to store in association with the gate voltage V _g is the calculation conditions of the drain current I _d.

The drain current I _d which are stored in the drain current storage means 20, for example, the threshold voltage V _th and the sub-threshold coefficient which is a characteristic value of the TFT (S value) is utilized for the calculation of such. In addition, the graph drawing means (not shown) can output the data to a display means or printing means connected to the computer and display it as a drain current characteristic (for example, see FIGS. 7 and 8).

  In the present embodiment, the device parameters input by the device parameter input means 10 are temporarily stored in the parameter storage means 18 and read out as appropriate by calculation means such as the Fermi level calculation means 11. The means 10 may output the input device parameters directly to the necessary calculation means.

The unique parameter may be input by the device parameter input unit 10 together with the device parameter. Furthermore, the source voltage V _s, which is one of the calculation conditions, may be input by the device parameter input unit 10 or the calculation range setting unit 13.

In the present embodiment, the charge carrier density such as the density N _dd0 ^{+ of} the positively charged donor-type defect (Deep state) calculated by the charge carrier density calculating unit 12 is temporarily stored in the charge carrier density storage unit 19. However, the charge carrier density calculating means 12 may output the calculated charge carrier density directly to the potential distribution calculating means 14 or the like.

[Operation of simulation device]
Next, the operation of the drain current simulation apparatus 1 in this embodiment will be described with reference to FIG.

  First, the simulation apparatus 1 inputs device parameters for a TFT to be simulated by the device parameter input unit 10 and stores the device parameters in the parameter storage unit 18 (step S10).

Next, the simulation apparatus 1 uses the device parameters stored in the parameter storage unit 18 by the Fermi level calculation unit 11 to calculate the Fermi level of the semiconductor film SC under the flat band condition according to the equation (18). E _f is calculated, and the calculated Fermi level E _f is output to the charge carrier density calculating means 12 (step S11).

Next, the simulation apparatus 1 uses the Fermi level E _f calculated by the Fermi level calculation unit 11 and the device parameters stored in the parameter storage unit 18 by the charge carrier density calculation unit 12 and the formula ( 5), Formula (6), Formula (A9), Formula (B10), and Formula (C9), respectively, as the charge carrier density in the flat band condition of the semiconductor film SC, the hole density p ₀ , the electron density n ₀ , calculated ^- charged density _{N dd0} ⁺ donor type defects (Deep state), negatively charged acceptor-type defects (Deep state) density _{N ad0} ^- and density _{N at0} negatively charged acceptor-type defects (Tail state) Then, these calculated values are stored in the charge carrier density storage means 19 (step S12).

Then, the simulator 1, the computation range setting means 13, when calculating potential distribution φ a (x), as data defining the setting range of the gate voltage V _g, the initial value V ₀ which is the gate voltage, the gate voltage and the maximum value V _max of the interval ΔV changing the gate voltage, entered from the keyboard (not shown), it sets the initial value V ₀ in the potential distribution calculating means 14 as the gate voltage V _g (step S13).

Next, the simulation apparatus 1 uses the potential distribution calculation unit 14 to store the positively charged donor-type defect ( _Neep state) density N _dd0 ⁺ stored in the charge carrier density storage unit 19 and the negatively charged acceptor-type defect. (Deep state) density N _ad0 ⁻ , negatively charged acceptor type defect (Tail state) density N _at0 ⁻ , hole density p ₀ , electron density n ₀ , device parameters stored in parameter storage means 18, etc. Is used to calculate the potential distribution φ (x) at the gate voltage V _g set by the calculation range setting means 13 by differentiating the Poisson equation shown in the equation (1). Is output to the carrier density distribution calculating means 15 (step S14).

  Next, the simulation apparatus 1 uses the carrier density distribution calculation means 15 to calculate the potential distribution φ (x) calculated by the potential distribution calculation means 14, the charge carrier density and parameter storage means 18 stored in the charge carrier density storage means 19. Is used to calculate the carrier density distribution n (x) according to the equation (19), and outputs the calculated carrier density distribution n (x) to the carrier surface density calculating means 16 ( Step S15).

  Next, the simulation apparatus 1 uses the carrier surface density calculation unit 16 to calculate the equation using the carrier density distribution n (x) calculated by the carrier density distribution calculation unit 15 and the device parameters stored in the parameter storage unit 18. The carrier surface density N is calculated by (20), and the calculated carrier surface density N is output to the drain current calculation means 17 (step S16).

Next, the simulation apparatus 1 uses the carrier surface density N calculated by the carrier surface density calculation unit 16 and the device parameters stored in the parameter storage unit 18 by the drain current calculation unit 17 and the equation (23). calculates a drain current _{I d,} the calculated drain current _{I d,} in association with a computing condition gate voltage _{V g,} and stored in the drain current storage unit 20 (step S17).

Then, the simulator 1, the computation range setting unit 13, the calculation conditions, in order to change the gate voltage V _g at the time of calculating the next drain current I _d, the previous gate voltage V _g, the calculated The interval ΔV is added and set in the potential distribution calculating means 14 (step S18).

Here, in the simulator 1, the computation range setting means 13, when the gate voltage _{V g} was condition changed in step S18 is to determine whether the maximum value greater than _{V max} calculation range (step S19), large ( Since the calculation of the drain current I _d in the predetermined calculation range is completed, the simulation apparatus 1 ends the process.

On the other hand, the gate voltage _{V g} was condition changed in step S18 is equal to or smaller than the maximum value _{V max} of the calculation range (No in step S19), the simulation apparatus 1 returns to step S14, the gate voltage V set in step S18 _{For g} , the calculation of the potential distribution φ (x) by the potential distribution calculating means 14 is repeated.

Further, the obtained drain current characteristic can be displayed in a graph on a display device (not shown), for example (see, for example, FIGS. 7 and 8). Then, whether the drain current characteristic is desired properties, for example, to calculate the threshold voltage V _th and S value check, if the desired properties, such as the gate insulating film thickness t _in and the semiconductor film thickness t _sc The device parameters are changed, the above procedure is repeated, the drain current characteristics are calculated, the device parameters are determined so as to obtain a desired drain current, and the device structure of the TFT can be determined.

Next, an example of the drain current simulation apparatus according to the embodiment of the present invention will be described.
7 and 8 show the calculation results (solid line, □, Δ) and measured values (◯) of the gate voltage dependence of the drain current of the TFT. Semiconductor film IGZO, gate insulating film and SiO _2, the semiconductor film thickness _{t sc,} calculations and measured variously changing the thickness of the gate insulating film _{t in} Been. Here, the channel length L = 80 [μm] and the channel width W = 130 [μm]. In addition, as described above, in order to evaluate the basic characteristics of the TFT, the drain-source voltage _Vds was measured under the condition of 1 [V]. Incidentally, the calculation results shown in FIGS. 7 and 8, other than the gate insulating film thickness t _in and the semiconductor film thickness t _sc performed a calculation using all common device parameters.

7, the vertical axis represents the drain current I _d, (graph L) log scale on the left shows a linear scale (graph R) on the right. The horizontal axis indicates the gate-source voltage _Vgs . In FIG. 8, the vertical axis represents the drain current _Id on a logarithmic scale, and the horizontal axis represents the gate-source voltage _Vgs .

FIG. 7A shows drain current characteristics when the gate insulating film thickness t _in = 10 [nm] and the semiconductor film thickness t _sc = 30 [nm]. As shown in FIG. 7A, the subthreshold coefficient (S value = 92 [mV / dec], that is, the S value is small) having a steep rise is shown, and the calculation result reproduces the measured value well. I understand that

FIG. 7B shows drain current characteristics when the gate insulating film thickness t _in = 100 [nm] and the semiconductor film thickness t _sc = 30 [nm], and are shown in FIG. since 10 times thicker gate insulating film _{t in} compared to if, rising indicates a gradual subthreshold coefficient (S value = 339 [mV / dec], i.e. larger S value). It can be seen that such a gentle drain current characteristic also accurately reproduces the actual measurement value (O) as shown in FIG. 7B.

Here, a method of calculating the subthreshold coefficient (S value) will be described. The subthreshold coefficient indicates the amount of change in the gate voltage V _g (gate-source voltage V _gs ) necessary for the drain current I _d to change by one digit. Therefore, the S value can be expressed as in Expression (24).

In this embodiment, for all the calculated gate-source voltages V _gs (gate voltage V _g ), the difference between the adjacent gate-source voltages and the difference between the respective drain currents I _d The S value was calculated according to the equation (24), and the minimum value among them was set as the S value in the TFT having the structure.

Further, when the calculation is performed using a general desktop computer (equipped with Intel CPU 2 (Central Processing Unit) Intel Core 2 Duo E8400 3.00 GHz), the calculation time in the simulation method of the present invention is as shown in FIG. In the TFT having the semiconductor film thickness t _sc = 30 [nm] shown, when the mesh size in the semiconductor film SC is Δx = 0.5 [nm], the time required for the calculation for the gate voltage V _g of 250 points Was about 10 seconds. Usually, the calculation time of drain current characteristics when using a commercially available two-dimensional device simulator (for example, two-dimensional device simulator “ATLAS” manufactured by SILVACO) is several minutes to several tens of minutes. It can be seen that the calculation by is sufficiently fast and accurate.

From the above, it can be seen that, by the simulation method of the present invention, high-speed and high-precision calculation of the drain current I _d is realized in a storage-type TFT including a defect that captures carriers in the semiconductor film SC.

FIG. 8 shows the calculation result of the dependency of the TFT drain current characteristic on the semiconductor film thickness t _sc . FIG. 8A shows a calculation result when the gate insulating film thickness t _in = 10 [nm]. The semiconductor film thickness t _sc is 10 [nm], 30 [nm], and 50 [nm]. The same parameters as those used in the calculation shown in FIG. 7 are used. Similarly, FIG. 8B shows a calculation result when the gate insulating film thickness t _in = 100 [nm], and other parameters are the same as those used in the calculation shown in FIG. Is used.

In the present embodiment, the threshold voltage _{V th} is defined as the drain current _I d ^{= 10} -7 [A] to become the gate voltage _{V g.} As shown in FIG. 8, it can be seen that as the film thickness of the semiconductor film SC becomes thinner, the rise of the graph becomes steeper, so that the S value becomes smaller and the threshold voltage _Vth also becomes smaller. Further, as shown in FIG. 8B, the thicker gate insulating film IN (t _in = 100 [nm]) is thinner than the thinner gate insulating film IN as shown in FIG. t _in = 10 [nm]) than in the semiconductor film thickness _{t sc} drain current characteristics dependent large, the difference in the gate insulating film thickness _{t in,} the semiconductor film thickness _{t sc} of S values and the threshold voltage _{V th} It can be seen that the dependencies are very different.

As shown above, by changing the device parameters such as the gate insulating film thickness t _in and the semiconductor film thickness t _sc, drain current characteristics vary greatly, whereby the value of the S value and the threshold voltage Vt _h is changed To do. By using the drain current simulation method according to the present invention, device parameters such as film thickness can be determined so that desired drain current characteristics can be obtained, thereby enabling the structural design of the TFT.

1 Drain current simulation device (simulation device)
DESCRIPTION OF SYMBOLS 10 Device parameter input means 11 Fermi level calculation means 12 Charge carrier density calculation means 13 Calculation range setting means 14 Potential distribution calculation means 15 Carrier density distribution calculation means 16 Carrier surface density calculation means 17 Drain current calculation means 18 Parameter storage means 19 Charge Carrier density storage means 20 Drain current storage means S Source electrode D Drain electrode G Gate electrode SC Semiconductor film IN Gate insulating film

Claims (3)

The field effect type thin film transistor having a structure in which the object of simulation is a storage type thin film transistor including defects that trap carriers in the semiconductor film, and the semiconductor film, the insulating film, and the gate electrode are stacked in this order. A drain current simulation device for calculating a drain current which is a current between the drain electrode and the source electrode when a drain-source voltage which is a voltage between the drain electrode and the source electrode is low,
Taking into account the electron density, hole density, donor density, and the density of acceptor-type defects and donor-type defects having an exponential density of states in the band gap as the charge density of the semiconductor film, the one-dimensional Poisson equation is solved. A potential distribution calculating means for calculating a potential distribution in the depth direction in the semiconductor film,
Carrier density distribution calculating means for calculating a carrier density distribution in the depth direction in the semiconductor film using the potential distribution calculated by the potential distribution calculating means;
A carrier surface density calculating unit that calculates the carrier surface density in the semiconductor film by integrating the carrier density distribution calculated by the carrier density distribution calculating unit over the entire range in the depth direction of the semiconductor film;
A drain current calculating means for calculating a drain current by multiplying the carrier surface density calculated by the carrier surface density calculating means by a ratio of mobility, elementary charge, drain-source voltage, and channel width and channel length;
Fermi level calculation means for calculating the Fermi level of the semiconductor film under a flat band condition from Equation (18) which is an equation for the Fermi level;
By substituting the Fermi level calculated by the Fermi level calculation means into Equation (5), Equation (6), Equation (A9), Equation (B10), and Equation (C9), the flat band condition of the semiconductor film Hole density, electron density, density of positively charged donor-type defects in deep state, density of negatively-charged acceptor-type defects in deep state, and negatively-charged acceptor type e Bei density in the tail state of the defect (tail state), the charge carrier density calculating means for calculating a charge carrier density, and
The potential distribution calculation means differentiates the equation (1) which is the one-dimensional Poisson equation, and the potential at the gate electrode is equal to a difference between a voltage between the gate electrode and the source electrode and a flat band voltage. Calculate by numerical analysis as the boundary condition,
The carrier distribution density calculating means calculates the carrier density distribution from the equation (19),
The carrier surface density calculating means calculates the carrier density distribution by the equation (20),
Formula (18) is

And
Here, Formula (5), Formula (6), Formula (A9), Formula (B10), and Formula (C9) are

And
The formula (1) is

And
here,

And
The formula (19) is

And
Formula (20) is

And
here,
β = q / kT,
γ _d = q / E _dd ,
γ _a = q / E _ad ,
And
k is the Boltzmann constant,
T is the absolute temperature,
q is the elementary charge,
ρ is the charge density of the semiconductor film,
p is the hole density of the semiconductor film,
n is the electron density of the semiconductor film,
N _dd ⁺ is the density in the deep state of positively charged donor-type defects in the semiconductor film,
N _ad ⁻ is the density in the deep state of the negatively charged acceptor type defect of the semiconductor film,
N _at ⁻ is the density in the tail state of the negatively charged acceptor type defect of the semiconductor film,
p ₀ is the hole density in the flat band condition of the semiconductor film,
n ₀ is the electron density in the flat band condition of the semiconductor film,
N _dd0 ⁺ is the density in the deep state of positively charged donor-type defects in the flat band condition of the semiconductor film,
N _ad0 ⁻ is the density in the deep state of the negatively charged acceptor type defect in the flat band condition of the semiconductor film,
N _at0 ⁻ is the density in the tail state of the negatively charged acceptor type defect in the flat band condition of the semiconductor film,
g _dd0 is the density of states in the deep state of the donor-type defect at the top of the valence band of the semiconductor film,
g _ad0 is the density of states in the deep state of the acceptor type defect at the lower end of the conduction band of the semiconductor film,
g _at0 is the density of states in the tail state of the acceptor type defect at the lower end of the conduction band of the semiconductor film,
_Ev is the energy at the top of the valence band of the semiconductor film,
E _c is the energy at the lower end of the conduction band of the semiconductor film,
E _f is the Fermi level under the flat band condition of the semiconductor film,
E _dd is the reciprocal of the gradient of the state density distribution in the deep state of the donor-type defect of the semiconductor film,
E _ad is the reciprocal of the slope of the state density distribution in the deep state of the acceptor type defect of the semiconductor film,
E _at is the reciprocal of the slope of the state density distribution in the tail state of the acceptor type defect of the semiconductor film,
n _i is the intrinsic carrier density of the semiconductor film,
E _i is the intrinsic Fermi level of the semiconductor film,
ε _sc is the dielectric constant of the semiconductor film,
t _sc is the film thickness of the semiconductor film,
φ is potential,
φ (x) is the potential distribution,
n (x) is the carrier density distribution,
N is the carrier surface density,
N _d is the effective donor density of the semiconductor film,
x is a position in the thickness direction of the semiconductor film,
Simulation device drain current you wherein a is. A calculation range setting means for sequentially setting a plurality of the gate voltages in a predetermined range as the potential distribution calculation conditions in the potential distribution calculation means;
According to claim 1, characterized in that to calculate the gate voltage dependence of the potential and the drain current calculated based on the distribution, the drain current that associates said gate voltage and the calculated condition of the potential distribution Drain current simulation device. The computer simulation program of the drain current for causing functioning as the simulation apparatus of the drain current according to claim 1 or claim 2.

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