JP5839922B2 - Surface potential simulation apparatus and surface potential simulation program - Google Patents

Description

  The present invention relates to an apparatus and a program for calculating the surface potential of a storage-type field effect thin film transistor including a defect that traps carriers in a semiconductor film.

  In general, circuit simulation using SPICE (Simulation Program with Integrated Circuit Emphasis) is used for circuit design using transistors. In order to use this SPICE, a simulation model called a compact model for calculating the electrical characteristics of the transistor is required.

  In the case of single crystal silicon MOSFET (Metal Oxide Semiconductor Field Effect Transistor), which is widely used in circuit design, many high-performance compact models such as HiSIM (Hiroshima-university STARC IGFET Model) (see Non-Patent Document 1) have been developed. ing. These high-performance models are formulated using a surface potential (surface potential), and electrical characteristics can be calculated with high accuracy. In addition, unlike the conventional model, these features do not calculate the terminal charge or current directly from the terminal voltage, but first calculate the surface potential based on the terminal voltage and use the surface potential. And calculate the charge and current. Therefore, in such a model, an important point is how to calculate the surface potential at high speed and with high accuracy.

  The surface potential can be calculated with high accuracy by numerically solving the Poisson equation (numerical analysis). However, in this method, in order to calculate the surface potential, it is necessary to calculate potentials at a large number of points between the back surface and the surface at the same time, and there is a problem that it takes a long calculation time. Therefore, a high-performance model such as HiSIM is devised so that the surface potential can be calculated in a short time so as to perform a high-speed and high-accuracy circuit simulation.

JP 2008-28328 A

M.Miura-Mattausch, H.J.Mattausch, and T.Ezaki, “The Physics and Modeling of MOSFETs: Surface-Potential Model HiSIM”, World Scientific Pub. Co. Inc., Singapore, (2008)

  In recent years, TFT (Thin Film Transistor) using an oxide semiconductor such as a-InGaZnO (IGZO; amorphous-indium gallium, zinc oxide) has attracted attention because of its high mobility and room temperature formation. ing. In the TFT circuit design using such an oxide semiconductor, in order to realize high-speed and high-precision circuit simulation, it is necessary to develop a high-speed and high-precision calculation method of the surface potential as described above.

  Here, a TFT using an oxide semiconductor is an accumulation-type transistor that includes defects that trap carriers in a semiconductor film and uses majority carriers. For this reason, such TFTs include a surface potential calculation method for single-crystal silicon MOSFETs used in the above-described HiSIM (Non-patent Document 1) and a calculation method developed for polycrystalline silicon TFTs ( Patent Document 1) cannot be applied.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a surface potential simulation apparatus and a simulation program applicable to a storage-type field effect thin film transistor including a defect that traps carriers in a semiconductor film.

  In order to solve the above-described problem, a surface potential simulation device according to claim 1 (hereinafter referred to as a simulation device as appropriate) is a storage-type thin film transistor including defects that trap carriers in a semiconductor film, A field effect thin film transistor having a structure in which a semiconductor film, an insulating film, and a gate electrode are stacked in this order. When the semiconductor film has a surface in contact with the insulating film as a front surface and the opposite surface as a back surface, the semiconductor A surface potential simulation device for calculating the surface potential of a film, comprising Fermi level calculation means, charge carrier density calculation means, back surface potential calculation means, and surface potential calculation means.

According to this configuration, the simulation apparatus calculates the Fermi level under the flat band condition of the semiconductor film from the equation (5), which is an equation for the Fermi level, by the Fermi level calculation means. Next, the simulation apparatus calculates the Fermi level calculated by the Fermi level calculation means by the charge carrier density calculation means using the expressions (2.3), (3.3), (4.2) and By substituting into equation (4.3), the density of positively charged donor type defects, the density of negatively charged acceptor type defects, the hole density and the electron density are calculated under the flat band condition of the semiconductor film. Next, the simulation apparatus calculates the density of positively charged donor type defects, the density of negatively charged acceptor type defects, the hole density, and the electron density calculated by the charge carrier density calculating unit by the back surface potential calculating unit. Substituting equation (22) into equation (12) and substituting the equation for the back surface potential of the semiconductor film from which the surface potential has been erased, the back surface potential is calculated from the equation for the back surface potential. Then, the simulation apparatus calculates the surface potential by substituting the back surface potential calculated by the back surface potential calculating unit into the equation (22) by the surface potential calculating unit.

  Here, the equation (5) is

Formula (2.3), Formula (3.3), Formula (4.2) and Formula (4.3) are

And the formula (12) is

And the formula (22) is

, And the where, β = q / kT, γ d = q / E td, γ a = q / E ta, c in = ε in / t in, V g '= V gs -V fb, is, k is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, p ₀ is the hole density under the flat band condition of the semiconductor film, n ₀ is the electron density under the flat band condition of the semiconductor film, and N _td0 ⁺ is the flat of the semiconductor film. The density of positively charged donor type defects under band conditions, N _ta0 ⁻ is the density of negatively charged acceptor type defects under flat band conditions of the semiconductor film , and g _td0 is the density of donor type defects at the top of the valence band of the semiconductor film . state density, g _ta0 state density of the acceptor-type defects in the conduction band of the semiconductor film, E _v is the valence band upper end of the energy of the semiconductor film, E _c is the conduction band of the semiconductor film energy, E _f is Fermi level of a flat band condition of the semiconductor film, E _td is the inverse of the slope of the density of states distribution in the donor-type defects in the semiconductor film, E _ta the inverse of the slope of the density of states distribution of the acceptor-type defects in the semiconductor film, n _i the intrinsic carrier density of the semiconductor film, _{E i} is the intrinsic Fermi level of the semiconductor film, epsilon _sc is the permittivity of the semiconductor _{film, t sc} is the thickness of the semiconductor film, the epsilon _in the dielectric constant of the insulating _{film, t in} the insulating The film thickness, φ is the potential, φ _s is the surface potential, φ _b is the back surface potential, N _d is the effective donor density of the semiconductor film , V _gs is the gate-source voltage, V _fb is the flat band voltage, It is.

  The simulation apparatus for surface potential according to claim 2 is the simulation apparatus according to claim 1, further comprising calculation range setting means.

According to such a configuration, the simulation apparatus, the calculation range setting means sets a plurality of Gate voltage in a predetermined range sequentially the back potential calculating means as the calculation conditions of the surface potential. Next, the simulation apparatus uses the back surface potential calculation means to use the difference between the gate voltage, which is the calculation condition set by the calculation range setting means, and the predetermined source voltage, as the gate-source voltage. Calculate the potential. Then, the simulation apparatus calculates the surface potential using the back surface potential calculated by the back surface potential calculating means by the surface potential calculating means. The simulation apparatus calculates the gate potential dependence of the surface potential by calculating the surface potential by the back surface potential calculating means and the surface potential calculating means for the gate voltages sequentially set by the calculation range setting means.

Simulation program of the surface potential of claim 3 (hereinafter, appropriately referred to as a simulation program), a computer, and configured to function as the simulation apparatus of the surface potential of claim 1 or claim 2.

According to the first or third aspect of the invention, the surface potential of the semiconductor film can be calculated at high speed and with high accuracy for a storage-type field effect thin film transistor including a defect that traps carriers in the semiconductor film. Can do.
According to the invention described in claim 2 or claim 3 , in the storage-type field effect thin film transistor including a defect that traps carriers in the semiconductor film , the gate voltage dependence of the surface potential of the semiconductor film is increased at high speed. It can be calculated with accuracy.

It is typical sectional drawing which shows the structure of TFT of calculation object in embodiment of this invention. It is a figure which shows the state density distribution in the band gap of the defect of the semiconductor film of TFT which is calculation object in embodiment of this invention. FIG. 5 is an energy band diagram for explaining flat band conditions in a TFT to be calculated in an embodiment of the present invention. It is a block diagram which shows the structure of the simulation apparatus of the surface potential in embodiment of this invention. It is a flowchart which shows the flow of a process of the simulation apparatus of the surface potential in embodiment of this invention. It is a figure which shows an example of the calculation result of the gate voltage dependence using the simulation method of the surface potential in embodiment of this invention, (a) And (b) is an example calculated using a different device parameter, respectively. . It is a figure which shows the other example of the calculation result of the gate voltage dependence using the simulation method of the surface potential in embodiment of this invention, (a) And (b) is the example calculated using a different device parameter, respectively. It is.

  Embodiments of the present invention will be described below with reference to the drawings as appropriate. Here, an n-type storage TFT will be described.

FIG. 1 schematically shows a cross section of a TFT for explaining a method for calculating a surface potential in the present invention. In the TFT, a source electrode S and a drain electrode D are provided at both ends in the left-right direction of the semiconductor film SC in the drawing, respectively, and a gate electrode G is provided below the semiconductor film SC in the drawing with the insulating film IN interposed therebetween. Field effect transistor (FET). _{Here, t sc} is the thickness of the semiconductor film SC, L is the channel length of the semiconductor film _{SC, t in} is the thickness of the insulating film IN. Note that in this specification, the potential means a potential.

In the coordinate system, the vertical direction of the drawing, which is the thickness direction (also referred to as the depth direction) of the semiconductor film SC, is the x direction, and the horizontal direction of the drawing, which is the channel length direction, is the y direction. The coordinates in the x direction are x = 0 at the interface between the semiconductor film SC and the insulating film IN, and x = _tsc at the upper end surface. The coordinates in the y direction are y = 0 where the semiconductor film SC is in contact with the right end of the source electrode S and y = L where the semiconductor film SC is in contact with the left end of the drain electrode D. Further, the surface at x = 0 of the semiconductor film SC is the front surface, and the surface at x = _tsc, which is the opposite surface, is the back surface.

  Here, the Poisson equation in the semiconductor film SC can be expressed as in Expression (1.1).

Here, ρ is the charge density, and ε _sc is the dielectric constant of the semiconductor. In addition, the charge density ρ in the semiconductor film SC including a defect that captures carriers is given by Expression (1.2) in consideration of the density of defects that capture carriers.

Here, φ is an electrostatic potential (hereinafter simply referred to as potential as appropriate), x is a distance in the depth direction (thickness direction) of the semiconductor film SC, q is an elementary charge, p is a hole density, n is an electron density, N _d is an effective donor density derived from oxygen deficiency or impurity hydrogen, N _td ⁺ is a density of positively charged donor type defects, and N _ta ⁻ is a density of negatively charged acceptor type defects. P ₀ is the hole density in the flat band condition of the semiconductor film SC, n ₀ is the electron density in the flat band condition of the semiconductor film SC, and β is the reciprocal (q / kT) of the thermal voltage (kT / q). It is. Here, k is a Boltzmann constant, and T is an absolute temperature.

  By substituting the formula (1.2) into the formula (1.1), the Poisson equation in the semiconductor film SC can be expressed as the formula (1.5).

The state density g _td of the donor-type defect and the state density g _ta of the acceptor-type defect are each represented by an exponential function of energy in the band gap as shown in FIG. Here, the state density g _td of the donor-type defect is given by Equation (2.1).

Here, g _td0 is the density of states of the donor-type defect at the top of the valence band, E _v is the energy of the top of the valence band, E is the energy in the band gap, and E _td is the slope of the density of state density of the donor-type defects. It is the reciprocal number.
Further, the density N _td ⁺ of the positively charged donor-type defect is obtained by multiplying Eq. (2.1) by (1−f (E)) as the defect level occupation probability and _Ev to E By integrating up to _c , it is given by equation (2.2). Here, f (E) is a Fermi distribution function shown in equation (2.5), _{E c} is the energy of the conduction band minimum.

Here, E _f is the Fermi level under flat band conditions, and E _fe is the Fermi energy.

Further, the state density g _ta of the acceptor type defect is given by the equation (3.1).

Here, g _ta0 is the state density of the acceptor type defect at the lower end of the conduction band, and E _ta is the reciprocal of the slope of the state density distribution of the acceptor type defect.

The density N _ta ⁻ of the negatively charged acceptor type defect is obtained by multiplying the formula (3.1) by the Fermi distribution function f (E) shown in the formula (2.5) as the occupation probability of the defect level, and the energy E By integrating from E _v to E _c , the equation (3.2) is given.

Next, a process for calculating the Fermi level E _f under the flat band condition based on the electrical neutral condition of the semiconductor film SC will be described.

Here, the flat band condition will be described with reference to FIG. As shown in FIG. 3, the flat band condition is a condition in which the energy band in the semiconductor film SC is flat in the vicinity of the insulating film IN in the energy band diagram of the MOS TFT. When the work function of the metal that is the gate electrode G is equal to the work function of the semiconductor film SC and there is no charge in the insulating film IN, the Fermi level E of the metal that is the gate electrode G under the flat band condition. _fm becomes equal to the Fermi level E _fs of the semiconductor film SC.

Further, when there is a difference between the work function of the metal that is the gate electrode G and the work function of the semiconductor film SC, or when there is an electric charge in the insulating film IN, the energy band in the semiconductor film SC that is generated by these changes. The flat band voltage V _fb is the gate voltage V _g required to compensate the bending and flatten the energy band.

The process of calculating the Fermi level E _f will be continued.
The electrical neutral condition can be expressed as in Formula (4.1) based on the Poisson equation shown in Formula (1.1) and Formula (1.2).

Here, n _i is the intrinsic carrier density, E _i is the intrinsic Fermi level.
By substituting Equation (2.3), Equation (3.3), Equation (4.2) and Equation (4.3) into Equation (4.1), Equation (5) is obtained.

Here, the state density g _td0 of the donor type defect at the upper end of the valence band, the reciprocal number E _td of the state density distribution of the donor type defect, the state density g _{ta0 of} the acceptor type defect at the lower end of the conduction band, The reciprocal of the gradient of the state density distribution E _ta , the effective donor density N _d , the intrinsic carrier density n _i , the intrinsic Fermi level E _i , the energy E _{v at the} top of the valence band, and the energy E _{c at the} bottom of the conduction band are It is given as a device parameter which is a design value of or a characteristic parameter specific to the material used. The absolute temperature T can be set to an arbitrary value (for example, 300K). Therefore, Equation (5) is an equation for the Fermi level E _f .

Therefore, the flat band is obtained by numerically analyzing Equation (5), which is an equation for the Fermi level E _f , by a known method such as Newton's method or bisection method, which is a root finding algorithm using iterative calculation. The Fermi level E _f under the condition can be calculated. Then, by substituting the calculated Fermi level E _f under the flat band condition into the equations (2.3), (3.3), (4.2), and (4.3), the semiconductor film The _values of the density N _td0 ^{+ of} positively charged donor-type defects, the density N _ta0 ^{− of} negatively charged acceptor-type defects, the hole density p ₀ and the electron density n ₀ are obtained under the SC flat band condition. These charge carrier density values are used in the subsequent calculation of the surface potential.

Next, the Poisson's equation shown in equation (1.1), it will be described equation derived relating the surface potential and the gate voltage V _g.
First, by multiplying both sides of the formula (1.1) by 2 (dφ / dx), the formula (6.1) is obtained.

  Here, the left side of the equation (6.1) can be transformed as in the equation (6.2).

  Expression (6.3) is obtained from Expression (6.1) and Expression (6.2).

Next, both sides of the formula (6.3) are integrated with respect to x from x = 0 to x = t _sc (film thickness: see FIG. 1).
here,

  Then, when the left side of equation (6.3) is integrated with respect to x, equation (7.1) is obtained.

  Next, when the right side of Expression (6.3) is integrated with respect to x, Expression (7.2) is obtained.

Here, φ _s is the surface potential (potential at the position of x = 0 in FIG. 1), and φ _b is the back surface potential (potential at the position of x = t _sc in FIG. 1).

  Therefore, Expression (8) is obtained from Expression (7.1) and Expression (7.2).

Here, with respect to the left side of Expression (8), the boundary conditions represented by Expression (9.1) and Expression (9.2) are satisfied according to Gauss's law. Note that Expression (9.1) is an expression in which the electric field is zero at x = t _sc , and Expression (9.2) indicates that the electric flux density on the insulating film IN side and the semiconductor film SC at x = 0. It is assumed that the electric flux density on the side is equal.

Here, V _gs is a gate-source voltage (a difference (V _g −V _s ) between the gate voltage V _g and the source voltage V _s ), V _fb is a flat band voltage, and ε _in is a dielectric of the insulating film IN. _{rate, t in} is the thickness of the insulating film iN.

  Further, when Expression (1.2) is substituted into the right side of Expression (8), Expression (10) is obtained.

  Then, when Expression (9.1), Expression (9.2), and Expression (10) are substituted into Expression (8), Expression (11) is obtained.

  Therefore, by taking the square root of Expression (11), the relationship between the potential and the gate voltage can be expressed as Expression (12).

In order to calculate the surface potential φ _s at the desired gate voltage V _g from the equation (12), a relational expression between the surface potential φ _s and the back surface potential φ _b is required.
In this embodiment, an approximate expression is used as a relational expression between the surface potential φ _s and the back surface potential φ _b .

Next, an approximate expression between the surface potential φ _s and the back surface potential φ _b used in the present embodiment will be described.
When the charge density at the back surface (x _{= t sc)} of the semiconductor film SC and [rho _b, the equation (1.2), equation (1.3), equation (1.4), equation (2.2) and substituting equation (3.2), by the phi = phi _b, to obtain a formula (13).

  Here, the charge density ρ in the Poisson equation of Expression (1.1) strictly depends on the value of x (position in the depth direction), but in the case of a thin film transistor, the charge density ρ is small. Does not depend on the value of x, and is approximated to be constant in the semiconductor film SC as shown in Expression (14).

  Then, when Expression (14) is substituted into Expression (1.1), Expression (15) is obtained.

  Here, since the right side of Expression (15) does not depend on the value of x, Expression (15) can be easily integrated, and sequentially integrated with respect to x to obtain Expression (16) and Expression (17). Can do.

Here, C ₁ and C ₂ are integral constants.
Further, from the equation (9.1), considering the case of x = t _sc , the equation (16) becomes the equation (18.1), and the integration constant C ₁ becomes as the equation (18.2). .

Next, substituting equation (18.2) into equation (17) yields equation (19.1). In equation (19.1), if x = t _sc , then φ = φ _b. (19.2) is obtained.

Accordingly, the integration constant _{C 2} is as shown in equation (20).

Substituting equation (20) into equation (19.1) yields equation (21.1). Furthermore, in equation (21.1), if x = 0, then φ = φ _s , so equation (21.2) is obtained.

  Then, when Expression (13) is substituted into Expression (21.2), Expression (22) can be obtained.

In the present embodiment, Expression (22) is used as an approximate expression indicating the relationship between the surface potential φ _s and the back surface potential φ _b .
Therefore, by substituting Equation (22) into Equation (12) and erasing the surface potential φ _s from Equation (12), an equation for the back surface potential φ _b can be obtained.

In the equation in which the equation (12) is substituted into the equation (22), the density N _td0 ^{+ of} the positively charged donor type defect, which is the charge carrier density in the flat band condition of the semiconductor film SC, and the acceptor type negatively charged. The defect density N _ta0 ⁻ , hole density p _0, and electron density n ₀ are calculated from the above-described formula (2.3), formula (3.3), formula (4.2), and formula (4.3), respectively. Use what was done.

In addition, the reciprocal number E _td of the state density distribution of the donor-type defects, which is other necessary values, the reciprocal number E _ta of the state density distribution of the acceptor-type defects, the effective donor density N _d , and the thickness of the insulating film The t _in , the flat band voltage V _fb , the dielectric constant ε _sc of the semiconductor film, and the dielectric constant ε _in of the insulating film are given as device parameters that are design values of the device or intrinsic parameters specific to the material to be used.

Further, the gate voltage V _g and the source voltage V _s necessary for determining the gate-source voltage V _gs in the equation (9.4) defining V _g ′ are values set as calculation conditions, and are absolute The temperature T can be set to an arbitrary value (for example, 300K).

Accordingly, the equation of the back surface potential φ _b obtained by substituting the equation (12) into the equation (22) is replaced with the Newton method or the bisection in the same manner as the Fermi level E _f is calculated from the equation (5). The back surface potential φ _b can be calculated by numerical analysis using a known method such as the method.

Then, by substituting the calculated back surface potential φ _b into the equation (22), the surface potential φ _s can be obtained.

Further, the value of the gate voltage V _g to set in the calculation of the back surface potential phi _b, variously changed, by calculating the corresponding surface potential phi _s, calculate the gate voltage dependence of the surface potential phi _s can do.

  Next, referring to FIG. 4 (refer to FIG. 1 as appropriate), a surface potential simulation apparatus (hereinafter referred to as a simulation apparatus as appropriate) that performs surface potential simulation using the surface potential calculation method according to the present invention described above. explain.

[Configuration of simulation device]
As shown in FIG. 4, the simulation apparatus (surface potential simulation apparatus) 1 in this embodiment includes a device parameter input unit 10, a Fermi level calculation unit 11, a charge carrier density calculation unit 12, a calculation range setting unit 13, The back surface potential calculation means 14, the surface potential calculation means 15, the parameter storage means 16, the charge carrier density storage means 17 and the surface potential storage means 18 are provided.

Although the simulation apparatus 1 can be configured by dedicated hardware, a program that realizes each of the above-described means for calculating the surface potential φ _s in a general computer such as a personal computer (personal computer) ( This can be realized by executing a surface potential simulation program. In the present embodiment, a personal computer executes a surface potential simulation program to realize a surface potential simulation apparatus 1.
Hereinafter, each means will be described in detail.

The device parameter input means 10 inputs device parameters, which are parameters indicating device configuration and characteristic values necessary for the calculation of the surface potential φ _s , via an input means such as a keyboard (not shown). The device parameter input unit 10 stores the input device parameters in the parameter storage unit 16.

The device parameters to be input, the semiconductor film SC thickness t _sc, the thickness t _in the insulating film _IN, at the valence band maximum donor type defects state density g _td0, the slope of the density of states distribution in the donor-type defects _Examples include the reciprocal E _td , the state density g _ta0 of the acceptor type defect at the lower end of the conduction band, the reciprocal number E _ta of the state density distribution of the acceptor type defect, the flat band voltage V _fb, and the effective donor density N _d .

In the present embodiment, the intrinsic Fermi level E _i , intrinsic carrier density n _i , energy E _{v at the} valence band upper end, energy E _{c at} the lower end of the conduction band, dielectric constant ε _sc, and insulating film IN As for the dielectric constant ε _in , a fixed value is stored in advance in the parameter storage means 16 as a specific parameter unique to the material to be used. Furthermore, as the source voltage V _s which is one of the calculation conditions, for example, a predetermined value (for example, 0 [V]) is stored in the parameter storage unit 16.
Hereinafter, the device parameters, unique parameters, and the like are collectively referred to as “device parameters”.

  The device parameter input means 10 may input device parameters via a storage medium such as an optical disk, a magnetic disk, or a flash memory in addition to the keyboard described above, or a LAN (Local Area Network) or the like. You may make it input via a communication line.

The Fermi level calculation means 11 calculates the Fermi level E _f under the flat band condition of the semiconductor film SC using the device parameters and the like stored in the parameter storage means 16, and calculates the calculated Fermi level E _f . This is output to the charge carrier density calculating means 12.

Specifically, the Fermi level calculation means 11 substitutes device parameters and the like into the above equation (5), and numerically analyzes the equation (5) by the Newton method, the bisection method, or the like, thereby obtaining the Fermi level of the semiconductor film SC. The level E _f is calculated.

The charge carrier density calculating means 12 uses the Fermi level E _f input from the Fermi level calculating means 11, and the density N _td0 ^{+ of} the positively charged donor type defect in the flat band condition of the semiconductor film SC is negatively charged. The density N _ta0 ⁻ , the hole density p _0, and the electron density n ₀ of the _accepted acceptor type defect are calculated, and the calculated charge carrier density is stored in the charge carrier density storage means 17.

Specifically, the charge carrier density calculating means 12 substitutes the Fermi level E _f into the above-described equations (2.3), (3.3), (4.2), and (4.3). _Thus , the density N _td0 ^{+ of} the positively charged donor type defect, the density N _ta0 ^{− of} the negatively charged acceptor type defect, the hole density p ₀ and the electron density n ₀ are calculated. When device parameters or the like are required for calculating these charge carrier densities, the charge carrier density calculation unit 12 refers to the device parameters stored in the parameter storage unit 16 as appropriate.

The calculation range setting means 13 inputs the range of the gate voltage V _g when calculating the gate voltage dependency of the surface potential φ _s via a keyboard (not shown), and calculates the back surface potential φ _b . Various gate voltages V _{g in} the range of the input gate voltage V _g are set as calculation conditions. The calculation range setting unit 13 sets the gate voltage _Vg in the back surface potential calculation unit 14 as a calculation condition.

Specifically, the calculation range setting means 13 inputs the initial value V ₀ of the gate voltage, the maximum value V _max of the gate voltage, and the interval ΔV for changing the gate voltage as the setting range of the gate voltage V _g. . Then, the calculation range setting means 13 sequentially V ₀ , V ₀ + ΔV, V ₀ + 2 × ΔV,..., V based on the input initial value V ₀ , maximum value V _max , and interval ΔV. _max setting the rear surface potential calculating means 14 as the gate voltage _{V g.}

Based on the charge carrier density stored in the charge carrier density storage unit 17, the device parameters stored in the parameter storage unit 16, etc., the back surface potential calculation unit 14 sets the gate voltage V set by the calculation range setting unit 13. The back surface potential φ _b at _g is calculated, and the calculated back surface potential φ _b is output to the surface potential calculation means 15.

Specifically, the back surface potential calculation means 14 calculates the density N _td0 ⁺ of positively charged donor type defects, the density N _ta0 ^{− of} negatively charged acceptor type defects, the hole density p _0, and the electron density n as the charge carrier density. ₀ , necessary device parameters and the like, and the gate voltage V _g are substituted into the equation for the back surface potential φ _b obtained by substituting the equation (22) into the above equation (12), and this back surface potential φ _b The back surface potential φ _b is calculated by numerically analyzing the equation with respect to Newton method, bisection method, or the like. Note that the gate-source voltage V _gs in the equation (9.4) defining V _g ′ in the equation (12) is the difference between the gate voltage V _g and a predetermined source voltage V _s (V _g − V _s ).

The surface potential calculation means 15 is based on the back surface potential φ _b input from the back surface potential calculation means 14, the charge carrier density stored in the charge carrier density storage means 17, the device parameters stored in the parameter storage means 16, and the like. The surface potential φ _s is calculated, and the calculated surface potential φ _s is stored in the surface potential storage means 18 in association with the gate voltage V _g which is a calculation condition.
The surface potential calculation means 15 may store the surface potential φ _s in the surface potential storage means 18 in association with V _g ′ instead of the gate voltage V _g .

Specifically, the surface potential calculation means 15 calculates the back surface potential φ _b , the positively charged donor-type defect density N _td0 ^{+ as} the charge carrier density, and the negatively charged acceptor-type defect density N in Equation (22). _The surface potential φ _s is calculated by substituting _ta0 ⁻ , hole density p ₀ , electron density n ₀ , and necessary device parameters.

Parameter storing means 16, the thickness t _sc semiconductor film SC is a device parameter device parameter input means 10 is _inputted, the thickness t _in the insulating film _IN, the state density of the donor-type defects in the valence band maximum g _td0 , The reciprocal number E _td of the state density distribution of the donor type defect, the state density g _ta0 of the acceptor type defect at the lower end of the conduction band, the reciprocal number E _ta of the state density distribution of the acceptor type defect, the flat band voltage V _fb, and the effective it is for storing the donors density N _d.

In addition, the parameter storage means 16 includes intrinsic Fermi level E _i , intrinsic carrier density n _i , valence band upper end energy E _v , conduction band lower end energy E _c , dielectric constant of the semiconductor film SC as other parameters. ε _sc and the dielectric constant ε _in of the insulating film IN are stored as pre-stored eigenvalues as eigenparameters specific to the material used.

The parameter storage unit 16 stores in advance predetermined values as the source voltage V _s and the absolute temperature T, which are other calculation conditions. Furthermore, a Boltzmann constant k and an electric elementary quantity q, which are constants, are stored in advance.

  The device parameters and the like stored in the parameter storage unit 16 are appropriately referred to by the Fermi level calculation unit 11, the charge carrier density calculation unit 12, the back surface potential calculation unit 14, and the surface potential calculation unit 15.

The charge carrier density storage means 17 is a charge carrier density calculated by the charge carrier density calculation means 12, which is a positively charged donor-type defect density N _td0 ⁺ , a negatively charged acceptor-type defect density N _ta0 ⁻ , The hole density p ₀ and the electron density n ₀ are stored. These data are referred to by the back surface potential calculating means 14 and the surface potential calculating means 15.

The surface potential storage means 18 stores the surface potential φ _s calculated by the surface potential calculation means 15 in association with the gate voltage V _g which is a calculation condition for the surface potential φ _s .

The surface potential φ _s stored in the surface potential storage means 18 is used for, for example, calculation of a current value of a TFT based on the surface potential φ _s . In addition, a graph drawing means (not shown) can output to a display means or a printing means connected to a computer and display it as a TFT characteristic value (for example, see FIGS. 6 and 7).

  In the present embodiment, the device parameters input by the device parameter input means 10 are temporarily stored in the parameter storage means 16 and read out as appropriate by calculation means such as the Fermi level calculation means 11. The means 10 may output the input device parameters directly to the necessary calculation means.

The unique parameter may be input by the device parameter input unit 10 together with the device parameter. Furthermore, the source voltage V _s, which is one of the calculation conditions, may be input by the device parameter input unit 10 or the calculation range setting unit 13.

In the present embodiment, the charge carrier density such as the density N _td0 ^{+ of} the positively charged donor type defect calculated by the charge carrier density calculating unit 12 is temporarily stored in the charge carrier density storing unit 17 to calculate the back surface potential. The charge carrier density calculating unit 12 may output the calculated charge carrier density directly to the back surface potential calculating unit 14 although it is appropriately read by the unit 14.

[Operation of simulation device]
Next, referring to FIG. 5 (refer to FIGS. 1 and 4 as appropriate), the operation of the surface potential simulation apparatus 1 in the present embodiment will be described.

  First, the simulation apparatus 1 inputs device parameters for a TFT to be simulated by the device parameter input means 10 and stores them in the parameter storage means 16 (step S10).

Next, the simulation apparatus 1 uses the device parameters stored in the parameter storage unit 16 by the Fermi level calculation unit 11 to calculate the Fermi level of the semiconductor film SC under the flat band condition according to the equation (5). E _f is calculated, and the calculated Fermi level E _f is output to the charge carrier density calculating means 12 (step S11).

Next, the simulation apparatus 1 uses the Fermi level E _f calculated by the Fermi level calculation unit 11 and the device parameters stored in the parameter storage unit 16 by the charge carrier density calculation unit 12 and the equation ( 2.3), formula (3.3), formula (4.2), and formula (4.3), respectively, the density N _td0 ⁺ of the positively charged donor-type defect under the flat band condition of the semiconductor film SC, negative The values of the density N _ta0 ⁻ , the hole density p ₀ and the electron density n ₀ of the acceptor-type defects charged to are calculated, and these calculated values are stored in the charge carrier density storage means 17 (step S12).

Next, the simulation apparatus 1 uses the calculation range setting means 13 as data for determining the setting range of the gate voltage V _g when calculating the surface potential φ _s , and the gate voltage initial value V ₀ and the maximum gate voltage. The value V _max and the interval ΔV for changing the gate voltage are input from a keyboard (not shown) or the like, and the initial value V ₀ is set as the gate voltage V _g in the back surface potential calculating means 14 (step S13).

Next, the simulation apparatus 1 uses the back surface potential calculation unit 14 to store the positively charged donor-type defect density N _td0 ⁺ and the negatively charged acceptor-type defect density N _ta0 stored in the charge carrier density storage unit 17. ^-, hole density p _0, using the electron density n _0, and device parameters stored in the parameter storage unit 16, etc., by the equation (12) and (22), set by the calculation range setting means 13 gate The back surface potential φ _b at the voltage V _g is calculated, and the calculated back surface potential φ _b is output to the surface potential calculation means 15 (step S14).

Next, the simulation apparatus 1 stores the back surface potential φ _b calculated by the back surface potential calculation unit 14, the charge carrier density stored in the charge carrier density storage unit 17 and the parameter storage unit 16 by the surface potential calculation unit 15. The surface potential φ _s is calculated by the equation (22) using the device parameters and the like, and the calculated surface potential φ _s is associated with the gate voltage V _g which is the calculation condition, and stored in the surface potential storage unit 18. Store (step S15).

Next, the simulation apparatus 1 uses the calculation range setting means 13 to change the calculation condition to the previous gate voltage V _g in order to change the calculation condition to the gate voltage V _g when the next surface potential φ _s is calculated. The interval ΔV is added and set in the back surface potential calculation means 14 (step S16).

Here, in the simulator 1, the computation range setting means 13, when the gate voltage _{V g} was condition changed in step S16 is to determine whether the maximum value greater than _{V max} calculation range (step S17), large ( Since the calculation of the surface potential φ _s in the predetermined calculation range is finished, the simulation apparatus 1 finishes the process.

On the other hand, the gate voltage _{V g} was condition changed in step S16 is equal to or smaller than the maximum value _{V max} of the calculation range (No in step S17), the simulation apparatus 1 returns to step S14, the gate voltage V set in step S16 _{For g} , the calculation of the back surface potential φ _b by the back surface potential calculation means 14 and the calculation of the surface potential φ _s by the surface potential calculation means 15 (step S15) are repeated.

Next, an example of the surface potential simulation method according to the embodiment of the present invention will be described.
6 and 7 show the calculation results of the gate voltage dependence of the surface potential of the TFT. Assuming that the semiconductor film is IGZO and the insulating film is SiO ₂ , the calculation was performed by changing the semiconductor film thickness t _sc , the insulating film thickness t _in , and the density of defects _in the semiconductor film.

The vertical axis represents the surface potential φ _s , and the horizontal axis represents the difference V _g ′ between the gate-source voltage V _gs and the flat band voltage V _fb . In FIG. 6 and FIG. The calculated results are indicated by white circles, and the results calculated by the surface potential simulation method according to the embodiment of the present invention are indicated by solid lines. Which may occur to those calculated for 250 points and the gate voltage _{V g} is changed by 0.1 [V] interval.

In the example illustrated in FIG. _6A , the calculation result when there is no defect in the semiconductor film (g _td0 = 0 [cm ⁻³ eV ⁻¹ ], g _ta0 = 0 [cm ⁻³ eV ⁻¹ ]) shows, an insulating film thickness _{t in} to 50nm, the semiconductor film thickness _{t sc} 30 nm, and 50nm and 100 nm.

In the example shown in FIG. 6B, the conditions of the insulating film thickness and the semiconductor film thickness are the same as those in the example shown in FIG. _6A, but there is a defect in the semiconductor film (g _td0 = 3 × 10 ²⁰ [cm ⁻³ eV ⁻¹ ], E _td = 0.25 [eV], g _ta0 = 8 × 10 ¹⁷ [cm ⁻³ eV ⁻¹ ], E _ta = 0.15 [eV]) Indicates.

Similarly, in the example illustrated in FIG. 7A, the _calculation is performed when there is no defect in the semiconductor film (g _td0 = 0 [cm ⁻³ eV ⁻¹ ], g _ta0 = 0 [cm ⁻³ eV ⁻¹ ]). the results indicate the, 100 nm insulating film thickness _{t in,} and a semiconductor film thickness _{t sc} 30 nm, and 50nm and 100 nm. In the example shown in FIG. 7B, the conditions of the insulating film thickness and the semiconductor film thickness are the same as those in the example shown in FIG. 7A, and there is a defect in the semiconductor film (g _td0 = 3 × 10 ²⁰ [cm ⁻³ eV ⁻¹ ], E _td = 0.25 [eV], g _ta0 = 8 × 10 ¹⁷ [cm ⁻³ eV ⁻¹ ], E _ta = 0.15 [eV]) Indicates.

  As shown in FIG. 6 and FIG. 7, the results (solid line) calculated using the simulation method according to the embodiment of the present invention for various conditions (semiconductor film thickness, insulating film thickness, defect density in the semiconductor film). ) Agrees very well with the exact calculation results (open circles). In addition, the calculation time simulated using an Intel CPU (Central Processing Unit) (Intel Core2 Duo E8400, operating frequency 3.00 GHz) was about 1 minute for a strict calculation of 250 points. On the other hand, the surface potential simulation method according to the embodiment of the present invention takes about 2 to 3 seconds.

  From the above results, the surface potential simulation method according to the embodiment of the present invention enables high-speed and high-accuracy calculation of the surface potential of a storage-type field effect TFT including defects that trap carriers in a semiconductor film. It can be seen that it has been realized.

DESCRIPTION OF SYMBOLS 1 Surface potential simulation apparatus 10 Device parameter input means 11 Fermi level calculation means 12 Charge carrier density calculation means 13 Calculation range setting means 14 Back surface potential calculation means 15 Surface potential calculation means 16 Parameter storage means 17 Charge carrier density storage means 18 Surface Potential storage means S source electrode D drain electrode G gate electrode SC semiconductor film IN insulating film

Claims (3)

A field effect thin film transistor having a structure in which a semiconductor film, an insulating film, and a gate electrode are stacked in this order, which is a storage type thin film transistor including defects in which carriers are trapped in a semiconductor film. A surface potential simulation device that calculates the surface potential of the semiconductor film when the surface in contact with the insulating film is the front surface and the opposite surface is the back surface,
Fermi level calculation means for calculating the Fermi level of the semiconductor film under a flat band condition from Equation (5) which is an equation for the Fermi level;
The semiconductor film is substituted by substituting the Fermi level calculated by the Fermi level calculation means into Equation (2.3), Equation (3.3), Equation (4.2) and Equation (4.3). Charge carrier density calculating means for calculating the density of positively charged donor type defects, the density of negatively charged acceptor type defects, the hole density and the electron density in the flat band condition of
The density of positively charged donor type defects, the density of negatively charged acceptor type defects, the hole density and the electron density calculated by the charge carrier density calculating means are substituted into formula (12). Substituting the equation for the back surface potential of the semiconductor film with the surface potential eliminated, and calculating the back surface potential from the equation for the back surface potential;
Surface potential calculation means for calculating the surface potential by substituting the back surface potential calculated by the back surface potential calculation means into the equation (22);
With
The formula (5) is

And
Formula (2.3), Formula (3.3), Formula (4.2), and Formula (4.3) are:

And
The formula (12) is

And
The formula (22) is

And
here,
β = q / kT,
γ _d = q / E _td ,
γ _a = q / E _ta ,
c _in = ε _in / t _in ,
V _g ′ = V _gs −V _fb
And
k is the Boltzmann constant,
T is the absolute temperature,
q is the elementary charge,
p ₀ is the hole density in the flat band condition of the semiconductor film,
n ₀ is the electron density in the flat band condition of the semiconductor film,
N _td0 ⁺ is the density of positively charged donor-type defects in the flat band condition of the semiconductor film,
N _ta0 ⁻ is the density of negatively charged acceptor defects in the flat band condition of the semiconductor film,
g _td0 is the density of states of donor-type defects at the top of the valence band of the semiconductor film ,
g _ta0 is the density of states of acceptor-type defects at the lower end of the conduction band of the semiconductor film ,
_Ev is the energy at the top of the valence band of the semiconductor film ,
E _c is the energy at the lower end of the conduction band of the semiconductor film ,
E _f is the Fermi level under the flat band condition of the semiconductor film ,
E _td is the reciprocal of the slope of the state density distribution of donor-type defects in the semiconductor film ,
E _ta is the reciprocal of the slope of the state density distribution of the acceptor type defect of the semiconductor film ,
n _i is the intrinsic carrier density of the semiconductor film ,
E _i is the intrinsic Fermi level of the semiconductor film ,
ε _sc is the dielectric constant of the semiconductor film,
t _sc is the film thickness of the semiconductor film,
ε _in is the dielectric constant of the insulating film,
t _in the thickness of the insulating film,
φ is potential,
φ _s is the surface potential,
φ _b is the back surface potential,
N _d is the effective donor density of the semiconductor film ,
V _gs is a gate-source voltage of the thin film transistor,
V _fb is a flat band voltage of the thin film transistor,
This is a surface potential simulation device. Further comprising a calculation range setting means for setting a plurality of Gate voltage in a predetermined range sequentially the back potential calculating means as the calculation conditions of the surface potential,
The back surface potential calculation means calculates the back surface potential by using a difference between the gate voltage and a predetermined source voltage as a voltage between the gate and the source,
The surface potential calculation means calculates the surface potential using the back surface potential,
And the surface potential, the simulation apparatus of the surface potential of claim 1, characterized in that to calculate the gate voltage dependence of the surface potential associated with the gate voltage and calculation conditions for their, the. The computer simulation of the surface potential to function as the simulation apparatus of the surface potential of claim 1 or claim 2 program.

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