JP2014045033A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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JP2014045033A
JP2014045033A JP2012185739A JP2012185739A JP2014045033A JP 2014045033 A JP2014045033 A JP 2014045033A JP 2012185739 A JP2012185739 A JP 2012185739A JP 2012185739 A JP2012185739 A JP 2012185739A JP 2014045033 A JP2014045033 A JP 2014045033A
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adhesive layer
manufacturing
semiconductor
semiconductor chip
semiconductor device
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JP6028460B2 (en
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Masako Taira
理子 平
Keiichi Hatakeyama
恵一 畠山
Yoshinobu Ozaki
義信 尾崎
Mika Tanji
美香 丹治
Masanobu Miyahara
正信 宮原
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Showa Denko Materials Co Ltd
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Hitachi Chemical Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which inhibits cracks of a semiconductor chip and double die pickup by improving pickup performance of the semiconductor chip and inhibits sinking of an end face of an adhesive layer.SOLUTION: A semiconductor device manufacturing method comprises: a process of preparing a laminate in which an adhesive layer containing a radiation curable component is stacked on one surface of a semiconductor wafer; a process of cutting the semiconductor wafer of the laminate by cutting means into a plurality of individual pieces and forming incisions in the adhesive layer; a process of irradiating the laminate with radiation rays from the other surface side of the semiconductor wafer; a process of obtaining, from the laminate, semiconductor chips each including the individual piece of the semiconductor wafer which is cut into a plurality of pieces and irradiated with radiation rays, and a part of the adhesive layer stacked on each of the individual pieces; and a process of manufacturing the semiconductor device including the semiconductor chip.

Description

本発明は、半導体装置の製造方法及び半導体装置に関する。   The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

半導体装置の製造方法において、半導体チップとチップ搭載用の支持基材との接合にフィルム状の接着剤(接着フィルム)が使用されるようになってきている(例えば特許文献1参照)。この半導体装置の製造方法では、接着フィルムを半導体ウェハ全体に貼り付けた後に回転刃にて個片化し、接着フィルム付きの半導体チップを複数得る。そして、この半導体チップを支持基材や他の半導体チップに熱圧着により固定させて、所望の半導体装置を得ている。   In the manufacturing method of a semiconductor device, a film-like adhesive (adhesive film) has come to be used for joining a semiconductor chip and a support substrate for chip mounting (see, for example, Patent Document 1). In this method of manufacturing a semiconductor device, an adhesive film is attached to the entire semiconductor wafer and then separated into pieces with a rotary blade to obtain a plurality of semiconductor chips with the adhesive film. And this semiconductor chip is fixed to a support base material and another semiconductor chip by thermocompression bonding, and the desired semiconductor device is obtained.

特開2005−11839号公報JP 2005-11839 A

ところで、半導体チップの薄肉化が進行し、例えば最終的な厚みが50μm以下となる半導体チップが使用されるようになってきている。このような薄い半導体チップでは、従来のように回転刃にて個片化した後にダイシングテープから剥離(ピックアップ)する際、切断部分に堆積しているバリによって半導体チップの剥離が阻害され、半導体チップが割れてしまう場合があった。また、近年、接合される半導体チップや支持基材における表面段差を吸収して両部材間に確実に接着層が充填されるように、より流動性の高い材料の使用が検討されているが、流動性の高い接着層を使用すると、隣接する半導体チップの接着層同士が切断後に再融着してしまい、隣接する半導体チップ同士が繋がってピックアップされるという現象(ダブルダイピックアップ)が発生してしまう場合があった。   By the way, the semiconductor chip is becoming thinner, and for example, a semiconductor chip having a final thickness of 50 μm or less is used. In such a thin semiconductor chip, when it is separated (picked up) from a dicing tape after being separated into pieces with a rotary blade as in the prior art, peeling of the semiconductor chip is hindered by burrs accumulated on the cut portion, and the semiconductor chip May break. Further, in recent years, the use of a material with higher fluidity has been studied so as to absorb the surface step in the semiconductor chip and the supporting base material to be bonded and reliably fill the adhesive layer between both members. If an adhesive layer with high fluidity is used, the adhesive layers of adjacent semiconductor chips will be re-fused after cutting, causing a phenomenon that adjacent semiconductor chips are connected and picked up (double die pickup). There was a case.

また、上記流動性の高い材料を使用すると、接着層の端面が半導体チップの端面よりも内側に引けてしまい、封止樹脂が内側に侵入することによって半導体装置の信頼性が低下してしまうという問題があった。   Moreover, when the material having high fluidity is used, the end surface of the adhesive layer is drawn to the inner side of the end surface of the semiconductor chip, and the reliability of the semiconductor device is lowered by the penetration of the sealing resin into the inner side. There was a problem.

本発明は、上記課題の解決のためになされたものであり、半導体チップのピックアップ性を改善し、半導体チップの割れ及びダブルダイピックアップを抑制するとともに、接着層の端面における引けを抑制する、半導体装置の製造方法及び半導体装置を提供することを目的とする。   The present invention has been made to solve the above-described problems, and improves the pickup performance of a semiconductor chip, suppresses cracking of the semiconductor chip and double die pickup, and suppresses shrinkage at the end face of the adhesive layer. An object of the present invention is to provide a device manufacturing method and a semiconductor device.

本発明に係る半導体装置の製造方法は、放射線硬化成分を含む接着層を半導体ウェハの一方の面に積層した積層体を準備する工程と、積層体の半導体ウェハを切断手段によって複数の個片に切断し、且つ、接着層に切り込みを入れる工程と、半導体ウェハの他方の面側から積層体に放射線を照射する工程と、複数に切断され且つ放射線を照射された半導体ウェハの個片及び当該個片に積層した接着層の一部を有する半導体チップを、積層体から取得する工程と、当該半導体チップを含む半導体装置を製造する工程と、を備える。   The method for manufacturing a semiconductor device according to the present invention includes a step of preparing a laminate in which an adhesive layer containing a radiation curing component is laminated on one surface of a semiconductor wafer, and the semiconductor wafer of the laminate is divided into a plurality of pieces by a cutting means. Cutting and cutting the adhesive layer, irradiating the laminated body with radiation from the other side of the semiconductor wafer, a plurality of semiconductor wafer pieces cut and irradiated with radiation, and the individual pieces A step of obtaining a semiconductor chip having a part of the adhesive layer laminated on the piece from the laminated body and a step of manufacturing a semiconductor device including the semiconductor chip are provided.

本製造方法では、複数の個片に切断された半導体ウェハの他方の面側(接着層と接していない面側)から放射線を照射することによって、放射線硬化成分を含む接着層の切り込み部付近及び堆積するバリが硬化する。このため、接着層を含む半導体チップをピックアップする際、バリの切れがよくなり、良好なピックアップ性を確保することができる。その結果、半導体チップの割れを抑制し、半導体装置の製造時の歩留りが向上する。   In this manufacturing method, by irradiating radiation from the other surface side (surface side not in contact with the adhesive layer) of the semiconductor wafer cut into a plurality of individual pieces, the vicinity of the cut portion of the adhesive layer containing the radiation curing component and The accumulated burrs are cured. For this reason, when picking up a semiconductor chip including an adhesive layer, burrs are better cut off and good pick-up properties can be secured. As a result, cracking of the semiconductor chip is suppressed, and the yield at the time of manufacturing the semiconductor device is improved.

また、本製造方法では同様に、積層体の切断部分は周辺部より硬化が進行した状態となるため、半導体チップの端部付近の接着層のタック性が低下し、上述したダブルダイピックアップ現象を抑制することができる。その結果、ピックアップ性がより改善し、製造時の歩留りが向上する。なお、本製造方法では、半導体ウェハがマスクとしても機能するため、積層体の切断部分以外の領域は硬化が進行しにくく、半導体チップの接着層は接着性を維持できる。   Similarly, in the present manufacturing method, the cut portion of the laminate is in a state of being hardened from the peripheral portion, so that the tackiness of the adhesive layer near the end of the semiconductor chip is lowered, and the double die pickup phenomenon described above is caused. Can be suppressed. As a result, the pick-up property is further improved and the production yield is improved. In this manufacturing method, since the semiconductor wafer also functions as a mask, the region other than the cut portion of the stacked body is hard to be cured, and the adhesive layer of the semiconductor chip can maintain the adhesiveness.

また、本製造方法によれば、接着層の端面は硬化が進行した状態になるため、引けが抑制された半導体装置を得ることができる。また、逆に、接着層の過剰なはみ出しの抑制も可能となる。さらに、半導体チップの薄型化が進行すると、半導体チップが凸状に反りやすくなり、上述した引けが顕著になるが、本製造方法によれば、引けを十分に抑制することができる。   Moreover, according to this manufacturing method, since the end surface of the adhesive layer is in a state of being hardened, a semiconductor device in which the shrinkage is suppressed can be obtained. Conversely, excessive protrusion of the adhesive layer can be suppressed. Further, as the semiconductor chip becomes thinner, the semiconductor chip is likely to warp in a convex shape, and the above-described shrinkage becomes remarkable. However, according to this manufacturing method, the shrinkage can be sufficiently suppressed.

本発明の製造方法では、積層体を準備する工程において、接着層の一方の面(半導体ウェハと接していない面)にダイシングテープを更に積層してもよい。これにより、切断工程時に半導体ウェハがより固定され、ハンドリング性が向上する。   In the manufacturing method of the present invention, in the step of preparing the laminate, a dicing tape may be further laminated on one surface (the surface not in contact with the semiconductor wafer) of the adhesive layer. Thereby, a semiconductor wafer is fixed more at the time of a cutting process, and handling property improves.

本発明の製造方法では、接着層の切り込みは、接着層の厚みの1〜99%であってもよい。接着層の厚みの1〜99%を切り込むことによって、半導体チップをピックアップする際、バリの切れがよくなり、良好なピックアップ性を確保することができる。   In the manufacturing method of the present invention, the cut of the adhesive layer may be 1 to 99% of the thickness of the adhesive layer. By cutting 1 to 99% of the thickness of the adhesive layer, when the semiconductor chip is picked up, the burrs are better cut off and good pick-up properties can be secured.

本発明の製造方法では、被着体との良好な密着力の確保及び半導体装置全体の厚みの薄化の観点から、接着層の厚みは1〜150μmであってもよい。   In the production method of the present invention, the thickness of the adhesive layer may be 1 to 150 μm from the viewpoint of ensuring good adhesion to the adherend and reducing the thickness of the entire semiconductor device.

本発明の製造方法では、接着層がフィルム状であってもよい。フィルム状接着層は、半導体ウェハに容易に積層できるなど、取扱い性にも優れている。   In the production method of the present invention, the adhesive layer may be a film. The film-like adhesive layer is excellent in handleability because it can be easily laminated on a semiconductor wafer.

また、本発明の製造方法では、半導体ウェハの仕上げ厚みは15〜200μmであってもよい。半導体ウェハの仕上げ厚みが上記範囲であれば、半導体チップ及び半導体装置を薄化しやすくなる。   In the manufacturing method of the present invention, the finished thickness of the semiconductor wafer may be 15 to 200 μm. When the finished thickness of the semiconductor wafer is within the above range, the semiconductor chip and the semiconductor device are easily thinned.

本発明の製造方法では、接着層を全て切断しないことから、目詰まりが起こりにくく、切断手段は回転刃であってもよい。   In the manufacturing method of the present invention, since the entire adhesive layer is not cut, clogging hardly occurs, and the cutting means may be a rotary blade.

本発明の製造方法では、半導体装置を製造する工程において、半導体チップを支持基材に加熱圧着すると共に、封止樹脂によって半導体チップを封止してもよい。本製造方法によれば、半導体チップの接着層の端面の引けが抑制されることから、封止樹脂が半導体チップと基板の間に侵入しにくくなり、半導体装置の信頼性を維持しやすくなる。   In the manufacturing method of the present invention, in the process of manufacturing the semiconductor device, the semiconductor chip may be heat-pressed to the supporting base material and the semiconductor chip may be sealed with a sealing resin. According to the present manufacturing method, the end surface of the adhesive layer of the semiconductor chip is prevented from being contracted, so that the sealing resin hardly enters between the semiconductor chip and the substrate, and the reliability of the semiconductor device can be easily maintained.

本発明は、上述した本製造方法に用いられる接着層であって、放射線硬化成分を含む接着層を提供する。また、本発明の半導体装置は、上述した本製造方法により製造される。   The present invention provides an adhesive layer that is used in the above-described production method and includes a radiation-curable component. The semiconductor device of the present invention is manufactured by the above-described manufacturing method.

本発明の半導体装置は、上述した本製造方法により製造され、接着層硬化体を含む半導体チップと、接着層硬化体を介して半導体チップを支持する支持基材と、半導体チップの少なくとも一部を覆う封止樹脂硬化体とを備え、接着層硬化体の端部に封止樹脂侵入抑制部が形成されている。本半導体装置は、接着層硬化体の端部に封止樹脂侵入抑制部が形成されており、製造時における半導体チップと支持基材との間への封止樹脂の侵入を抑制したものであることから、信頼性に優れたものとなる。   A semiconductor device of the present invention is manufactured by the above-described manufacturing method, and includes a semiconductor chip including an adhesive layer cured body, a support base that supports the semiconductor chip via the adhesive layer cured body, and at least a part of the semiconductor chip. And a sealing resin intrusion suppressing portion is formed at an end of the adhesive layer cured body. In this semiconductor device, the sealing resin intrusion suppressing portion is formed at the end of the adhesive layer cured body, and the intrusion of the sealing resin between the semiconductor chip and the support base during manufacturing is suppressed. As a result, the reliability is excellent.

本発明によれば、半導体チップのピックアップ性を改善し、半導体チップの割れ及びダブルダイピックアップを抑制するとともに、接着層の端面における引けを抑制する半導体装置の製造方法及び半導体装置を提供することができる。   According to the present invention, it is possible to provide a semiconductor device manufacturing method and a semiconductor device that improve the pick-up property of a semiconductor chip, suppress cracking of the semiconductor chip and double die pick-up, and suppress shrinkage at the end face of the adhesive layer. it can.

本実施形態に係る半導体装置の一実施形態の断面図である。It is sectional drawing of one Embodiment of the semiconductor device which concerns on this embodiment. 支持基材の断面図である。It is sectional drawing of a support base material. 半導体チップの断面図である。It is sectional drawing of a semiconductor chip. ダイシングテープ上に、接着層及び半導体ウェハを設置する工程を示す図である。It is a figure which shows the process of installing an adhesive layer and a semiconductor wafer on a dicing tape. 図4の半導体ウェハをダイシングする工程を示す図である。It is a figure which shows the process of dicing the semiconductor wafer of FIG. 図5で切断された半導体ウェハ及び接着層に、放射線を照射する工程を示す図である。It is a figure which shows the process of irradiating a semiconductor wafer and the contact bonding layer cut | disconnected in FIG. 5 with a radiation. 図6の放射線照射工程後に、半導体チップをピックアップする工程を示す図である。It is a figure which shows the process of picking up a semiconductor chip after the radiation irradiation process of FIG. 半導体チップを支持基材等に接着する工程を示す図である。It is a figure which shows the process of adhere | attaching a semiconductor chip on a support base material. 電極同士をボンディングワイヤで接続する工程を示す図である。It is a figure which shows the process of connecting electrodes with a bonding wire.

以下、本発明の好適な実施形態について、図面を参照して詳細に説明する。図中、同一又は同等の構成要素については同一符号を付し、重複する説明は適宜省略する。   DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the figure, the same or equivalent components are denoted by the same reference numerals, and repeated description is omitted as appropriate.

まず、本実施形態に係る半導体装置について説明する。図1〜図3に示されるように、半導体装置1は、支持基材2と、半導体チップ10とを有し、モールド部(封止樹脂硬化体)6で封止されている。   First, the semiconductor device according to the present embodiment will be described. As shown in FIGS. 1 to 3, the semiconductor device 1 includes a support base 2 and a semiconductor chip 10, and is sealed with a mold part (encapsulated resin cured body) 6.

支持基材2は、図1及び図2に示されるように、板状の部材であり、基板3と、基板3の一方の面3a上に設けられた複数の電極4とを有している。基板3のうち電極4と対向する部分には、一方の面3aから他方の面3bに向かって開口する貫通孔3cが形成されている。各貫通孔3cには、電極4の下面に接するように半田が充填された半田部4aがそれぞれ形成されている。半田部4aは、基板3の他方の面3bから半球状に膨出している。   As shown in FIGS. 1 and 2, the support base material 2 is a plate-like member, and includes a substrate 3 and a plurality of electrodes 4 provided on one surface 3 a of the substrate 3. . A through hole 3c that opens from one surface 3a to the other surface 3b is formed in a portion of the substrate 3 that faces the electrode 4. Each through hole 3c is formed with a solder portion 4a filled with solder so as to be in contact with the lower surface of the electrode 4. The solder portion 4a bulges out from the other surface 3b of the substrate 3 in a hemispherical shape.

半導体チップ10は、図1〜図3に示されるように、チップ本体13と、チップ本体13の下面13aに積層された個片化された接着層14が硬化した接着層硬化体14bと、チップ本体13の上面13b上に設けられた複数の電極15とを有している。半導体チップ10の接着層硬化体14bは、後述する製造方法によって端部に封止樹脂侵入抑制部(放射線硬化部)14aを形成する。   As shown in FIGS. 1 to 3, the semiconductor chip 10 includes a chip body 13, an adhesive layer cured body 14 b obtained by curing an individual adhesive layer 14 laminated on the lower surface 13 a of the chip body 13, and a chip. A plurality of electrodes 15 provided on an upper surface 13b of the main body 13; The adhesive layer cured body 14b of the semiconductor chip 10 forms the sealing resin intrusion suppressing portion (radiation curing portion) 14a at the end by a manufacturing method described later.

各半導体チップ10は、図1〜図3に示されるように、互いに重なった状態で、支持基材2の上面2a又は他の半導体チップ10の上面13bに接着層14を介して貼り合わされている。各半導体チップ10の電極15と支持基材2の電極4又は他の半導体チップ10の電極15とは、ボンディングワイヤ5によって互いに接続されている。支持基材2の上面2a上には、封止樹脂によってモールド部6が形成され、各半導体チップ10はモールド部6内に封止されている。   As shown in FIGS. 1 to 3, each semiconductor chip 10 is bonded to the upper surface 2 a of the support base 2 or the upper surface 13 b of another semiconductor chip 10 with an adhesive layer 14 in a state of overlapping each other. . The electrode 15 of each semiconductor chip 10 and the electrode 4 of the support base 2 or the electrode 15 of another semiconductor chip 10 are connected to each other by a bonding wire 5. On the upper surface 2 a of the support base 2, a mold part 6 is formed by sealing resin, and each semiconductor chip 10 is sealed in the mold part 6.

続いて、上述した構成を有する半導体装置1の製造方法について説明する。   Next, a method for manufacturing the semiconductor device 1 having the above-described configuration will be described.

まず、半導体装置1に含まれる半導体チップ10を、図4〜7に示す工程によって製造する。具体的には、最初に、半導体ウェハ30、接着層40(半導体チップ10に積層する接着層40の一部は「接着層14」として示す)、ダイシングテープ50及びリングフレーム60を準備する。なお、図4〜図7では、説明を容易にするため、半導体ウェハ30上の複数の電極15は図示を省略している。   First, the semiconductor chip 10 included in the semiconductor device 1 is manufactured by the steps shown in FIGS. Specifically, first, a semiconductor wafer 30, an adhesive layer 40 (a part of the adhesive layer 40 laminated on the semiconductor chip 10 is indicated as “adhesive layer 14”), a dicing tape 50, and a ring frame 60 are prepared. 4 to 7, the illustration of the plurality of electrodes 15 on the semiconductor wafer 30 is omitted for ease of explanation.

[半導体ウェハ]
半導体ウェハ30は、特に制限されないが、例えばシリコンウェハである。半導体ウェハ30は、集積回路形成面に集積回路保護用のバックグラインドテープを貼り付け、この状態で半導体ウェハ30の裏面をグラインダで研削し、続いて、この研削によって生じた裏面のダメージ層を、ウエットエッチング、ドライポリッシング、プラズマエッチングなどの方法によって除去することにより、薄くすることが好ましい。
[Semiconductor wafer]
The semiconductor wafer 30 is not particularly limited, but is a silicon wafer, for example. The semiconductor wafer 30 is affixed with a back grind tape for protecting the integrated circuit on the integrated circuit forming surface, and in this state, the back surface of the semiconductor wafer 30 is ground with a grinder. It is preferable to make it thin by removing it by a method such as wet etching, dry polishing, or plasma etching.

半導体ウェハ30の仕上げ厚みは、半導体装置を薄型化する観点から、15〜200μmであることが好ましく、15〜125μmであることがより好ましく、15〜75μmであることがさらに好ましい。なお、ウエットエッチング、ドライポリッシング、プラズマエッチングなどの処理方法は、半導体ウェハ30の厚さ方向に進行する処理速度が、グラインダによる研削の速度に比べて遅い反面、半導体ウェハ内部に与えるダメージがグラインダによる研削に比較して小さいという効果がある。さらに、グラインダによる研削で発生する半導体ウェハ30内部のダメージ層を除去することができ、半導体ウェハ30及び半導体チップ10が割れにくくなるという効果もある。   From the viewpoint of reducing the thickness of the semiconductor device, the finished thickness of the semiconductor wafer 30 is preferably 15 to 200 μm, more preferably 15 to 125 μm, and still more preferably 15 to 75 μm. The processing methods such as wet etching, dry polishing, and plasma etching are slower in processing speed in the thickness direction of the semiconductor wafer 30 than the grinding speed by the grinder, but damage to the semiconductor wafer is caused by the grinder. There is an effect that it is smaller than grinding. Furthermore, the damage layer inside the semiconductor wafer 30 generated by grinding by the grinder can be removed, and there is an effect that the semiconductor wafer 30 and the semiconductor chip 10 are hardly broken.

[接着層]
接着層40は、フィルム状、又は、液状材を塗布後に半硬化状態としたものを準備する。フィルム状の接着層40は、後述する各構成成分を含有するワニス(混合物)を調合し、調合したワニスを剥離処理済のセパレートフィルム(例えば、ポリエチレンテレフタレートフィルム)上に塗布して加熱処理することによって作製される。ダイボンディングフィルムとしての使用に際しては、例えば、円形状のフィルムとして用いることができる。なお、後述するダイシングテープ50にフィルム状の接着層40を積層させた一体構造の接着シートとして作製してもよい。
[Adhesive layer]
The adhesive layer 40 is prepared as a film or a semi-cured state after applying a liquid material. The film-like adhesive layer 40 is prepared by preparing a varnish (mixture) containing each component described later, applying the prepared varnish on a separate film (for example, polyethylene terephthalate film) that has been subjected to a release treatment, and subjecting it to a heat treatment. It is produced by. When used as a die bonding film, for example, it can be used as a circular film. In addition, you may produce as an adhesive sheet of the integral structure which laminated | stacked the film-like adhesive layer 40 on the dicing tape 50 mentioned later.

また、液状の接着層40は、上記同様の材料を混練してワニスを調合し、調合したワニスを半導体ウェハ30の裏面30aにスピンコータ等を用いて塗布する。次に、熱や放射線照射を行い、塗布したワニスを半硬化状態にすることにより作製できる。なお、混練の際にワニスを加熱することもできる。また、半導体ウェハ30への塗布は、スピンコート以外に、スプレーコート、スクリーン印刷、インクジェット塗布などを単独又は組み合わせて行うことができる。   The liquid adhesive layer 40 is prepared by kneading the same materials as described above to prepare a varnish, and applying the prepared varnish to the back surface 30a of the semiconductor wafer 30 using a spin coater or the like. Next, it can be produced by applying heat or radiation to bring the applied varnish into a semi-cured state. The varnish can also be heated during kneading. Further, the application to the semiconductor wafer 30 can be performed by spray coating, screen printing, ink jet coating or the like alone or in combination other than spin coating.

接着層40は、放射線硬化成分を含む接着性を有する層であれば特に限定されず、例えば構成成分として、エポキシ樹脂、硬化剤及び硬化促進剤を含む混合物(接着剤組成物)を含有することが好ましい。   The adhesive layer 40 is not particularly limited as long as it is an adhesive layer containing a radiation curing component. For example, the adhesive layer 40 contains a mixture (adhesive composition) containing an epoxy resin, a curing agent and a curing accelerator as constituent components. Is preferred.

エポキシ樹脂は、2個以上のエポキシ基を有する化合物が好ましい。エポキシ樹脂としては、硬化性や硬化物特性の点から、フェノールのグリシジルエーテル型のエポキシ樹脂が好ましい。フェノールのグリシジルエーテル型のエポキシ樹脂としては、例えば、ビスフェノールA、ビスフェノールAD、ビスフェノールS、ビスフェノールF又はハロゲン化ビスフェノールAとエピクロルヒドリンの縮合物、フェノールノボラック樹脂のグリシジルエーテル、クレゾールノボラック樹脂のグリシジルエーテル及びビスフェノールAノボラック樹脂のグリシジルエーテルが挙げられる。これらの中でも、ノボラック型エポキシ樹脂(クレゾールノボラック樹脂のグリシジルエーテル及びフェノールノボラック樹脂のグリシジルエーテル等)は、硬化物の架橋密度が高く、フィルム加熱時の接着強度を高くすることができる点で好ましい。これらは1種単独で又は複数組み合わせて用いることができる。   The epoxy resin is preferably a compound having two or more epoxy groups. The epoxy resin is preferably a phenol glycidyl ether type epoxy resin from the viewpoint of curability and cured product characteristics. Examples of phenolic glycidyl ether type epoxy resins include bisphenol A, bisphenol AD, bisphenol S, bisphenol F or a condensate of halogenated bisphenol A and epichlorohydrin, glycidyl ether of phenol novolac resin, glycidyl ether of cresol novolac resin and bisphenol. A novolak resin glycidyl ether. Among these, novolac type epoxy resins (such as glycidyl ether of cresol novolac resin and glycidyl ether of phenol novolac resin) are preferable in that the cured product has a high cross-linking density and can increase the adhesive strength during heating of the film. These can be used singly or in combination.

本実施形態において、エポキシ樹脂が放射線硬化成分として機能してもよい。ここでいう放射線硬化成分とは、紫外線、電子線、X線、β線又はγ線等の放射線の照射により硬化しうる成分のことをいう。また、エポキシ樹脂とは別に、放射線硬化成分を含有してもよい。   In this embodiment, an epoxy resin may function as a radiation curing component. The term “radiation curable component” as used herein refers to a component that can be cured by irradiation with radiation such as ultraviolet rays, electron beams, X-rays, β rays, or γ rays. Moreover, you may contain a radiation hardening component separately from an epoxy resin.

エポキシ樹脂の硬化剤としては、例えば、フェノール系化合物、脂肪族アミン、脂環族アミン、芳香族ポリアミン、ポリアミド、脂肪族酸無水物、脂環族酸無水物、芳香族酸無水物、ジシアンジアミド、有機酸ジヒドラジド、三フッ化ホウ素アミン錯体、イミダゾール類及び第3級アミンが挙げられる。これらの中でもフェノール系化合物が好ましく、その中でも2個以上のフェノール性水酸基を有するフェノール系化合物が特に好ましい。より具体的には、ナフトールノボラック樹脂及びトリスフェノールノボラック樹脂が好ましい。これらのフェノール系化合物をエポキシ樹脂の硬化剤として用いると、半導体装置の製造時の加熱によるチップ表面及び装置の汚染や、臭気の原因となるアウトガスの発生を有効に低減できる。   Examples of epoxy resin curing agents include phenolic compounds, aliphatic amines, alicyclic amines, aromatic polyamines, polyamides, aliphatic acid anhydrides, alicyclic acid anhydrides, aromatic acid anhydrides, dicyandiamide, Examples include organic acid dihydrazide, boron trifluoride amine complex, imidazoles and tertiary amines. Among these, phenol compounds are preferable, and phenol compounds having two or more phenolic hydroxyl groups are particularly preferable. More specifically, a naphthol novolak resin and a trisphenol novolak resin are preferable. When these phenolic compounds are used as a curing agent for an epoxy resin, it is possible to effectively reduce the contamination of the chip surface and the device due to heating during the production of the semiconductor device and the generation of outgas which causes odor.

エポキシ樹脂の硬化促進剤としては、例えば、イミダゾール類やホスフィン系化合物が挙げられる。これらの中でも、イミダゾール又はTPPK(テトラフェニルホスフォニウムテトラフェニルボレート)が好ましく用いられる。   Examples of the epoxy resin curing accelerator include imidazoles and phosphine compounds. Among these, imidazole or TPPK (tetraphenylphosphonium tetraphenylborate) is preferably used.

接着層40は、ベース樹脂及びフィラーを含有してもよい。ベース樹脂は、エポキシ樹脂との相溶性に優れていれば特に限定されないが、例えば、アクリルゴム、ポリイミド等を用いることができる。   The adhesive layer 40 may contain a base resin and a filler. Although base resin will not be specifically limited if it is excellent in compatibility with an epoxy resin, For example, an acrylic rubber, a polyimide, etc. can be used.

フィラーは、他の成分に悪影響を及ぼさなければ特に限定はされないが、無機フィラーであることが好ましい。より具体的には、水酸化アルミニウム、水酸化マグネシウム、炭酸カルシウム、炭酸マグネシウム、ケイ酸カルシウム、ケイ酸マグネシウム、酸化カルシウム、酸化マグネシウム、アルミナ、窒化アルミニウム、ほう酸アルミニウムウイスカ、窒化ホウ素、結晶性シリカ、非晶性シリカ及びアンチモン酸化物からなる群より選ばれる少なくとも1種の無機材料を含む無機フィラーが好ましい。これらの中でも、熱伝導性向上のためには、アルミナ、窒化アルミニウム、窒化ホウ素、結晶性シリカ及び非晶性シリカが好ましい。溶融粘度の調整やチクソトロピック性の付与の目的には、水酸化アルミニウム、水酸化マグネシウム、炭酸カルシウム、炭酸マグネシウム、ケイ酸カルシウム、ケイ酸マグネシウム、酸化カルシウム、酸化マグネシウム、アルミナ、結晶性シリカ及び非晶性シリカが好ましい。また、耐湿性を向上させるためには、アルミナ、シリカ、水酸化アルミニウム及びアンチモン酸化物が好ましい。これらは1種単独で又は複数組み合わせて用いることができる。   The filler is not particularly limited as long as it does not adversely affect other components, but is preferably an inorganic filler. More specifically, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, alumina, aluminum nitride, aluminum borate whisker, boron nitride, crystalline silica, An inorganic filler containing at least one inorganic material selected from the group consisting of amorphous silica and antimony oxide is preferred. Among these, alumina, aluminum nitride, boron nitride, crystalline silica, and amorphous silica are preferable for improving thermal conductivity. For the purpose of adjusting melt viscosity and imparting thixotropic properties, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, alumina, crystalline silica and non-crystalline silica Crystalline silica is preferred. In order to improve moisture resistance, alumina, silica, aluminum hydroxide and antimony oxide are preferred. These can be used singly or in combination.

本実施形態において、接着層40の厚みは、1〜150μmであることが好ましく、3〜125μmであることがより好ましく、5〜100μmであることがさらに好ましく、7〜80μmであることが特に好ましい。接着層40の厚みが1μm以上であれば、被着体との良好な密着力を確保しやすくなり、150μm以下であれば半導体装置全体の厚みを薄化しやすくなる。   In the present embodiment, the thickness of the adhesive layer 40 is preferably 1 to 150 μm, more preferably 3 to 125 μm, further preferably 5 to 100 μm, and particularly preferably 7 to 80 μm. . If the thickness of the adhesive layer 40 is 1 μm or more, it is easy to ensure good adhesion to the adherend, and if it is 150 μm or less, the thickness of the entire semiconductor device is easily reduced.

[ダイシングテープ]
ダイシングテープ50は、基材フィルム51と、基材フィルム51上に積層される粘着層52とを含んだものを準備する。基材フィルム51は、例えば、ポリエチレンフィルム、ポリプロピレンフィルム、ポリ塩化ビニルフィルム、ポリエチレンテレフタレートフィルム、エチレン−酢酸ビニル共重合体フィルム、又は、アイオノマー樹脂フィルムを用いることができる。基材フィルム51の厚さは、例えば、15〜200μm程度が好ましく、40〜150μmがより好ましく、60〜120μmがさらに好ましい。
[Dicing tape]
The dicing tape 50 is prepared including a base film 51 and an adhesive layer 52 laminated on the base film 51. As the base film 51, for example, a polyethylene film, a polypropylene film, a polyvinyl chloride film, a polyethylene terephthalate film, an ethylene-vinyl acetate copolymer film, or an ionomer resin film can be used. For example, the thickness of the base film 51 is preferably about 15 to 200 μm, more preferably 40 to 150 μm, and still more preferably 60 to 120 μm.

ダイシングテープ50の粘着層52は、基材フィルム51の一方の主面51a全体を覆うように配置されている。粘着層52の厚さは、5〜50μmが好ましく、5〜40μmがより好ましく、5〜30μmがさらに好ましい。粘着層を構成する粘着剤としては、例えば、アクリル系粘着剤、ゴム系粘着剤及びシリコーン系粘着剤が用いられる。   The adhesive layer 52 of the dicing tape 50 is disposed so as to cover the entire one main surface 51 a of the base film 51. 5-50 micrometers is preferable, as for the thickness of the adhesion layer 52, 5-40 micrometers is more preferable, and 5-30 micrometers is further more preferable. As an adhesive which comprises an adhesion layer, an acrylic adhesive, a rubber adhesive, and a silicone adhesive are used, for example.

粘着層52は、後述する半導体チップを取得する工程(ピックアップ工程)において、接着層40からダイシングテープ50を容易に剥離可能な粘着性を有する層であれば特に制限なく用いることができ、例えば弱粘着性の感圧粘着層を用いることができる。粘着層52と接着層40との密着力の上限値は、0.6N/25mm以下が好ましく、0.5N/25mm以下がより好ましく、0.4N/25mm以下がさらに好ましい。両者の密着力の上限値が上記範囲であれば、後述するピックアップ工程において、粘着層52及び接着層40間での剥離が容易になる。   The pressure-sensitive adhesive layer 52 can be used without particular limitation as long as it has a pressure-sensitive adhesive property that allows the dicing tape 50 to be easily peeled off from the adhesive layer 40 in a process (pickup process) for obtaining a semiconductor chip to be described later. An adhesive pressure-sensitive adhesive layer can be used. The upper limit value of the adhesion between the adhesive layer 52 and the adhesive layer 40 is preferably 0.6 N / 25 mm or less, more preferably 0.5 N / 25 mm or less, and further preferably 0.4 N / 25 mm or less. If the upper limit value of both adhesion forces is within the above range, peeling between the pressure-sensitive adhesive layer 52 and the adhesive layer 40 is facilitated in a pickup process described later.

一方、粘着層52と接着層40との密着力の下限値は、0.01N/25mm以上が好ましく、0.03N/25mm以上がより好ましく、0.05N/25mm以上がさらに好ましい。両者の密着力の下限値が上記範囲であれば、後述するダイシング時に接着層40が粘着層52から剥離することを十分に抑制できる。   On the other hand, the lower limit value of the adhesion between the adhesive layer 52 and the adhesive layer 40 is preferably 0.01 N / 25 mm or more, more preferably 0.03 N / 25 mm or more, and even more preferably 0.05 N / 25 mm or more. When the lower limit value of the adhesion between the two is within the above range, it is possible to sufficiently suppress the adhesive layer 40 from peeling from the adhesive layer 52 during dicing described later.

なお、粘着層52と接着層40との密着力は、例えば、株式会社オリエンテック社製「テンシロン引張強度試験機 RTA−100型」を用いて垂直方向に200mm/minの速度で剥離(90°剥離)したときの剥離力の測定により求めることができる。   The adhesive force between the adhesive layer 52 and the adhesive layer 40 is, for example, peeled off at a rate of 200 mm / min in the vertical direction using a “Tensilon tensile strength tester RTA-100 type” manufactured by Orientec Co., Ltd. (90 ° It can be determined by measuring the peeling force when peeling.

粘着層52を構成する粘着剤は、接着層40と同様に、放射線硬化成分を含んでいてもよい。後述する製造方法における放射線照射によれば、粘着層52の照射された部分の粘着性を低下させることができ、切断された半導体チップ10と粘着層52との剥離性が向上することから、安定したピックアップ性を確保しやすくなる。   The pressure-sensitive adhesive constituting the pressure-sensitive adhesive layer 52 may contain a radiation curable component, like the adhesive layer 40. According to the radiation irradiation in the manufacturing method to be described later, the adhesiveness of the irradiated part of the adhesive layer 52 can be reduced, and the peelability between the cut semiconductor chip 10 and the adhesive layer 52 is improved. It becomes easy to secure the pick-up property.

[リングフレーム]
リングフレーム60は、金属製又はプラスチック製の成形体を準備する。リングフレーム60は、例えば、略円環状をなしており、リングフレーム60の外周の一部には、ガイド用の平坦切欠部(図示せず)が形成されている。リングフレーム60は、中央部に開口を有している。リングフレーム60の開口の内径寸法(直径)は、ダイシングされる半導体ウェハ30のウェハ径よりも幾分大きいものが好適に用いられる。リングフレーム60の形状は、円環状のものに限定されず、従来用いられている種々の形状(例えば、矩形環状)のものを用いてもよい。
[Ring frame]
The ring frame 60 prepares a molded body made of metal or plastic. The ring frame 60 has, for example, a substantially annular shape, and a flat cutout (not shown) for guide is formed on a part of the outer periphery of the ring frame 60. The ring frame 60 has an opening at the center. The inner diameter dimension (diameter) of the opening of the ring frame 60 is preferably slightly larger than the wafer diameter of the semiconductor wafer 30 to be diced. The shape of the ring frame 60 is not limited to an annular shape, and various shapes conventionally used (for example, a rectangular shape) may be used.

(積層体を作製する工程)
上述したような半導体ウェハ30等の準備の次に、図4に示されるように、ダイシングテープ50の上に環状のリングフレーム60を設置する。また、ダイシングテープ50のうち、リングフレーム60の内側の部分の上にフィルム状の接着層40を介して半導体ウェハ30を設定する。この際、ダイシングテープ50は、接着層40の外縁よりも外側に張り出している。このような配置により、半導体ウェハ30、接着層40、ダイシングテープ50がこの順に積層された積層体Aが作製(準備)される。
(Process for producing a laminate)
After the preparation of the semiconductor wafer 30 and the like as described above, an annular ring frame 60 is set on the dicing tape 50 as shown in FIG. Further, the semiconductor wafer 30 is set on the inner portion of the ring frame 60 of the dicing tape 50 via the film-like adhesive layer 40. At this time, the dicing tape 50 protrudes outside the outer edge of the adhesive layer 40. With such an arrangement, a stacked body A in which the semiconductor wafer 30, the adhesive layer 40, and the dicing tape 50 are stacked in this order is manufactured (prepared).

なお、セパレートフィルム付きフィルム状接着層40を用いる場合には、例えば、以下の(1)又は(2)に示す方法により、半導体ウェハ30、接着層40及びダイシングテープ50が積層された積層体Aを得ることができる。
(1)まず、セパレートフィルム付きフィルム状接着層40と半導体ウェハ30とを貼り合わせる。次に、セパレートフィルム付きフィルム状接着層40のセパレートフィルムを剥離し、ダイシングテープ50の粘着層52とフィルム状接着層40とを貼り合わせる。
(2)まず、セパレートフィルム付きフィルム状接着層40と、ダイシングテープ50の粘着層52とを貼り合わせる。次に、セパレートフィルム付きフィルム状接着層40のセパレートフィルムを剥離し、フィルム状接着層40(セパレートフィルムが付いていた側)と半導体ウェハ30とを貼り合わせる。
In addition, when using the film-like adhesive layer 40 with a separate film, for example, the laminate A in which the semiconductor wafer 30, the adhesive layer 40, and the dicing tape 50 are laminated by the method shown in the following (1) or (2). Can be obtained.
(1) First, the film-like adhesive layer 40 with a separate film and the semiconductor wafer 30 are bonded together. Next, the separate film of the film-like adhesive layer 40 with a separate film is peeled off, and the adhesive layer 52 of the dicing tape 50 and the film-like adhesive layer 40 are bonded together.
(2) First, the film-like adhesive layer 40 with a separate film and the adhesive layer 52 of the dicing tape 50 are bonded together. Next, the separate film of the film-like adhesive layer 40 with a separate film is peeled off, and the film-like adhesive layer 40 (the side on which the separate film is attached) and the semiconductor wafer 30 are bonded together.

また、液状の接着層40を用いる場合は、以下の(3)に示す方法により、半導体ウェハ30、接着層40及びダイシングテープ50が積層された積層体Aを得ることができる。
(3)半導体ウェハ30の裏面30aにワニス(液状ワニス)をスピンコート等により塗布し、加熱又は放射線照射を行うことで半硬化状態とする。その面にダイシングテープ50の粘着層52を貼り合わせることによって積層体Aを得る。
Moreover, when using the liquid contact bonding layer 40, the laminated body A by which the semiconductor wafer 30, the contact bonding layer 40, and the dicing tape 50 were laminated | stacked by the method shown to the following (3) can be obtained.
(3) A varnish (liquid varnish) is applied to the back surface 30a of the semiconductor wafer 30 by spin coating or the like, and is heated or irradiated to give a semi-cured state. The laminated body A is obtained by bonding the adhesive layer 52 of the dicing tape 50 to the surface.

(半導体ウェハ及び接着層の厚みの一部を切断する工程)
次に、図5に示されるように、上述した積層体Aに含まれる半導体ウェハ30を切断装置(切断手段、ダイサー)の回転刃Bで切断し、複数の個片である複数のチップ本体13へと分割する。また、接着層40にも切断手段によって切り込み(接着層40の一部の切断)が入れられる。図5に示すように、本実施形態の製造方法においては、接着層40を完全に切断せずに一部を残す工法(ハーフカット工法)を用いているため、分割されたチップ本体13は、接着層40によって保持されている。なお、回転刃Bで切断された領域30cの下方には、切断によって生じる接着層40の切断片などからなるバリ(図示せず)が堆積している。
(Process of cutting a part of the thickness of the semiconductor wafer and the adhesive layer)
Next, as shown in FIG. 5, the semiconductor wafer 30 included in the above-described stacked body A is cut with the rotary blade B of the cutting device (cutting means, dicer), and a plurality of chip bodies 13 which are a plurality of pieces. Divide into Further, the adhesive layer 40 is also cut by a cutting means (part of the adhesive layer 40 is cut). As shown in FIG. 5, in the manufacturing method of the present embodiment, since the method of leaving a part without completely cutting the adhesive layer 40 (half-cut method) is used, the divided chip body 13 is: It is held by the adhesive layer 40. In addition, below the region 30c cut by the rotary blade B, burrs (not shown) made of cut pieces of the adhesive layer 40 generated by cutting are accumulated.

接着層の切り込みは、接着層の厚み(接着層の厚み方向の高さ)の1〜99%であることが好ましく、3〜85%であることがより好ましく、5〜80%であることがさらに好ましい。   The cut of the adhesive layer is preferably 1 to 99% of the thickness of the adhesive layer (height in the thickness direction of the adhesive layer), more preferably 3 to 85%, and 5 to 80%. Further preferred.

半導体ウェハ30を切断する際に使用するダイサーや回転刃B(ブレード)は、一般に市販されているものを使用することができる。ダイサーとしては、例えば、株式会社ディスコ社製のフルオートマチックダイシングソー6000シリーズやセミオートマチックダイシングソー3000シリーズなどが使用できる。ブレードとしては、例えば、株式会社ディスコ社製のダイシングブレードNBC−ZH05シリーズやNBC−ZHシリーズなどが使用できる。   As the dicer and the rotary blade B (blade) used when cutting the semiconductor wafer 30, commercially available ones can be used. As the dicer, for example, a full automatic dicing saw 6000 series and a semi-automatic dicing saw 3000 series manufactured by DISCO Corporation can be used. As the blade, for example, a dicing blade NBC-ZH05 series or NBC-ZH series manufactured by DISCO Corporation can be used.

また、積層体Aを切断する工程において、例えば、株式会社ディスコ社製のフルオートマチックダイシングソー6000シリーズなどの回転刃だけではなく、株式会社ディスコ社製のフルオートマチックレーザソー7000シリーズ等のレーザを用いて切断してもよい。   In the step of cutting the laminate A, for example, not only a rotary blade such as a full automatic dicing saw 6000 series manufactured by Disco Corporation, but also a laser such as a full automatic laser saw 7000 series manufactured by Disco Corporation is used. May be cut.

(放射線を照射する工程)
半導体ウェハ30の切断工程が終了すると、次に、図6に示すように、回転刃Bで個片化された積層体A(複数のチップ本体13)に対して、半導体ウェハ30(チップ本体13)の上面側(接着層40が配置されていない側)から放射線Lを照射する。すなわち、ダイシング工程で切り込みを入れた方向から、個片化されたチップ本体13に対して放射線Lを放射線源Rから照射する。この照射された放射線Lは、チップ本体13の下に位置する部分ではチップ本体13によって遮られるが、切断によって形成された領域30c内を通過し、接着層40の切り込み部付近を照射する。
(Process to irradiate radiation)
When the cutting process of the semiconductor wafer 30 is completed, next, as shown in FIG. 6, the semiconductor wafer 30 (chip body 13) is applied to the stacked body A (a plurality of chip bodies 13) separated by the rotary blade B. ) Is irradiated from the upper surface side (side where the adhesive layer 40 is not disposed). That is, the radiation L is irradiated from the radiation source R to the chip body 13 that has been separated into pieces from the direction in which the cut is made in the dicing process. The irradiated radiation L is blocked by the chip body 13 at a portion located below the chip body 13, but passes through the region 30 c formed by cutting and irradiates the vicinity of the cut portion of the adhesive layer 40.

この放射線Lの照射により、接着層40の切り込み部分及びその付近に堆積しているバリ(半導体ウェハ30や接着層40の切断片含む)が硬化し、放射線硬化部14aを形成する。なお、放射線の種類としては、例えば、紫外線、電子線、X線、β線、γ線等の何れを用いても構わないが、接着層40に含まれる硬化材料に対応した放射線を用いることが必要である。   By this radiation L irradiation, the burrs (including the cut pieces of the semiconductor wafer 30 and the adhesive layer 40) deposited in the vicinity of the cut portion of the adhesive layer 40 and the vicinity thereof are cured to form the radiation curing portion 14a. In addition, as a kind of radiation, for example, any of ultraviolet rays, electron beams, X-rays, β rays, γ rays and the like may be used, but radiation corresponding to the curable material included in the adhesive layer 40 is used. is necessary.

放射線源Rとしては、紫外線などの放射線を照射するものであれば特に制限されず、例えば高圧水銀灯やメタルハライドランプなどを用いることができる。また、放射線Lの放射線量は、バリを硬化させることができる量であれば特に制限されないが、例えば100〜5000mJ/cmが好ましく、200〜4000mJ/cmがより好ましく、300〜3000mJ/cmがさらに好ましい。 The radiation source R is not particularly limited as long as it emits radiation such as ultraviolet rays. For example, a high-pressure mercury lamp or a metal halide lamp can be used. Further, the radiation dose of the radiation L is not particularly limited as long as it is an amount that can be cured burrs, for example, preferably 100~5000mJ / cm 2, more preferably 200~4000mJ / cm 2, 300~3000mJ / cm 2 is more preferable.

(ピックアップする工程)
放射線を照射して接着層40の切り込み部を硬化させた後は、図7に示すように、ダイシングテープ50と接着層40との界面で剥離し、接着層14付きの半導体チップ10が図示矢印に示す方向にピックアップされる。これにより、複数の半導体チップ10が取得される。なお、図7に示す半導体チップ10では、放射線硬化部14aや切断工程によるバリの発生等を強調するため、切断による段差を図示しているが、認識できない程度に略平坦となっていてもよい。
(Picking up process)
After curing the cut portion of the adhesive layer 40 by irradiating with radiation, the semiconductor chip 10 with the adhesive layer 14 is peeled off at the interface between the dicing tape 50 and the adhesive layer 40 as shown in FIG. Picked up in the direction shown in. Thereby, a plurality of semiconductor chips 10 are acquired. In the semiconductor chip 10 shown in FIG. 7, the step due to the cutting is illustrated in order to emphasize the generation of burrs due to the radiation curing portion 14 a and the cutting process, but may be substantially flat so that it cannot be recognized. .

(圧着体を得る工程)
複数の半導体チップ10が取得されると、次に、図8に示すように、半導体チップ10は支持基材2(配線付き基板)又は他の半導体チップ10上にマウントされる。そして、接着層14付きの半導体チップ10と支持基材2又は他の半導体チップ10とを、半導体チップ10の接着層14を介して、60〜150℃で加熱圧着して圧着体Cを得ることができる(図9参照)。加熱圧着には、例えば、ゴム製、金属製の圧着冶具を用いることができる。加熱温度が60℃以上であれば、被着体との良好な密着性を確保することができ、150℃以下であれば、圧着時の接着層14のブリードアウト過多を抑制できる。このような観点から、本工程における加熱温度は70〜140℃がより好ましく、80〜130℃がさらに好ましい。また、製造にかかる時間短縮と被着体との密着性両立の観点から、加熱圧着時間は0.5〜5.0秒が好ましく、0.5〜4.0秒がより好ましく、0.5〜3.0秒がさらに好ましい。
(Step of obtaining a crimped body)
When a plurality of semiconductor chips 10 are obtained, next, as shown in FIG. 8, the semiconductor chip 10 is mounted on the support base 2 (substrate with wiring) or another semiconductor chip 10. Then, the semiconductor chip 10 with the adhesive layer 14 and the support base 2 or another semiconductor chip 10 are heat-pressed at 60 to 150 ° C. via the adhesive layer 14 of the semiconductor chip 10 to obtain a crimped body C. (See FIG. 9). For thermocompression bonding, for example, a rubber or metal crimping jig can be used. If the heating temperature is 60 ° C. or higher, good adhesion to the adherend can be secured, and if it is 150 ° C. or lower, excessive bleeding out of the adhesive layer 14 during press bonding can be suppressed. From such a viewpoint, the heating temperature in this step is more preferably 70 to 140 ° C, and further preferably 80 to 130 ° C. Further, from the viewpoint of shortening the time required for production and adhesion to the adherend, the thermocompression bonding time is preferably 0.5 to 5.0 seconds, more preferably 0.5 to 4.0 seconds, More preferably, -3.0 seconds.

(接着層を硬化させる工程)
上記の工程により得られた圧着体Cを加熱し、半導体チップ10における接着層14を硬化してもよい。昇温及び保温には、例えば、一般的に市販されているクリーンオーブンのようなオーブンを用いることができる。昇温及び保温の温度及び時間は、接着層14を硬化できれば特に制限されず、例えば昇温は、80〜150℃で10分〜1時間が好ましく、90〜140℃で20〜50分がより好ましい。また、例えば保温は、80〜150℃で30分〜2時間が好ましく、90〜140℃で50〜90分がより好ましい。
(Step of curing the adhesive layer)
The pressure-bonded body C obtained by the above process may be heated to cure the adhesive layer 14 in the semiconductor chip 10. For example, an oven such as a clean oven that is generally commercially available can be used for raising the temperature and keeping the temperature. The temperature and time of temperature increase and heat retention are not particularly limited as long as the adhesive layer 14 can be cured. For example, the temperature increase is preferably 10 to 1 hour at 80 to 150 ° C, more preferably 20 to 50 minutes at 90 to 140 ° C. preferable. For example, the heat retention is preferably 80 to 150 ° C. for 30 minutes to 2 hours, more preferably 90 to 140 ° C. for 50 to 90 minutes.

接着層14の硬化後、接着層硬化体14b付きの半導体チップ10は、図9に示されるように、ボンディングワイヤ5を介して支持基材2上の電極4と接続される。そして、複数の半導体チップ10(図1では3枚の場合を示し、例えば16枚の半導体チップ10を積む場合もある)を含む積層体Aを封止樹脂によって封止し、図1に示す半導体装置1が得られる。このようにして得られる半導体装置1としては、例えば、携帯型音楽プレーヤー(MP3)やSDカードに用いられるフラッシュメモリ等が挙げられる。   After the adhesive layer 14 is cured, the semiconductor chip 10 with the adhesive layer cured body 14b is connected to the electrode 4 on the support substrate 2 through the bonding wires 5, as shown in FIG. Then, the stacked body A including a plurality of semiconductor chips 10 (in the case of three in FIG. 1, for example, 16 semiconductor chips 10 may be stacked) is sealed with a sealing resin, and the semiconductor shown in FIG. Device 1 is obtained. Examples of the semiconductor device 1 thus obtained include a portable music player (MP3) and a flash memory used for an SD card.

以上、説明したとおり、半導体装置1の製造方法では、放射線Lを照射することによって、接着層40の切り込み部付近及び堆積するバリが硬化するため、半導体チップ10をピックアップする際、バリが切れ易くなり、良好なピックアップ性を確保することができる。
また、放射線Lの照射により、積層体の切断部分は周辺部より硬化が進行した状態となるため、接着層14の端部のタック性が低下することから、半導体チップ10をピックアップする際に、隣接する接着層14同士が熱によって繋がってピックアップされる現象(ダブルダイピックアップ)も抑制される。
また、流動性の高い材料を使用した場合でも、放射線Lの照射により、接着層14の端部(端面)は硬化が進行した状態になるため、接着層14の端面が半導体チップ10の端面の内側に引けることを抑制できる。逆に、接着層14の過剰なはみ出しの抑制も可能となる。さらに、半導体チップの薄型化が進行すると、半導体チップが凸状に反りやすくなり、上述した引けが顕著になるが、本製造方法によれば係る問題は生じにくくなる。
また、接着層14の硬化した端部は封止樹脂侵入抑制部として機能する。つまり、封止樹脂を封入しても、空気が引けによる窪みに閉じ込められることがなく、また窪んだ部分に封止樹脂が侵入することによって、半導体チップ表面へダメージを及ぼすなどの問題も抑制できる。
As described above, in the method for manufacturing the semiconductor device 1, by irradiating the radiation L, the vicinity of the cut portion of the adhesive layer 40 and the accumulated burrs are cured. Thus, good pick-up properties can be ensured.
Moreover, since the cut portion of the laminate is in a state where the hardening has proceeded from the peripheral portion by irradiation with the radiation L, the tackiness of the end portion of the adhesive layer 14 is reduced, so when picking up the semiconductor chip 10, A phenomenon (double die pickup) in which adjacent adhesive layers 14 are connected by heat and picked up is also suppressed.
Even when a material with high fluidity is used, the end portion (end surface) of the adhesive layer 14 is in a cured state by irradiation with the radiation L, so that the end surface of the adhesive layer 14 is the end surface of the semiconductor chip 10. It can suppress pulling inward. Conversely, excessive protrusion of the adhesive layer 14 can be suppressed. Further, as the semiconductor chip becomes thinner, the semiconductor chip tends to warp in a convex shape and the above-mentioned shrinkage becomes remarkable, but according to the present manufacturing method, the problem is less likely to occur.
Moreover, the hardened edge part of the contact bonding layer 14 functions as a sealing resin penetration | invasion suppression part. In other words, even if the sealing resin is sealed, air is not trapped in the recess due to the drawing, and problems such as damage to the semiconductor chip surface can be suppressed by the sealing resin entering the recessed portion. .

以上、本発明に係る半導体装置の製造方法及び半導体装置の実施形態について説明したが、本発明は、上述した実施形態に限定されるものではなく、その要旨を逸脱しない範囲で様々な変形が可能である。   Although the semiconductor device manufacturing method and the semiconductor device embodiment according to the present invention have been described above, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. It is.

例えば、上述した実施形態では、接着層の構成成分としてエポキシ樹脂を例示したが、他の樹脂を用いてもよい。   For example, in the above-described embodiment, the epoxy resin is exemplified as the constituent component of the adhesive layer, but other resins may be used.

以下、本発明を実施例により詳細に説明するが、本発明は、これらに制限されるものではない。   EXAMPLES Hereinafter, although an Example demonstrates this invention in detail, this invention is not restrict | limited to these.

<フィルム状接着層の作製>
半導体装置用のフィルム状接着層(接着フィルム)を作製するための各材料を以下の通り準備した。
<Preparation of film adhesive layer>
Each material for producing a film adhesive layer (adhesive film) for a semiconductor device was prepared as follows.

(a)ベース樹脂(熱可塑性成分)
温度計、攪拌機、冷却管及び窒素流入管を装着した300mLフラスコ中に、4,4’−オキシジフタル酸二無水物(マナック社製、製品名:ODPA−M)7.6g(0.7mol)、デカメチレンビストリメリテート二無水物(黒金化成社製 6.5g(0.3mol))、1,3−ビス(3−アミノプロピル)−1,1,3,3−テトラメチルジシロキサン(東レダウコーニングシリコーン社製、製品名:BY16−871EG)5g(0.5mol)及びN−メチル−2−ピロリドン30gを仕込んだ反応液を攪拌した。その後、窒素ガスを吹き込みながら180℃で加熱することにより、水と共にN−メチル−2−ピロリドンを50%共沸除去し、ポリイミド樹脂(ベース樹脂)を得た。得られたポリイミド樹脂をGPC(ゲル浸透クロマトグラフィー)で測定したところ、ポリスチレン換算で重量平均分子量(Mw)が52,800であった。GPC測定における機器等は以下のとおりである。
使用機器:日立L−6000型(日立製作所(株)製)
検出器:L−40000UV(日立製作所(株)製)
カラム:日立化成工業製Gelpack GL−S300MDT−5(計2本)
試料濃度:5mg/ml
溶離液DMF/TFH=1/1+リン酸0.06M+臭化リチウム0.06M
また、得られたポリイミド樹脂のTgを粘弾性ピークから算出されるtanδにより測定したところ、72℃であった。粘弾性測定条件は以下のとおりである。
測定装置:ティー・エイ・インスツルメント社製粘弾性アナライザー「RSA−3」(商品名)
測定温度範囲:−50℃〜300℃
周波数:1HZ
昇温:5℃/min
(A) Base resin (thermoplastic component)
In a 300 mL flask equipped with a thermometer, a stirrer, a cooling pipe and a nitrogen inflow pipe, 7.6 g (0.7 mol) of 4,4′-oxydiphthalic dianhydride (manac, product name: ODPA-M), Decamethylene bistrimellitic dianhydride (6.5 g (0.3 mol) manufactured by Kurokin Kasei Co., Ltd.), 1,3-bis (3-aminopropyl) -1,1,3,3-tetramethyldisiloxane (Toray Industries, Inc.) A reaction solution charged with 5 g (0.5 mol) of Dow Corning Silicone, product name: BY16-871EG) and 30 g of N-methyl-2-pyrrolidone was stirred. Thereafter, heating was performed at 180 ° C. while blowing nitrogen gas to remove azeotropically 50% of N-methyl-2-pyrrolidone together with water to obtain a polyimide resin (base resin). When the obtained polyimide resin was measured by GPC (gel permeation chromatography), the weight average molecular weight (Mw) was 52,800 in terms of polystyrene. The equipment etc. in GPC measurement are as follows.
Equipment used: Hitachi L-6000 type (manufactured by Hitachi, Ltd.)
Detector: L-40000UV (manufactured by Hitachi, Ltd.)
Column: Gelpack GL-S300MDT-5 manufactured by Hitachi Chemical Co., Ltd. (two in total)
Sample concentration: 5 mg / ml
Eluent DMF / TFH = 1/1 + phosphoric acid 0.06M + lithium bromide 0.06M
Moreover, it was 72 degreeC when Tg of the obtained polyimide resin was measured by tan-delta computed from a viscoelastic peak. Viscoelasticity measurement conditions are as follows.
Measuring apparatus: TS Instruments viscoelasticity analyzer “RSA-3” (trade name)
Measurement temperature range: -50 ° C to 300 ° C
Frequency: 1HZ
Temperature rise: 5 ° C / min

(b)エポキシ樹脂
2−[4−(2,3エポキシプロポキシ)フェニル]−2−[4−[1,1−ビス[4−([2,3エポキシプロポキシ]フェニル)]エチル]フェニル]プロパン(製品名:VG3101L、(株)プリンテック製)
(B) Epoxy resin 2- [4- (2,3epoxypropoxy) phenyl] -2- [4- [1,1-bis [4-([2,3epoxypropoxy] phenyl)] ethyl] phenyl] propane (Product name: VG3101L, manufactured by Printec Co., Ltd.)

(c)硬化剤
4,4’−(1−(4−(1−(4−ヒドロキシフェニル)−1−メチルエチル)−フェニル)−エチリデン)−ビスフェノ−ル(製品名:TrisP−PA−MF、本州化学工業(株)製)
(C) Curing agent 4,4 ′-(1- (4- (1- (4-hydroxyphenyl) -1-methylethyl) -phenyl) -ethylidene) -bisphenol (product name: TrisP-PA-MF , Honshu Chemical Industry Co., Ltd.)

(d)硬化促進剤
2−フェニル−4−メチルイミダゾ−ル(製品名:2P4MZ、四国化成工業(株)製)
(D) Curing accelerator 2-phenyl-4-methylimidazole (Product name: 2P4MZ, manufactured by Shikoku Kasei Kogyo Co., Ltd.)

(e)フィラー
酸化ケイ素(平均粒径5μm)(製品名:H26、CIKナノテック製)
酸化ケイ素(平均粒径0.5μm)(製品名:H27、CIKナノテック製)
(E) Filler Silicon oxide (average particle size 5 μm) (Product name: H26, manufactured by CIK Nanotech)
Silicon oxide (average particle size 0.5 μm) (Product name: H27, manufactured by CIK Nanotech)

(f)その他成分
ナジイミド樹脂:下記一般式(1)で示す構造を有するキシリレン型ビスアリルナジイミド(製品名:BANI−X、丸善石油化学製)
(F) Other components Nadiimide resin: Xylylene-type bisallylnadiimide having a structure represented by the following general formula (1) (Product name: BANI-X, manufactured by Maruzen Petrochemical)

Figure 2014045033
Figure 2014045033

アクリレート:エトキシ化ビスフェノールFジアクリレート(製品名:R−712、日本化薬製)   Acrylate: Ethoxylated bisphenol F diacrylate (Product name: R-712, manufactured by Nippon Kayaku)

ビスマレイミド:2,2’−ビス[4−(4−マレイミドフェノキシ)フェニル]プロパン(製品名:BMI−80、ケイ・アイ化成製)   Bismaleimide: 2,2'-bis [4- (4-maleimidophenoxy) phenyl] propane (product name: BMI-80, manufactured by Kay Kasei)

開始剤:
(2,4,6−トリオキソ−1,3,5−トリアジン−1,3,5(2H,4H,6H)−トリイル)トリ−2,1−エタンジイルトリアクリラ−ト(製品名:A9300、新中村化学工業(株)製)
1,1−ビス(tert−ブチルペルオキシ)シクロヘキサン(製品名:トリゴノックス22−70E、化薬アクゾ(株)製)
Initiator:
(2,4,6-trioxo-1,3,5-triazine-1,3,5 (2H, 4H, 6H) -triyl) tri-2,1-ethanediyltriacrylate (product name: A9300, Shin-Nakamura Chemical Co., Ltd.)
1,1-bis (tert-butylperoxy) cyclohexane (product name: Trigonox 22-70E, manufactured by Kayaku Akzo Co., Ltd.)

次に、エポキシ樹脂13質量部、硬化促進剤2質量部、ナジイミド樹脂15質量部、アクリレート15質量部、硬化剤5質量部、ビスマレイミド20質量部及び開始剤1質量部をベース樹脂100質量部に加えた後、フィラー(上記H26、H27を2:1の割合で配合)を全質量に対して40質量%となるよう加え、フィルム塗工ワニスを調合した。   Next, 13 parts by mass of epoxy resin, 2 parts by mass of curing accelerator, 15 parts by mass of nadiimide resin, 15 parts by mass of acrylate, 5 parts by mass of curing agent, 20 parts by mass of bismaleimide and 1 part by mass of initiator are combined with 100 parts by mass of base resin. Then, a filler (containing H26 and H27 in a ratio of 2: 1) was added to 40% by mass with respect to the total mass to prepare a film coating varnish.

このフィルム塗工ワニスを、剥離処理済みのポリエチレンテレフタレート(PET)フィルム上に塗布し、120℃で8分間加熱した。これにより、ポリエチレンテレフタレートフィルム上に、厚さ25μmのフィルム状接着層(ダイボンディングフィルム)を得た。   This film coating varnish was applied on a polyethylene terephthalate (PET) film that had been subjected to a release treatment, and heated at 120 ° C. for 8 minutes. As a result, a film-like adhesive layer (die bonding film) having a thickness of 25 μm was obtained on the polyethylene terephthalate film.

<ダイシングテープの作製>
まず、主モノマーとして2−エチルヘキシルアクリレートとメチルメタクリレートを用い、官能基モノマーとしてヒドロキシエチルメタクリレートとアクリル酸を用いて、溶液重合法にてアクリル共重合体を得た。この合成したアクリル共重合体の重量平均分子量は40万であり、Tgは−38℃であった。このアクリル共重合体100重量部に対し、多官能イソシアネート架橋剤(三菱化学株式会社製)を15重量部配合した粘着剤溶液を調製し、シリコーン系離型剤を塗布したニ軸延伸ポリエステルフィルムセパレータ(厚さ38μm)の上に乾燥時の粘着剤厚さが10μmになるよう塗工乾燥した。更に、ポリオレフィンフィルム(厚さ100μm)を粘着剤面にラミネートした。この多層フィルムを室温で1週間放置し、十分にエージングを行った後、試験に使用した。
<Production of dicing tape>
First, an acrylic copolymer was obtained by a solution polymerization method using 2-ethylhexyl acrylate and methyl methacrylate as main monomers and hydroxyethyl methacrylate and acrylic acid as functional group monomers. The synthesized acrylic copolymer had a weight average molecular weight of 400,000 and Tg of −38 ° C. A biaxially stretched polyester film separator prepared by preparing a pressure-sensitive adhesive solution in which 15 parts by weight of a polyfunctional isocyanate crosslinking agent (manufactured by Mitsubishi Chemical Corporation) is blended with 100 parts by weight of this acrylic copolymer, and applying a silicone release agent The coating was dried so that the thickness of the pressure-sensitive adhesive when dried was 10 μm. Further, a polyolefin film (thickness: 100 μm) was laminated on the pressure-sensitive adhesive surface. The multilayer film was allowed to stand at room temperature for 1 week and sufficiently aged, and then used for the test.

<評価用ウェハの作製>
半導体ウェハ表面に、回路保護層としてワニス(日立化成デュポンマイクロシステムズ社製、製品名:HD−8820)を製膜した。まず、直径12インチの半導体ウェハ表面にワニスを10g滴下し、1000rpmで10秒、続いて2000rpmで30秒回転させ、ウェハ表面全体にワニスを塗布した。次に、120℃で3分プリベークを行い、光洋サーモシステムズ社製イナートガスオーブンINH−9CD−Sを用いて、窒素雰囲気下、320℃で60分加熱して硬化させ、厚さ7μmの回路保護層付き半導体ウェハを得た。次に、裏面仕上げをドライポリッシュとし、回路保護層を含めた半導体ウェハを50μmまで研削し(仕上げ厚み)、評価用ウェハとした。
<Production of evaluation wafer>
A varnish (manufactured by Hitachi Chemical DuPont Microsystems Co., Ltd., product name: HD-8820) was formed on the surface of the semiconductor wafer as a circuit protective layer. First, 10 g of varnish was dropped on the surface of a semiconductor wafer having a diameter of 12 inches and rotated at 1000 rpm for 10 seconds and then at 2000 rpm for 30 seconds to apply the varnish to the entire wafer surface. Next, pre-baking is performed at 120 ° C. for 3 minutes, and curing is performed by heating at 320 ° C. for 60 minutes in a nitrogen atmosphere using an inert gas oven INH-9CD-S manufactured by Koyo Thermo Systems Co., Ltd., and a circuit protective layer having a thickness of 7 μm A semiconductor wafer was obtained. Next, the back surface finish was dry-polished, and the semiconductor wafer including the circuit protective layer was ground to 50 μm (finished thickness) to obtain an evaluation wafer.

<接着フィルム付き半導体チップの作製>
上記のようにして得られた各半導体装置用接着フィルムと評価用ウェハとを、ホットロールラミネータ(株式会社JCM社製、製品名:DM−300−H)を用いて60℃で貼り合わせた。そして、接着フィルムのPETフィルムを剥離し、接着フィルムとダイシングテープの粘着層とを貼り合わせ、サンプル(半導体装置製造用接着シート付き半導体ウェハ)を得た。
<Production of semiconductor chip with adhesive film>
Each adhesive film for a semiconductor device and the wafer for evaluation obtained as described above were bonded at 60 ° C. using a hot roll laminator (manufactured by JCM Corporation, product name: DM-300-H). And the PET film of an adhesive film was peeled, the adhesive film and the adhesion layer of the dicing tape were bonded together, and the sample (semiconductor wafer with an adhesive sheet for semiconductor device manufacture) was obtained.

<ダイシング工程>
次に、株式会社ディスコ社製のフルオートダイサー「DFD−6361」を用いて、各サンプルを切断した。サンプルの切断では、直径250mmの開口を有する円環状のリングフレームを用いた。また、ブレード1枚で加工が完了するシングルカット方式を採用し、株式会社ディスコ社製のダイシングブレード「NBC−ZH104F−SE 27HDBB」をブレードとして用いた。切断条件は、ブレード回転数45,000rpm、切断速度50mm/sにて行った。切断時のブレードハイトは、接着フィルムを0〜25μm切り込む設定(110〜135μm)とした。半導体ウェハは10×10mmのサイズに切断し、接着フィルム付き半導体チップを得た。
<Dicing process>
Next, each sample was cut | disconnected using the full auto dicer "DFD-6361" by DISCO Corporation. In cutting the sample, an annular ring frame having an opening with a diameter of 250 mm was used. In addition, a single cut method in which processing is completed with one blade was employed, and a dicing blade “NBC-ZH104F-SE 27HDBB” manufactured by DISCO Corporation was used as the blade. The cutting conditions were a blade rotation speed of 45,000 rpm and a cutting speed of 50 mm / s. The blade height at the time of cutting was set to cut the adhesive film from 0 to 25 μm (110 to 135 μm). The semiconductor wafer was cut into a size of 10 × 10 mm to obtain a semiconductor chip with an adhesive film.

<バリの評価>
本ダイシング工程において、ダイシング後のダイシングテープから接着フィルム付のチップを剥離し、ダイシングテープ表面及び接着フィルム付チップの側面を、電子顕微鏡(フィリップス社製、製品名:XL30)を用いて観察し、バリが無いものを良好(A)、あるものを不良(B)とした。
<Evaluation of Bali>
In this dicing step, the chip with the adhesive film is peeled from the dicing tape after dicing, and the dicing tape surface and the side surface of the chip with the adhesive film are observed using an electron microscope (manufactured by Philips, product name: XL30). Those with no burr were judged as good (A) and those with no burr were judged as bad (B).

<ピックアップ性評価>
上記方法で作製した各接着フィルム付き半導体チップを、ルネサス東日本セミコンダクタ社製「フレキシブルダイボンダーDB−730」を使用し、ピックアップ性評価を行った。
<Pickup evaluation>
Each semiconductor chip with an adhesive film produced by the above method was evaluated for pickup properties using “Flexible Die Bonder DB-730” manufactured by Renesas East Japan Semiconductor.

具体的には、ピックアップ用コレットにはマイクロメカニクス社製「RUBBER TIP 13−087E−33(サイズ:10×10mm)」、突上げピンにマイクロメカニクス社製「EJECTOR NEEDLE SEN2−83−05(直径:0.7mm、先端形状:直径350μmの半円)」を用いた。突上げピンは、ピン中心間隔4.2mmで9本配置した。ピックアップ時のピンの突上げ速度は10mm/s、突上げ高さは400μmという条件でピックアップした。このようにして20チップを連続でピックアップし、チップ割れやピックアップミス、ダブルダイピックアップが発生しなかった場合を良好(A)、1チップでもチップ割れやピックアップミスが発生した場合を不良(B)とした。   Specifically, “RUBBER TIP 13-087E-33 (size: 10 × 10 mm)” manufactured by Micromechanics is used for the pickup collet, and “EJECTOR NEEDLE SEN2-83-05” manufactured by Micromechanics is used for the push-up pin (diameter: 0.7 mm, tip shape: semicircle with a diameter of 350 μm) ”. Nine push-up pins were arranged with a pin center interval of 4.2 mm. The pick-up speed was 10 mm / s and the pick-up height was 400 μm. In this way, 20 chips are picked up continuously, and chip breaks, pickup mistakes, and double die pick-ups are not good (A). Even if one chip is chip broken or pick-up mistakes are bad (B) It was.

<接着層ヒケ有無評価>
上記ピックアップ性評価にて得られた接着層付き半導体装置(半導体チップ)を、配線付き基板に積層した。具体的には、フレキシブルダイボンダー(日立ハイテク社製、製品名:DB−730)を用い、熱板表面温度80〜120℃、荷重10N(0.1MPa)、時間1秒にて積層(圧着)を行った(未硬化サンプル)。更に、積層した未硬化サンプルをクリーンオーブン(ESPEC社製、製品名:CLEAN OVEN PVHC−211)を用いて加熱処理し、接着層硬化サンプルを作製した。接着層を硬化させる条件は室温から120℃まで30分で昇温後、120℃で1時間保持する条件とした。各実施例及び比較例の硬化サンプル及び未硬化サンプルについて、環境対応型電子顕微鏡(フィリップス社製、製品名:XL−30)を用いてチップ側面部を観察し、接着層がチップ端部より内側まで引けているもの(未硬化サンプルについて圧着時の引け、硬化サンプルについては硬化時の引け)を不良(B)、チップ端部より適度にはみ出しているもの(未硬化サンプルについて圧着時のはみ出し、硬化サンプルについては硬化時のはみ出し)を良好(A)とした。
<Evaluation of adhesion layer sink marks>
The semiconductor device with an adhesive layer (semiconductor chip) obtained by the pickup property evaluation was laminated on a substrate with wiring. Specifically, using a flexible die bonder (manufactured by Hitachi High-Tech, product name: DB-730), laminating (crimping) at a hot plate surface temperature of 80 to 120 ° C., a load of 10 N (0.1 MPa), and a time of 1 second. Performed (uncured sample). Furthermore, the laminated uncured sample was heat-treated using a clean oven (manufactured by ESPEC, product name: CLEAN OVEN PVHC-211) to prepare a cured adhesive layer sample. The conditions for curing the adhesive layer were such that the temperature was raised from room temperature to 120 ° C. in 30 minutes and then held at 120 ° C. for 1 hour. About the cured sample and the uncured sample of each example and comparative example, the side surface of the chip was observed using an environmentally friendly electron microscope (manufactured by Philips, product name: XL-30), and the adhesive layer was inside the chip end. (B), those that protrude moderately from the end of the chip (extruding of uncured sample during crimping, Regarding the cured sample, the protrusion at the time of curing was defined as good (A).

実施例1〜5及び比較例1〜4の切断条件、紫外線照射条件は以下のとおりである。   The cutting conditions and ultraviolet irradiation conditions of Examples 1 to 5 and Comparative Examples 1 to 4 are as follows.

(実施例1)
半導体ウェハ、フィルム状接着層及びダイシングテープを上から順に積層し、回転刃にてフィルム状接着層の一部まで切断する条件(フィルム状接着層へ3μm切り込む)で切断後、半導体チップ側から紫外線を2,000mJ/cm照射した。その後、熱板表面温度100℃で基板に圧着した。
Example 1
A semiconductor wafer, a film-like adhesive layer and a dicing tape are laminated in order from the top, and after cutting under the condition of cutting to a part of the film-like adhesive layer with a rotary blade (3 μm cut into the film-like adhesive layer), ultraviolet rays are emitted from the semiconductor chip side. Was irradiated with 2,000 mJ / cm 2 . Thereafter, it was pressure-bonded to the substrate at a hot plate surface temperature of 100 ° C.

(実施例2)
半導体ウェハ、フィルム状接着層及びダイシングテープを上から順に積層し、回転刃にてフィルム状接着層の一部まで切断する条件(フィルム状接着層へ19μm切り込む)で切断後、半導体チップ側から紫外線を2,000mJ/cm照射した。その後、熱板表面温度100℃で、基板に圧着した。
(Example 2)
A semiconductor wafer, a film-like adhesive layer, and a dicing tape are laminated in order from the top, cut under conditions that cut to a part of the film-like adhesive layer with a rotary blade (cut into the film-like adhesive layer by 19 μm), and then ultraviolet rays from the semiconductor chip side Was irradiated with 2,000 mJ / cm 2 . Thereafter, it was pressure-bonded to the substrate at a hot plate surface temperature of 100 ° C.

(実施例3)
半導体ウェハ、フィルム状接着層及びダイシングテープを上から順に積層し、回転刃にてフィルム状接着層の一部まで切断する条件(フィルム状接着層へ15μm切り込む)で切断後、半導体チップ側から紫外線を2,000mJ/cm照射した。その後、熱板表面温度100℃で、基板に圧着した。
(Example 3)
A semiconductor wafer, a film-like adhesive layer, and a dicing tape are laminated in order from the top, cut under conditions that cut to a part of the film-like adhesive layer with a rotary blade (15 μm cut into the film-like adhesive layer), and then ultraviolet rays from the semiconductor chip side Was irradiated with 2,000 mJ / cm 2 . Thereafter, it was pressure-bonded to the substrate at a hot plate surface temperature of 100 ° C.

(実施例4)
半導体ウェハ、フィルム状接着層及びダイシングテープを上から順に積層し、回転刃にてフィルム状接着層の一部まで切断する条件(フィルム状接着層へ15μm切り込む)で切断後、半導体チップ側から紫外線を2,000mJ/cm照射した。その後、熱板表面温度120℃で、基板に圧着した。
Example 4
A semiconductor wafer, a film-like adhesive layer, and a dicing tape are laminated in order from the top, cut under conditions that cut to a part of the film-like adhesive layer with a rotary blade (15 μm cut into the film-like adhesive layer), and then ultraviolet rays from the semiconductor chip side Was irradiated with 2,000 mJ / cm 2 . Thereafter, it was pressure-bonded to the substrate at a hot plate surface temperature of 120 ° C.

(実施例5)
半導体ウェハ、フィルム状接着層及びダイシングテープを上から順に積層し、回転刃にてフィルム状接着層の一部まで切断する条件(フィルム状接着層へ15μm切り込む)で切断後、半導体チップ側から紫外線を2,000mJ/cm照射した。その後、熱板表面温度80℃で、基板に圧着した。
(Example 5)
A semiconductor wafer, a film-like adhesive layer, and a dicing tape are laminated in order from the top, cut under conditions that cut to a part of the film-like adhesive layer with a rotary blade (15 μm cut into the film-like adhesive layer), and then ultraviolet rays from the semiconductor chip side Was irradiated with 2,000 mJ / cm 2 . Thereafter, it was pressure-bonded to the substrate at a hot plate surface temperature of 80 ° C.

(比較例1)
紫外線を照射しないこと以外は実施例1と同様とした。
(Comparative Example 1)
The procedure was the same as in Example 1 except that ultraviolet rays were not irradiated.

(比較例2)
紫外線を照射しないこと以外は実施例2と同様とした。
(Comparative Example 2)
The procedure was the same as in Example 2 except that ultraviolet rays were not irradiated.

(比較例3)
紫外線を照射しないこと以外は実施例3と同様とした。
(Comparative Example 3)
The same procedure as in Example 3 was performed except that ultraviolet rays were not irradiated.

(比較例4)
紫外線を照射しないこと以外は実施例4と同様とした。
(Comparative Example 4)
The same procedure as in Example 4 was performed except that ultraviolet rays were not irradiated.

Figure 2014045033
Figure 2014045033

実施例1〜5はいずれもダイシング性、ピックアップ性が良好であり、引けの発生は抑制されていた。一方、比較例1〜4は何れもピックアップ性が悪く、チップ端部での引けが発生した。   In each of Examples 1 to 5, the dicing property and the pickup property were good, and the occurrence of shrinkage was suppressed. On the other hand, all of Comparative Examples 1 to 4 have poor pick-up properties, and shrinkage at the end of the chip occurred.

1…半導体装置、2…支持基材、10…半導体チップ、14,40…接着層、14a…放射線硬化部(封止樹脂侵入抑制部)、14b…接着層硬化体、30…半導体ウェハ、50…ダイシングテープ、A…積層体、B…回転刃、L…放射線。
DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Support base material, 10 ... Semiconductor chip, 14, 40 ... Adhesion layer, 14a ... Radiation hardening part (encapsulation resin penetration suppression part), 14b ... Adhesion layer hardening body, 30 ... Semiconductor wafer, 50 ... Dicing tape, A ... Laminated body, B ... Rotating blade, L ... Radiation.

Claims (11)

放射線硬化成分を含む接着層を半導体ウェハの一方の面に積層した積層体を準備する工程と、
前記積層体の前記半導体ウェハを切断手段によって複数の個片に切断し、且つ、前記接着層に切り込みを入れる工程と、
前記半導体ウェハの他方の面側から前記積層体に放射線を照射する工程と、
複数に切断され且つ放射線を照射された前記半導体ウェハの個片及び当該個片に積層した前記接着層の一部を有する半導体チップを、前記積層体から取得する工程と、
当該半導体チップを含む半導体装置を製造する工程と、
を備えた半導体装置の製造方法。
Preparing a laminate in which an adhesive layer containing a radiation curing component is laminated on one surface of a semiconductor wafer;
Cutting the semiconductor wafer of the laminate into a plurality of pieces by a cutting means, and cutting the adhesive layer;
Irradiating the laminated body with radiation from the other surface side of the semiconductor wafer;
Obtaining a semiconductor chip having a piece of the semiconductor wafer cut into a plurality of pieces and irradiated with radiation and a part of the adhesive layer laminated on the piece, from the laminate;
Manufacturing a semiconductor device including the semiconductor chip;
A method for manufacturing a semiconductor device comprising:
前記積層体を準備する工程において、前記接着層の一方の面にダイシングテープを積層する、請求項1に記載の製造方法。   The manufacturing method according to claim 1, wherein in the step of preparing the laminated body, a dicing tape is laminated on one surface of the adhesive layer. 前記接着層の切り込みは、前記接着層の厚みの1〜99%である、請求項1又は2に記載の製造方法。   The manufacturing method according to claim 1 or 2, wherein the cut of the adhesive layer is 1 to 99% of the thickness of the adhesive layer. 前記接着層の厚みは1〜150μmである、請求項1〜3の何れか一項記載の製造方法。   The manufacturing method according to claim 1, wherein the adhesive layer has a thickness of 1 to 150 μm. 前記接着層がフィルム状である、請求項1〜4の何れか一項記載の製造方法。   The manufacturing method as described in any one of Claims 1-4 whose said contact bonding layer is a film form. 前記半導体ウェハの仕上げ厚みは15〜200μmである、請求項1〜5の何れか一項記載の製造方法。   The manufacturing method as described in any one of Claims 1-5 whose finishing thickness of the said semiconductor wafer is 15-200 micrometers. 前記切断手段が回転刃である、請求項1〜6の何れか一項記載の製造方法。   The manufacturing method according to claim 1, wherein the cutting means is a rotary blade. 前記半導体装置を製造する工程において、前記半導体チップを支持基材に加熱圧着すると共に、封止樹脂によって前記半導体チップを封止する、請求項1〜7の何れか一項に記載の製造方法。   The manufacturing method according to any one of claims 1 to 7, wherein, in the step of manufacturing the semiconductor device, the semiconductor chip is thermocompression-bonded to a supporting base material, and the semiconductor chip is sealed with a sealing resin. 請求項1〜8の何れか一項に記載の製造方法に用いられる接着層であって、放射線硬化成分を含む接着層。   It is an contact bonding layer used for the manufacturing method as described in any one of Claims 1-8, Comprising: The contact bonding layer containing a radiation hardening component. 請求項1〜8の何れか一項に記載の製造方法により製造される半導体装置。   A semiconductor device manufactured by the manufacturing method according to claim 1. 請求項1〜8の何れか一項に記載の製造方法により製造される半導体装置であって、接着層硬化体を含む半導体チップと、前記接着層硬化体を介して前記半導体チップを支持する支持基材と、前記半導体チップの少なくとも一部を覆う封止樹脂硬化体を備え、
前記接着層硬化体の端部に封止樹脂侵入抑制部が形成されている、半導体装置。
It is a semiconductor device manufactured by the manufacturing method as described in any one of Claims 1-8, Comprising: The semiconductor chip containing a contact bonding layer hardening body, and the support which supports the said semiconductor chip via the said contact bonding layer hardening body Comprising a base material and a cured sealing resin covering at least a part of the semiconductor chip;
A semiconductor device, wherein a sealing resin intrusion suppressing portion is formed at an end of the adhesive layer cured body.
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