JP2014027211A - Method for manufacturing wiring board and composition for seed layer formation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a wiring board which can obtain high productivity and a finer wiring pattern.SOLUTION: A method for manufacturing a wiring board 1000 comprises steps of: printing or applying a composition for seed layer formation including a metal salt and a reducing agent, on a substrate 100 which has an insulator layer 3 provided with a bottom layer wiring pattern 2 and an opening 4, and heating the composition for seed layer formation printed or applied on the substrate 100 to form a seed layer 5; forming a wiring layer 7 on a predetermined region on the seed layer 5, which is a region smaller than a region where the seed layer 5 is arranged; and removing the seed layer 5 exposed not being covered by the wiring layer 7. In the step of forming the wiring layer 7, a resist pattern 6 is formed in a region on the seed layer 5 excluding the predetermined region, the wiring layer 7 is formed on the seed layer 5 which is exposed not being covered by the resist pattern 6, and then the resist pattern 6 is removed, to form the patterned wiring layer 7 on the seed layer 5.

Description

  The present invention relates to a method for producing a wiring board and a composition for forming a seed layer.

The wiring board is also called a printed wiring board or the like, and is a main component of electronic equipment for fixing and wiring electronic components.
In recent years, the wiring formed on the wiring board tends to be further miniaturized and complicated with the downsizing and high functionality of electronic devices. Therefore, in the field of wiring boards, highly accurate wiring forming technology is required.

As a wiring formation technique for forming a wiring pattern, an electrode pattern, or the like, which is a metal film patterned on a substrate, for example, a method using a photolithography technique or a technique of laminating a metal foil on a glass epoxy resin substrate or a polyimide film It has been known.
In the subtractive method, which is one of the methods using photolithography technology, a uniform solid metal film is first formed on a substrate. As a method for forming the metal film, it is possible to use a vapor deposition method or a sputtering method in addition to the plating method. Then, a resist solution is applied to the entire surface of the formed metal film to form a resist layer. Next, this resist layer is irradiated with ultraviolet rays using a photomask, and then developed to form a resist pattern. Next, the metal film exposed without being covered with the resist pattern is removed by etching, and the remaining resist portion is peeled off. In this way, a wiring layer is formed on the substrate as a metal film that has been subjected to desired patterning to obtain a wiring substrate.

  Further, as another method using a photolithography technique, a semi-additive method is known (see, for example, Patent Document 1). In the semi-additive method, first, a thin conductive layer (hereinafter referred to as a seed layer) is formed on the entire surface of the substrate. As a method for forming the seed layer, sputtering, electroless plating, or the like is generally used. Then, a resist solution is applied over the entire area of the formed metal film to form a resist layer. Next, this resist layer is irradiated with ultraviolet rays using a photomask, and then developed to form a resist pattern. The obtained resist pattern is made to be a complementary pattern to a wiring layer pattern to be formed later. Next, a metal pattern is formed by electrolytic plating on the seed layer exposed without being covered with the resist pattern. Thereafter, the resist pattern is removed, and then the seed layer in the region that is the base of the resist pattern and is exposed by removing the resist pattern is removed. In this way, a wiring layer is formed on the substrate as a metal film having a desired patterning, and a wiring substrate is obtained.

  The semi-additive method has a feature that a pattern shape having a rectangular cross section can be obtained with a desired metal thickness and is suitable for miniaturization of a wiring layer as compared with the subtract method.

JP 2012-104647 A

  As described above, a semi-additive method that is easy to form a fine pattern and is suitable for forming a highly accurate wiring layer on a substrate is a wiring substrate wiring that is effective for miniaturization and high functionality of electronic devices. It is a forming technology.

  Conventionally, the semi-additive method requires formation of a seed layer, which is formed by sputtering or electroless plating. However, the sputtering method needs to be performed in a vacuum, which leads to an increase in size of the apparatus and a large restriction on the operation of the apparatus. Furthermore, the process takes a long time and the production efficiency is low. In addition, in electroless plating, for example, in the case of electroless copper plating, generally, conditioning, soft etching, catalyzing, accelerating, electroless plating and many steps are required, and there is a problem that manufacturing efficiency is low.

  Therefore, in the field of electronic equipment that requires improvement in productivity as well as downsizing and high functionality, improvement in productivity in a wiring board is strongly demanded.

  The present invention has been made based on the above findings. That is, an object of the present invention is to provide a method of manufacturing a wiring board having wiring that can obtain high productivity and can be miniaturized. Moreover, it is providing the composition for seed layer formation which can be used suitably for the manufacturing method of the wiring board.

  Other objects and advantages of the present invention will become apparent from the following description.

The first aspect of the present invention includes a step of forming a seed layer by heating a film formed by printing or applying a composition containing a metal salt and a reducing agent on a substrate;
Forming a wiring layer in a predetermined region on the seed layer;
And a step of removing the exposed seed layer without being covered with the wiring layer.

In the first aspect of the present invention, the step of forming the wiring layer includes a step of forming a resist pattern in a region other than the predetermined region on the seed layer;
Forming a wiring layer on the seed layer exposed without being covered with the resist pattern;
And a step of removing the resist pattern.

In the first aspect of the present invention, the step of forming the seed layer includes the step of forming an insulating layer having an opening on the substrate;
Forming a seed layer on the insulating layer and on the inner surface of the opening;
The predetermined region on the seed layer preferably includes the opening.

  In the first aspect of the present invention, the metal salt is preferably a copper salt.

  In the first aspect of the present invention, the copper salt is preferably at least one selected from copper formate and copper formate tetrahydrate.

  In the first aspect of the present invention, the composition preferably further contains a solvent.

  In the first aspect of the present invention, the step of forming the seed layer preferably heats the composition at 120 ° C. to 260 ° C. in a non-oxidizing atmosphere.

  In the first aspect of the present invention, it is preferable to form the seed layer after roughening the surface of the substrate.

  In the first aspect of the present invention, it is preferable to include a step of forming a barrier metal film between the substrate and the seed layer.

  In the first aspect of the present invention, the predetermined region on the seed layer is preferably a region smaller than a region where the seed layer is provided.

  In the first aspect of the present invention, the step of forming the wiring layer is preferably performed by electrolytic plating using an electrolytic solution containing copper.

  A second aspect of the present invention relates to a composition for forming a seed layer, which is used in the method for manufacturing a wiring board according to the first aspect of the present invention.

  According to the first aspect of the present invention, there is provided a method of manufacturing a wiring board having wiring that can obtain high productivity and can be miniaturized.

  According to the second aspect of the present invention, there is provided a seed layer forming composition that is suitably used in a method for manufacturing a wiring board having wiring that can achieve high productivity and can be miniaturized.

(A)-(d) is typical sectional drawing which shows each manufacturing process of the manufacturing method of the wiring board of embodiment of this invention. (A)-(c) is typical sectional drawing which shows each manufacturing process of the manufacturing method of the board | substrate used for manufacture of the wiring board of embodiment of this invention. (A) And (b) is typical sectional drawing which shows each process for formation of a wiring layer in the manufacturing method of the wiring board of embodiment of this invention. It is typical sectional drawing of the wiring board which is an Example of this invention.

  According to the present invention, in manufacturing a wiring board, first, a seed layer for electrolytic plating is formed on the board. The formation of the seed layer in the present invention is performed by a method of heating a film obtained by printing or applying a composition containing a metal salt and a reducing agent without using a vacuum process such as sputtering.

  Then, a wiring layer is formed in a predetermined region on the seed layer. At this time, the wiring layer on the seed layer is patterned in a desired shape, and is preferably formed in a region smaller than a region where the seed layer is provided on the substrate.

  Note that the photolithography method can be used for patterning the wiring layer. That is, a resist layer is formed on the seed layer, and patterning using a photolithography method is performed to form a resist pattern. Next, a wiring layer is formed as a metal pattern on the seed layer exposed without being covered with the resist pattern by electrolytic plating. Here, the resist pattern is formed in advance so as to be complementary to the pattern of the wiring layer, and as a result, the wiring layer can have a desired pattern shape.

  Thereafter, the resist pattern is removed, and then the seed layer in the lower layer of the resist pattern and exposed by the removal of the resist pattern is removed. By doing in this way, a wiring layer can be formed on a board | substrate as a metal film by which the desired patterning was made, and a wiring board can be obtained.

As described above, the method for manufacturing a wiring board according to the present invention includes the same steps as the wiring forming method known as the additive method. However, in the method for manufacturing a wiring board according to the present invention, the step of forming the seed layer is not performed by a vacuum process such as sputtering. It is possible to improve the productivity of the wiring board by heating the formed film.
Below, the manufacturing method of the wiring board of this invention is demonstrated using drawing.

  Drawing 1 (a)-(d) is a typical sectional view showing each manufacturing process of a manufacturing method of a wiring board of an embodiment of the present invention.

  In the present embodiment, the multilayer wiring board of the present embodiment can be manufactured as an example using the wiring board manufacturing method of the present invention.

The manufacturing method of the wiring board of the embodiment of the present invention includes the following steps (A) to (C).
(A) a step of heating a film formed by applying a liquid composition containing a metal salt and a reducing agent on a substrate to form a seed layer;
(B) forming a wiring layer in a predetermined region on the seed layer;
(C) A step of removing the exposed seed layer without being covered with the wiring layer.

  Step (A) corresponds to, for example, FIGS. 1 (a) and 1 (b). Step (B) corresponds to, for example, FIG. 1C, and step (C) corresponds to, for example, FIG. 1D.

  When manufacturing a multilayer wiring board, as shown in FIG. 1A, the substrate used in the above-described step (A) is formed with a lower layer wiring pattern 2 on a substrate 1 constituting the substrate, and the lower layer wiring pattern. 2 can be formed into a substrate 100 in which an insulating layer 3 made of resin is coated and an opening 4 reaching the lower wiring pattern 2 is formed on a part of the insulating layer 3.

The manufacturing method of the wiring board of this embodiment corresponds to FIGS. 2A to 2C described later in order to manufacture the substrate 100 used in the above-described step (A) when manufacturing a multilayer wiring board. The following steps (a-1) to (a-3) can be included.
(A-1) a step of forming a lower layer wiring pattern on a substrate constituting the substrate used in the method for manufacturing the wiring substrate of the present embodiment;
(A-2) a step of forming an insulating layer covering the lower wiring pattern;
(A-3) A step of forming an opening reaching the lower wiring pattern in the insulating layer.

Moreover, the manufacturing method of the wiring board of this embodiment can provide the process of roughening a board | substrate surface, before forming a seed layer at a process (A).
When a multilayer wiring board is manufactured by the method for manufacturing a wiring board according to the present embodiment, the surface of the insulating layer, which is the surface of the substrate, is a step (a-4-i) after the above step (a-3). A step of roughening can be provided.

And after the above-mentioned process (a-3), the process of forming a barrier metal film so that it may be arranged between a substrate and a seed layer can be provided as process (a-4-ii).
The barrier metal film is a general term for metal films used for preventing diffusion of metal materials and preventing mutual reaction. A material that does not react well with the mutual base material such as an insulating layer and a seed layer of the substrate is used. For example, when a wiring layer made of copper (Cu) is provided on a seed layer, it is known that copper has a property of easily diffusing into an insulating layer or the like. In that case, the barrier metal film functions to prevent (barrier) copper atoms from diffusing from the wiring layer into the insulating layer. The barrier metal film for preventing copper diffusion is formed of titanium nitride (TiN), tantalum (Ta), tantalum (Ta) / tantalum nitride (TaN), titanium (Ti), or the like.

  In the step (A), the lower layer wiring is obtained by the above steps (a-1) to (a-3), and the steps (a-4-i) and (a-4-ii) provided when necessary. A substrate 100 having the pattern 2 and the insulating layer 3 having the opening 4 reaching the lower wiring pattern 2 can be obtained.

  In the step (A), when a multilayer wiring board is manufactured, as shown in FIG. 1A, the insulating layer 3 having the opening 4 is formed on the substrate 1 by the above-described step (a-3). Then, as shown in FIG. 1B, a step of forming a seed layer 5 on the insulating layer 3 and on the inner surface of the opening 4 can be provided. As a result, as shown in FIG. 1C, in the step of forming the wiring layer 7 on the seed layer 5 in the step (B) described above, the opening 4 of the insulating layer 3 is formed in the formation region of the wiring layer 7. Can be included.

Next, the above-mentioned process (B) can be comprised including the following processes (b-1)-processes (b-3) corresponding to Drawing 3 (a) and (b) mentioned below.
(B-1) forming a resist pattern in a region other than a predetermined region for forming a wiring layer on the seed layer;
(B-2) forming a wiring layer on the seed layer exposed without being covered with the resist pattern;
(B-3) A step of removing the resist pattern.

  Below, the manufacturing method of the wiring board of this embodiment including the above-described steps (A) to (C) will be described in more detail with reference to the drawings.

[Process (A)]
When manufacturing a multilayer wiring board, in order to prepare the board | substrate 100 to be used at a process (A), it can have the process (a-1)-process (a-3) mentioned above.

  2A to 2C are schematic cross-sectional views showing respective manufacturing steps of the substrate manufacturing method used for manufacturing the wiring substrate of the present embodiment.

  2A to 2C illustrate the above-described steps (a-1) to (a-3) included in the step (A), respectively. In FIG. 2C, the process will be described using the same drawing as FIG.

[Step (a-1)]
Step (a-1) is a step of forming the lower layer wiring pattern 2 on the base 1 constituting the substrate, as shown in FIG.
The lower wiring pattern 2 can be formed from a conductive metal such as copper (Cu). When the lower layer wiring pattern 2 is made of copper, a copper-clad laminate in which copper foil is laminated on both surfaces of the substrate 1 made of resin is used, and the surface copper foil is patterned according to a known method such as etching. . Then, a lower wiring pattern 2 having a desired pattern is formed on the substrate 1.

  The substrate 1 can be a substrate used for an organic printed wiring board. For example, a substrate made of an epoxy resin, a bismaleimide triazine resin, a polyimide resin, a polyamide resin, a polyester resin, a phenol resin, an acrylic resin, a substrate in which these resins are reinforced with glass fiber, or the like can be used.

[Step (a-2)]
Step (a-2) is a step of forming an insulating layer 3 that covers the lower wiring pattern 2 as shown in FIG.

As a material for forming the insulating layer 3, a material having a low dielectric constant are preferable, for example, other inorganic oxides such as SiO _2, a resin material. Examples of the resin material include an epoxy resin, a bismaleimide triazine resin, a polyimide resin, a polyamide resin, a polyester resin, a phenol resin, and an acrylic resin. If necessary, inorganic particles such as silica, alumina, talc, A material reinforced with glass fiber can be used. In addition, by providing photosensitivity to these resin materials, an opening (also referred to as a via hole) 4 described later with reference to FIG. 2C can be used as a material that can be formed using a photolithography method.

  As a method for forming the insulating layer 3 using a resin, it is possible to form the resin composition for forming the insulating layer 3 by a method such as coating and curing it. Further, for example, the insulating layer 3 can be formed on the substrate 1 by using a pre-formed thermosetting resin sheet and laminating with a vacuum press.

[Step (a-3)]
Step (a-3) is a step of forming an opening 4 reaching the lower wiring pattern 2 in the insulating layer 3 as shown in FIG.

As a specific method for forming the opening 4, the insulating layer 3 formed on the lower wiring pattern 2 is formed on the lower wiring pattern 2 by using, for example, a high-pressure mercury lamp, excimer laser, CO ₂ laser, YAG laser or the like. A reaching opening 4 is formed.

  Further, when the insulating layer 3 formed in the step (a-2) is made of the above-described photosensitive resin, the opening 4 may be formed by a known photolithography process.

  The shape and size of the opening 4 are not particularly limited, but the opening width of the opening 4 is 1 μm to 500 μm, preferably 5 μm to 300 μm, more preferably 5 μm to 200 μm, and particularly preferably 5 μm to 50 μm. The aspect ratio of the opening 4 (a value obtained by gradually reducing the depth of the opening 4 by the opening width of the opening 4) is preferably 0.1 or more, more preferably 0.1 to 50, particularly preferably 1 to 1. 25. When the opening width and aspect ratio of the opening 4 are in the above-described ranges, a seed layer described later can be efficiently formed.

  In the step (a-3), a resin piece (resin smear) generated as a residue by a laser drilling process or a photolithography process remains on the lower wiring pattern 2 in the opening 4. is there. The resin smear is preferably removed by a desmear process described below.

  In the desmear treatment, hot water treatment is performed for about 5 minutes using the substrate 1 having the insulating layer 3 in which the openings 4 are formed. Thereafter, the resin smear on the lower wiring pattern 2 is swollen in advance in a swelling tank using a solvent or a commercially available chemical solution. Next, for example, after washing twice with water, an N-methylpyrrolidone solution or an alkaline permanganate solution (a solution containing sodium permanganate or potassium permanganate) is used as the desmear solution, and the desmear solution Dissolve and remove. Then, the surface of the lower layer wiring pattern 2 is cleaned by immersing it in a chemical solution in a neutralization tank, neutralizing it, and washing it with water.

  Here, MLB-6001A, MLB-6001S, and MLB-6001W manufactured by Meltex can be used as commercially available chemicals for swelling the above-described resin smear. Moreover, as a commercially available desmear liquid, MLB-497A and MLB-497B by Meltex can be used. Moreover, as a commercially available chemical for neutralization, MLB-790M manufactured by Meltex and 98% sulfuric acid manufactured by Maejima Shoten may be used.

  Moreover, in order to manufacture the board | substrate used in the above-mentioned process (A), the surface of the insulating layer 3 which is the surface of a board | substrate is roughened as a process (a-4-i) after the above-mentioned process (a-3). Can be provided (also simply referred to as a surface roughening step).

In the surface roughening step, the surface of the insulating layer 3 is roughened in order to improve adhesion with a layer formed on the seed layer, such as a seed layer formed on the insulating layer 3. The roughening of the surface is performed by a wet process or a dry etching process similar to the desmear process. In addition, when a desmear process process is provided, it is preferable to implement a surface roughening process following the process of a desmear process.
Examples of the wet treatment in the surface roughening step include a method of forming irregularities on the surface of the insulating layer 3 by using an acid, an alkali, an organic solvent that is soluble in the material forming the insulating layer 3, or the like.

Moreover, as a dry etching process, the method of generating an unevenness | corrugation in the surface of the insulating layer 3 by generating plasma gas in a decompression atmosphere is mentioned.
By providing the surface roughening step as described above, the surface of the insulating layer 3 is roughened, and furthermore, the inner wall surface of the opening 4 formed in the insulating layer 3 is similarly roughened. Become. In the present embodiment, even if the method is different from the method exemplified above, the same effects can be obtained as long as the treatment method can roughen the surface.

  By providing the surface roughening step, the adhesion between the insulating layer 3 and a layer formed thereon, such as a seed layer, is increased, and the reliability of the manufactured wiring board is improved. Furthermore, the state of the inner wall surface of the opening 4 formed in the insulating layer 3 can be set to a state suitable for formation of a seed layer, for example.

  The step (A) includes the steps (a-1) to (a-3) described above, and if necessary, includes a surface roughening step and the like, so that FIG. 1 (a) (FIG. 2 (c) The board | substrate 100 used for manufacture of a wiring board shown to)) can be prepared.

  In the step (A), as shown in FIG. 1A, the substrate 100 is prepared by the steps (a-1) to (a-3), and as shown in FIG. A film formed by printing or applying a composition containing a reducing agent on the substrate 100 is heated to form the seed layer 5. The step (A) includes a step of forming the insulating layer 3 having the opening 4 on the substrate 100 and a step of forming the seed layer 5 on the insulating layer 3 and on the inner surface of the opening 4. 5 is formed on the insulating layer 3 on the substrate 100 and on the inner surface of the opening 4.

  That is, in the method for manufacturing a wiring board according to the present embodiment, the composition for forming the seed layer according to the present embodiment is applied onto the substrate 100 described above, and the obtained film is heated in a non-oxidizing atmosphere to form the substrate. A conductive seed layer 5 can be easily formed on 100. That is, by heating, the metal salt is reduced, and at the same time, organic substances are removed by decomposition and volatilization, and the seed layer 5 can be formed as a metal film. When the substrate 100 is a multilayer wiring substrate, the seed layer 5 can be formed on the insulating layer 3 and on the inner surface of the opening 4 as shown in FIG.

<Composition for seed layer formation>
Next, the seed layer forming composition of the present embodiment (hereinafter simply referred to as a composition) will be described in more detail.

[Composition]
The composition of this embodiment is a composition containing a metal salt and a reducing agent. Moreover, the composition of this embodiment can contain a solvent further.

  The state of the composition of the present embodiment is not particularly limited as long as it can be printed or coated on a substrate, but is preferably liquid or pasty at room temperature. The normal temperature refers to a temperature of 10 ° C. to 30 ° C., the liquid state refers to a state in which a certain volume of the composition cannot maintain a specific shape, and the paste state refers to a certain amount. The volume composition indicates a state where the shape can be freely changed and the shape can be maintained.

[Metal salt]
The metal salt contained in the metal salt can be reduced by the reducing agent in the composition to form a metal simple substance, and can play a role in expressing the conductivity of the formed seed layer. For example, when the metal salt is a copper salt, copper ions contained in the copper salt are reduced by a reducing agent to form copper alone, thereby forming a seed layer of the conductive film.

As a metal salt of the composition of this embodiment, a copper salt and a silver salt are preferable.
The copper salt is not particularly limited as long as it is a compound containing copper ions, and examples thereof include copper salts composed of copper ions and inorganic anion species and / or organic anion species. Among these, from the viewpoint of solubility, it is preferable to use one or more selected from the group consisting of a copper carboxylate, a copper hydroxide, and a complex salt of copper and an acetylacetone derivative.

  For example, specific examples of copper carboxylates include copper acetate, copper trifluoroacetate, copper propionate, copper butyrate, copper isobutyrate, copper 2-methylbutyrate, copper 2-ethylbutyrate, copper valerate, Copper salt with carboxylic acid such as copper valerate, copper pivalate, copper hexanoate, copper heptanoate, copper octoate, copper 2-ethylhexanoate, copper nonanoate, copper malonate, copper succinate, malee Copper salt with dicarboxylic acid such as acid copper, Copper salt with aromatic carboxylic acid such as copper benzoate and copper salicylate, Copper formate, Copper hydroxyacetate, Copper glyoxylate, Copper lactate, Copper oxalate, Copper tartrate, Apple Suitable examples include copper salts with organic acids having a carboxy group such as acid copper and copper citrate. Note that copper formate may be anhydrous or hydrated. Examples of the hydrate of copper formate include tetrahydrate.

  Examples of complex salts of copper and acetylacetone derivatives include acetylacetonato copper, 1,1,1-trimethylacetylacetonatocopper, 1,1,1,5,5,5-hexamethylacetylacetonatocopper, Suitable examples include 1,1,1-trifluoroacetylacetonato copper, 1,1,1,5,5,5-hexafluoroacetylacetonato copper and the like.

  Among these, considering the solubility and dispersibility in the reducing agent or solvent and the resistance characteristics of the seed layer to be formed, copper acetate, copper propionate, copper isobutyrate, copper valerate, copper isovalerate, copper formate Copper carboxylates such as copper glyoxylate are preferred.

The silver salt is not particularly limited as long as it is a silver salt.
For example, silver nitrate, silver acetate, silver oxide, silver acetylacetone, silver benzoate, silver bromate, silver bromide, silver carbonate, silver chloride, silver citrate, silver fluoride, silver iodate, silver iodide, silver lactate, Mention may be made of silver nitrite, silver perchlorate, silver phosphate, silver sulfate, silver sulfide and silver trifluoroacetate.

  In the composition of the present embodiment, it is preferable to use a copper salt from the viewpoint of suppressing migration of metal atoms into the insulating layer in the formed seed layer. Among the copper salts, copper formate having a reducing property is particularly preferable. Copper formate may be anhydrous or copper formate tetrahydrate.

  As content of metal salt, the range of 0.01 mass%-50 mass% is preferable with respect to the whole quantity of the composition of this embodiment, and the range of 0.1 mass%-30 mass% is more preferable. By setting the content of the metal salt in the range of 0.01% by mass to 50% by mass, a metal film having stable and excellent conductivity can be formed. From the viewpoint of obtaining a metal film having a low resistance value, the metal salt content is preferably 0.01% by mass or more. Moreover, it is preferable that content of a metal salt is 50 mass% or less from a viewpoint of obtaining the stable copper film formation composition.

[Reducing agent]
The composition of this embodiment contains a reducing agent together with the metal component described above for the purpose of reducing metal ions contained in the metal salt to form a simple metal. The reducing agent is not particularly limited as long as it has reducibility to the metal ions contained in the metal component of the composition. Moreover, reducing property refers to the property which can reduce | restore the metal ion contained in the metal salt of a composition.

  Examples of the reducing agent include monomolecular compounds having one or more functional groups selected from the group consisting of thiol groups, nitrile groups, amino groups, hydroxy groups, and hydroxycarbonyl groups, nitrogen atoms, oxygen Examples thereof include polymers having in the molecular structure one or more heteroatoms selected from the group consisting of atoms or sulfur atoms.

  Examples of such monomolecular compounds include alkanethiols, amines, hydrazines, monoalcohols, diols, hydroxyamines, α-hydroxyketones, and carboxylic acids.

Examples of the polymer include polyvinylpyrrolidone, polyethyleneimine, polyaniline, polypyrrole, polythiophene, polyacrylamide, polyacrylic acid, carboxymethylcellulose, polyvinyl alcohol, and polyethylene oxide.
Among these, considering the solubility of the metal salt and the removability when forming the seed layer, one or more selected from the group consisting of alkanethiols and amines are preferable.

  Examples of alkanethiols include ethanethiol, n-propanethiol, i-propanethiol, n-butanethiol, i-butanethiol, t-butanethiol, n-pentanethiol, n-hexanethiol, cyclohexanethiol, n -Heptanethiol, n-octanethiol, 2-ethylhexanethiol and the like are exemplified.

  Examples of amines include amine compounds such as ethylamine, n-propylamine, i-propylamine, n-butylamine, i-butylamine, t-butylamine, n-pentylamine, n-hexylamine, Cyclohexylamine, n-heptylamine, n-octylamine, 2-ethylhexylamine, 2-ethylhexylpropylamine, 3-ethoxypropylamine, n-nonylamine, n-decylamine, n-undecylamine, n-dodecylamine, n -Monoamine compounds such as tridecylamine, n-tetradecylamine, n-pentadecylamine, n-hexadecylamine, benzylamine, aminoacetaldehyde diethyl acetal, ethylenediamine, N-methylethylenediamine, N, N'- Methylethylenediamine, N, N, N ′, N′-tetramethylethylenediamine, N-ethylethylenediamine, N, N′-diethylethylenediamine, 1,3-propanediamine, N, N′-dimethyl-1,3-propanediamine 1,4-butanediamine, N, N′-dimethyl-1,4-butanediamine, 1,5-pentanediamine, N, N′-dimethyl-1,5-pentanediamine, 1,6-hexanediamine, Diamine compounds such as N, N′-dimethyl-1,6-hexanediamine, isophoronediamine, diethylenetriamine, N, N, N ′, N ″ N ″ -pentamethyldiethylenetriamine, N- (aminoethyl) piperazine, N And triamine compounds such as-(aminopropyl) piperazine.

  Examples of the monoalcohols include methanol, ethanol, n-propyl alcohol, i-propyl alcohol, n-butyl alcohol, i-butyl alcohol, sec-butyl alcohol, pentanol, hexanol, heptanol, octanol, cyclohexanol, and benzyl. Examples include alcohol and terpineol.

  Diols include ethylene glycol, propylene glycol, 1,2-butanediol, 1,2-pentanediol, 1,2-hexanediol, 2,3-butanediol, 2,3-pentanediol, 2,3- Hexanediol, 2,3-heptanediol, 3,4-hexanediol, 3,4-heptanediol, 3,4-octanediol, 3,4-nonanediol, 3,4-decanediol, 4,5-octane Diol, 4,5-nonanediol, 4,5-decanediol, 5,6-decanediol, 3-N, N-dimethylamino-1,2-propanediol, 3-N, N-diethylamino-1,2 -Propanediol, 3-N, N-di-n-propylamino-1,2-propanediol, 3-N, N-di-i-propylamino -1,2-propanediol, 3-N, N-di-n-butylamino-1,2-propanediol, 3-N, N-di-i-butylamino-1,2-propanediol, and 3 -N, N-di-t-butylamino-1,2-propanediol can be mentioned.

  Carboxylic acids are not particularly limited as long as they are reducible to metal salts, and examples thereof include formic acid, hydroxyacetic acid, glyoxylic acid, lactic acid, oxalic acid, tartaric acid, malic acid, and citric acid. be able to.

  As the reducing agent, one or two or more of those capable of reducing the metal salt can be selected or combined as appropriate according to the type of the metal salt. For example, when copper formate is used as the metal salt, an amine compound is preferable, and 2-ethylhexylpropylamine and 3-ethoxypropylamine are more preferable.

  As content of a reducing agent, the range of 1 mass%-99 mass% is preferable with respect to the whole quantity of the seed layer forming composition of this Embodiment, and the range of 10 mass%-90 mass% is more preferable. By setting the content of the reducing agent in the range of 1% by mass to 99% by mass, a seed layer having excellent conductivity can be formed. Moreover, the copper film of a lower resistance value can be formed by making content into the range of 1 mass%-99 mass%. Furthermore, the seed layer excellent in adhesiveness with a low resistance value and a base | substrate can be obtained by setting it as the range of 10 mass%-90 mass%.

[solvent]
The composition of this embodiment preferably contains a solvent from the viewpoint of improving the productivity by adjusting the viscosity of the composition and obtaining a low resistance and uniform conductive layer.
Examples of the solvent include organic solvents that can dissolve or disperse each component in the composition and do not participate in the reduction reaction of the metal salt. Specifically, one type selected from the group consisting of ethers, esters, aliphatic hydrocarbons, and aromatic hydrocarbons, or a mixture of two or more types compatible with each other can be used.

  Examples of ethers include hexyl methyl ether, diethylene glycol dimethyl ether, diethylene glycol diethyl ether, triethylene glycol dimethyl ether, triethylene glycol diethyl ether, tetrahydrofuran, tetrahydropyran, 1,4-dioxane, and the like.

  Examples of the esters include methyl formate, ethyl formate, butyl formate, methyl acetate, ethyl acetate, butyl acetate, methyl propionate, ethyl propionate, butyl propionate, and γ-butyrolactone.

  Examples of the aliphatic hydrocarbon include n-pentane, n-hexane, n-heptane, n-octane, n-nonane, n-decane, n-undecane, n-dodecane, cyclohexane, decalin and the like.

  Examples of aromatic hydrocarbons include benzene, toluene, xylene, ethylbenzene, n-propylbenzene, i-propylbenzene, n-butylbenzene, mesitylene, chlorobenzene, dichlorobenzene, and the like.

  Of these organic solvents, ethers are particularly preferable from the viewpoint of easy adjustment of the viscosity of the composition solution, and hexyl methyl ether, diethylene glycol dimethyl ether, and the like are particularly preferable.

  The content of the solvent contained in the seed layer forming composition of the present embodiment is in the range of 0% by mass to 95% by mass with respect to the total amount of the composition of the present embodiment, and 1% by mass to 70% by mass. It is preferable that it is the range of 10 mass%-50 mass%.

  The mixing method for producing the composition of the present embodiment is not particularly limited. For example, stirring with a stirring blade, stirring with a stirrer and a stirrer, stirring with a boiler, ultrasonic (homogenizer) Stirring and the like can be mentioned. As stirring conditions, for example, in the case of stirring with stirring blades, the rotation speed of the stirring blades is usually in the range of 1 rpm to 4000 rpm, preferably in the range of 100 rpm to 2000 rpm.

<Manufacturing method of wiring board>
The wiring board manufacturing method of the present embodiment is formed by using the composition described above and printing or applying a composition containing a metal salt and a reducing agent on the substrate 100 as shown in FIG. The seed layer 5 can be formed by heating the film.

As said printing method, when the base | substrate 1 is rigid, methods, such as inkjet printing, gravure printing, flexographic printing, (silk) screen printing, letterpress printing, are mentioned. Examples of the coating method include spin coating, spray coating, and bar coating.
In addition to the above-described method, a coating method using a roll coater can be used for the substrate 100 formed using the flexible substrate 1.

  The viscosity of the composition can be adjusted in accordance with the printing or coating method on the substrate 100. The possible viscosity of the composition is 0.01 poise to 1000 poise, and it is preferable to adjust the viscosity of the composition by adjusting the type and amount of the reducing agent and solvent according to the method used.

For example, when a composition having a high viscosity region such as letterpress printing or (silk) screen printing is a suitable method, 10 Poise to 100 Poise is preferable. In the case where a composition having a low viscosity region such as ink jet, gravure and flexographic printing is suitable, 0.01 Poise to 10 Poise is preferable. In the spin coating method, the spray coating method, and the bar coating method, 0.01 poise to 100 poise is preferable. In addition, the temperature in the said viscosity is 20 degreeC, and a shear rate is 10 sec- ¹ .

The viscosity of the composition of the present embodiment can be measured by any method as long as it is a viscosity measuring method that can regulate the shear rate, such as a capillary type, a double cylinder type, etc. In particular, a cone / plate type (E type) ) Viscometer is preferable in that the viscosity in the above range can be easily and accurately evaluated at a shear rate of 10 sec ⁻¹ .

  In the method for manufacturing a wiring board according to the present embodiment, it is preferable to heat the film of the composition for forming the seed layer 5 in a non-oxidizing atmosphere. Examples of the non-oxidizing atmosphere include a nitrogen atmosphere, a helium atmosphere, and an argon atmosphere. In order to improve the processing capacity, it is also possible to perform heat treatment using a continuous firing furnace such as a nitrogen flow reflow furnace. Among these, a nitrogen atmosphere in which inexpensive nitrogen gas can be used is preferable. That is, in the method for manufacturing a wiring board according to the present embodiment, the composition does not need to form a reducing atmosphere using a reducing gas such as hydrogen gas, and forms the seed layer 5 by heating in a safe state. be able to.

  In the method for manufacturing a wiring board according to the present embodiment, the heating temperature of the film formed from the composition for forming the seed layer 5 is, for example, a temperature at which a metal component such as a copper salt is reduced and an organic substance is decomposed or volatilized. If there is no particular limitation. Preferably, it is the range of 50 to 260 degreeC, and the range of 120 to 200 degreeC is more preferable. The heating temperature is preferably 50 ° C. or higher in order to promote the reduction of the metal component such as a copper salt and to prevent the remaining organic substance, and in order to use the substrate made of an organic material for the substrate 1, the heating temperature is used. Is preferably 260 ° C. or lower.

  In the method for manufacturing a wiring board of the present embodiment, the heating time may be appropriately selected in consideration of the type of metal component contained and the conductivity of the seed layer 5 to be formed, and is not particularly limited. When a heating temperature of about 200 ° C. is set, it is usually about 10 minutes to 60 minutes.

[Process (B)]
As shown in FIG. 1C, the step (B) included in the method for manufacturing the wiring board of the present embodiment is a predetermined region on the seed layer 5 that is more than the region where the seed layer 5 is provided. This is a step of forming the wiring layer 7 in a small region. As described above, the process (B) can be configured to include each of the processes (b-1) to (b-3).

FIGS. 3A and 3B are schematic cross-sectional views showing each process for forming a wiring layer.
In FIG. 3B, the process will be described using the same drawing as FIG.

[Step (b-1)]
In step (b-1), as shown in FIG. 3A, the resist pattern 6 is formed in a region other than the predetermined region for forming the wiring layer 7 on the seed layer 5 in FIG. 3B. It is.

  When forming the resist pattern 6, for example, a photosensitive insulating resin composition is used. The photosensitive insulating resin composition is not particularly limited as long as it is a photosensitive insulating resin composition used in the production of ordinary printed wiring boards. For example, acrylic resin-based, epoxy resin-based, phenolic resin-based, polyimide-based, etc. The resin composition is mentioned. In particular, as a photosensitive insulating resin composition, disclosed in JP-A-2002-139835 (A) an alkali-soluble resin having a phenolic hydroxyl group, (B) at least two alkyl etherified molecules. A resin composition containing an amino group-containing compound, (C) crosslinked fine particles, (D) a light-sensitive acid generator, and (E) a solvent can be suitably used. The photosensitive insulating resin composition may be used in the form of a liquid or a film such as a dry film having sticking properties.

  Commercially available products can be used for the photosensitive dry film resist, and for example, FP-225 (manufactured by Tokyo Ohka Co., Ltd.), RY3225 (manufactured by Hitachi Chemical Co., Ltd.) and the like can be used.

  Specifically, the photosensitive insulating resin composition is applied to the entire surface including the inside of the opening 4 (in the case of a liquid) or laminated (in the case of a film) to form a “photosensitive resist layer”. Then, exposure and development (resist patterning) are performed using a mask (not shown) patterned so as to follow a desired shape of the wiring layer 7 in FIG. A resist pattern 6 patterned so as to have a complementary shape according to the pattern shape is formed.

[Step (b-2)]
Step (b-2) is a step of forming a wiring layer 7 on the seed layer 5 exposed without being covered with the resist pattern 6 as shown in FIG. 3B (FIG. 1C). is there.

  In step (b-2), the seed layer 5 formed on the insulating layer 3 and on the inner surface of the opening 4 is used as a power feeding layer, and the seed layer 5 exposed without being covered with the resist pattern 6 including the opening 4 is formed. A wiring layer 7 is formed thereon. The formed wiring layer 7 is patterned into a desired shape on the seed layer 5 by the resist pattern 6 and is formed in a region smaller than the region where the seed layer 5 is provided.

  As a constituent material of the wiring layer 7, copper (Cu) is usually used. The method for forming the wiring layer 7 in the region on the seed layer 5 is not particularly limited as long as it is a method used in the production of a normal printed wiring board. For example, electrolytic plating, electroless plating, The CVD (Chemical Vapor Deposition) method is mentioned. In particular, electrolytic plating is preferable as a method for forming the wiring layer 7 in the region on the seed layer 5 including the opening 4.

As a specific example of electrolytic plating, the substrate 100 on which the resist pattern 6 obtained in the above step (b-1) is formed is subjected to hot water treatment at a temperature of 97 ° C. or higher, and then a conditioner chemical solution is used. Pre-treatment (for example, heating at about 50 ° C.), washing with water at room temperature, and then soft-etching the substrate surface using a soft-etching chemical.
Next, after washing with water and pretreatment using a pre-dip chemical solution, activation using an activator chemical solution is performed. Then, after washing with water, a deposition promoting process using an accelerator is performed, and an electrolytic copper plating process using a copper plating solution is performed.
Thereafter, an activation process using an acid is performed to form a wiring layer 7 made of copper on the seed layer 5 exposed without being covered with the resist pattern 6.

  As a plating solution used for electrolytic plating, an electrolytic solution containing copper can be used. Specifically, a material containing copper sulfate (concentration: 75 g / liter), sulfuric acid (concentration: 230 g / liter), chlorine ion (concentration: 50 mg / liter), a brightener and a correction agent is used. Can do.

In electroplating, a plating solution described above, under the setting temperature of about 23 ° C., a current density of ^{0.1A / dm 2 ~10A / dm 2} , performs deposition of copper-containing components. The preferable copper deposition rate is about 0.33 μm / min. In this case, the current density of the electrolytic plating treatment is preferably about 2 A / dm ² .

  In addition, the commercially available chemical | medical solution for the electrolytic plating process mentioned above can be used. For example, JX Nippon Mining & Metals' Iupinogue (registered trademark) (copper sulfate pentahydrate) can be used as copper sulfate. As the brightener, Superslow 2000 brightener manufactured by Cookson Electronics can be used. As the corrector, Cooksong Electronics Super Slow 2000 corrector can be used. As the acid for the activation treatment, 98% sulfuric acid manufactured by Maejima Shoten Co., Ltd. can be used.

[Step (b-3)]
Step (b-3) is a step of removing the resist pattern 6. In accordance with a known method, the resist pattern 6 on the seed layer 5 shown in FIG. 1C is removed, and the seed layer 5 underneath is exposed.

[Process (C)]
The step (C) contained in the method for manufacturing a wiring board of this embodiment is a step of removing the seed layer 5 exposed without being covered with the wiring layer 7 as shown in FIG. In the step (C), the wiring layer 7 having a desired pattern can be formed on the substrate 100 including the inside of the opening 4. Then, the seed layer 5 between the parts of the pattern of the wiring layer 7 is removed, and insulation is ensured when necessary between the parts of the wiring layer 7. And the wiring board 1000 of this embodiment can be obtained.

  The seed layer 5 exposed without being covered with the wiring layer 7 is dissolved by using a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate, ammonium persulfate, ferric chloride, cupric chloride or the like. This can be done by removing.

  As described with reference to FIGS. 1A to 1D, the method for manufacturing a wiring board according to the embodiment of the present invention includes the steps (A) to (C) and can manufacture the wiring substrate. . The wiring board manufacturing method according to the present embodiment forms a seed layer for electrolytic plating. However, the formation does not use a vacuum process such as sputtering, and the number of steps is different from that of electroless plating. Is performed by a method of heating a film obtained by applying a composition containing a metal salt or the like which is unnecessary. Therefore, the wiring board manufacturing method of this embodiment can manufacture a wiring board with a fine pattern and high productivity.

  Hereinafter, embodiments of the present invention will be described more specifically based on examples. However, the present invention is not limited to these examples.

  FIG. 4 is a schematic cross-sectional view of a wiring board that is an embodiment of the present invention.

  A wiring board 1000 shown in FIG. 4 is manufactured by the method for manufacturing a wiring board according to the embodiment of the present invention shown in FIGS. 1A to 1D, and has the same structure as the wiring board 1000 shown in FIG. Have. Accordingly, common components are given the same reference numerals, and redundant descriptions are omitted.

(Preparation of composition)
[Adjustment Example 1]
The total amount of the composition was 20% by mass of copper formate tetrahydrate as a metal salt and 80% by mass of 2-ethylhexylamine as a reducing agent. The composition was prepared by performing bead mill dispersion for a minute.

[Adjustment Example 2]
Copper hydroxide 10% by mass as a metal salt, 3-ethoxypropylamine 75% by mass, and formic acid 15% by mass as a metal salt are mixed with the whole composition, and a rotational speed of 2000 rpm, 60 at room temperature using a bead mill. The composition was prepared by performing bead mill dispersion for a minute.

[Adjustment Example 3]
To the entire composition, 10% by mass of copper formate tetrahydrate as a metal salt and 90% by mass of 3-ethoxypropylamine as a reducing agent were mixed, using a bead mill, at a rotation speed of 2000 rpm for 60 minutes at room temperature. Bead mill dispersion was performed to prepare a composition.

[Adjustment Example 4]
15% by mass of copper formate tetrahydrate as a metal salt and 85% by mass of aminoacetaldehyde diethyl acetal as a reducing agent are mixed with the whole composition, and the bead mill is used at room temperature and at a rotation speed of 2000 rpm for 60 minutes. Dispersion was performed to prepare a composition.

[Adjustment Example 5]
For the whole composition, 10% by mass of copper acetate as a metal salt, 80% by mass of 3-ethoxypropylamine and 10% by mass of formic acid as a reducing agent are mixed, and using a bead mill, rotation speed is 2000 rpm at room temperature for 60 minutes. A bead mill dispersion was performed to prepare a composition.

[Adjustment Example 6]
To the entire composition, 15% by mass of anhydrous copper formate as a metal salt, 50% by mass of 2-ethylhexylpropylamine as a reducing agent, and 35% by mass of diethylene glycol dimethyl ether as a solvent are mixed, and the number of revolutions at room temperature using a bead mill. The composition was prepared by carrying out bead mill dispersion at 2000 rpm for 60 minutes.

[Example of adjustment 7]
With respect to the entire composition, 15% by mass of anhydrous copper formate as a metal salt, 35% by mass of 2-ethylhexylpropylamine as a reducing agent, 25% by mass of 2-ethoxyethylamine, and 25% by mass of hexyl methyl ether as a solvent are mixed. The composition was prepared by carrying out bead mill dispersion for 60 minutes at a rotation speed of 2000 rpm at room temperature.

[Manufacture and evaluation of wiring boards]
[Example 1]
A copper-clad laminate in which 18 μm copper foil was laminated on both sides of a 1 mm thick substrate 1 made of glass epoxy resin was etched to form a lower wiring pattern 2 made of copper having a width of 100 μm on the substrate 1. Next, a resin layer (GX-13: manufactured by Ajinomoto Fine Techno Co., Ltd.) having a thickness of 70 microns was laminated with a laminator to form an insulating layer 3.

  An opening 4 having a diameter of 100 microns is formed in a predetermined position on the lower wiring pattern 2 in the insulating layer 3 laminated on the base 1, and further immersed in a permanganate solution to include the side surface of the opening 4 The surface of the insulating layer 3 was roughened to obtain a substrate 100.

  Next, the surface of the insulating layer 3 was coated with the composition prepared in Preparation Example 1 by a bar coating method. Next, the seed layer 5 having a thickness of about 1 μm was formed on the surface of the insulating layer 3 by subjecting the substrate 100 coated with the composition to a heat treatment at 170 ° C. for 10 minutes in a nitrogen atmosphere.

  Next, a resist pattern 6 (not shown in FIG. 4) was formed on the seed layer 5 formed by heating the composition using a lithography method. Next, the substrate 100 was immersed in a copper sulfate plating solution, and a wiring layer 7 made of copper having a thickness of 10 μm was formed at a predetermined position by electrolytic copper plating.

  After the electrolytic copper plating process, the resist pattern 6 was removed, and the seed layer 5 under the resist pattern 6 was removed with a normal copper etching solution. Then, wiring layers 7a, 7b, and 7c were formed as the wiring layer 7 having a width of 50 μm, and the wiring board 1000 was manufactured.

The manufactured wiring board 1000 was evaluated by measuring a resistance value between the wirings.
As a result of measurement using a digital multimeter (Ketley 2000), the insulation resistance between the wiring layer 7b and the wiring layer 7c (minimum electrode distance 30 μm) is 10 MΩ or more, and the conduction resistance between the wiring layer 7a and the lower wiring pattern 2a is 10Ω or less. It was confirmed that.

[Example 2]
A wiring substrate 1000 having the structure shown in FIG. 4 was manufactured by the same manufacturing method as in Example 1 using the composition prepared in Preparation Example 2 instead of the composition of Adjustment Example 1. And the resistance value between wiring was measured with the measuring method similar to Example 1. FIG. As a result of the measurement, it was confirmed that the insulation resistance between the wiring layer 7b and the wiring layer 7c (minimum electrode distance 30 μm) was 10 MΩ or more, and the conduction resistance between the wiring layer 7a and the lower wiring pattern 2a was 10Ω or less.

[Example 3]
A wiring substrate 1000 having the structure shown in FIG. 4 was manufactured by the same manufacturing method as in Example 1 using the composition prepared in Preparation Example 3 instead of the composition of Adjustment Example 1. And the resistance value between wiring was measured with the measuring method similar to Example 1. FIG. As a result of the measurement, it was confirmed that the insulation resistance between the wiring layer 7b and the wiring layer 7c (minimum electrode distance 30 μm) was 10 MΩ or more, and the conduction resistance between the wiring layer 7a and the lower wiring pattern 2a was 10Ω or less.

[Example 4]
A wiring substrate 1000 having the structure shown in FIG. 4 was manufactured by the same manufacturing method as in Example 1 using the composition prepared in Preparation Example 4 instead of the composition of Adjustment Example 1. And the resistance value between wiring was measured with the measuring method similar to Example 1. FIG. As a result of the measurement, it was confirmed that the insulation resistance between the wiring layer 7b and the wiring layer 7c (minimum electrode distance 30 μm) was 10 MΩ or more, and the conduction resistance between the wiring layer 7a and the lower wiring pattern 2a was 10Ω or less.

[Example 5]
A wiring substrate 1000 having the structure shown in FIG. 4 was manufactured by the same manufacturing method as in Example 1 using the composition prepared in Preparation Example 5 instead of the composition of Adjustment Example 1. And the resistance value between wiring was measured with the measuring method similar to Example 1. FIG. As a result of the measurement, it was confirmed that the insulation resistance between the wiring layer 7b and the wiring layer 7c (minimum electrode distance 30 μm) was 10 MΩ or more, and the conduction resistance between the wiring layer 7a and the lower wiring pattern 2a was 10Ω or less.

[Example 6]
A wiring substrate 1000 having the structure shown in FIG. 4 was manufactured by the same manufacturing method as in Example 1 using the composition prepared in Preparation Example 6 instead of the composition of Adjustment Example 1. And the resistance value between wiring was measured with the measuring method similar to Example 1. FIG. As a result of the measurement, it was confirmed that the insulation resistance between the wiring layer 7b and the wiring layer 7c (minimum electrode distance 30 μm) was 10 MΩ or more, and the conduction resistance between the wiring layer 7a and the lower wiring pattern 2a was 10Ω or less.

[Example 7]
A wiring substrate 1000 having the structure shown in FIG. 4 was manufactured by the same manufacturing method as in Example 1 using the composition prepared in Preparation Example 7 instead of the composition of Adjustment Example 1. And the resistance value between wiring was measured with the measuring method similar to Example 1. FIG. As a result of the measurement, it was confirmed that the insulation resistance between the wiring layer 7b and the wiring layer 7c (minimum electrode distance 30 μm) was 10 MΩ or more, and the conduction resistance between the wiring layer 7a and the lower wiring pattern 2a was 10Ω or less.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  For example, in the above-described embodiment of the present invention, an example in which a multilayer substrate is manufactured using the method for manufacturing a wiring substrate of the present invention has been described. However, the manufactured wiring substrate is not limited to the multilayer substrate. If it is a wiring board which forms a wiring layer using a seed layer, the manufacturing method of the wiring board of this invention can be applied suitably.

  The method for manufacturing a wiring board according to the present invention does not require a vacuum process such as a sputtering method for forming a seed layer for forming a wiring layer having a fine pattern. A highly reliable wiring board can be manufactured.

DESCRIPTION OF SYMBOLS 1 Base | substrate 2, 2a Lower layer wiring pattern 3 Insulating layer 4 Opening part 5 Seed layer 6 Resist pattern 7, 7a, 7b, 7c Wiring layer 100 Board | substrate 1000 Wiring board

Claims (12)

Heating a film formed by printing or applying a composition containing a metal salt and a reducing agent on a substrate to form a seed layer;
Forming a wiring layer in a predetermined region on the seed layer;
And a step of removing the seed layer exposed without being covered with the wiring layer. Forming the wiring layer includes forming a resist pattern in a region other than the predetermined region on the seed layer;
Forming the wiring layer on the seed layer exposed without being covered with the resist pattern;
The method for manufacturing a wiring board according to claim 1, further comprising a step of removing the resist pattern. Forming the seed layer includes forming an insulating layer having an opening on the substrate;
Forming the seed layer on the insulating layer and on the inner surface of the opening,
The method for manufacturing a wiring board according to claim 1, wherein the predetermined region includes the opening.   The method for manufacturing a wiring board according to claim 1, wherein the metal salt is a copper salt.   The method for manufacturing a wiring board according to claim 4, wherein the copper salt is at least one selected from copper formate and copper formate tetrahydrate.   The said composition contains a solvent further, The manufacturing method of the wiring board of any one of Claims 1-5 characterized by the above-mentioned.   The method for manufacturing a wiring board according to claim 1, wherein the step of forming the seed layer comprises heating the composition at 120 ° C. to 260 ° C. in a non-oxidizing atmosphere.   The method for manufacturing a wiring board according to claim 1, wherein the seed layer is formed after the surface of the substrate is roughened.   The method for manufacturing a wiring board according to claim 1, further comprising a step of forming a barrier metal film between the substrate and the seed layer.   The method for manufacturing a wiring board according to claim 1, wherein the predetermined region on the seed layer is a region smaller than a region where the seed layer is provided.   The method for manufacturing a wiring board according to claim 1, wherein the step of forming the wiring layer is performed by electrolytic plating using an electrolytic solution containing copper.   It uses for the manufacturing method of the wiring board of any one of Claims 1-11, The composition for seed layer formation characterized by the above-mentioned.

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