JP2014023235A - Power supply device, power supply control method, and power supply control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply device which can acquire high power conversion efficiency according to an output state, a power supply control method, and a power supply control program.SOLUTION: The power supply device includes: a plurality of digital control power supply sections; a sequence control section for controlling the digital control power supply sections; a storage section for storing sequence data that is control information on output settings of the plurality of digital control power supply sections and processor operation frequency control data; a digital processor for calculating feedback control processing and sequence control processing of the plurality of digital control power supply sections. In the power supply device, the operation frequency of the digital processor is controlled according to the output state by the sequence control section.

Description

  The present invention relates to a power supply device that generates and supplies a plurality of DC voltages, a power supply control method, and a power supply control program.

  Generally, in a power supply device having a plurality of DC (Direct Current) power supplies, the output of each DC power supply is controlled by an analog circuit. However, the control of the DC power supply by the analog circuit needs to change the circuit configuration when it is desired to change it according to the change in the usage situation, and this imposes a heavy burden on the person in charge of the system. Therefore, recently, digital control power supply apparatuses that digitally control each DC power supply have become widespread (for example, Patent Documents 1 and 2).

  The invention described in Patent Document 1 is based on the premise of a configuration including a processor, and a plurality of power supply circuits that respectively generate DC outputs, and conversion means that converts parameters related to the outputs of the plurality of power supply circuits into digital data, respectively. Have Based on the digital data obtained by the conversion means, the processor executes processing for controlling the outputs of the plurality of power supply circuits.

  The invention described in Patent Document 2 presupposes a configuration including a processor, monitors the output of the digital control circuit unit, and when it is determined that the load in the power control target device does not change, the digital control circuit unit The operation of the processor is stopped.

  Here, the power source of the LSI (Large-Scale Integrated circuit) requires a plurality of different voltage DC power sources such as a core power source and an IO (Input Output) power source. In addition, an element using a plurality of power supplies does not operate normally unless the power-on sequence for each element is observed. Therefore, in the power supply device that generates a plurality of different power supplies from the input power supply, the order of starting the power supplies is controlled.

In particular, it is an indispensable technique for a controller of a device having a plurality of functions such as a printer, a scanner, a facsimile, and an image processing device having a post-processing function for output paper. In such an apparatus, the order in which each power supply is started up is defined in detail for each device that realizes each function. There is a possibility that a malfunction may occur in the device due to the occurrence of wraparound.
In addition, while power saving is required, the necessary power changes by supplying the required power at the required timing for each device or by having the device in the power saving mode. A corresponding power supply is required.

  The rapid advancement of digital technology and the dramatic improvement in processor performance has made it easier to obtain high-performance processors at a low price. Thus, on the premise of a configuration including a processor, each of the plurality of power supply circuits for generating a DC output and a conversion unit for converting each parameter related to each output of the plurality of power supply circuits into digital data are provided. A digital control power supply that makes a processor execute a process of controlling outputs of a plurality of power supply circuits based on the obtained digital data has become practical.

  By the way, according to the invention described in Patent Document 1, it is possible to control a plurality of power supplies by processing of a processor. However, the power consumed by the processor is constant, and when the output power is low, the power consumption of the processor becomes a large loss, and there is a problem that the power conversion efficiency decreases.

  Further, according to the invention described in Patent Document 2, when it is determined that the load does not change, the operation of the processor in the digital control circuit unit is stopped, thereby realizing low power consumption of the arithmetic unit. . However, in the case of controlling a plurality of power supplies, there is a problem that the operation of the processor is stopped only when it is determined that the loads of all the power supplies do not change, and the power consumption cannot be reduced in other states.

  Accordingly, an object of the present invention is to provide a power supply device, a power supply control method, and a power supply control program capable of obtaining high power conversion efficiency according to the output state.

  In order to solve the above-mentioned problem, the invention according to claim 1 is a control information relating to a plurality of digital control power supply units, a sequence control unit for controlling the digital control power supply units, and output settings of the plurality of digital control power supply units. In the power supply apparatus comprising: a storage unit storing certain sequence data and processor operating frequency control data; a feedback control process of a plurality of digital control power supply units; and a digital processor that calculates the sequence control process. The operating frequency of the digital processor is controlled in accordance with the output state of the unit.

  According to the present invention, it is possible to obtain high power conversion efficiency according to the output state.

It is a figure which shows the structural example which concerns on one Embodiment of the digital control power supply device as a power supply device. It is a figure which shows the structural example which concerns on other embodiment of the digital control power supply device as a power supply device. It is a figure which shows the structural example which concerns on other embodiment of the digital control power supply device as a power supply device. It is a figure which shows the structural example which concerns on other embodiment of the digital control power supply device as a power supply device. (A) is an example of the flowchart for demonstrating operation | movement of the digital control power supply part of the digital control power supply device shown in FIG. 1, (b) is the sequence control part of the digital control power supply device shown in FIG. It is an example of the flowchart for demonstrating operation | movement. It is an example of the flowchart for demonstrating operation | movement of the sequence control part of the digital control power supply device shown in FIG. It is an example of the flowchart for demonstrating operation | movement of the sequence control part of the digital control power supply device shown in FIG. FIG. 5 is an example of a flowchart for explaining the operation of a sequence control unit of the digital control power supply device shown in FIG. 4.

Embodiments of the present invention will be described below with reference to the drawings.
<Overview>
The digital control power supply device mainly includes a digital control power supply unit and a sequence control unit, and the sequence control unit controls the digital power supply unit. When an event occurs in the sequence unit, the digital control power supply unit uses event condition data and each power ON / OFF control data describing the rising / falling control of each digital control power supply unit corresponding to each event Control. At the same time, the sequence control unit outputs clock information to the processor clock control unit, and the processor clock control unit changes the clock frequency of the processor clock unit according to the clock information. The digital processor operates at the changed clock frequency.

  In this digital control power supply device, the original operation is divided into digital feedback processing and sequence processing. Digital feedback processing is performed by interrupt processing every sampling cycle of AD converter, and sequence processing generates an event by sequence clock Is detected.

<Embodiment 1>
[Constitution]
FIG. 1 is a diagram illustrating a configuration example according to an embodiment of a digital control power supply device as a power supply device.
The digital control power supply device shown in FIG. 1 is a power supply device provided in a device having a plurality of power supply voltage generation circuits such as a copier, a printing machine, a FAX, and a multifunction peripheral.
It has a sequence control unit 16 and digital control power supply units 1 to 4 (21-1 to 21-4). The sequence control unit 16 has an output of the sequence clock 11, an output of the sequence data 12, an output of the processor operating frequency control data 13, an input of the memory writing unit 14, an output of the data memory unit 15, an input of the processor clock control unit 25, And the input of each digital control power supply device 1-4 (21-1 to 21-4) is connected. The output of the memory writing unit 14 is connected to the input of the data memory unit 15.

The sequence data 12 includes event condition data 12a and power ON / OFF control data 12b.
The data memory unit 15 as a non-volatile memory has event condition data 15a and power ON / OFF control data 15b.

  The output of the processor clock control unit 25 is connected to the input of the processor clock unit 26, and the output of the processor clock unit 26 is connected to the input of the digital processor 27.

The digital control power supply unit 1 (21-1) includes a target reference voltage data generation unit 17, a feedback control unit 18, an AD conversion unit 19, and a converter unit 20. The feedback control unit 18 includes an error detection unit 18a, a compensation unit 18b, and a PWM (Pulse Width Modulation) signal generation unit 18c.
The digital control power supply unit 1 (21-1) is configured such that the generation of the power supply voltage is collectively controlled by the sequence control unit 16 based on the sequence data 12.

  The input of the target reference voltage data generation unit 17 is connected to the output of the sequence control unit 16, and the output of the target reference voltage data generation unit 17 is connected to one input of the error detection unit 18a. The output of the error detector 18a is connected to the input of the compensator 18b, and the output of the compensator 18b is connected to the input of the PWM signal generator 18c. The output of the PWM signal generation unit 18c is connected to the input of the converter unit 29. The converter unit 20 outputs the voltage V1 and also outputs the DC voltage V1 and is connected to the input of the AD conversion unit 19. . The output of the AD converter 19 is connected to the other input of the error detector 18a.

  The digital control power supply unit 2 (21-2) to the digital control power supply unit 4 (21-4) output the DC voltage V2 to the DC voltage V4, respectively, but have the same configuration as the digital control power supply unit 1 (21-1). Therefore, explanation is omitted.

  A plurality of digital control power supply units 1 to 4 (21-1 to 21-4) (four circuits are not limited in the figure) are outputs to which a PWM signal is input to the converter unit 20 and output from the converter unit 20. Each voltage is held at a constant value.

[Operation]
Next, the operation of the digital control power supply apparatus shown in FIG. 1 will be described with reference to the drawings.
FIG. 5A is an example of a flowchart for explaining the operation of the digital control power supply unit of the digital control power supply device shown in FIG. 1, and FIG. 5B is the digital control power supply device shown in FIG. It is an example of the flowchart for demonstrating operation | movement of this sequence control part.

In the PWM control for controlling the output voltage, the following processing is usually performed.
5A, when the sampling clock is input (S101), the digital control power supply unit 1 (21-1) converts the output voltage of the converter unit 20 into digital data by the AD converter 19 (S102). The difference from the target reference voltage data is calculated by the error detection unit 18a (S103), and the compensation unit 18b generally performs a digital filter process to amplify the error between the output voltage data and the target reference data, and to provide a negative feedback characteristic. Compensation is performed (S104).
The digital control power supply unit 1 (21-1) determines whether or not the sampling clock has been re-input (S105). If there is a re-input (S105 / Yes), the process returns to step S101, where there is no trickle force ( (S105 / No), the process ends.
A PWM signal is generated by the PWM signal generation unit 18c based on the duty value of the PWM signal obtained as a result of the calculation, and is input to the converter unit 20 to adjust the output voltage V1. That is, feedback control is executed.

  In this embodiment, the digital processor 27 provided in the digital control power supply apparatus executes this feedback control. In the embodiment of FIG. 1, the error detection unit 18a, the compensation unit 18b, and the PWM signal generation unit 18c are collectively referred to as a feedback control unit 18. The plurality of digital control power supply units 1 to 4 (21-1 to 21-4) have the same configuration, and in the embodiment of FIG. 1, four digital control power supply units 1 to 4 (21-1 to 21-4) are provided. Show.

  Here, the digital filter processing of the compensation unit 18b is generally known to compensate a characteristic called PID (Proportional Integral Differential) control, but it is also possible to calculate a modern control method other than the classical control digital filter processing. good. “Classical control digital filter processing” means digital filter processing for PID control used in classic control, or digital filter processing for a compensator (securing negative feedback stability) based on the classic control theory. Means.

  The sequence control unit 16 controls the order of rising and falling of each output voltage of the plurality of digital control power supply units 1 to 4 (21-1 to 21-4). The output voltage rises by changing the target reference voltage data from 0 to a predetermined voltage value. Similarly, the output voltage falls by changing the target reference voltage data from a predetermined voltage value to zero. The order of rising and falling of each output voltage is input to the sequence control unit 16 as sequence data. The sequence data includes event condition data describing conditions that cause rising and falling events, and rising and rising edges of a plurality of digital control power supply units 1 to 4 (21-1 to 21-4) corresponding to each event. It consists of power ON / OFF control data describing the drop control.

In FIG. 5B, event condition data is retrieved at sequence clock intervals to detect whether an event has occurred (S111). If an event has occurred (S111 / Yes), each power ON / OFF The target reference voltage data is changed according to the OFF control data (S112). If no event occurs (S111 / No), the process waits.
The processing of the sequence control unit 16 is also executed by the digital processor 27 provided in the digital control power supply unit 1 (21-1).

Due to the occurrence of an event, the ON / OFF state of each digital control power supply unit changes, and the processing content performed by the digital processor 27 changes accordingly. For example, when only one of the digital control power supply units 1 to 4 (21-1 to 21-4) is operating, and all the digital control power supply units 1 to 4 (21-1 to 21-4) are operating. In this case, the amount of digital filtering processing necessary for feedback control is different. Or, in a state where the load fluctuation represented by the sleep state is reduced, the digital filter processing calculation amount required for feedback control of each of the digital control power supply units 1 to 4 (21-1 to 21-4) is reduced. be able to.
The digital processor 27 generally consumes power proportional to the operating frequency. When the operating frequency of the digital processor 27 is fixed at an operating frequency at which the maximum digital filter processing calculation is possible in the ON / OFF state of the digital control power supply units 1 to 4 (21-1 to 21-4) As power is consumed by the digital processor 27, a constant power loss occurs. When the output power is large, the power consumption of the digital processor 27 has little influence on the power conversion efficiency.

  However, only one of the digital control power supply units 1 to 4 (21-1 to 21-4) is operating, or the digital control power supply units 1 to 4 (21-1 to 21-4) are in a sleep state. ) Is small, the influence of the loss of power consumption of the digital processor 27 becomes large, and the power conversion efficiency deteriorates.

For example, when the power consumption at a fixed operating frequency of the digital processor 27 is 300 mW, only one of the digital control power supply units 1 to 4 (21-1 to 21-4) is output, and the output power thereof Is 100 mW, even if it is assumed that other losses such as the converter unit 20 are zero, the input power is 400 mW and the output power is 100 mW, so the power conversion efficiency is 25%.
On the other hand, when four digital control power supply units 1 to 4 (21-1 to 21-4) output four output powers of 10 W each, other losses such as the converter unit 20 are zero. Assuming that there is an input power of 40.3 mW and an output power of 40 W, the power conversion efficiency is 99.3%. As described above, the influence of the power consumption of the digital processor 27 on the power conversion efficiency differs depending on the output state.

Therefore, the processor condition frequency control data corresponding to the event condition data of the sequence data and each power supply unit ON / OFF control data is configured to turn on / off each of the digital control power supply units 1 to 4 (21-1 to 21-4). The sequence control unit 16 outputs clock information to the processor clock control unit 25 according to the output power mode state according to the OFF state or the event condition (S113), and the processor clock control unit 25 changes the clock frequency of the processor clock unit 26 based on the clock information. (S114).
Digital processor 27 operates at the changed clock frequency.

  1 is a process performed by the digital processor 27 shown in the lower part of the drawing, and the processing contents and the actual hardware are mixed. .

For example, when only one of the previous digital control power supply units 1 to 4 (21-1 to 21-4) is output and the output power is 0.1 W, each digital control power supply unit 1 corresponding to the state is output. To 4 (21-1 to 21-4) and whether or not the event condition is satisfied (S115), if not applicable, wait (S115 / No), if applicable (S115 / Yes) ), The sequence control unit 16 performs sequence control of each of the digital control power supply units 1 to 4 (21-1 to 21-4) corresponding to the event condition data and each power supply unit ON / OFF control data, and the sequence output state The processor operating frequency control data corresponding to is read (S116).
Since this state corresponds to a sleep state in which there is one output of the digital control power supply units 1 to 4 (21-1 to 21-4) and the load fluctuation is small, the processor operating frequency control data is set to 1/30 clock. Output clock information.
The clock information may be a clock frequency of the digital processor 27, or a division ratio or a divisor of the maximum operation clock frequency. The clock information may be configured by estimating the amount of digital processor processing corresponding to the sequence data, or may be obtained by experiment.

The sequence control unit 16 outputs this clock information to the processor clock control unit 25 (S117), and the processor clock control unit 25 changes the processor clock frequency that is the output of the processor clock unit 26 (S118).
After changing the processor clock frequency, the process returns to step S111.
Since the digital processor 27 operates with the changed clock, the power consumption becomes 1/30. Assuming that other losses such as the converter unit 20 are zero, the power consumption of the digital processor 27 of the previous example is 1/30 to 10 mW, so the input power is 110 mW and the output power is 100 mW. Is 91%, and the power conversion efficiency is greatly improved.

<Embodiment 2>
[Constitution]
FIG. 2 shows a configuration example according to another embodiment of a digital control power supply device as a power supply device.
The difference between the embodiment shown in FIG. 2 and the embodiment shown in FIG. 1 is that the digital control power supply units 1 to 4 (22-1 to 22-4) are connected to the sequence control unit 16 and the output is output. Has a feedback control ON / OFF unit 33 connected to the feedback control unit 16, and instead of the memory writing unit 14 and the data memory unit 14, the power supply unit ON state number detection unit whose input is connected to the sequence control unit 16 31 and a processor operating frequency control data 32 unit whose input is connected to the power supply unit ON state number detection unit 31 and whose output is connected to the sequence control unit 16.

[Operation]
FIG. 6 is an example of a flowchart for explaining the operation of the sequence control unit of the digitally controlled power supply apparatus shown in FIG. Hereinafter, the flowchart for explaining the operation of the digital control power supply unit of the digital control power supply apparatus is the same as that described above, and is omitted.

In the embodiment shown in FIG. 2, it is determined whether or not an event has occurred (S201). If no event has occurred, the process waits (S201 / No), and if an event has occurred (S201 / Yes). Then, the target reference voltage data is changed (S202).
The sequence control unit 16 outputs clock information to the processor clock control unit 25 (S203).
The processor clock control unit 25 changes the clock frequency of the processor clock unit according to the clock information (S204).
It is determined whether or not the output voltage of the digital control power supply units 1 to 4 (22-1 to 22-4) satisfies a predetermined condition (S205), and if not, it waits (S205 / No) and corresponds. In the case (S205 / Yes), the process proceeds to step S206.
The sequence control unit 16 corresponds to the event condition data of the sequence data and each power supply unit ON / OFF control data, and controls the digital control power supply units 1 to 4 (22-1) to turn off the power supply operation from each power supply ON / OFF control data. ˜22-4), the feedback control ON / OFF unit 33 stops the operation of the feedback control unit 18 (S206).
Since the processing of the feedback control unit 18 is performed by the digital processor 27, when there are a plurality of feedback control units 18 as in the present embodiment, the feedback control processing of the digital control power supply unit 1 (22-1) is performed, and the next Next, the digital control power supply unit 2 (22-2) performs the feedback control process sequentially (S207).

Therefore, stopping the operation of the feedback control unit 18 by the feedback control ON / OFF unit 33 means not performing the corresponding feedback control process, and does not execute the corresponding feedback control program in terms of the program of the digital processor 27. The program is controlled (the program flow is controlled by a jump instruction, a branch instruction, etc.).
By not performing the feedback control process, the processing amount of the digital processor 27 is reduced.

Next, the sequence control unit 16 outputs the power supply unit ON / OFF state to the power supply unit ON state number detection unit 31 (S208).
The power supply unit ON state number detection unit 31 outputs the number of power supply units performing feedback control processing to the processor operating frequency control data unit 32 (S209).
The processor operating frequency control data unit 32 outputs clock information corresponding to the number of power supply units performing feedback control processing (S210), and the sequence control unit 16 outputs clock information to the processor clock control unit (S211). The processor clock control unit 25 changes the clock frequency of the processor clock unit 26 according to the clock information (S212).
The digital processor 27 operates at the changed clock frequency (S213).
In the present embodiment, the digital processor 27 operates at an operating frequency corresponding to the number of ON states of the power supply unit, whereby the power consumption of the digital processor 27 can be reduced, and the power conversion efficiency is improved as in the embodiment of FIG. The

<Embodiment 3>
[Constitution]
FIG. 3 shows a configuration example according to another embodiment of a digital control power supply device as a power supply device.
The difference between the embodiment shown in FIG. 3 and the embodiment shown in FIG. 1 is that the digital control power supply units 1 to 4 (23-1 to 23-4) are connected to the sequence control unit 16 and the output is A sampling frequency control unit 43 connected to the AD conversion unit 19; instead of the memory writing unit 14 and the data memory unit 15, a sampling frequency detection unit 41 whose input is connected to the sequence control unit 16; The processor operating frequency control data unit 42 is connected to the frequency detection unit 41 and the output is connected to the sequence control unit 16.

[Operation]
FIG. 7 is an example of a flowchart for explaining the operation of the sequence control unit of the digitally controlled power supply apparatus shown in FIG.
In the embodiment of FIG. 3, it is determined whether or not an event has occurred (S301). If no event has occurred, the process waits (S301 / No), and if an event has occurred (S301 / Yes), the target The reference voltage data is changed (S302).
The sequence controller 16 outputs clock information to the processor clock controller 25 (S303).
The processor clock control unit 25 changes the clock frequency of the processor clock unit according to the clock information (S304).
It is determined whether or not the output voltage of the digital control power supply units 1 to 4 (22-1 to 22-4) satisfies a predetermined condition (S305), and if not, it waits (S305 / No) and corresponds. In the case (S305 / Yes), the process proceeds to step S306.
The sequence control unit 16 corresponds to the event condition data of the sequence data and each power supply unit ON / OFF control data, and the digital control power supply units 1 to 4 (23-) in which the load fluctuation is reduced as in the sleep mode. 1 to 23-4), the sampling frequency of the AD converter 19 is changed by an instruction from the sampling frequency control unit 43 (S306).

  The higher the sampling frequency of the Ad converter 19, the faster the response performance to load fluctuations. However, in the mode in which the load fluctuation is small and the output power is small as in the sleep mode, the influence of the power consumption of the digital processor 27 is large. For this reason, the sampling frequency of the AD converter 19 is lowered to reduce the amount of feedback control processing calculation (S307).

  Since the amount of feedback control processing calculation is proportional to the sampling frequency of the AD converter 19, by making the sampling frequency of the AD converter 19 1/10, the amount of feedback control processing calculation is also reduced to about 1/10. The frequency can also be changed to about 1/10, and the power consumption of the digital processor 27 can be reduced.

  By changing the sampling frequency of the AD converter 19, the sampling frequency detection unit 41 inputs the changed sampling frequency information to the processor operating frequency control data unit 42 (S 308), and the processor operating frequency control data unit 42 responds. (S309), the sequence control unit 16 outputs the clock information to the processor clock control unit.

The processor clock control unit 16 changes the clock frequency of the processor clock unit 26 according to the clock information (S310).
The digital processor 27 operates at the changed clock frequency (S311).
In the present embodiment, the digital processor 27 operates at an operating frequency corresponding to the changed sampling frequency of the AD converter 19, so that the power consumption of the digital processor 27 can be reduced. As in the embodiment of FIG. Efficiency is improved.

<Embodiment 4>
[Constitution]
FIG. 4 shows a configuration example according to another embodiment of a digital control power supply device as a power supply device.
The difference between the embodiment shown in FIG. 4 and the embodiment shown in FIG. 1 is that digital control power supply units 1 to 4 (24-1 to 24-4) are connected to the sequence control unit 16. A filter coefficient control unit 51 whose output is connected to the compensation unit 18b; and a sampling frequency control unit 52 whose input is connected to the sequence control unit 16 and whose output is connected to the AD conversion unit 19; In place of the data memory unit 15, the sampling frequency detection unit 41 whose input is connected to the sequence control unit 16, and the processor operating frequency whose input is connected to the sampling frequency detection unit 41 and whose output is connected to the sequence control unit 16 And a control data unit 42.

[Operation]
FIG. 8 is an example of a flowchart for explaining the operation of the sequence control unit of the digitally controlled power supply apparatus shown in FIG.
In the embodiment shown in FIG. 4, it is determined whether or not an event has occurred (S401). If no event has occurred, the process waits (S401 / No), and if an event has occurred (S401 / Yes). Then, the target reference voltage data is changed (S402).
The sequence control unit 16 outputs clock information to the processor clock control unit 25 (S403).
The processor clock control unit 25 changes the clock frequency of the processor clock unit according to the clock information (S404).
It is determined whether or not the output voltage of the digital control power supply units 1 to 4 (22-1 to 22-4) satisfies a predetermined condition (S405), and if not, it waits (S405 / No) and corresponds. In the case (S405 / Yes), the process proceeds to step S306.
The sequence control unit 16 controls the sampling frequency with respect to the digital control power supply unit in which the load fluctuation is reduced like the sleep mode in response to the event condition data of the sequence data and each power supply unit ON / OFF control data. The sampling frequency of the AD converter 19 is changed and the filter coefficient of the compensation unit 18b is changed (S406).

  The filter characteristic of the compensation unit 18b is determined in order to stabilize the negative feedback characteristic by the feedback control unit 18, but the optimum filter characteristic changes when the sampling frequency of the AD converter 19 is lowered. Therefore, a stable negative feedback characteristic can be obtained by changing the sampling frequency of the AD converter 19 and changing to a filter coefficient corresponding to the sampling frequency.

The sampling frequency of the AD converter 19 and the instruction of the filter coefficient control unit 51 change the digital filter coefficient of the compensation unit 18b, and the sampling frequency detection unit inputs the changed sampling frequency information to the processor operating frequency control data unit 42. (S407), the corresponding clock information is output from the processor operating frequency control data (S408), the sequence control unit outputs the clock information to the processor clock control unit (S409), and the processor clock control unit receives the processor clock unit based on the clock information. The clock frequency is changed (S410).
The digital processor 27 operates at the changed clock frequency (S411).
In the present embodiment, the digital processor 27 operates at an operating frequency corresponding to the changed sampling frequency of the AD converter 19 so that the power consumption of the digital processor 27 can be reduced. As in the embodiment of FIG. Efficiency is improved.

  Note that the sequence data and the processor operating frequency control data section shown in FIG. 1 may be stored in a nonvolatile memory. When the power supply device is activated, the sequence data and the processor operating frequency control data are read from the non-volatile memory unit and the sequence control is performed. In addition, the sequence data and the processor operating frequency control data can be changed by writing the data stored in the nonvolatile memory from the sequence control unit 16 through the memory writing unit 14.

<Program>
The digital power supply control apparatus according to the present invention described above is realized by a power supply control program that causes a computer to execute processing. Examples of the computer include general-purpose computers such as personal computers and workstations, but the present invention is not limited to this. Therefore, as an example, a case where the present invention is realized by a program will be described below.

For example,
A plurality of digital control power supply units, a sequence control unit that controls the digital control power supply units, a sequence data that is control information relating to output settings of the plurality of digital control power supply units, and a storage unit that stores processor operating frequency control data; In a power supply control program for controlling a power supply device including a digital processor that calculates feedback control processing and sequence control processing of a plurality of digital control power supply units,
To computer of digital control power supply part,
When an event occurs, the sequence control unit digitally controls the event condition data and the power ON / OFF control data describing the rise / fall control of each of the plurality of digital control power supply units corresponding to each event Procedures for controlling the power supply,
The sequence control unit outputs the clock information to the processor clock control unit,
The processor clock control unit is a procedure for changing the clock frequency of the processor clock unit according to the clock information,
The procedure for the digital processor to operate at the changed clock frequency of the processor clock part,
A power supply control program for executing

  Thus, the power supply apparatus according to the present invention can be realized anywhere as long as there is a computer environment capable of executing the program.

<Storage medium>
Such a program may be stored in a computer-readable storage medium.
Here, examples of the storage medium include a computer-readable storage medium such as a CD-ROM (Compact Disc Read Only Memory), a flexible disk (FD), and a CD-R (CD Recordable), a flash memory, and a RAM (Random). Examples include semiconductor memories such as Access Memory (ROM), Read Only Memory (ROM), and FeRAM (ferroelectric memory), and HDD (Hard Disc Drive).

<Effect>
High power conversion efficiency according to the output state by changing the digital processor operating frequency according to the output state in the digital control power supply device that calculates the feedback control processing and sequence control processing of multiple digital control power supply units with the digital processor Can be earned.
That is, according to the present embodiment, it is possible to obtain high power conversion efficiency according to the output state by changing to the digital processor operating frequency according to the output state.

  The above-described embodiment shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. is there.

11 Sequence clock 12 Sequence data 12a, 15a Event condition data 12b, 15b Power ON / OFF control data 13 Processor operating frequency control data 14 Memory writing unit 15 Data memory unit 16 Sequence control unit 17 Target reference data generation unit 18 Feedback control unit 19 AD conversion unit 20 Converter unit 21-1 to 21-4, 22-1 to 22-4, 233-1 to 23-4, 24-1 to 24-4 Digital control power supply unit 25 Processor clock control unit 26 Processor clock Unit 27 Digital Processor 31 Power Supply Unit ON State Number Detection Unit 32 Processor Operating Frequency Control Data Unit 33 Feedback Control ON / OFF Unit 41 Sampling Frequency Detection Unit 42 Processor Operating Frequency Control Data Unit 43, 52 Sampler Frequency control unit 51 Filter coefficient control unit

JP 11-272344 A JP 2010-17022 A

Claims (8)

A plurality of digital control power supply units, a sequence control unit that controls the digital control power supply units, a sequence data that is control information related to output settings of the plurality of digital control power supply units, and a memory that stores processor operating frequency control data And a digital processor that computes feedback control processing and sequence control processing of a plurality of digital control power supply units,
The power supply apparatus characterized by controlling the operating frequency of the said digital processor according to the output state by the said sequence control part.   2. The power supply according to claim 1, wherein the number of ON states of the power supply unit corresponding to the output state by the sequence control unit is detected, and the operating frequency of the digital processor is controlled by the corresponding processor operating frequency data. apparatus.   The sampling frequency of the AD converter used in the digital control power supply unit is changed according to the output state of the sequence control unit, and the operating frequency of the digital processor is controlled by the corresponding processor operating frequency data. The power supply device according to claim 1.   4. A sampling frequency of the AD converter is changed according to an output state by the sequence control unit, and a digital filter coefficient of a compensator used in the digital control power source unit is changed. The power supply device described in 1.   2. The power supply device according to claim 1, wherein the sequence data and the processor operating frequency control data are stored in a nonvolatile memory.   6. The power supply device according to claim 5, wherein data stored in the nonvolatile memory is written from a sequence control unit through a memory writing unit. A plurality of digital control power supply units, a sequence control unit that controls the digital control power supply units, a sequence data that is control information related to output settings of the plurality of digital control power supply units, and a memory that stores processor operating frequency control data And a digital processor that calculates a feedback control process of a plurality of digital control power supply units and a sequence control process.
When an event occurs, the sequence control unit uses the event condition data and the power ON / OFF control data describing the rise / fall control of each of the plurality of digital control power supply units corresponding to each event. Control the control power supply,
The sequence control unit outputs clock information to the processor clock control unit,
The processor clock control unit changes the clock frequency of the processor clock unit according to clock information,
The digital processor operates at the changed clock frequency of the processor clock unit. A plurality of digital control power supply units, a sequence control unit that controls the digital control power supply units, a sequence data that is control information related to output settings of the plurality of digital control power supply units, and a memory that stores processor operating frequency control data A power supply control program for controlling a power supply device including a digital processor for calculating a feedback control process of a plurality of digital control power supply units and a sequence control process,
In the computer of the digital control power supply unit,
When an event occurs, the sequence control unit uses the event condition data and the power ON / OFF control data describing the rise / fall control of each of the plurality of digital control power supply units corresponding to each event. Procedure for controlling the control power supply,
The sequence control unit outputs a clock information to the processor clock control unit,
The processor clock control unit changes the clock frequency of the processor clock unit according to clock information,
The digital processor operates at the changed clock frequency of the processor clock unit;
The power supply control program characterized by performing this.

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