JP2009110385A - Data processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processing system, which controls processing performance with reasonable accuracy by controlling the processing performance of data processing with hardware. <P>SOLUTION: The data processing system having a data processing section 110 includes: a first register 121 for measuring processing performance of data processing and storing the measured performance value as the result; a second register 122 for storing a target performance value which is target predetermined processing performance: a performance comparison section 123 for comparing the measured performance value stored in the first register 121 and a target performance value stored in the second register 122; and a performance adjustment section 124 for adjusting processing performance of data processing according to the comparison result by the performance comparison section 123. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data processing system, and more particularly to a data processing system that controls processing performance of an LSI.

  Recent rapid advances in semiconductor technology have enabled the development of LSIs with significantly higher performance than before. As the performance of LSIs becomes more powerful, there is a need for technology for controlling the processing performance of LSIs as needed.

  An example in which LSI performance control is particularly useful is power consumption reduction due to LSI performance suppression. As the operating frequency is improved and the integration density is increased, the power consumption of the LSI is significantly increased as compared with the prior art, which causes a problem of increasing the maintenance cost of the data processing system. Therefore, in developing a data processing system, reducing the power consumption of LSI is an important issue.

  As a method for reducing the power consumption of the LSI, there are a method for reducing the power consumption required for the LSI to operate by improving semiconductor technology and a method for reducing the power consumption by reducing unnecessary operations of the LSI. As a method for reducing power consumption, many of recent high-performance LSIs have a function of performing performance control according to the amount of processing load. This is a method of reducing power consumption by reducing the latter unnecessary operation. It is.

  As a technique for controlling the processing performance of an LSI, Patent Document 1 describes a technique relating to dynamic management of processor performance and power in a computer system that controls the frequency of an LSI operation clock. As another technique for controlling the processing performance of an LSI, there is a technique for stopping the power supply and clock distribution to a part of the logic part of the LSI and stopping the function of the logic part.

Special table 10-501911

  However, since the conventional technology does not have a function for performing performance control such as setting a target performance value and performing data processing according to the processing performance, the processing performance of the LSI varies depending on the internal or external state of the LSI. End up. Therefore, in order to ensure that the LSI operates with a constant processing performance, it is necessary for software to control the processing performance of the LSI so that a target performance value is set and data processing is performed with the processing performance.

  However, LSI performance control by such software has a problem that accuracy in controlling performance is low. In performance control by software, it is necessary to adjust the LSI processing performance to the target performance while measuring the LSI processing performance. However, the software measures the LSI processing performance and then adjusts the LSI processing performance. In the meantime, the processing performance of the LSI fluctuates, so that an error occurs between the target performance value and the actual processing performance of the LSI.

  An object of the present invention is to provide a data processing system that controls processing performance with reasonable accuracy by controlling processing performance of data processing by hardware.

  In order to achieve the above object, a data processing system of the present invention includes a first register for measuring a processing performance of data processing and storing a measurement performance value as a result in the data processing system having a data processing unit. A second register for storing a target performance value, which is a target predetermined processing performance, the measurement performance value stored in the first register, and the target performance value stored in the second register And a performance adjustment unit that adjusts the processing performance of the data processing according to the comparison result of the performance comparison unit.

  In addition, the second register can be configured to have an input interface for setting the target performance value.

  The performance adjustment unit can be configured to control the measured performance values of the plurality of data processing units to be equal to the predetermined target performance value stored in the second register.

In addition, a comparison unit that compares the measurement performance values of a plurality of the data processing units is included, and the lowest measurement performance value among the comparison results by the comparison unit is stored in the second register as the target performance value. It can be constituted as follows.
A clock generation unit configured to generate a clock; and a clock frequency conversion unit configured to convert a frequency of the clock generated by the clock generation unit. The performance adjustment unit is configured to convert a clock frequency converted by the clock frequency conversion unit. The data processing system according to claim 1, wherein the control is variably controlled.

  An object of the present invention is to provide a data processing system that controls processing performance with reasonable accuracy by controlling processing performance of data processing by hardware.

Next, the best mode for carrying out the present invention will be described based on the following embodiments with reference to the drawings.
[Example 1]
FIG. 1 is a diagram illustrating a basic configuration example of a data processing system according to the first embodiment.
The data processing system includes an LSI 00 including a data processing logic unit 110 and a performance control logic unit 120.

  The data processing logic unit 110 is composed of a logic circuit such as a control circuit that executes data processing for realizing the functions of the LSI 100, and performs data processing performance measurement and performance adjustment (details) from outside the data processing logic unit 110. Can be performed later).

  The performance control logic unit 120 includes a measurement performance register 121, a target performance register 122, a performance comparison logic unit 123, and a performance adjustment logic unit 124.

  The measurement performance register 121 stores a value obtained by measuring the throughput of data processing executed by the data processing logic unit 110 as a measurement performance value. The target performance register 122 stores a target performance value for data processing by the data processing logic 110. The input of the target performance value to the target performance register 122 can be set from the outside of the performance control logic unit 120 by a program or hardware, and an input terminal is provided as an interface therefor.

  The performance comparison logic unit 123 compares the measured performance value stored in the measured performance register 112 with the target performance value stored in the target performance register 122. The performance adjustment logic unit 124 adjusts the performance of the data processing logic unit 110 based on the comparison result compared by the performance comparison logic unit 123.

  Here, FIG. 2 is a diagram for explaining the performance adjustment operation by the performance adjustment logic unit 124.

  In the graph, the horizontal axis represents time, and the vertical axis represents the measurement performance value of the data processing unit 110. When the measured performance value is larger than the target performance value (T1, T3), the performance adjustment logic unit 124 adjusts the processing performance of the data processing logic unit 110 to be lowered. On the other hand, when the measured performance value is smaller than the target performance value (T2), the performance adjustment logic unit 124 adjusts so as to increase the processing performance of the data processing logic 110. As described above, according to the magnitude relation between the measured performance value and the target performance value, the processing performance by the performance adjustment logic unit 124 is repeated up and down until the measured performance value and the target performance value become equal (T4), thereby obtaining data. The performance of the processing logic unit 110 is adjusted. When the measured performance value is equal to the target performance value, the performance adjustment logic unit 124 does not adjust the data processing performance of the data processing logic unit 110.

  Through the negative feedback control described above, the performance control of the data processing logic 110 can be performed so that the measured performance value indicating the data processing performance of the data processing logic 110 is equal to the target performance value, and the data processing logic unit can be controlled with high accuracy. Performance control can be performed.

In this embodiment, the data processing logic unit 110 and the performance control logic unit 120 are configured on the same LSI, but may be configured to have both on different LSIs.
[Example 2]
When there is a difference in data processing performance between data processing logic units in a data processing system composed of a plurality of data processing logic units operating in cooperation, the data processing logic unit with the lowest processing performance is This becomes a bottleneck and other data processing logic units operate with excessive processing performance.

  Accordingly, as a second embodiment, a data processing system that suppresses the processing performance of a data processing logic unit that operates with excessive processing performance and reduces unnecessary power consumption by equalizing the processing performance of a plurality of data processing logic units. Will be described.

FIG. 3 is a diagram illustrating a configuration example of a data processing system according to the second embodiment.
The data processing system includes an LSI 200, an LSI 300, an LSI 400, a clock frequency conversion LSI (1) 501, a clock frequency conversion LSI (2) 502, and a clock generator 503.

  The clock generator 503 generates a clock having a predetermined frequency. The clock frequency conversion LSI (1) 501 converts the clock generated by the clock generator 503 into a clock having an arbitrary frequency by external control, and supplies the clock to the LSI 200. The clock frequency conversion LSI (2) 502 converts the clock generated by the clock generator 503 into a clock with an arbitrary frequency by external control, and supplies the clock to the LSI 300.

  The LSI 200 includes a data processing logic unit (1) 210, a QUEUE 211, and a performance measurement logic unit 212.

  The data processing logic unit (1) 210 includes a logic circuit such as a control circuit that executes data processing for realizing the functions of the LSI 200.

  The QUEUE 211 holds the data processed by the data processing logic unit 210. A plurality of data can be held. When the processing performance difference between the data processing logic unit 210 and the data processing logic unit 310 is large, the QUEUE 211 enters the FULL or EMPTY state and interrupts the processing of the data processing logic unit 210 or the data processing logic unit 310. When the data processing performance of the data processing logic unit 210 is higher than that of the data processing logic unit 310, the number of data held in the QUEUE 211 increases, and when the limit of data capacity that can be held by the QUEUE 211 is reached, the QUEUE 211 enters a FULL state. Data processing of the data processing logic unit 210 stops until the QUEUE 211 becomes available. On the contrary, when the data processing performance of the data processing logic unit 210 is lower than that of the data processing logic unit 310, the number of data held in the QUEUE 211 gradually decreases, and there is no more data held in the QUEUE 211. The QUEUE 211 enters the EMPTY state, and the data processing of the data processing logic unit 310 stops until data is held in the QUEUE 211.

  The performance measurement logic unit 212 measures the throughput of processing data that the data processing logic unit 210 inputs to the QUEUE 211 and the throughput of processing data that the data processing logic unit 310 extracts from the QUEUE 211.

  The LSI 300 includes a data processing logic unit (2) 310 including a logic circuit such as a control circuit that executes data processing for realizing the functions of the LSI 300.

  The LSI 400 includes a measurement performance register (1) 411, a measurement performance register (2) 412, a performance comparison logic unit (1) 413, a performance comparison logic unit (2) 414, a performance adjustment logic unit (1) 415, and a performance adjustment logic unit. (2) Consists of a performance control logic unit 410 composed of 416 and target performance register 417. The performance control logic unit 410 has a function of performing performance control of the data processing logic unit 210 and the data processing logic unit 310.

  The measurement performance register (1) 411 stores the throughput of processing data that the data processing logic unit 210 inputs to the QUEUE 211 as the measurement performance value of the data processing logic unit 210. The measurement performance register (2) 412 stores the throughput of processing data that the data processing logic unit 310 retrieves from the QUEUE 211 as the measurement performance value of the data processing logic unit 310. The target performance register 417 stores data processing target performance values of the data processing logic unit 210 and the data processing logic unit 310. The target performance value can be set from outside the performance control logic 410.

  The performance comparison logic unit (1) 413 reads the measurement performance value and the target performance value of the data processing logic unit 210 from the measurement performance register (1) 411 and the target performance register 417, respectively, and compares them. The performance comparison logic unit (2) 414 reads the measurement performance value and the target performance value of the data processing logic unit 310 from the measurement performance register (2) 412 and the target performance register 417, respectively, and compares them. The performance adjustment logic unit (1) 415 controls the clock frequency conversion LSI (1) 501 based on the comparison result by the performance comparison logic unit (1) 413, and changes the clock frequency, thereby changing the data processing logic unit 210. Performance adjustment is performed so that the data processing performance becomes equal to the target performance value. The performance adjustment logic unit (2) 416 controls the clock frequency conversion LSI (2) 502 based on the comparison result by the performance comparison logic unit (2) 414, and changes the clock frequency, thereby changing the data processing logic unit 310. Performance adjustment is performed so that the data processing performance becomes equal to the target performance value.

As described above, according to the present embodiment, the data processing performance of the data processing logic unit 210 and that of the data processing logic unit 310 are equalized, so that generation of unnecessary power consumption can be reduced.
[Example 3]
The data processing system according to the second embodiment needs to set a target performance value from the outside in order to perform performance control. However, as the third embodiment, the performance control logic unit detects a bottleneck in the data processing system and detects the target performance. A data processing system that has a function of setting a value and can perform performance control without setting a target performance value from the outside will be described.

FIG. 4 is a diagram illustrating a configuration example of a data processing system according to the third embodiment.
Here, since the configuration other than the LSI 600 is the same as that of the second embodiment, a description thereof will be omitted.

  The performance adjustment logic unit (1) 615 notifies the target performance setting logic unit 618 whether or not the performance adjustment logic unit (1) 615 suppresses the performance of the data processing logic unit 210. Similarly, the performance adjustment logic unit (2) 616 notifies the target performance setting logic unit 618 whether or not the performance adjustment logic unit (2) suppresses the performance of the data processing logic unit 310. The target performance setting logic unit 618 determines a target performance value for data processing and sets the target performance value in the target performance register 617.

  When neither the performance adjustment logic unit (1) 615 nor the performance adjustment logic unit (2) 616 performs performance suppression, the measurement performance value and measurement of the data processing logic unit 210 stored in the measurement performance register (1) 611 are measured. The measured performance value of the data processing logic unit 310 stored in the performance register (2) 612 is compared, and the smaller measured performance value is set in the target performance register 617.

  When the performance adjustment logic unit (1) 615 performs performance suppression and the performance adjustment logic unit (2) 616 does not suppress performance, the performance measurement value of the measurement performance register (2) 612 is stored in the target performance register 617. Set. On the contrary, when the performance adjustment logic unit (1) 615 is not performing performance suppression and the performance adjustment logic unit (2) 616 is performing performance suppression, the performance measurement of the measurement performance register (1) 611 is performed. A value is set in the target performance register 617.

  With the above operation, the target performance setting logic unit 618 performs performance adjustment so that the processing performances of the data processing logic unit 210 and the data processing logic unit 310 are equal. Further, the target performance setting logic unit 618, when both the performance adjustment logic unit (1) 615 and the performance adjustment logic unit (2) 616 perform performance suppression, sets the target performance value set in the target performance register 617. Increase the value gradually. At this time, as the target performance value increases, the data processing performance of the data processing logic unit 210 and the data processing logic unit 310 also increases, but the performance suppression of the performance adjustment logic unit 615 or the performance adjustment logic unit 616 disappears, When the performance of the corresponding data processing logic unit reaches the maximum, the increase of the target performance value is stopped. By this operation, while the data processing logic unit 210 and the data processing logic unit 310 repeatedly match the processing performance to the lower data processing performance, the data processing performance is prevented from decreasing indefinitely.

  As described above, according to the present embodiment, it is possible to detect the bottleneck of the data processing system and set the target performance value without setting the target performance value from the outside.

  In addition, since it is possible to perform LSI performance control with higher accuracy than when performance control is performed by software, the following effects can also be obtained.

  The power consumption of the CMOS LSI is proportional to the square of the clock frequency and the power supply voltage. Therefore, when the same amount of data processing is performed as shown in FIG. 5, the power consumption is reduced by performing the processing while suppressing the processing performance by reducing the clock frequency and the power supply voltage, rather than performing the processing in a short time. be able to. When processing a specific amount of data within a certain period of time, the processing performance of the LSI can be controlled with high accuracy in this embodiment, so that the processing performance is suppressed to the minimum that can be completed within the allowable time. It is possible to reduce power consumption effectively.

  Furthermore, in a data processing system composed of a plurality of data processing logic units operating in cooperation, unnecessary power consumption can be reduced by equalizing the processing performance of the plurality of data processing logic units. If there is a difference in data processing performance in a data processing system that consists of multiple data processing logics that operate in cooperation, the data processing logic unit with the lowest processing performance becomes the bottleneck, and the other data processing logic units It will operate with excessive processing performance. In this embodiment, by making the processing performance of the plurality of data processing logic units equal, the processing performance of the data processing logic unit operating with excessive processing performance can be suppressed, and unnecessary power consumption can be reduced.

  The present embodiment is also useful as a method for realizing COD (Capacity On Demand). The COD is equipped with a spare CPU in advance when it is difficult to predict the future load increase, or when it is desired to reduce the initial installation cost. This is a service for purchasing a license and activating a spare CPU. As an alternative, instead of mounting a spare CPU, a method of suppressing the CPU performance at the time of initial introduction and increasing the CPU performance by performance control as necessary can be considered. By applying the performance control in the present invention to the COD, it is possible to guarantee a certain processing performance when performing performance suppression.

  Note that the present invention is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

1 is a diagram illustrating a configuration example of a data processing system according to Embodiment 1. FIG. The figure for demonstrating operation | movement of performance adjustment. FIG. 5 is a diagram illustrating a configuration example of a data processing system according to a second embodiment. FIG. 10 is a diagram illustrating a configuration example of a data processing system according to a third embodiment. The figure for demonstrating the power consumption reduction effect.

Explanation of symbols

100: 200, 300, 400, 600: LSI, 121: Measurement performance register, 122: Target performance register, 123: Performance comparison logic unit, 124: Performance adjustment logic unit, 120, 410, 610: Performance control logic unit, 110 210: 310: Data processing logic unit 212: Performance measurement logic unit 618: Target performance setting logic unit

Claims (5)

In a data processing system having a data processing unit,
A first register that measures the processing performance of the data processing and stores the resulting measured performance value;
A second register for storing a target performance value, which is a target predetermined processing performance;
A performance comparison unit that compares the measured performance value stored in the first register with the target performance value stored in the second register;
A data processing system comprising: a performance adjustment unit that adjusts the processing performance of the data processing according to a comparison result of the performance comparison unit.   2. The data processing system according to claim 1, further comprising an input interface for setting the target performance value in the second register.   2. The data according to claim 1, wherein the performance adjustment unit controls the measured performance values of the plurality of data processing units to be equal to the predetermined target performance value stored in the second register. Processing system.   A comparison unit that compares the measurement performance values of a plurality of the data processing units, and storing the lowest measurement performance value among the comparison results by the comparison unit in the second register as the target performance value; 2. A data processing system according to claim 1, wherein: A clock generator for generating a clock;
A clock frequency conversion unit that converts the frequency of the clock generated by the clock generation unit,
The data processing system according to claim 1, wherein the performance adjustment unit variably controls the clock frequency converted by the clock frequency conversion unit.

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