JP2014186522A - Calculation system, and power management method therein - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a calculation system capable of achieving higher processing performance than that when operating whole processing elements, and to provide a power management method therein.SOLUTION: A calculation system includes: a plurality of processing elements; a first setup unit (S503) that sets a frequency and a power voltage of at least one processing element in the plurality of processing element on the basis of a power of the processing element; and a second setup unit (S504) that sets the number of operation processing elements on the basis of a frequency, the power voltage and a restricted power.

Description

  The present invention relates to a calculation system and its power management method.

  The performance of massively parallel high-performance computing systems (so-called supercomputers) is increasing year by year due to the increased use of large-scale parallel simulation in various fields such as industry and basic science. Among various problems for increasing the scale of such a calculation system is reduction of power consumption. Although the computing performance of a CPU (Central Processing Unit) is increasing, the computing system is becoming unable to deliver the processing performance due to power consumption restrictions of the computing system. It is also important to maximize job execution efficiency under given power consumption constraints as well as to reduce power consumption of computing systems.

  In a server or a data center, as a technique for executing a job within a range that does not exceed the power consumption limitation of a system composed of a large number of CPUs, as a technique on the CPU side, a DFS (Dynamic Frequency) that dynamically adjusts a frequency is used. Scaling) and DVFS (Dynamic Voltage and Frequency Scaling) technology for controlling the voltage according to the frequency are known. In addition, a power capping technology that sets an upper limit of power consumption in a register in the CPU and autonomously protects the setting, or a clock used for rapid power consumption reduction when the power exceeds the upper limit with the power capping technology A technique of Throttling (forcing frequency reduction by masking a clock pulse) is known. Also known is the technology of Pipeline Throttling (forcibly reducing the amount of instruction processing due to instruction issue restrictions, memory access restrictions, etc.).

  The power management technology on the system side determines a power consumption allocation value for each active CPU based on the settings if the system power constraint, power management policy, power management mode, etc. are set separately. Each CPU controls the CPU power by using the above-described CPU power management technology so as to keep the assigned value, thereby keeping the power consumption constraint of the entire system.

  A parallel computing device having at least one arithmetic unit and a control unit is known (see, for example, Patent Document 1). The arithmetic units process tasks whose number varies depending on the processing timing and whose processing time is constant. The control unit controls the number of arithmetic units used for task processing and the operating frequency of the arithmetic units to be used, with the processing capability of the entire arithmetic unit being constant.

  In addition, a method of proactive power management in a parallel computer is known (see, for example, Patent Document 2). The parallel computer includes a service node and a plurality of calculation nodes. The service node is connected to the compute node via an out-of-band service network. Each compute node includes a computer processor and computer memory operably coupled to the computer processor.

JP 2006-190104 A JP 2010-537266 Gazette

In a parallel processing program, there are a portion that can be parallelized and a sequential processing portion that cannot be parallelized. The processing time T of the parallel processing program can be roughly expressed as the following equation. Here, Cp is the total number of cycles of the parallel processing part. Cs is the total number of cycles in the sequential processing portion. Fp is the clock frequency of the parallel processing part. Fs is the clock frequency of the sequential processing part. PL is a parallel number.
T = Cp / (Fp × PL) + Cs / Fs

  Thus, since the processing time T of the parallel processing program is separated between the parallel processing portion and the sequential processing portion, the effect of increasing the speed of the parallel processing portion and the effect of increasing the speed of the sequential processing portion can be considered independently. . Since the sequential processing portion has one operating CPU, it can be speeded up by clock frequency and voltage control using DVFS. However, there is room for improvement in speeding up the parallel processing portion of the processing of the parallel processing program.

  An object of the present invention is to provide a computing system and a power management method thereof that can achieve higher processing performance than when all the processing elements are operated.

  The calculation system includes a plurality of processing elements, a first setting unit that sets a frequency and a power supply voltage of the processing element based on power of at least one of the plurality of processing elements, and the frequency And a second setting unit for setting the number of operation of the processing element based on the power supply voltage and the restricted power.

  By setting the number of operation of the processing elements in addition to the frequency and power supply voltage of the processing elements, higher processing performance can be achieved than when all the processing elements are operated.

FIG. 1 is a diagram illustrating a configuration example of a calculation system according to the present embodiment. FIG. 2 is a graph showing the leakage current of the transistor. FIG. 3 is a graph showing an example of the clock frequency and the delay time. FIG. 4 is a graph showing the number of operating processing elements and the performance of the computing system. FIG. 5 is a flowchart showing a power management method of the computing system. 6A and 6B are diagrams for explaining the processing subject in FIG. FIG. 7 is a diagram illustrating a configuration example of the optimum frequency derivation table in FIG. FIG. 8 is a graph showing the variation of the optimum operating point according to the non-operating power of the processing element. FIG. 9 is a diagram illustrating a configuration example of a CPU of a multi-core processor. FIG. 10 is a diagram illustrating a configuration example of a CPU having a buffer full rate detection circuit. FIG. 11 is a flowchart illustrating a processing example of the power management controller. FIG. 12 is a graph for explaining the effect of the present embodiment. FIG. 13 is a diagram showing an example of the optimum frequency derivation table in FIG.

  FIG. 1 is a diagram illustrating a configuration example of a calculation system according to the present embodiment. In the computing system 100, a plurality of processing elements (PE) 101 are connected to a network 104. Each processing element 101 is a processing element that performs processing, and includes a central processing unit (CPU) 102 for arithmetic processing and a local memory 103 connected to the CPU 102. The computing system 100 may be composed of a single rack or a plurality of racks. In the case of a configuration of a plurality of racks, the network 104 between the processing elements 101 includes an intra-rack network and an inter-rack network.

  In the computing system 100, a parallel processable portion that occupies most of the entire processing of the parallel processing program to be processed is divided into a plurality of subtasks having similar processing by parallel programming, a parallelizing compiler, or the like. These subtasks are assigned to each processing element 101 at the time of program execution (or each processor core in the processing element 101 when the processing element 101 is a multi-core processor), loaded into the corresponding processing element 101 at the time of execution, and then parallelized. To be executed. Each parallel processing program may be processed by the entire computing system 100 depending on the scale of the task, or may be executed by one of the entire computing system 100 partitioned into several parts. In the latter case, the power consumption constraint value of the entire computing system 100 is distributed to each partition as the power consumption constraint of the partition based on some policy. Since the parallel processing program processed in each partition is executed so as to satisfy the power consumption constraint assigned to the partition that processes the job, even in this case, the power constraint of each partition of the calculation system 100 is calculated. This is considered a power constraint of the system 100.

  The parallel processing part of the parallel processing program has a parallel number sufficiently larger than the number of processing elements 101. The number of divisions (number of subtasks) of the parallel processing portion is parameterized in advance when the parallel processing program is created, or can be easily changed by compiling with the parallel number specifying the parallel number. In addition, the amount of change in communication time between processing elements 101 such as subtask assignment and communication between subtasks by adjusting the number of parallel executions is small enough to be ignored compared to the overall processing time of each parallel execution processing element 101. To do.

The power consumption Pa per processing element 101 is expressed as follows: the average operating rate per clock signal of all the gates in the CPU 102 is α, the total capacity involved in switching of wiring and elements is C, the power supply voltage of the CPU 102 is V, When the leak current is Ik and the clock frequency (operating frequency) of the CPU 102 is f, it can be expressed as the following equation (1). Here, Pb is fixed power of the CPU 102, and Pc is memory-related power.
Pa = α × C × V ² × f + Ik × V + Pb + Pc (1)

  The memory-related power Pc is the power consumption of the local memory 103 itself and the power consumption for data transfer between the CPU 102 and the local memory 103 and correlates with the frequency of memory access. The fixed power Pb of the CPU 102 represents a power component that is consumed by a certain amount regardless of the clock frequency in the semiconductor chip, such as an analog macro or serial I / O that is separately supplied with power in the CPU 102.

FIG. 2 is a graph showing the leakage current Ik of the transistor. The horizontal axis represents the drain-source voltage Vds. The vertical axis represents the drain-source current Ids. When the voltage Vds increases due to the DIBL (Drain Induced Barrier Lowering) effect or the like, the threshold voltage Vth decreases and the leakage current Ik increases. The curve of the leakage current Ik can be approximated with a polynomial having a positive coefficient of about 2 to 3 in a narrow range that can be varied during the operation of the transistor. For example, the leakage current Ik can be approximated to the quadratic curve 201 as in the following equation. Here, the voltage Vds is, for example, the power supply voltage V, and a and b are constants.
Ik = a × V ² + b

FIG. 3 is a graph showing an example of the clock frequency 301 and the delay time 302. The horizontal axis indicates the power supply voltage V. When the power supply voltage V increases, the switching performance of the element increases, so that the delay time 301 decreases and the clock frequency 302 increases. On the contrary, when the power supply voltage V is lowered, the switching performance of the element is lowered, and when the power supply voltage V is lower than the threshold voltage Vth, the element becomes difficult to operate. With respect to the relationship between the power supply voltage V and the clock frequency f, the power supply voltage V becomes a monotonically increasing function of the clock frequency f with the threshold voltage Vth as an intercept. Become. Here, γ is a constant.
V = γ × f + Vth

When the frequency f of the clock signal of the CPU 102 to which the local memory 103 is connected increases, the memory access frequency also increases due to an increase in internal processing speed. Therefore, the memory-related power Pc is given by a fixed value P0m Can be modeled as a linear increase in clock frequency f.
Pc = P0m + f × Pm

In consideration of such a relationship, when the above equation (1) is arranged with respect to the clock frequency f, it can be approximated as a positive coefficient polynomial as the following equation. Here, C ₀ , C ₁ , C ₂ , and C ₃ are positive real numbers.

Pa = α × C × V ² × f + Ik × V + Pb + Pc
= {Α × C × V ² × f + Ik × V} + {P0m + f × Pm} + Pb
= Α × C × (γ × f + Vth) ² × f + (a × V ² + b) × V + P0m + f × Pm + Pb
= Α × C × (γ × f + Vth) ² × f + (a × (γ × f + Vth) ² + b) × (γ × f + Vth) + P0m + f × pm + Pb
= (Α × C × γ ² + a × γ ³ ) × f ³ + (2 × α × C × γ × Vth + 3 × a × γ ² × Vth) × f ² +.
= C ₀ × f ³ + C ₁ × f ² + C ₂ × f + C ₃

  Since the performance of the single processing element 101 is proportional to the clock frequency f, the performance of the entire computing system 100 during parallel processing is the product N × f of the number N of processing elements 101 performing parallel processing and the clock frequency f. It can be regarded as proportional. Here, assuming that the power of the computing system 100 is Ps and the power of the processing element 101 is Pp, in order to maximize performance under the power constraint of the computing system 100, Ps = N so as not to generate surplus power. The number N of processing elements, the power supply voltage V, and the clock frequency f are adjusted so as to be × Pp. The performance Gs of the calculation system 100 at this time is expressed by the following equation (2).

Gs∝N × f = f × Ps / Pp
_{= F × Ps / (C 0} × f 3 + C 1 × f 2 + C 2 × f + C 3)
= Ps / (C ₀ × f ² + C ₁ × f + C ₂ + C ₃ / f) (2)

FIG. 4 is a graph showing the number of operations N of the processing element 101 in Expression (2) and the processing performance Gs of the calculation system 100. The horizontal axis indicates the clock frequency f of the CPU 102. As shown in Expression (2), the performance Gs of the calculation system 100 is expressed as a function of the clock frequency f, and becomes a curve having one maximum point 401 when f> 0. The description so far is a model in which the power consumption of the processing element 101 that has become non-operating in the computing system 100 is regarded as almost zero. Next, consider a case where the power of the processing element 101 during non-operation is not zero. When the non-operating power of the processing element 101 is C ₄ and N out of the number M of all processing elements 101 in the computing system 100 is operating, the performance Ms of the above equation (2) is expressed by the following equation (3) become that way.
Gs∝N × f = (Ps−C ₄ × M) / {C ₀ × f ² + C ₁ × f + C ₂ + (C ₃ -C ₄ ) / f} (3)

The number N of optimum processing elements 101 after the power Pp1 of the optimum processing element 101 during operation is derived is obtained by the following equation.
N = (Ps−M × C ₄ ) / (Pp 1 −C ₄ ) (4)

Also in this case, the numerator of the equation (4) is a fixed value, and the denominator of the equation (4) has the same form as the equation (2). As shown in FIG. Here, if it is considered that the clock signal stops when not in operation, it can be considered that C ₃ ≧ C _4, and therefore the 1 / f coefficient can also be considered positive.

  From this, under the power consumption constraint of the computing system 100, there exists an optimum value of the clock frequency f that maximizes the performance Gs of the computing system 100, the corresponding power supply voltage V, and the number N of processing elements 101, It can be seen that using all possible processing elements 101 does not necessarily lead to maximizing the performance Gs of the computing system 100.

In the high-performance massively parallel computing system 100, serial transfer using a high-speed input / output (I / O) control circuit that consumes a large amount of power as communication between processing elements 101 in order to suppress a decrease in processing performance due to communication between processing elements 101. Can be used. In this case, regardless of whether the input / output control circuit is accessed, a large amount of power is constantly consumed, and the power consumption type fixed power component of the processing element 101 is very large. The optimum point of the performance Gs in the equation (2) is that the fixed power component C ₃ of the processing element 101 in FIG. 4 becomes larger in FIG. 4 due to the nature of the equation, the larger the clock frequency f (the smaller the number N of processing elements 101). Move on. For this reason, the processing element 101 having such a large fixed power component C ₃ reduces the number N of operating processing elements 101 to be operated rather than operating all the processing elements 101 and raises the power supply voltage V and the clock frequency f accordingly. In many cases, the performance Gs of the entire computing system 100 becomes higher.

Further, as can be seen from the equation (2), the maximum performance point 401 in the characteristic graph of FIG. 4 is such that C ₀ and C ₁ are large (the power consumption of the program to be executed is large) and the clock frequency f is low (processing). Move to the side where the number N of elements 101 is large. Thus, it can be seen that the optimum operating point 401 varies depending on the power consumption of the program to be executed.

  In the present embodiment, the performance Gs of the computing system 100 is maximized by adjusting the number N of processing elements 101 to be operated, the clock frequency f, and the power supply voltage V based on the operating point 401.

  FIG. 5 is a flowchart showing a power management method of the computing system 100. The processing in FIG. 5 includes processing information acquisition processing of the processing element 101 in step 511, performance maximization processing element number and operation condition calculation processing in step S512, operation condition setting processing in step S505, and parallel processing program in step S506. Execution processing. Step S511 includes steps S501 and S502. Step S512 includes steps S503 and S504.

  FIG. 6A is a diagram for explaining the processing subject of FIG. The computing system 100 has a plurality of CPUs 102. Each CPU 102 is a multi-core processor having a plurality of arithmetic cores 601. One computation core 601 in one CPU 102 performs the processing of FIG. 5 by executing a program, inputs information 603 from each CPU 102, and supplies the power supply voltage V and clock frequency f to each CPU 102. A control signal 602 for setting is output. One processing element 101 may perform the processing of FIG. In this case, the processing element 101 that performs the processing of FIG. 5 communicates with the other processing elements 101 via the network 104 of FIG.

  FIG. 6B is a diagram for explaining another processing subject of FIG. The computing system 100 includes a power management controller 611 in addition to the plurality of CPUs 102. The power management controller 611 performs the processing of FIG. 5 by executing a program, inputs information 603 from each CPU 102, and receives a control signal 602 for setting the power supply voltage V, the clock frequency f, and the like for each CPU 102. Output. In this case, the power management controller 611 communicates with the processing element 101 via a network different from the network 104 in FIG. Hereinafter, an example in which the power management controller 611 performs the process of FIG. 5 will be described.

  All the processing elements 101 to be operated are set to the same clock frequency f in order to align the processing time of each parallel task. The power supply voltage V may be the same for all the processing elements 101, or may be adjusted according to the process variation for each processing element 101.

  The power consumption of the processing element 101, particularly the power of the CPU 102, includes dynamic power and leak power. The leakage power is treated as a known fixed value on the assumption that the calculation system 100 is temperature-controlled at a low temperature by water cooling or the like and operates in a region where the fluctuation of the leakage power is small. The processing element 101 has a function of recording operation information of each internal unit during operation and calculating its own power consumption (dynamic power) based on the operation information.

  The power management controller 611 obtains the following three parameters for a plurality of operating loads with different power consumption of the processing element 101 under the same clock frequency f.

(1) Dynamic power of the processing element 101 when the load is processed under a specific reference frequency (2) Optimal frequency at the load (optimum operating point 401 in FIG. 4)
(3) The power of the processing element 101 when the frequency is changed to the optimum frequency of (2) with the load

  FIG. 7 is a diagram showing a configuration example of the optimum frequency derivation table 521 in FIG. The optimum frequency derivation table 521 is stored in the power management controller 611, for example. The optimum frequency derivation table 521 shows the dynamic power values P1 to Pm of the processing element 101 when executed at the specified frequency, the optimum performance frequencies F1 to Fm at that time, the optimum performance frequencies F1 to Fm and the corresponding power supply voltage V1. It has the electric power P1a-Pma after a change at the time of using -Vm. The optimum frequency derivation table 521 is created in advance.

  Since the information of (1) to (3) above can be obtained if the power and frequency characteristics of the processing element 101 are known, for example, power consumption analysis using design data at the time of design, The optimum frequency derivation table 521 can be obtained before assembling the calculation system 100 by measuring the actual machine of the processing element 101 alone.

  The optimum frequency derivation table 521 sorts the entries in advance according to the dynamic powers P1 to Pm for a search process to be described later. Since the optimal frequency derivation table 521 is created with a value determined by the f / Pp portion of Gs∝f × Ps / Pp in the equation (2), even when the parallel processing program is processed by the entire computing system 100, The same optimum frequency derivation table 521 can be used even when processing is performed on a partitioned part.

  The parallel processing program to be executed is created (compiled) by parameterizing N so that the number N of parallel executions can be designated at the time of execution before the processing of FIG. 5 is started, or all processing elements assigned to the processing of this program The number of parallels is equal to or smaller than the number M of 101 and is precompiled by a parallelizing compiler.

  First, in step S501, the power management controller 611 causes each processing element 101 to test-execute a parallel processing program for acquiring power information. This process is executed at a sufficiently low frequency so that the power consumption does not exceed the power limit of the computing system 100, and is executed for a time sufficient to acquire the steady state characteristics.

  Next, in step S <b> 502, the power management controller 611 obtains steady dynamic power Pd of the parallel processing portion of the one or more processing elements 101. For the parallel processing portion, the parallel processing program is executed for a length sufficient to acquire steady dynamic power, and then the dynamic power Pd of the processing element 101 at that time is acquired.

  There may be one processing element 101 for acquiring the dynamic power Pd. When considering the variation in the dynamic power Pd, the dynamic power Pd is acquired from the plurality of processing elements 101, and the average processing is performed. The dynamic power Pd may be obtained.

  Also, the processing element 101 alone may acquire a plurality of dynamic powers Pd by preparing a plurality of registers for holding the steady state dynamic powers Pd for different periods. The power management controller 611 uses the average dynamic power Pd based on the obtained plurality of dynamic powers Pd.

  Further, the power management controller 611 may obtain the dynamic power Pd corresponding to, for example, “average + 1σ” in consideration of dispersion by statistical processing.

In addition, a coefficient α for taking into account the effect that multiple processing elements 101 are simultaneously operated to reduce variation by overlapping them may be introduced, and dynamic power Pd calculated by the following equation may be used.
Pd = average power value + (maximum power−average power) × α

  Next, the performance maximizing processing element number and operation condition calculation process in step S512 will be described.

In step S503, the power management controller 611 searches the optimum frequency derivation table 521 based on the obtained dynamic power Pd, and obtains the optimum frequency f for the parallel processing program. For example, using the optimum frequency derivation table 521 in FIG. 7, when the dynamic power is P1, the optimum frequency is F1. When the obtained dynamic power Pd is between the dynamic power P (i) of the i-th entry and the dynamic power P (i + 1) of the i + 1-th entry in the optimum frequency derivation table 521 of FIG. 611 uses the optimal frequency F (i) of the i-th entry and the optimal frequency F (i + 1) of the i + 1-th entry to derive the optimal frequency f by the following linear interpolation.
f = F (i) + {F (i + 1) -F (i)} * {Pd-P (i)} / {P (i + 1) + P (i)}

  Further, the power management controller 611 obtains the optimum power supply voltage V corresponding to the optimum frequency f. The optimum power supply voltage V is a power supply voltage that allows the CPU 102 to operate normally at the optimum frequency f.

  Next, in step S504, the power management controller 611 uses the optimum frequency derivation table 521 in FIG. 7 to change the power of the processing element 101 during the operation of the obtained optimum frequency f and optimum power supply voltage V to the changed power P1a˜ Obtained as Pma. Also in this case, the power management controller 611 obtains the changed powers P1a to Pma by linear interpolation as in the derivation of the optimum frequency f.

Next, the power management controller 611 is based on the constraint power Ps of the computing system 100, the changed power Pp (P1a to Pma) at the optimal operation, the total number of processing elements M, and the non-operating power C ₄ of the processing element 101. Using the equation (4), the optimum operation processing element number N is derived by the following equation.
N = (Ps−C ₄ × M) / (Pp−C ₄ )

  Here, when the optimum operation processing element number N is larger than the total processing element number M, the optimum operation processing element number N is set to M. In that case, each processing element 101 is operated with power of Ps / M. In this control, the test execution similar to the processing of step S511 is performed, and the optimum frequency f and the optimum power supply voltage V at which the dynamic power Pd to be acquired becomes Ps / M while changing the combination of the optimum frequency f and the optimum power supply voltage V. You can find a combination of the above, or set the restricted power Ps / M to each processing element 101 as in the Power Capping method, and let each processing element 101 operate autonomously so that it operates below the set power. May be.

  Next, in step S505, the power management controller 611 determines the processing element 101 to be operated based on the above-mentioned optimal operation processing element number N, and sets the optimal frequency f and the optimal power supply voltage V of the processing element 101 to be operated. To do. In addition, the power management controller 611 notifies the optimum operation processing element number N to a process for scheduling a parallel task such as an operating system (OS). If the task to be executed is compiled with a fixed number of parallel executions, the power management controller 611 uses the parallelizing compiler as the target task in this processing, sets the parallel number as the optimum operation processing element number N, and sets the target task. Recompile. In the case of a program created by parameterizing the parallel number of tasks, the power management controller 611 sets the parallel number at the time of execution to the optimum operation processing element number N.

  Next, in step S506, the power management controller 611 causes each processing element 101 to execute the target parallel processing program based on the operation condition setting in step S505.

FIG. 8 is a graph showing the variation of the optimum operating point according to the non-operating power C ₄ of the processing element 101. The performance 801 of the computing system 100 is a performance when the non-operating power C ₄ of the processing element 101 is large, and has an optimum operating point 802. The performance 803 of the computing system 100 is a performance when the non-operating power C ₄ of the processing element 101 is small, and has an optimum operating point 804.

As can be seen from equation (3), when the value of the non-operating power C ₄ of the processing element 101 changes, the coefficient C ₄ -C ₃ of the denominator 1 / f changes, and therefore the performance of the computing system 100 is optimal. The fluctuating frequency also varies. That is, when the processing element 101 has a plurality of low power modes with different power consumption at the time of suspension, the optimum operating point 802 or 804 changes depending on which low power mode the suspended processing element 101 is made to stand by. . Therefore, when the processing element 101 has a plurality of low power modes with different power during rest, the optimum frequency derivation table 521 of FIG. 7 is prepared for each low power mode, and the low power mode setting of the computing system 100 By switching the optimum frequency derivation table 521 to be used, it is possible to cope with a case where the resting power has different modes.

  FIG. 9 is a diagram illustrating a configuration example of the CPU 102 of the multi-core processor. The CPU 102 is a multi-core processor and has a plurality of arithmetic cores 601. The CPU 102 includes a shared cache memory 901, a memory control circuit 902, and an input / output (I / O) control circuit 903. Each arithmetic core 601 outputs a command CMD and inputs / outputs data DT to the memory control circuit 902 via the shared cache memory 901. Further, each arithmetic core 601 outputs a command CMD to the input / output control circuit 903 via the shared cache memory 901 and inputs / outputs data DT. The memory control circuit 902 has an internal buffer, controls reading / writing of data to / from the local memory 103, and outputs a busy signal MBSY when the internal buffer becomes full. The input / output control circuit 903 has an internal buffer, performs input / output control of data with respect to the network 104, and outputs a busy signal IBSY when the internal buffer becomes full.

  The calculation system 100 in the above description is considered as the multi-core CPU 102, the processing element 101 in the above description is considered as the arithmetic core 601, the scale is reduced, and the above formulas are applied. In that case, since the arithmetic core 601 has almost no power component that does not depend on the frequency f and the power supply voltage V corresponding to the fixed power in Expression (1), the fixed power is 0 with the performance Gs in Expressions (2) and (3). Therefore, it can be understood that the performance per power is highest when all the arithmetic cores 601 in the processing element 101 are used. That is, if the frequency f is lowered and a larger amount of the processing element 101 is operated, the overall performance is improved. Therefore, when the processing element 101 is a multi-core processor, the performance is maximized by operating all the arithmetic cores 601 in the processing element 101 and determining the number N of processing elements 101 in this embodiment. it can. As a result, even when the processing element 101 is a multi-core processor, the performance can be maximized.

  In the description so far, the performance Gs has been performed on the assumption that it is proportional to N × f. However, in the case of processing with many memory accesses, for example, even if the frequency f is increased, waiting for memory access processing becomes a bottleneck, and no matter how much the frequency f is increased, the actual processing performance does not increase. The premise of xf may be broken. Typical examples are the memory control circuit 902 and the input / output control circuit 903 of the CPU 102. Since these control circuits 902 and 903 have a maximum bandwidth and communication latency determined by the specifications, no matter how much the internal frequency f of the CPU 102 is increased, it will not be faster. When the optimum frequency f obtained by the present embodiment is in a region where performance degradation due to memory access or input / output access is large, the maximum performance cannot be achieved and wasted power that does not lead to performance improvement. Will be consumed. As a countermeasure against such a case, as described below, performance degradation due to memory access or input / output access is detected, and a mechanism that does not increase the frequency unnecessarily is included to suppress power consumption. Suppressing unnecessary power consumption leads to reduction of electricity bills and failure rate. When the computer system 100 is partitioned and a plurality of jobs are executed, the power consumption surplus generated by this mechanism is converted into the power constraint value of the job being processed in another partition in the upper system control. In addition, it is possible to further improve the performance of the job in the other section.

  FIG. 10 is a diagram illustrating a configuration example of the CPU 102 having the buffer full rate detection circuit. The CPU 102 has a buffer full rate detection circuit. The buffer full rate detection circuit includes a clock counter 1001, a counter 1002, a divider 1003, and a buffer full rate register 1004, and detects the buffer full rate of the buffer of the memory control circuit 902. The count values of the clock counter 1001 and the counter 1002 are reset by the reset signal RS. The clock counter 1001 counts clock signals. The memory control circuit 902 outputs a busy signal MBSY when the internal buffer becomes full. The counter 1002 counts the busy signal MBSY from the memory control circuit 902. The divider 1003 divides the count value of the counter 1002 and the count value of the clock counter 1001 and outputs the division result as a buffer full rate. When the holding signal HLD is input, the buffer full rate register 1004 holds the buffer full rate output by the divider 1003. Although the method of detecting the buffer full rate of the memory control circuit 902 has been described, similarly, a buffer full rate detection circuit of the input / output control circuit 903 of FIG. 9 can be provided.

  As a circuit for detecting performance degradation due to memory access or input / output access, in the buffer of the memory control circuit 902 and input / output control circuit 903 in the CPU 102, the counter 1002 counts the number of clocks in which the buffer is full. The buffer full rate register 1004 holds the buffer full rate. The buffer full rate is the ratio of the number of clocks that become buffer full to the total number of execution clocks.

  FIG. 11 is a flowchart showing a processing example of the power management controller 611 for the CPU 102 in FIG. 10, which is processing performed after the optimum frequency is obtained in steps S511 and S512 in FIG. 5 and before step S506. This process may be executed by a sufficient number of processing elements 101 for sample acquisition, and need not be executed by all the processing elements 101.

  In step S1001, the power management controller 611 applies and cancels the reset signal RS, and resets the count values of the clock counter 1001 and the counter 1002.

  Next, in step S1002, the power management controller 611 operates the processing element 101 for a certain period (a period sufficient as a steady state).

  Next, in step S1003, the power management controller 611 stores the buffer full rate in the register 1004 by the holding signal HLD.

  In step S <b> 1003, the power management controller 611 reads the buffer full rate stored in the buffer full rate register 1004.

  Next, when the buffer full rate is smaller than the threshold value, the power management controller 611 considers that the memory bottleneck is negligible, and causes each processing element 101 to execute the process of step S506 in FIG. 5 at the set optimum frequency. .

  In addition, when the buffer full rate is larger than the threshold, the power management controller 611 acquires the buffer full rate in the same manner as described above while gradually decreasing the frequency from the optimum frequency. Then, the power management controller 611 sets the frequency at the time when the buffer full rate becomes smaller than the threshold, and performs the process of step S506 in FIG.

  With such control, parallel processing can be executed with appropriate power consumption without increasing the frequency unnecessarily when there is a memory bottleneck.

  As can be understood from the above description, in the case of an operation situation where the optimum number N of processing elements obtained from the performance characteristics of the computing system 100 is smaller than the total number M of processing elements in the computing system 100, all the processing elements 101 are operated. Sometimes, it is operating at an operating point that is not the optimum point 401 on the characteristic graph of FIG. Therefore, it can be seen that the performance is improved by using this embodiment by the amount corresponding to the difference between the performance at the operating point and the performance at the optimum operating point 401.

  FIG. 12 is a graph for explaining the effect of the present embodiment, and shows the performance 1201 and the number of active processing elements 1208 of the computing system 100. For example, assume that a parallel processing program having the characteristics shown in FIG. When the total number of processing elements 1206 of the computing system 100 is 17000, when all the 17000 processing elements 101 are operated, the computing system performance 1201 operates at the operating point 1202, and the computing system performance 1201 is 8.0 [a. u.]. On the other hand, the optimum operating point 1203 of the present embodiment has 12,500 active processing elements 1205 and a frequency 1204 of 1.6 [au]. When operated at the optimum operating point 1203 of the present embodiment, the computing system performance 1207 is 9.5 [au], which is about 19% of the performance 1209 with respect to the operating point 1202 in which all the processing elements are operated. Will be improved.

FIG. 13 is a diagram showing an example of the optimum frequency derivation table 521 in FIG. Hereinafter, a processing example using the optimum frequency derivation table 521 of FIG. 13 will be described with reference to FIG. For example, the total number M of processing elements is 17000, the calculation system constraint power is 950 kW, and the non-working processing element power C ₄ is 11 W.

  In step S <b> 501, the power management controller 611 first causes each processing element 101 to temporarily operate the parallel processing program at the frequency f and the power supply voltage V in the reference operation mode assumed in the optimum frequency derivation table 521.

  Next, in step S502, the power management controller 611 obtains steady dynamic power of the processing element 101 responsible for parallel processing. It is assumed that this dynamic power is 38W. As described above, this may be an average of a plurality of electric powers, or a correction value considering variation in electric power values.

Next, in step S503, the power management controller 611 obtains the optimum frequency when the dynamic power is 38 W, based on the optimum frequency derivation table 521 in FIG. In the optimum frequency derivation table 521 of FIG. 13, the second row is 36 W and the third row is 40 W. Therefore, the optimum frequency f is obtained by linear interpolation of the following equation.
f = 1.7 + (1.5-1.7) × (38-36) / (40-36)
= 1.6 [au]
Thereafter, the power management controller 611 derives the power supply voltage V corresponding to the optimum frequency f.

Next, in step S504, the power management controller 611 derives the changed power Pp of the processing element 101 by linear interpolation of the following equation based on the optimum frequency derivation table 521 of FIG.
Pp = 73 + (71−73) × (1.5−1.6) / (1.5−1.7)
= 72 [W]

Next, the power management controller 611 derives the optimum operation processing number N using Expression (4).
N = (950000-17000 × 11) / (72-11)
≒ 12500

  Next, in step S505, the power management controller 611 calculates the optimum frequency (= 1.6 [au]) obtained above, the power supply voltage corresponding to the optimum frequency, and the number of operating processing elements (≈12500). This is reflected in the setting of the system 100. Further, when the program parallel number setting is not 12,500, the power management controller 611 sets the parallel number to 12,500 by a method such as parameter setting and recompilation.

  Next, in step S506, the power management controller 611 causes each processing element 101 to execute a parallel processing program based on the setting of the computing system 100 and the parallel number setting performed as described above.

  Next, an example in which the processing element 101 has m operation modes shown in FIG. 7 will be described. Each of the m operation modes has a set of frequency and power supply voltage. For example, in the first operation mode, the frequency F1 and the power supply voltage V1 corresponding to the frequency F1 are set. In other words, the processing element 101 has a plurality of operation modes Mi defined as a set (Fi, Vi) of power supply voltages Vi that normally operate the CPU 102 at a plurality of different frequencies Fi. Here, i is a natural number. The operation mode can be set from a program that executes the processing of FIG. In this case, in step S503 in FIG. 5, one operation mode is selected from the plurality of operation modes Mi.

In step S503, the power management controller 611 refers to the optimum frequency derivation table 521 in FIG. 7 and derives the optimum frequency f by linear interpolation of the following equation using the obtained dynamic power Pd, similarly to the above. .
f = F (i) + {F (i + 1) -F (i)} * {Pd-P (i)} / {P (i + 1) -P (i)}

  Next, the power management controller 611 selects an operation mode Mi having a frequency Fi that is lower than the optimum frequency f and closest to the optimum frequency f as an operation mode, and sets the frequency Fi and the power supply voltage Vi of the selected operation mode Mi. .

  Next, in step S504, the power management controller 611 reads the changed power Pp of the processing element 101 at the frequency Fi and the power supply voltage Vi of the selected operation mode Mi with reference to the optimum frequency derivation table 521 of FIG. And the power management controller 611 calculates | requires the optimal operation processing element number N like the above based on the electric power Pp after the change.

  If the frequency f is a frequency between the frequency fi of the operation mode Mi and the frequency fi + 1 of the operation mode Mi + 1, which of the operation mode Mi and the operation mode Mi + 1 performs better depends on the characteristics. In some cases, it cannot be decided in advance. In the present embodiment, the operation mode on the lower frequency side is selected, the changed power Pp in the selected operation mode is read, and the total power does not exceed the constraint power of the calculation system 100. Since the actual power after the change is smaller than the changed power Pp because the operation is performed in the operation mode whose frequency is lower than the frequency f, the original optimum operation processing element number N is the operation obtained using the changed power Pp. It becomes larger than the number N of processing elements. Since the operation is performed with the number of operation processing elements slightly smaller than the optimal number of operation processing elements, the power of the computing system 100 does not exceed the constraint power. Thus, by obtaining the number N of operating processing elements based on the changed power Pp, the operation mode Mi and the number N of operating processing elements can be easily determined. If the steps of the frequencies F1 to Fm of the operation modes M1 to Mm are sufficiently fine, performance degradation due to simplification of processing is reduced.

  Next, another method will be described. For example, the changed power in the last column of the optimum frequency derivation table 521 in FIG. 7 is recorded separately for dynamic power and static power. Here, the changed power of each operation mode used for obtaining the optimum frequency by the above method is Ppo1, the changed dynamic power is Ppd1, and the changed static power is Pps1. In addition, the dynamic power in the target operation mode is Ppo2, the changed dynamic power is Ppd2, and the changed static power is Pps2.

In this case, the power Pp in the intended operation mode is derived from the following equation.
Pp = Ppo1 × Ppd2 / Ppo2 + Pps2

  The power Pp is obtained by correcting the original dynamic power Ppo1 using the dynamic power fluctuation ratio Ppd2 / Ppo2 after the change in the target operation mode, so that the power accuracy is more accurate than the above-described simple derivation of the changed power. The number N of optimum operation processing elements with less waste can be obtained. Alternatively, the dynamic power conversion coefficient Ppd2 / Ppo2 may be obtained in advance and stored in a table.

In the above-described simple method, the operation mode with the smaller frequency is selected as the operation mode. However, in order to improve the accuracy of the processing element power as described above, the operation on both sides sandwiching the obtained frequency f is performed. Using the frequency Fi of the mode Mi, the performance Gs may be calculated by the following equation, and the operation mode with the higher performance may be selected.
Gs∝N × Fi

  Next, the effect of this embodiment will be described. Assume that the performance characteristics of the parallel operation portion when the computing system 100 executes the parallel processing program are as shown in FIG. The number of operating processing elements 1208 is adjusted so that the power consumption of the entire computing system 100 is maximized within a range that does not exceed the prescribed constraint power. The horizontal axis represents the clock frequency of the CPU 102. The calculation system performance 1201 is represented on the right vertical axis. The number of active processing elements 1208 is represented on the left vertical axis. The calculation system performance 1201 is a curve having one maximum point 203 with respect to the frequency f, as represented by Expression (3). The number of operating processing elements 1208 has a characteristic of decreasing as the frequency f increases, because the power consumption of the processing element 101 itself increases. In this embodiment, since the total number of processing elements 1206 of the calculation system 100 is 17000, the number of active processing elements 1208 is flat at 17000 on the left side of the graph exceeding the total number of processing elements 1206, and the corresponding calculation Since the system performance 1201 cannot increase the number of active processing elements 1208, the performance when the frequency f is lowered is drastically reduced.

  When all the processing elements 101 of the computing system 100 are operated, the frequency is 1.0 [a. u. In the vicinity, the operating point 1202 at which the frequency is maximum under the calculation system constrained power is obtained. On the other hand, in the present embodiment, since the optimum operating point 1203 obtained from the computing system performance 1201 is obtained in advance and tabulated in the optimum frequency derivation table 521, the computing system performance 1201 has a frequency 1204 of 1.6 [a .u.] near the operating point 1203. The computing system performance 1207 at the operating point 1203 of this embodiment is 8.0 [au] to 9.5 [au] with respect to the computing system performance at the operating point 1202 when all the processing elements are operating. This is an improvement of about 17%. At this time, the number of active processing elements 1208 decreases from 17000 to about 12000. From this, it can be seen that the performance of the computing system is improved by this embodiment.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

100 computing system 101 processing element 102 CPU
103 local memory 104 network

Claims (8)

Multiple processing elements,
A first setting unit configured to set a frequency and a power supply voltage of the processing element based on power of at least one processing element of the plurality of processing elements;
A calculation system comprising: a second setting unit that sets an operation number of the processing element based on the frequency, the power supply voltage, and the constraint power.   The calculation system according to claim 1, wherein the second setting unit sets the number of operation of the processing elements so that performance is higher than that of operating all of the plurality of processing elements.   The calculation system according to claim 1, wherein the first setting unit sets the frequency and the power supply voltage so that performance is maximized.   The said 1st setting part sets the said frequency and said power supply voltage of the group that performance becomes the maximum among the combinations of a some frequency and power supply voltage, The any one of Claims 1-3 characterized by the above-mentioned. The calculation system described in.   The second setting unit derives the power of the processing element based on the frequency and the power supply voltage, and sets the number of operation of the processing element based on the derived power of the processing element and the constraint power. The calculation system according to claim 1, wherein: At least one of the plurality of processing elements is
Memory,
A memory control circuit having a buffer and controlling the memory;
A detection circuit for detecting a full rate of the buffer;
The calculation system according to claim 1, wherein the first setting unit sets the frequency based on a full rate of the buffer. And a network connected to the plurality of processing elements,
At least one of the plurality of processing elements is
An input / output control circuit having a buffer and controlling input / output of the network;
A detection circuit for detecting a full rate of the buffer;
The calculation system according to claim 1, wherein the first setting unit sets the frequency based on a full rate of the buffer. A power management method for a computing system having a plurality of processing elements, comprising:
Based on the power of at least one processing element of the plurality of processing elements, the frequency and power supply voltage of the processing element are set,
A power management method for a computing system, wherein the number of operating processing elements is set based on the frequency, the power supply voltage, and the restricted power.

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