JP2014011167A - Group iii nitride-based compound semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a group III nitride-based compound semiconductor device and a manufacturing method of the same, which achieves formation of an electrode having etching resistance in less steps.SOLUTION: A group III nitride-based compound semiconductor device manufacturing method comprises: forming a metal layer S11 on an n-type layer 140, and subsequently forming a metal layer S12 on the metal layer S11 (metal layer formation process); performing a heat treatment in an oxygen-containing mixed gas atmosphere with a surface S12a of the metal layer S12 being exposed; and forming an oxide layer S13 by oxidizing the surface part of the metal layer S12 by the heat treatment (oxide layer formation process).

Description

  The present invention relates to a group III nitride compound semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to a group III nitride compound semiconductor device and a method for manufacturing the same, in which a good ohmic contact is made and the process is simplified.

  In a semiconductor device, it is preferable to make a good ohmic contact between the semiconductor and the electrode. This is because the contact resistance is reduced. Thereby, heat generation can be suppressed and energy saving can be achieved. Therefore, techniques for obtaining a suitable ohmic contact between the semiconductor and the electrode have been developed.

  For example, Patent Document 1 discloses a technique for forming a multilayer film including a Ti layer and an Al layer on an n-type contact layer in a light-emitting element (see paragraph [0009] and the like of Patent Document 1). Thereby, it is said that a good ohmic contact can be obtained (see paragraph [0012] of FIG. 1 and FIG. 1 etc.).

JP 7-45867 A

  By the way, in a semiconductor device, the periphery is generally covered with an insulating film. This is because the semiconductor device is protected from an external impact and an electrical load is prevented from being applied to the semiconductor. In the case where the semiconductor device is covered with an insulating film after the electrodes are formed, it is necessary to expose the electrodes from the insulating film. This is to establish electrical continuity with an external power source.

  In order to expose the electrode, the insulating film on the electrode may be removed by etching. However, in this case, not only the insulating film but also the underlying Al layer may be removed by etching. When the Al layer is deeply cut, the contact resistance between the semiconductor and the electrode increases.

  Therefore, a cover layer may be formed on the Al layer of the electrode. Examples of the cover layer include a case where a Ni layer and an Au layer are formed from the electrode side. This cover layer can prevent the Al layer from being removed by etching. However, this requires a separate cover layer forming step for forming the cover layer, which increases the number of steps.

  The present invention has been made to solve the above-described problems of the prior art. That is, an object of the present invention is to provide a group III nitride compound semiconductor device and a method for manufacturing the same, which are intended to produce an electrode having resistance to etching in a few steps.

  According to a first aspect of the present invention, there is provided a method of manufacturing a group III nitride compound semiconductor device comprising: a semiconductor forming step of forming a semiconductor layer made of a group III nitride compound semiconductor; and an electrode forming step of forming an electrode on the semiconductor layer. Have. The electrode forming step includes a metal layer forming step for forming two or more metal layers in the semiconductor layer, and a heat treatment step for performing a heat treatment after the metal layer forming step. The heat treatment step is performed in an oxygen-containing atmosphere with the surface of the outermost metal layer of the two or more metal layers exposed, thereby oxidizing the surface portion of the outermost metal layer. This is an oxide layer forming step for forming an oxide layer.

  In this group III nitride compound semiconductor device manufacturing method, an electrode having high etching resistance can be formed without forming a cover layer on the electrode layer. Therefore, the number of steps can be reduced and the cycle time can be shortened. Of course, a good ohmic contact can be obtained.

  In the Group III nitride compound semiconductor device manufacturing method according to the second aspect, the oxide layer forming step also serves as an ohmic alloy step for reducing the resistance between the electrode and the semiconductor layer. Since the oxide layer forming process also serves as an ohmic alloy process that is normally performed, the number of separate processes does not increase.

  In the oxide layer forming step of the method for manufacturing a Group III nitride compound semiconductor device according to the third aspect, a mixed gas of nitrogen and oxygen is used as the atmosphere, and the oxygen concentration in the mixed gas is 1% or more in terms of a flow rate ratio. . Thereby, a favorable oxide layer can be formed.

  In the method for manufacturing a Group III nitride compound semiconductor device according to the fourth aspect, the heat treatment temperature in the oxide layer forming step is 500 ° C. or higher and 650 ° C. or lower. Since the heat treatment temperature is not so high, there is almost no possibility that the formed semiconductor crystals deteriorate.

  In the metal layer forming step in the method for manufacturing a group III nitride compound semiconductor device according to the fifth aspect, the thickness of the outermost metal layer is in the range of not less than 300 nm and not more than 1000 nm. This is because good ohmic contact can be obtained.

In the manufacturing method of a group III nitride compound semiconductor device according to a sixth aspect, the outermost layer of the metal layer is a Al layer composed of Al, an oxide layer, in the Al ₂ O ₃ layer of Al ₂ O ₃ is there. This is because better ohmic contact can be obtained.

  In the metal layer forming step of the method for manufacturing a group III nitride compound semiconductor device according to the seventh aspect, two or more metal layers are formed on the n-type semiconductor layer. This is because better ohmic contact can be obtained.

  The group III nitride compound semiconductor device according to the eighth aspect includes a substrate, a semiconductor layer made of a group III nitride compound semiconductor formed on the substrate, and a plurality of electrodes formed on the semiconductor layer. Further, at least one of the electrodes includes two or more metal layers formed on the semiconductor layer and an oxide layer formed on the outermost metal layer of the two or more metal layers. And have. The oxide layer is made of an oxide obtained by oxidizing the metal of the outermost metal layer. Since this group III nitride compound semiconductor device has not undergone a high-temperature heat treatment step, the crystallinity of the semiconductor layer is hardly deteriorated by the heat treatment step.

In the group III nitride compound semiconductor device according to the ninth aspect, the outermost metal layer is a layer made of Al, and the oxide layer is a layer made of Al ₂ O ₃ . In this group III nitride compound semiconductor device, a good ohmic contact is obtained.

  In the group III nitride compound semiconductor device according to the tenth aspect, the thickness of the outermost metal layer is in the range of 300 nm to 1000 nm.

  In the group III nitride compound semiconductor device according to the eleventh aspect, two or more metal layers are formed on the n-type semiconductor layer.

In the group III nitride compound semiconductor device according to the twelfth aspect, the carrier concentration in the n-type semiconductor layer is in the range of 1 × 10 ¹⁶ cm ^{−3 to} 1 × 10 ²⁰ cm ⁻³ .

  According to the present invention, there are provided a group III nitride compound semiconductor device and a method for manufacturing the same, which are intended to produce an electrode resistant to etching in a small number of steps.

It is a schematic block diagram for demonstrating the structure of the group III nitride compound semiconductor device which concerns on 1st Embodiment. It is a figure for demonstrating the structure of the electrode of the group III nitride compound semiconductor device which concerns on embodiment. It is FIG. (1) for demonstrating the formation method of the electrode in the group III nitride compound semiconductor device which concerns on embodiment. It is FIG. (2) for demonstrating the formation method of the electrode in the group III nitride compound semiconductor device which concerns on embodiment. It is FIG. (3) for demonstrating the formation method of the electrode in the group III nitride compound semiconductor device which concerns on embodiment. It is a figure for demonstrating the structure of the electrode of the conventional group III nitride compound semiconductor device. It is a figure which shows the structure of the electrode of the laminated body which concerns on an Example. It is a figure which shows the structure of the electrode of the laminated body which concerns on a comparative example. It is a voltage-current curve (after heat processing process) of the laminated body which concerns on an Example. It is a voltage-current curve (after an electroconductive part formation process) of the laminated body which concerns on an Example. It is a voltage-current curve (after a washing process) of a layered product concerning an example. It is a voltage current curve (after a heat treatment process) of a layered product concerning a comparative example. It is a voltage-current curve (after an electroconductive part formation process) of the laminated body which concerns on a comparative example. It is a voltage-current curve (after a washing process) of a layered product concerning a comparative example. It is a schematic block diagram for demonstrating the structure of the group III nitride compound semiconductor device which concerns on 2nd Embodiment. It is a schematic block diagram for demonstrating the structure of the group III nitride compound semiconductor device which concerns on 3rd Embodiment.

  Hereinafter, specific embodiments will be described with reference to the drawings, taking a semiconductor device as an example. However, it is not limited to these embodiments. Also, the laminated structure and electrode structure of each layer of each semiconductor device described later are examples. Of course, a laminated structure different from that of the embodiment may be used. And the thickness of each layer in each figure is shown conceptually and does not indicate the actual thickness. In addition, the uneven shape in each figure is drawn large for easy understanding. However, in practice, these uneven shapes are very fine shapes.

(First embodiment)
1. Vertical Structure Semiconductor Device FIG. 1 shows a power element 100 according to this embodiment. The power element 100 is a semiconductor device having a vertical structure. The power element 100 includes a drain electrode D1 as shown on the lower side in FIG. 1, a gate electrode G1 and a source electrode S1 as shown on the upper side in FIG.

The power element 100 has a plurality of semiconductor layers made of a group III nitride compound semiconductor. In addition to the above electrodes, the power element 100 includes a substrate 110, an n-type layer 120, a p-type layer 130, an n-type layer 140, and an insulating film 150, as shown in FIG. Yes. The n-type layer 120 includes an n ⁺ GaN layer 121 and an n ⁻ GaN layer 122 in order from the substrate 110 side.

  The substrate 110 is for supporting the power element 100 and increasing the strength. It also serves as a growth substrate for growing the power element 100. As the substrate 110, for example, a GaN substrate can be used. In addition, a conductive substrate such as a Si substrate or a SiC substrate can be used.

  The source electrode S1 is in ohmic contact with the n-type layer 140. The source electrode S1 is obtained by forming a Ti layer from the n-type layer 140 side and an Al layer on the Ti layer. Further, other Al alloys can be used. Moreover, you may use Mo or Mo compound. Ti or Ti compounds may be used. Furthermore, W or a W compound can also be used.

  The drain electrode D1 is in ohmic contact with the substrate 110. The drain electrode D1 is obtained by forming a Ti layer from the substrate 110 side and an Al layer on the Ti layer. Further, other metals and compounds used for the source electrode S1 may be used.

  The gate electrode G <b> 1 is formed on the insulating film 150 and in the trench 160. The trench 160 is not V-shaped but rectangular. Therefore, the cross-sectional shape of the gate electrode G1 is also a rectangular shape. The gate electrode G1 is obtained by forming a Ni layer from the insulating film 150 side and an Au layer on the Ni layer. Alternatively, the Pd layer and the Au layer may be formed in this order. Other metals and compounds can also be used. Al can also be used.

The n type impurity concentration of the n ⁺ GaN layer 121 is higher than the n type impurity concentration of the n ⁻ GaN layer 122. The n ⁺ GaN layer 121 has an n-type impurity concentration of about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ . The n-type impurity concentration of the n ⁻ GaN layer 122 is about 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ .

The p-type layer 130 is a layer made of p-type GaN. The carrier concentration of the p-type layer 130 is about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ . The n-type layer 140 is a layer made of n-type GaN. The carrier concentration of the n-type layer 140 is in the range of 1 × 10 ¹⁶ cm ^{−3 to} 1 × 10 ²⁰ cm ⁻³ .

The insulating film 150 serves as both a gate insulating film and a protective film. The material of the insulating film 150 is SiO ₂ . SiN _x , Al ₂ O ₃ , HfO ₂ , ZrO ₂ , AlN, or the like may be used.

2. Electrode of Semiconductor Device The power element 100 of this embodiment is characterized by the structure of the source electrode S1 and the manufacturing method thereof. As shown in FIG. 2, the source electrode S1 includes a metal layer S11, a metal layer S12, an oxide layer S13, and an insulating film S14 (150). The formation order of each layer is metal layer S11, metal layer S12, and oxide layer S13 in order from n-type layer 140.

  A recess S15 is formed in the source electrode S1. The recess S15 is a non-through hole that penetrates the thickness of the insulating film S14 and the oxide layer S13 and partially exposes the metal layer S12. A conductive portion S16 is formed in the recess S15. The conductive portion S16 is for electrically connecting the source electrode S1 to the external power source of the power element 100.

  The metal layer S11 is a first electrode layer that is preferably in close contact with the source electrode S1. The material of the metal layer S11 is, for example, Ti. Or V may be sufficient. Further, other materials may be used. The thickness of the metal layer S11 is in the range of 10 nm to 100 nm.

  The metal layer S12 is a second electrode layer formed on the metal layer S11. The material of the metal layer S12 is, for example, Al. Further, other materials may be used. The metal layer S12 has a thickness in the range of 300 nm to 1000 nm.

The oxide layer S13 is a layer for suppressing etching of the metal layer S12 by covering the surface of the metal layer S12. The material of the oxide layer S13 is an oxide of the metal layer S12. For example, when the metal layer S12 is Al, the oxide layer S13 is Al ₂ O ₃ . As will be described later, the oxide layer S13 is formed by oxidizing the metal layer S12.

The insulating film S14 is a protective film that covers each semiconductor layer and the source electrode S1. However, the insulating film S14 does not cover only the recess S15. The material of the insulating film S14 is, for example, SiO ₂ . The thickness of the insulating film S14 is in the range of 200 nm to 1000 nm.

3. Next, a method for forming an electrode will be described. This electrode forming method is a method used to form the electrode described above. And it will actually be used in the electrode formation process mentioned later. The electrode forming step includes a metal layer forming step of forming two or more metal layers, and an oxide that forms an oxide layer by oxidizing the surface portion of the outermost metal layer of the two or more metal layers. And a layer forming step.

3-1. Metal layer forming step 3-1-1. First Metal Layer Formation Step First, the metal layer S11 is formed on the exposed n-type layer 140. Thereby, as shown in FIG. 3, a metal layer S <b> 11 is formed on the n-type layer 140.

3-1-2. Second Metal Layer Formation Step Next, a metal layer S12 is formed on the metal layer S11. Thereby, as shown in FIG. 4, the metal layer S11 and the metal layer S12 are formed in this order from the n-type layer 140 side. Here, the metal layer S12 is the outermost metal layer of the two or more metal layers. At this time, the surface S12a of the metal layer S12 is exposed. Here, the surface S12a is a surface opposite to the surface in contact with the metal layer S11. That is, the surface S12a is a surface opposite to the semiconductor layer side.

3-2. Oxide layer formation process (heat treatment process)
Subsequently, an oxide layer forming step is performed after the metal layer forming step. Specifically, heat treatment is performed in an atmosphere containing oxygen on the metal layers S11 and S12. At this time, it is performed with the surface S12a of the metal layer S12 exposed. By this heat treatment, the surface portion of the metal layer S12 is oxidized. Thereby, an oxide layer S13 as shown in FIG. 5 is formed. Of course, the material of the oxide layer S13 is an oxide of the metal layer S12. Thus, the single metal layer S12 becomes two layers of the metal layer S12 and the oxide layer S13.

  Table 1 shows the conditions for this heat treatment. As a gas to be supplied, a mixed gas of nitrogen and oxygen is used. Here, the oxygen concentration in the supply gas is in the range of 1% to 100% in terms of flow rate ratio. Here, the flow rate ratio is (volume of supplied oxygen) / (volume of the whole mixed gas to be supplied). However, it is not limited to this range. If the oxygen concentration is low, the metal layer S12 cannot be sufficiently oxidized. If the oxygen concentration is high, the metal layer S12 may be oxidized too much. In addition, another portion of the power element 100 may be oxidized. However, this is due to a balance with the processing time. The substrate temperature is in the range of 500 ° C. or higher and 650 ° C. or lower. The processing time is in the range of 5 seconds to 1000 seconds. These are merely examples, and values outside this range may be used.

[Table 1]
Type of supply gas Nitrogen and oxygen mixed gas Supply gas mixing ratio Oxygen concentration 1% to 100% (flow rate ratio)
Substrate temperature 500 ° C to 650 ° C Processing time 5 seconds to 1000 seconds

  This heat treatment process also serves as an ohmic alloy process for reducing the contact resistance between the source electrode S1 and the n-type layer 140.

4). Semiconductor Device Manufacturing Method Here, a semiconductor device manufacturing method will be described.

4-1. Semiconductor Layer Formation Step First, a semiconductor layer formation step is performed in which crystals of each semiconductor layer are epitaxially grown by metal organic chemical vapor deposition (MOCVD). Specifically, the n-type layer 120, the p-type layer 130, and the n-type layer 140 are formed on the substrate 110 in this order. Thus, a stacked body in which each semiconductor layer is formed on the substrate 110 is formed.

4-2. Uneven shape forming step Next, an uneven shape is formed in the semiconductor layer by etching. Thereby, the trapezoidal shape and the trench 160 shown in FIG. 1 are formed in a stripe shape. For this etching, for example, Cl ₂ can be used. Alternatively, other gases such as SiCl ₄ may be used. Alternatively, other dry etching or wet etching may be used.

4-3. Electrode formation process (source electrode)
Subsequently, an electrode forming step is performed. In this step, the above-described electrode forming method may be used. A source electrode S <b> 1 is formed on the n-type layer 140.

4-4. Insulating Film Formation Step Next, the insulating film 150 is formed. The formation location is the upper surface of FIG. An insulating film is not formed on the surface on which the drain electrode D1 is formed.

4-5. Conductive part forming step Etching is then performed using Cl ₂ . A portion other than the portion to be etched is covered with a mask, and Cl ₂ gas is supplied to the portion where the recess 15 is formed. Thereby, a part of insulating film S14 and oxide layer S13 is removed, and a part of metal layer S12 is exposed. As a result, a recess S15 is formed. Then, a metal layer is formed in the recess S15 to form a conduction part S16 as shown in FIG.

4-6. Electrode formation process (gate electrode, drain electrode)
Next, the gate electrode G1 and the drain electrode D1 are formed.

4-7. Cleaning Step Finally, wet etching is performed on the power element 100 using a BHF solution (NH ₄ F / HF / H ₂ 0). Thereby, the insulating film and the like remaining on the surface of the power element 100 are removed. Note that a DHF solution (dilute hydrofluoric acid) or an HCl solution may be used instead of the BHF solution.

5. Comparison with Conventional Example FIG. 6 illustrates a conventional electrode structure of a power element. In the conventional power element 400, a Ti layer 420, an Al layer 430, a Ni layer 440, and an Au layer 450 are formed in this order on the n-type layer 410. Here, the Ni layer 440 and the Au layer 450 are cover layers for preventing the Al layer 430 from being removed by etching. As described above, conventionally, it is necessary to provide an extra cover layer composed of a Ni layer and an Au layer as compared with the power element 100 of the present embodiment. That is, in this embodiment, the process of forming the cover layer can be omitted. Therefore, the cycle time in the method for manufacturing the power element 100 of the present embodiment is shorter than that in the case of the conventional method for manufacturing the power element.

6). Experiment Content Here, an experiment conducted on the laminates of the following examples and comparative examples will be described. A laminate is a substrate in which a semiconductor layer and electrodes are formed. And the following experiment was done with the laminated body of the Example mentioned later and the laminated body of a comparative example.
Experiment 1) Voltage-current curve after the heat treatment step In this experiment, the characteristics of the electrical resistance between the GaN layer and the electrode may be examined. Therefore, the measurement was performed not on the element but on the laminated body in which an electrode was formed on a GaN substrate described later.

6-1. Example laminate (with oxide layer forming step)
The laminated body 500 of an Example is shown in FIG. The stacked body 500 includes a GaN substrate 510, a Ti layer 520, an Al layer 530, and an Al ₂ O ₃ layer 540.

Here, the thickness of each layer is shown below. However, the thickness of the Al ₂ O ₃ layer 540 varies depending on various conditions such as the substrate temperature in the oxide layer forming step. In the example, the oxygen concentration in the process corresponding to the oxide layer forming process was set to 10% in flow rate ratio.
Ti layer 17.5nm
Al layer 295nm
Al ₂ O ₃ layer 5nm

  In the oxide layer forming step, oxygen was supplied at 0.2 slm and nitrogen was supplied at 2.0 slm under normal pressure. The heat treatment temperature was 550 ° C. The heat treatment time was 10 minutes.

6-2. Laminate of Comparative Example 1 (no oxide layer forming step)
FIG. 8 shows a laminate 600 of a comparative example. The stacked body 600 includes a GaN substrate 610, a Ti layer 620, and an Al layer 630. In the comparative example, the laminated body 600 was created by removing the process corresponding to the oxide layer forming process from the example. Therefore, the stacked body 600 does not have an Al ₂ O ₃ layer.

However, in order to improve ohmic properties, heat treatment with nitrogen gas is performed. This heat treatment is the same step as that in which oxygen gas is not mixed in the oxide layer forming step of the embodiment. In addition, the thickness of each layer is as follows.
Ti layer 17.5nm
Al layer 300nm

6-3. Experimental Results of Experiment 1 Next, experimental results will be described. FIG. 9 is a voltage-current curve after the oxide layer forming step in the stacked body 500 of the example. Here, the distance between the terminals is 5 μm. In FIG. 9, the horizontal axis represents voltage, and the vertical axis represents current. The current is normalized so that the current value when a voltage of 1 V is applied is “1”. The same applies to the following drawings. As shown in FIG. 9, in the laminated body 500, a good ohmic contact is obtained.

  FIG. 10 is a voltage-current curve after the conductive part forming step in the multilayer body 500 of the example. As shown in FIG. 10, the current flowing through the stacked body 500 of the example is almost the same as that in FIG. That is, the Al layer 530 is hardly etched by the oxide layer forming step. Therefore, the ohmic properties of the GaN substrate 510, the Ti layer 520, and the Al layer 530 remain good.

  FIG. 11 is a voltage-current curve after the cleaning process in the laminated body 500 of the example. As shown in FIG. 11, the current flowing through the stacked body 500 of the example is almost the same as that in FIG. As described above, the ohmic property is maintained well even in a wet environment. In addition, the ohmic properties of the GaN substrate 510, the Ti layer 520, and the Al layer 530 remain good throughout the manufacturing process.

  FIG. 12 is a voltage-current curve after the heat treatment step (ohmic alloy step) in the laminated body 600 of the comparative example. The current value in this case is the same as in FIG. Moreover, ohmic property is also favorable.

  FIG. 13 is a voltage-current curve after the conductive part forming step in the laminated body 600 of the comparative example. As shown in FIG. 13, the current flowing through the laminated body 600 of the comparative example is halved compared to the case of FIG. This is presumably because the Al layer 630 with ohmic contact has been removed too much by etching. Therefore, it is considered that the contact resistance is increased between the GaN substrate 610 and the Ti layer 620 and Al layer 630.

  FIG. 14 is a voltage-current curve after the cleaning process in the laminated body 600 of the comparative example. The current value (see FIG. 14) of the stacked body 600 after the cleaning process is substantially the same as the current value (see FIG. 13) of the stacked body 600 after the conductive portion forming process. Also in FIG. 14, as in FIG. 13, the current flowing in the laminated body 600 of the comparative example is halved compared to the case of FIG. 12.

As described above, the stacked body 500 in which the Al ₂ O ₃ layer 540 is formed has higher etching resistance than the stacked body 600. That is, an oxide layer forming step in which oxygen gas is mixed in the heat treatment step is preferably performed. Moreover, there is almost no possibility that the ohmic contact deteriorates in the subsequent steps.

7). Modification 7-1. Group III nitride compound semiconductor layer In this embodiment, the semiconductor layer is made of GaN. However, it may be a layer made of other group III nitride compound semiconductors such as AlGaN, InGaN, and AlInGaN. Of course, a layer made of these group III nitride compound semiconductors may be included in part.

7-2. Drain electrode and gate electrode The electrode forming method of this embodiment is applied to the source electrode S1. However, when the conductive portion as shown in FIG. 2 is formed according to the structure of the element, it can be applied to the drain electrode and the gate electrode.

7-3. p-Type Semiconductor Layer In this embodiment, the source electrode S1 is formed on the n-type layer 140, which is an n-type semiconductor layer. However, the present invention can also be applied to the case where an electrode is formed on a p-type semiconductor layer.

7-4. Number of laminated metal layers In this embodiment, the source electrode S1 has a two-layer structure of a metal layer S11 made of a Ti layer and a metal layer S12 made of an Al layer. However, three or more layers may be stacked. For example, the metal layer S11 is a metal layer having a two-layer structure in which a Pd layer and a Ti layer are sequentially formed from the n-type layer 140 side. In this case, a Pd layer, a Ti layer, and an Al layer are sequentially formed from the n-type layer 140 side.

7-5. Outermost Metal Layer In the present embodiment, the outermost metal layer S12 is an Al layer. However, metals other than Al may be used as long as they can be used as electrodes. In that case, a metal that forms an oxide by heat treatment in an atmosphere containing oxygen can be used.

8). Summary As described in detail above, in the method for manufacturing the power element 100 of the present embodiment, the metal layers S11 and S12 are formed on the n-type layer 140, and the surface S12a of the metal layer S12 is oxidized. As a result, the oxide layer S13 was formed. The material of the oxide layer S13 is an oxide of the metal layer S12. Therefore, the etching resistance of the metal layer S12 can be increased. Thereby, conduction | electrical_connection part S16 can be formed suitably. That is, there is almost no possibility of deteriorating the ohmic characteristics in the source electrode S1. Moreover, it is not necessary to form a cover layer.

  This embodiment is merely an example. Therefore, naturally, various improvements and modifications can be made without departing from the scope of the invention. In this embodiment, metal organic chemical vapor deposition (MOCVD) is used as the epitaxial growth method. However, vapor phase growth methods such as hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), pulsed sputter deposition (PSD), and liquid phase epitaxy may be used.

(Second Embodiment)
A second embodiment will be described. The semiconductor device of this embodiment is a power element 200 having a lateral structure. The electrode structure and the electrode formation method are the same as in the first embodiment. Therefore, only different parts will be described.

1. FIG. 15 shows a power device 200 having a horizontal structure. The power element 200 includes a substrate 210, a buffer layer 220, a first carrier traveling layer 230, a second carrier traveling layer 240, a carrier supply layer 250, an insulating film 260, a drain electrode D2, and a source electrode S2. And a gate electrode G2.

  As the substrate 210, a sapphire substrate, a SiC substrate, a ZnO substrate, a spinel substrate, or a GaN substrate can be used in addition to the Si substrate. As the buffer layer 220, a layer made of AlN or GaN is formed. Further, the buffer layer 220 is not necessarily formed.

The first carrier traveling layer 230 is a layer made of non-doped GaN. The second carrier traveling layer 240 is a layer made of, for example, GaN. The carrier supply layer 250 is a layer made of, for example, AlGaN. The carrier concentration of the carrier supply layer 250 is in the range of 1 × 10 ¹⁶ cm ^{−3 to} 1 × 10 ²⁰ cm ⁻³ .

  The second carrier traveling layer 240 and the carrier supply layer 250 are hetero bonds. The band gap of the carrier supply layer 250 is larger than the band gap of the second carrier traveling layer 240. Other group III nitride compound semiconductors may be used as long as these conditions are satisfied.

  For example, InGaN can be used for the second carrier transit layer 240 and GaN or AlGaN can be used for the carrier supply layer 250. Further, an n-type layer doped with an impurity such as Si may be used as the carrier supply layer 250. Further, a cap layer may be provided on the carrier supply layer 250. Further, the composition of the second carrier running layer 240 may be the same as that of the first carrier running layer 230. Of course, these compositions may be different.

  The electrode structure is as shown in FIG. However, in the present embodiment, the source electrode S2 and the drain electrode D2 are formed on the carrier supply layer 250. The gate electrode G <b> 2 is a part facing the recess 261 and is formed on the insulating film 260.

2. Manufacturing Method of Semiconductor Device When manufacturing the power element 200, a semiconductor layer is formed on the substrate 210 (semiconductor layer forming step). Then, using the mask, the recess 261 is formed, and the insulating film 260 is formed. Then, the source electrode S2 and the drain electrode D2 are formed on the carrier supply layer 250. Then, the gate electrode G2 is formed on the insulating film 260 (electrode formation process). That is, similarly to the first embodiment, the semiconductor forming process and the electrode forming process are included.

3. Modifications Also in the second embodiment, all the modification examples described in the first embodiment can be applied.

4). Summary As described in detail above, in the method for manufacturing the power element 200 of the present embodiment, the metal layers S11 and S12 are formed on the carrier supply layer 250, and the surface S12a of the metal layer S12 is oxidized. As a result, the oxide layer S13 was formed. The material of the oxide layer S13 is an oxide of the metal layer S12. Therefore, the etching resistance of the metal layer S12 can be increased. Thereby, conduction | electrical_connection part S16 can be formed suitably. That is, there is almost no possibility of deteriorating the ohmic characteristics in the source electrode S2. Moreover, it is not necessary to form a cover layer.

  This embodiment is merely an example. Therefore, naturally, various improvements and modifications can be made without departing from the scope of the invention. In this embodiment, metal organic chemical vapor deposition (MOCVD) is used as the epitaxial growth method. However, vapor phase growth methods such as hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), pulsed sputter deposition (PSD), and liquid phase epitaxy may be used.

(Third embodiment)
A third embodiment will be described. The semiconductor device of this embodiment is a light emitting element 300. The electrode structure and the electrode formation method are the same as in the first embodiment. Therefore, only different parts will be described.

1. Light-Emitting Element The light-emitting element 300 will be described with reference to FIG. The light emitting element 300 is a face-up type semiconductor light emitting element. As shown in FIG. 16, the light-emitting element 300 includes a substrate 310, a low-temperature buffer layer 320, an n-type contact layer 330, an n-type ESD layer 340, an n-type SL layer 350, and a light-emitting layer. 360, a p-type cladding layer 370, and a p-type contact layer 380. Further, the n-type contact layer 330 is formed with an n-electrode N3. A p-electrode P3 is formed on the p-type contact layer 380.

  As the substrate 310, sapphire, SiC, ZnO, Si, GaN, or the like can be used. The material of the low temperature buffer layer 320 is, for example, AlN or GaN.

The n-type contact layer 330 is a layer made of n-type GaN. The carrier concentration of the n-type contact layer 330 is in the range of 1 × 10 ¹⁶ cm ^{−3 to} 1 × 10 ²⁰ cm ⁻³ .

  The n-type ESD layer 340 is an electrostatic withstand voltage layer for preventing electrostatic breakdown of each semiconductor layer. The structure of the n-type ESD layer 40 is a laminated structure of non-doped GaN and Si-doped n-type GaN.

  The n-type SL layer 350 is a strain relaxation layer for relaxing stress applied to the light emitting layer 360. More specifically, n-type SL layer 350 is an n-type superlattice layer having a superlattice structure. As will be described later, the n-type SL layer 350 is formed by repeatedly laminating a unit laminated body in which InGaN, GaN, and n-type GaN are laminated.

  The light-emitting layer 360 is a light-emitting layer that emits light when electrons and holes are recombined. Therefore, the light emitting layer 360 has a multiple quantum well structure in which well layers having a small band gap and barrier layers having a large band gap are alternately formed. Here, InGaN can be used as the well layer and AlGaN can be used as the barrier layer. Thus, the well layer contains In. Further, AlInGaN may be used as the barrier layer.

  The p-type cladding layer 370 is a layer formed by repeating a unit structure including a layer made of p-type InGaN and a layer made of p-type AlGaN as a unit structure. Of course, you may use things other than this.

  The p-type contact layer 380 is a layer made of p-type GaN doped with Mg. In addition, as the material of the p-type contact layer 380, any one of InGaN, AlGaN, and AlInGaN may be used.

  The material of the p electrode P3 is, for example, ITO. Of course, other materials may be used. A pad electrode may be formed on the p-electrode P3.

  As shown in FIG. 2, the n-electrode N <b> 3 has a metal layer S <b> 11 and a metal layer S <b> 12 formed on the n-type contact layer 330. An oxide layer S13 is formed on the metal layer S13.

2. Manufacturing Method of Semiconductor Device When manufacturing the light emitting element 300, a semiconductor layer is formed on the substrate 310 (semiconductor layer forming step). Then, the p-electrode P3 is formed, the n-type contact layer 330 is exposed, and the n-electrode N3 is formed (electrode formation process). That is, similarly to the first embodiment, the semiconductor forming process and the electrode forming process are included.

3. Modifications Also in the third embodiment, all the modification examples described in the first embodiment can be applied.

4). Summary As described in detail above, in the method of manufacturing the light emitting device 300 of this embodiment, the metal layers S11 and S12 are formed on the n-type contact layer 330, and the surface S12a of the metal layer S12 is oxidized. As a result, the oxide layer S13 was formed. The material of the oxide layer S13 is an oxide of the metal layer S12. Therefore, the etching resistance of the metal layer S12 can be increased. Thereby, conduction | electrical_connection part S16 can be formed suitably. That is, there is almost no possibility of deteriorating the ohmic characteristics in the n-electrode N3. Moreover, it is not necessary to form a cover layer.

  This embodiment is merely an example. Therefore, naturally, various improvements and modifications can be made without departing from the scope of the invention. In this embodiment, metal organic chemical vapor deposition (MOCVD) is used as the epitaxial growth method. However, vapor phase growth methods such as hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), pulsed sputter deposition (PSD), and liquid phase epitaxy may be used.

  The power elements 100 and 200 and the light emitting element 300 have been described above from the first embodiment to the third embodiment. However, the present invention is not limited to power elements and light emitting elements, and can be applied to other semiconductor devices.

DESCRIPTION OF SYMBOLS 100 ... Power element 110 ... Substrate 120 ... n-type layer 130 ... p-type layer 140 ... n-type layer 150 ... Insulating film G1 ... Gate electrode D1 ... Drain electrode S1 ... Source electrode S11 ... Metal layer S12 ... Metal layer S13 ... Oxide Layer S14 ... Insulating film S15 ... Recess S16 ... Conductive part 200 ... Power element 250 ... Carrier supply layer G2 ... Gate electrode D2 ... Drain electrode S2 ... Source electrode 300 ... Light emitting element 330 ... n-type contact layer 380 ... p-type contact layer N3 ... n electrode P3 ... p electrode

Claims (12)

Forming a semiconductor layer comprising a group III nitride compound semiconductor; and
Forming an electrode on the semiconductor layer; and
In the method of manufacturing a group III nitride compound semiconductor device having
The electrode forming step includes
A metal layer forming step of forming two or more metal layers on the semiconductor layer;
A heat treatment step of performing a heat treatment after the metal layer forming step;
Have
The heat treatment step includes
The surface of the outermost metal layer of the two or more metal layers is exposed in an atmosphere containing oxygen, thereby oxidizing the surface portion of the outermost metal layer to form an oxide layer. A manufacturing method of a group III nitride compound semiconductor device, characterized in that it is an oxide layer forming step to be formed. In the manufacturing method of the group III nitride compound semiconductor device according to claim 1,
The oxide layer forming step includes
A method for producing a group III nitride compound semiconductor device, which also serves as an ohmic alloy process for reducing resistance between the electrode and the semiconductor layer. In the manufacturing method of the group III nitride compound semiconductor device according to claim 1 or 2,
In the oxide layer forming step,
Using a mixed gas of nitrogen and oxygen as the atmosphere,
The oxygen concentration in the mixed gas is
A method for producing a Group III nitride compound semiconductor device, wherein the flow rate ratio is 1% or more. In the manufacturing method of the group III nitride compound semiconductor device of any one of Claim 1- Claim 3,
The heat treatment temperature in the oxide layer forming step is
A method for producing a Group III nitride compound semiconductor device, wherein the temperature is 500 ° C. or higher and 650 ° C. or lower. In the manufacturing method of the group III nitride compound semiconductor device according to any one of claims 1 to 4,
In the metal layer forming step,
A method of manufacturing a group III nitride compound semiconductor device, wherein the thickness of the outermost metal layer is in the range of 300 nm to 1000 nm. In the manufacturing method of the group III nitride compound semiconductor device according to any one of claims 1 to 5,
The outermost metal layer is an Al layer made of Al,
The method for manufacturing a group III nitride compound semiconductor device, wherein the oxide layer is an Al ₂ O ₃ layer made of Al ₂ O ₃ . In the manufacturing method of the group III nitride compound semiconductor device according to any one of claims 1 to 6,
In the metal layer forming step,
A method for producing a Group III nitride compound semiconductor device, comprising forming two or more metal layers on an n-type semiconductor layer. A substrate,
A semiconductor layer made of a group III nitride compound semiconductor formed on the substrate;
A plurality of electrodes formed in the semiconductor layer;
In a group III nitride compound semiconductor device having
At least one of the electrodes is
Two or more metal layers formed on the semiconductor layer;
An oxide layer formed on the outermost metal layer of the two or more metal layers,
The oxide layer is
A Group III nitride compound semiconductor device comprising an oxide obtained by oxidizing a metal of the outermost metal layer. The group III nitride compound semiconductor device according to claim 8,
The outermost metal layer is a layer made of Al,
The Group III nitride compound semiconductor device, wherein the oxide layer is a layer made of Al ₂ O ₃ . In the group III nitride compound semiconductor device according to claim 8 or 9,
The group III nitride compound semiconductor device, wherein the thickness of the outermost metal layer is in a range of 300 nm to 1000 nm. In the group III nitride compound semiconductor device according to any one of claims 8 to 10,
Two or more metal layers are
A group III nitride compound semiconductor device characterized by being formed on an n-type semiconductor layer. The group III nitride compound semiconductor device according to claim 11,
The carrier concentration in the n-type semiconductor layer is
A Group III nitride compound semiconductor device having a range of 1 × 10 ¹⁶ cm ^{−3 to} 1 × 10 ²⁰ cm ⁻³ .

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