WO2015115396A1 - Sige photodiode - Google Patents

Sige photodiode Download PDF

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WO2015115396A1
WO2015115396A1 PCT/JP2015/052117 JP2015052117W WO2015115396A1 WO 2015115396 A1 WO2015115396 A1 WO 2015115396A1 JP 2015052117 W JP2015052117 W JP 2015052117W WO 2015115396 A1 WO2015115396 A1 WO 2015115396A1
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layer
region
type
type semiconductor
semiconductor layer
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PCT/JP2015/052117
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French (fr)
Japanese (ja)
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藤方　潤一
真 三浦
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技術研究組合光電子融合基盤技術研究所
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Publication of WO2015115396A1 publication Critical patent/WO2015115396A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H01L31/1812—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table including only AIVBIV alloys, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12035—Materials
    • G02B2006/12061—Silicon
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12083—Constructional arrangements
    • G02B2006/12121—Laser
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/12004—Combinations of two or more optical elements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a SiGe photodiode that converts a light signal including infrared light into an electric signal.
  • a light receiving element having a pin structure in which an i-type semiconductor layer and an n-type semiconductor layer are stacked on a p-type semiconductor layer is known (see, for example, Patent Document 1 and Patent Document 2).
  • a method for forming the i-type semiconductor layer for example, a method in which an i-type semiconductor crystal layer is epitaxially grown on a crystal plane forming the surface of the p-type semiconductor layer is used.
  • the i-type semiconductor layer has good crystallinity.
  • an i-type semiconductor crystal layer is epitaxially grown on a crystal plane forming the surface of the p-type semiconductor layer
  • the impurity concentration of the p-type semiconductor layer which is a base layer is lowered. It is necessary to. The reason for this is that as a pretreatment before growing the i-type semiconductor layer, the natural oxide film formed on the surface of the p-type semiconductor layer which is the base layer is removed with hydrofluoric acid (HF), so that silicon (p-type) is formed.
  • HF hydrofluoric acid
  • the surface of the dangling bond on the surface is hydrogen-terminated.
  • the impurity concentration of the p-type semiconductor layer is high, the silicon surface is less likely to be hydrogen-terminated and the oxide film tends to remain. This is because it inhibits the epitaxial growth of the i-type semiconductor layer.
  • the impurity concentration of the p-type semiconductor layer is lowered, the electrical resistance as the electrode layer increases, and the operating characteristics at high frequencies of the light receiving element are degraded.
  • the present invention has been made in view of the above points, and one of its purposes is to provide a light receiving element having high photoelectric conversion efficiency and excellent operating characteristics at high frequencies.
  • one embodiment of the present invention provides a p-type semiconductor layer including a first region and a second region located below the first region, and the first region of the p-type semiconductor layer. And an n-type semiconductor layer formed on the i-type semiconductor layer, wherein the impurity concentration of the first region is the impurity concentration of the second region.
  • This is a SiGe photodiode characterized in that the concentration is lower than that of the SiGe photodiode.
  • the p-type semiconductor layer includes a third region connected to a metal electrode on a side portion of the first region,
  • the SiGe photodiode is characterized in that the impurity concentration is higher than the impurity concentration of the first region.
  • the impurity concentration of a surface layer portion in contact with the metal electrode in the third region is higher than the impurity concentration of the first region.
  • This is a SiGe photodiode.
  • the p-type semiconductor layer includes a fourth region below the second region, and the impurity concentration of the fourth region is equal to that of the second region.
  • the SiGe photodiode is characterized by having a lower concentration than the impurity concentration.
  • Another embodiment of the present invention is the SiGe photodiode according to the above embodiment, wherein the impurity concentration of the first region is 1 ⁇ 10 19 cm ⁇ 3 or less.
  • Another aspect of the present invention is the SiGe photodiode according to the above aspect, wherein the thickness of the first region in the p-type semiconductor layer is 50 nm or less.
  • Another embodiment of the present invention is the SiGe photodiode according to the above embodiment, wherein the impurity concentration of the third region is 1 ⁇ 10 19 cm ⁇ 3 or more.
  • the n-type semiconductor layer is an upper surface portion of the first SiGe layer in a protective film made of a second SiGe layer formed to cover the first SiGe layer.
  • This is a SiGe photodiode characterized in that it is a semiconductor layer doped with an n-type impurity.
  • Another aspect of the present invention is the SiGe photodiode according to the above aspect, wherein an n-type impurity is further doped in a surface layer of the first SiGe layer.
  • Another aspect of the present invention is the SiGe photodiode according to the above aspect, wherein the Si composition of the second SiGe layer is larger than the Si composition of the first SiGe layer.
  • the p-type semiconductor layer is a semiconductor layer in which an SOI layer over a buried oxide film layer is doped with a p-type impurity. It is a diode.
  • the waveguide includes the lower clad layer made of the buried oxide film layer, the core layer made of the SOI layer, and the upper clad layer covering the core layer.
  • the SiGe photodiode is characterized in that the waveguide is optically connected to the p-type semiconductor layer.
  • the waveguide includes a tapered silicon layer on the core layer and is optically connected to the i-type semiconductor layer. This is a characteristic SiGe photodiode.
  • a SiGe photodiode having high photoelectric conversion efficiency and excellent operating characteristics at high frequencies can be realized.
  • FIG. 1 is a diagram showing a schematic cross-sectional configuration of a SiGe photodiode 100 according to the first embodiment of the present invention.
  • the SiGe photodiode 100 includes a p-type semiconductor layer 102 formed on a substrate 101, an i-type semiconductor layer 103 formed on the p-type semiconductor layer 102, and an n-type semiconductor formed on the i-type semiconductor layer 103.
  • the p-type semiconductor layer 102 is a semiconductor layer doped with p-type impurities.
  • the i-type semiconductor layer 103 is a silicon germanium (Si x Ge 1-x ) layer that is not doped with impurities.
  • the n-type semiconductor layer 104 is a semiconductor layer doped with n-type impurities.
  • the SiGe photodiode 100 has a pin structure in which an i-type (intrinsic) silicon germanium layer is sandwiched between a p-type semiconductor layer and an n-type semiconductor layer.
  • the p-type semiconductor layer 102 includes a first region 102a that is an upper region on the i-type semiconductor layer 103 side and a second region 102b that is a lower region on the substrate 101 side.
  • the first region 102 a forms the surface layer (uppermost layer) of the p-type semiconductor layer 102 and is in contact with the i-type semiconductor layer 103. That is, the i-type semiconductor layer 103 is formed on the first region 102 a of the p-type semiconductor layer 102.
  • the second region 102b is located below the first region 102a and is in contact with the substrate 101.
  • the concentration of the p-type impurity doped in the first region 102a is lower than the concentration of the p-type impurity doped in the second region 102b.
  • the p-type is sufficiently low in concentration so that the surface of the first region 102a is not oxidized during the process before forming the i-type semiconductor layer 103 on the first region 102a.
  • the impurities are doped.
  • the second region 102b is doped with p-type impurities at a higher concentration than the first region 102a so that the p-type semiconductor layer 102 has a sufficiently large electrical conductivity.
  • the resistance value of the p-type semiconductor layer 102 decreases, and the SiGe photodiode 100 can be operated at high speed.
  • FIG. 2 is a diagram showing a schematic cross-sectional configuration in the XZ cross section of the SiGe photodiode 200 according to the second embodiment of the present invention.
  • the SiGe photodiode 200 shows a more detailed configuration of the SiGe photodiode 100.
  • the SiGe photodiode 200 includes a p-type silicon layer 203 formed on a buried oxide film layer (BOX layer) 202, an i-type germanium layer 204 formed on the p-type silicon layer 203, and an i-type germanium layer 204.
  • BOX layer buried oxide film layer
  • the n-type silicon germanium layer 205 is formed, and has a pin structure of the p-type silicon layer 203, the i-type germanium layer 204, and the n-type silicon germanium layer 205.
  • the p-type silicon layer 203, the i-type germanium layer 204, and the n-type silicon germanium layer 205 are respectively the p-type semiconductor layer 102, the i-type semiconductor layer 103, and the n-type semiconductor layer of the SiGe photodiode 100 shown in FIG. 104.
  • the SiGe photodiode 200 is manufactured using an SOI substrate including a silicon substrate 201, a BOX layer 202, and an SOI (Silicon On Insulator) layer on the BOX layer 202.
  • the p-type silicon layer 203 is a layer made of silicon (Si) doped with p-type impurities.
  • Si silicon
  • B boron
  • the p-type silicon layer 203 is formed by doping a SOI layer on the BOX layer 202 with a p-type impurity.
  • the p-type silicon layer 203 has a first region 203a that is an upper region on the i-type germanium layer 204 side and a second region 203b that is a lower region on the BOX layer 202 side.
  • the first region 203a and the second region 203b are partial regions of the p-type silicon layer 203 in plan view, and are regions where the i-type germanium layer 204 will grow on the regions.
  • the first region 203 a forms the surface layer (uppermost layer) of the p-type silicon layer 203 and is in contact with the i-type germanium layer 204.
  • the second region 203b is located below the first region 203a and is in contact with the BOX layer 202.
  • the concentration of the p-type impurity doped in the first region 203a is lower than the concentration of the p-type impurity doped in the second region 203b.
  • the first region 203a is doped with a p-type impurity at a sufficiently low concentration so that the surface of the first region 203a is not oxidized.
  • the concentration of the p-type impurity in the first region 203a is preferably 1 ⁇ 10 19 cm ⁇ 3 or less, and more preferably about 1 ⁇ 10 18 cm ⁇ 3 .
  • the second region 203b is doped with p-type impurities at a higher concentration than the first region 203a so that the p-type silicon layer 203 has a sufficiently large electric conductivity.
  • the concentration of the p-type impurity in the second region 203b is preferably 1 ⁇ 10 19 cm ⁇ 3 or more, and more preferably about 1 ⁇ 10 20 cm ⁇ 3 .
  • the concentration of the p-type impurity in the second region 203b is preferably 5 ⁇ 10 19 cm ⁇ 3 cm ⁇ 3 or less in order to avoid carrier plasma absorption in the p-type silicon layer 203.
  • the thickness of the first region 203a be as thin as possible. This is because the potential of a very thin region of the surface layer of the p-type silicon layer 203 is considered to affect the surface potential of the p-type silicon layer 203, that is, the ease of hydrogen termination on the surface of the p-type silicon layer 203. .
  • the thickness of the first region 203a may be 50 nm or less.
  • the p-type silicon layer 203 further has a third region 203c on the side of the first region 203a and the second region 203b.
  • the third region 203c is a partial region of the p-type silicon layer 203 in plan view, and is a region extending laterally from the end portions of the first region 203a and the second region 203b.
  • the concentration of the p-type impurity doped in the third region 203c is higher than the concentration of the p-type impurity doped in the first region 203a.
  • the third region 203c is doped with p-type impurities at a higher concentration than the first region 203a so that the p-type silicon layer 203 has a sufficiently large electrical conductivity.
  • the concentration of the p-type impurity in the third region 203c is preferably 1 ⁇ 10 19 cm ⁇ 3 or more, and more preferably about 1 ⁇ 10 20 cm ⁇ 3 .
  • the surface layer of the third region 203c may include a p-type impurity at a high concentration.
  • the i-type germanium layer 204 is a layer made of germanium (Ge) that is not doped with impurities.
  • the i-type semiconductor layer of the SiGe photodiode 200 is composed of a germanium layer which is a kind of silicon germanium layer.
  • the i-type germanium layer 204 is also referred to as a first silicon germanium (SiGe) layer.
  • the i-type germanium layer 204 is formed by epitaxially growing a germanium crystal layer on the first region 203 a of the p-type silicon layer 203.
  • the i-type germanium layer 204 is configured with a low-temperature grown germanium layer 204a at the bottom.
  • the low-temperature grown germanium layer 204a is a layer that becomes a buffer layer (crystal strain relaxation layer) of the i-type germanium layer 204 during epitaxial growth.
  • the first region 203a of the p-type silicon layer 203 is doped with impurities at a low concentration, and the surface of the first region 203a is not oxidized and a silicon crystal plane appears. Therefore, the low temperature growth germanium layer 204a and the i-type germanium layer 204 with good crystallinity can be epitaxially grown.
  • the n-type silicon germanium layer 205 is a layer made of silicon germanium (Si x Ge 1-x ) doped with n-type impurities.
  • silicon germanium Si x Ge 1-x
  • n-type impurities For example, phosphorus (P), arsenic (As), or the like can be used as the n-type impurity.
  • the impurity concentration of the n-type silicon germanium layer 205 is preferably 1 ⁇ 10 19 cm ⁇ 3 or more, for example, so that the n-type silicon germanium layer 205 has a sufficiently large electric conductivity, and more preferably 1 ⁇ 10 20 More preferably, it is about cm ⁇ 3 .
  • the n-type silicon germanium layer 205 is obtained by epitaxially growing a second silicon germanium (SiGe) layer 205a, which is a silicon germanium crystal layer, so as to cover the upper surface and side surfaces of the i-type germanium layer (first silicon germanium layer) 204.
  • a second silicon germanium (SiGe) layer 205a which is a silicon germanium crystal layer, so as to cover the upper surface and side surfaces of the i-type germanium layer (first silicon germanium layer) 204.
  • the upper surface portion of the i-type germanium layer 204 is doped with an n-type impurity.
  • the portion of the second silicon germanium layer 205a covering the side surface of the i-type germanium layer 204 serves as a protective film for reducing leakage current caused by crystal defects existing on the surface of the i-type germanium layer 204. Function.
  • the surface of the SiGe photodiode 200 is covered with an insulating film 206.
  • the insulating film 206 is, for example, a SiO 2 film.
  • an opening reaching the surface of the n-type silicon germanium layer 205 is provided above the n-type silicon germanium layer 205, and a first metal electrode 207 is formed in the opening.
  • an opening reaching the surface of the p-type silicon layer 203 is provided in an upper part (a part) of the third region 203c of the p-type silicon layer 203 in the insulating film 206, and the second metal is contained in the opening.
  • An electrode 208 is formed.
  • the first metal electrode 207 and the second metal electrode 208 are electrodes for taking out current from the light receiving element 200.
  • FIG. 3 is a diagram showing a schematic cross-sectional configuration in the YZ cross section of the SiGe photodiode 200 according to the second embodiment of the present invention described above.
  • the SiGe photodiode 200 includes a lower clad layer constituted by the BOX layer 202, a core layer 209 constituted by the SOI layer on the BOX layer 202, and an upper clad layer constituted by the insulating film 206.
  • a waveguide 210 is provided.
  • the BOX layer 202 constituting the lower cladding layer and the insulating film 206 constituting the upper cladding layer are the same as the BOX layer 202 and the insulating film 206 shown in FIG.
  • the SOI layer constituting the core layer 209 is the same as the SOI layer before impurity doping constituting the p-type silicon layer 203 shown in FIG.
  • the core layer 209 is seamlessly formed with the p-type silicon layer 203 by a common SOI layer.
  • the waveguide 210 is formed adjacent to the pin structure using the same SOI substrate on which the pin structure of the SiGe photodiode 200 shown in FIG. 2 is formed.
  • the SiGe photodiode 200 is configured such that light propagating in the Y direction through the core layer 209 of the waveguide 210 is incident on the p-type silicon layer 203 via the side end portion of the p-type silicon layer 203.
  • the light incident on the p-type silicon layer 203 propagates in the Y direction in the pin structure while the light field gradually moves from the p-type silicon layer 203 to the i-type germanium layer 204, and the i-type germanium layer 204 absorbs light. Is done.
  • carriers (electrons and holes) are generated according to the absorbed light, and the generated carriers move to the p-type silicon layer 203 and the n-type silicon germanium layer 205, respectively.
  • the photocurrent is extracted from the first metal electrode 207 and the second metal electrode 208 to the outside.
  • the second region 203b and the third region 203c of the p-type silicon layer 203 and the n-type silicon germanium layer 205 have a high impurity concentration and a large electric conductivity. Excellent operating characteristics can be shown.
  • FIGS. 4 to 7 are process diagrams showing a method of manufacturing the SiGe photodiode 200 according to the second embodiment of the present invention described above. Hereinafter, a method for manufacturing the SiGe photodiode 200 will be described.
  • the first region 203a and the second region 203b of the p-type silicon layer 203 are formed in the SOI layer of the SOI substrate.
  • an SOI substrate including a silicon substrate 201, a BOX layer 202, and an SOI layer 211 is prepared, and a resist film 212 is formed on the SOI layer 211.
  • the resist film 212 is processed by exposure / development so as to have an opening in a portion to be the first region 203a.
  • a p-type impurity for example, boron (B)
  • B boron
  • the p-type impurity is doped by ion implantation.
  • the depth at which ions are implanted can be controlled by the acceleration energy of ions (B + ).
  • the acceleration energy is set to such an energy that the peak of the concentration of implanted ions comes to the second region 203b.
  • a p-type silicon layer 203 having a first region 203a having a low impurity concentration and a second region 203b having a high impurity concentration is formed. Thereafter, the resist film 212 is removed.
  • FIG. 4 shows an XZ cross section, and thus the core layer 209 is not drawn in FIG. 4.
  • a core layer 209 is formed from the SOI layer 211 by processing into a desired pattern by etching.
  • the third region 203c of the p-type silicon layer 203 is formed in the SOI layer of the SOI substrate.
  • a resist film 213 having an opening in the portion to be the third region 203c is formed on the SOI layer 211, and p-type impurities are doped by ion implantation through the opening of the resist film 213.
  • the resist film 213 is removed.
  • an i-type germanium layer 204 is formed on the first region 203 a of the p-type silicon layer 203.
  • the SiO 2 film is formed first on a p-type silicon layer 203, by the SiO 2 film so as to have an opening in the first region 203a is processed by photolithography and etching, SiO 2 mask 214 Create Next, the low temperature growth germanium layer 204a and the i-type germanium layer 204 are sequentially formed in the opening portion of the SiO 2 mask 214 by epitaxial growth.
  • the low-temperature grown germanium layer 204a and the i-type germanium layer 204 with good crystallinity are epitaxially grown. It is possible to make it.
  • an n-type silicon germanium layer 205 is formed on the i-type germanium layer 204.
  • the second silicon germanium layer 205a is epitaxially grown so as to cover the first silicon germanium layer composed of the low-temperature grown germanium layer 204a and the i-type germanium layer 204.
  • a resist film 215 having an opening is formed on the i-type germanium layer 204, and an n-type impurity (by ion implantation into the second silicon germanium layer 205 a on the upper surface portion of the i-type germanium layer 204 through the opening of the resist film 215.
  • the n-type silicon germanium layer 205 is formed by doping phosphorus (P), arsenic (As), or the like.
  • the first metal electrode 207 and the second metal electrode 208 are formed (see FIG. 2). Specifically, first, an insulating film 206 is formed so as to cover the n-type silicon germanium layer 205 and the p-type silicon layer 203. Next, the n-type silicon germanium layer 205 is formed on the upper part of the n-type silicon germanium layer 205 and the upper part (a part) of the third region 203c of the p-type silicon layer 203 by photolithography and etching, respectively. An opening reaching the surface and the surface of the p-type silicon layer 203 is formed. Then, the first metal electrode 207 and the second metal electrode 208 are formed by filling the inside of these openings with a metal material.
  • FIG. 8 is a diagram showing a schematic cross-sectional configuration of a SiGe photodiode 300 according to the third embodiment of the present invention.
  • the SiGe photodiode 300 has the same structure in the XZ cross section and the YZ cross section.
  • the same components as those of the SiGe photodiode 200 according to the second embodiment described above are denoted by the same reference numerals.
  • an opening reaching the surface of the n-type silicon germanium layer 205 is provided at the center of the first metal electrode 301 above the n-type silicon germanium layer 205, and a transparent protective film is formed in the opening.
  • the point where 302 is formed is different from the SiGe photodiode 200 according to the second embodiment.
  • the protective film 302 is a SiO 2 film, for example.
  • the configuration of other parts of the SiGe photodiode 300 is the same as that of the SiGe photodiode 200 according to the second embodiment.
  • the SiGe photodiode 300 is configured such that light from above the n-type silicon germanium layer 205 is incident on the i-type germanium layer 204 via the protective film 302 and the n-type silicon germanium layer 205.
  • the incident light is absorbed by the i-type germanium layer 204, and similarly to the SiGe photodiode 200, the i-type germanium layer 204 generates and generates carriers (electrons and holes) according to the absorbed light.
  • the carriers move to the p-type silicon layer 203 and the n-type silicon germanium layer 205, respectively, and a photocurrent flows.
  • the photocurrent is extracted from the first metal electrode 301 and the second metal electrode 208 to the outside.
  • FIG. 9 is a diagram showing a schematic cross-sectional configuration in the XZ cross section of the SiGe photodiode 400 according to the fourth embodiment of the present invention.
  • FIG. 10 is a diagram showing a schematic cross-sectional configuration of the SiGe photodiode 400 in the YZ cross section. 9 and 10, the same components as those in the SiGe photodiode 200 according to the second embodiment described above are denoted by the same reference numerals.
  • the SiGe photodiode 400 is different from the SiGe photodiode 200 according to the second embodiment in that the SiGe photodiode 400 includes silicon layers 401 and 402 formed by epitaxial growth on the side portion of the i-type germanium layer 204.
  • the structure of other parts of the SiGe photodiode 400 is the same as that of the SiGe photodiode 200 according to the second embodiment.
  • the silicon layer 402 is formed on the core layer 209 of the waveguide 210.
  • a side surface 402a that forms an interface with the insulating film 206 (upper cladding layer) is configured as an inclined surface that is inclined with respect to the substrate surface (XY plane).
  • the substantial core layer thickness of the waveguide 210 composed of the core layer 209 and the silicon layer 402 becomes thicker in the Y direction in FIG. That is, the silicon layer 402 is a tapered core layer that changes the thickness of the substantial core layer of the waveguide 210.
  • the waveguide 210 constitutes a tapered waveguide whose thickness of the core layer changes in the height direction (Z direction).
  • the light propagating in the Y direction in the core layer 209 of the waveguide 210 is a portion of the tapered waveguide composed of the core layer 209 and the silicon layer 402, and the light field is directed to the silicon layer 402 side. Zoom in and go further in the Y direction.
  • the light whose field is expanded is incident not only on the side end portion of the p-type silicon layer 203 but also directly on the i-type germanium layer 204 from the side end portion of the i-type germanium layer 204. Therefore, the SiGe photodiode 400 can efficiently make the light propagating in the Y direction through the core layer 209 of the waveguide 210 incident on the i-type germanium layer 204.
  • the i-type germanium layer 204 As in the case of the SiGe photodiode 200, incident light is absorbed to generate carriers (electrons and holes), and the generated carriers are respectively converted into the p-type silicon layer 203 and the n-type silicon. By moving to the germanium layer 205, a photocurrent flows. The photocurrent is extracted from the first metal electrode 207 and the second metal electrode 208 to the outside.
  • 11 to 16 are process diagrams showing a method of manufacturing the SiGe photodiode 400 according to the fourth embodiment of the present invention described above. Hereinafter, a method for manufacturing the SiGe photodiode 400 will be described.
  • a p-type silicon layer 203 and a core layer 209 are formed on the BOX layer 202.
  • the p-type silicon layer 203 is formed so that the impurity concentration of the first region 203a is low and the impurity concentration of the second region 203b is high.
  • 11 shows a YZ cross section, the third region 203c of the p-type silicon layer 203 is not drawn in FIG.
  • a silicon layer 403 is formed so as to cover a part of the core layer 209 and the first region 203 a of the p-type silicon layer 203. Specifically, first, an SiO 2 film is formed on the entire surface of the core layer 209 and the p-type silicon layer 203, and this SiO 2 is exposed so that a part of the core layer 209 and the first region 203a of the p-type silicon layer 203 are exposed.
  • a SiO 2 mask 404 is formed by processing the film by photolithography and etching.
  • a silicon layer 403 is formed in the opening portion of the SiO 2 mask 404 by epitaxial growth. At this time, an inclined surface 402 a is formed by the crystal plane (facet) of the grown silicon layer 403. As described above, the slope 402a is a surface constituting the tapered core layer.
  • an insulating film 206 is formed so as to cover the silicon layer 403, and the upper part of the first region 203a of the p-type silicon layer 203 in the formed insulating film 206 is subjected to photolithography and An opening is formed by etching.
  • a part of the silicon layer 403 is etched from the opening of the insulating film 206 to expose the first region 203 a of the p-type silicon layer 203.
  • anisotropic wet etching with an alkaline solution is applied for the etching of the silicon layer 403, for example, anisotropic wet etching with an alkaline solution is applied.
  • the upper part of the core layer 209 becomes a tapered core layer 402.
  • an i-type germanium layer 204 is formed on the exposed first region 203 a of the p-type silicon layer 203.
  • the low-temperature grown germanium layer 204a and the i-type germanium layer 204 are sequentially formed by epitaxial growth through the opening of the insulating film 206.
  • the low-temperature grown germanium layer 204a and the i-type germanium layer 204 are crystal-grown using the tapered core layer 402 and the silicon layer 401 in the opening of the insulating film 206 as masks.
  • the low-temperature grown germanium layer 204a and the i-type germanium layer 204 with good crystallinity are epitaxially grown. It is possible to make it.
  • an n-type silicon germanium layer 205 is formed on the i-type germanium layer 204. Specifically, first, a silicon germanium crystal layer (second silicon germanium layer) is grown on the i-type germanium layer 204 (first silicon germanium layer) by epitaxial growth. Next, an n-type silicon germanium layer 205 is formed by doping the silicon germanium crystal layer with an n-type impurity (for example, phosphorus (P) or arsenic (As)) by ion implantation.
  • an n-type impurity for example, phosphorus (P) or arsenic (As)
  • first metal electrode 207 and the second metal electrode 208 are formed (see FIGS. 9 and 10). Specifically, an opening reaching the surface of the p-type silicon layer 203 is formed by photolithography and etching in an upper part (a part) of the third region 203c of the p-type silicon layer 203 in the insulating film 206. A first metal electrode 207 and a second metal electrode 208 are formed by filling the inside and the inside of the opening of the insulating film 206 formed in the step of FIG. 13 with a metal material.
  • the first region 102a of the p-type semiconductor layer 102 and the first region 203a of the p-type silicon layer 203 may be regions having a uniform impurity concentration, It may be a region having a concentration distribution (concentration gradient).
  • the second region 102b of the p-type semiconductor layer 102 and the second region 203b of the p-type silicon layer 203 may be regions having a uniform impurity concentration or have an impurity concentration distribution (concentration gradient). It may be a region.
  • the p-type semiconductor layer 102 and the p-type silicon layer 203 have an internal impurity concentration (that is, an impurity concentration on the surface in contact with the i-type semiconductor layer 103 and the i-type germanium layer 204). It is necessary that the impurity concentration be lower than the impurity concentration on the lower side of the surface), but in each region of the first region (102a, 203a) and the second region (102b, 203b). The concentration distribution in is unquestioned. As an example, the p-type semiconductor layer 102 and the p-type silicon layer 203 may be formed so that the impurity concentration gradually increases as the depth from the surface increases.
  • the p-type semiconductor layer 102 and the p-type silicon layer 203 gradually increase in impurity concentration as the depth from the surface becomes deeper, the impurity concentration becomes maximum near the center of the depth, and the depth is deeper than that. Then, the impurity concentration may be gradually decreased.
  • the p-type semiconductor layer 102 and the p-type silicon layer 203 are lower in impurity concentration than the second regions 102b and 203b below the second regions 102b and 203b.
  • Four regions may be further provided. That is, the p-type semiconductor layer 102 and the p-type silicon layer 203 have a three-layer structure in which a low-concentration fourth region, high-concentration second regions 102b and 203b, and a low-concentration first region are stacked in order from the bottom. Also good.
  • the third region 203c of the p-type silicon layer 203 is composed of a layer having a high impurity concentration on the upper layer side (side in contact with the second metal electrode 208), and the impurity concentration on the lower layer side. May be composed of a low layer.
  • i-type germanium layer 204 instead of the i-type germanium layer 204, i-type silicon germanium (Si x Ge 1-x) in which the composition ratio x of silicon and germanium is in the range of 0 ⁇ x ⁇ 0.5, for example. ) Layer may be employed.
  • the optimum composition ratio x may be selected according to the wavelength used.
  • an n-type silicon layer may be employed instead of the n-type silicon germanium layer 205.
  • the composition ratio of silicon and germanium in the i-type first silicon germanium layer 204 is different from the composition ratio of silicon and germanium in the n-type second silicon germanium layer 205.
  • the silicon composition in the second silicon germanium layer 205 may be larger than the silicon composition in the first silicon germanium layer 204.
  • the protective film (second silicon germanium layer 205) for protecting the first silicon germanium layer 204 a pure silicon layer is more stable and preferable, but silicon is grown on the first silicon germanium layer 204 with good crystallinity. Is difficult because of the large difference in crystal lattice constant between silicon and silicon germanium.
  • the second silicon germanium layer 205 is a pure silicon layer, the activation annealing temperature required after doping the n-type impurity becomes high, and the doped impurity is likely to diffuse. Although the diffusion of impurities can be suppressed by lowering the activation annealing temperature, the activation of the impurities becomes insufficient and the recovery of crystal defects due to ion implantation becomes insufficient.
  • the second silicon germanium layer 205 is preferably not a pure silicon layer but a silicon germanium layer.
  • the surface layer portion of the first silicon germanium layer 204 may be doped with n-type impurities.
  • the doping of the n-type impurity into the surface layer portion of the first silicon germanium layer 204 is performed by the step of doping the second silicon germanium layer 205 with the n-type impurity (the process of FIG. 7 and the fourth embodiment described in the second embodiment). This can be performed in the step shown in FIG.
  • the thickness of the second silicon germanium layer 205 is thin
  • the n-type impurity is doped into the second silicon germanium layer 205 by ion implantation
  • a part of the n-type impurity is part of the second silicon germanium layer 205.
  • doped into the surface layer of the first silicon germanium layer 204 by changing the acceleration energy of ion implantation, ion implantation into the second silicon germanium layer 205 and ion implantation into the first silicon germanium layer 204 may be performed in two stages.
  • phosphine (PH) is added to silane (SiH 4 ) and germane (GeH 4 ) which are source gases when the silicon germanium layer is epitaxially grown instead of ion implantation. 3 ) In-situ doping with mixing may be employed.

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Abstract

Provided is a SiGe photodiode that has high incident photon-to-current conversion efficiency and has superior operating characteristics at high frequencies. A SiGe photodiode (100) is provided with: a P-type semiconductor layer (102) having a first region (102a) and a second region (102b) located below the first region (102a); an I-type semiconductor layer (103) formed on the first region (102a) of the P-type semiconductor layer (102); and an N-type semiconductor layer (104) formed on the I-type semiconductor layer (103). The concentration of impurities in the first region (102a) is lower than that in the second region (102b).

Description

ＳｉＧｅフォトダイオードSiGe photodiode
　本発明は、赤外を含む光の信号を電気信号に変換するＳｉＧｅフォトダイオードに関する。 The present invention relates to a SiGe photodiode that converts a light signal including infrared light into an electric signal.
　ｐ型半導体層上にｉ型半導体層とｎ型半導体層を積層して構成されたｐｉｎ構造の受光素子が知られている（例えば、特許文献１及び特許文献２を参照）。ｉ型半導体層の形成方法として、例えば、ｐ型半導体層の表面をなす結晶面上にｉ型半導体の結晶層をエピタキシャル成長させる方法が用いられる。 2. Description of the Related Art A light receiving element having a pin structure in which an i-type semiconductor layer and an n-type semiconductor layer are stacked on a p-type semiconductor layer is known (see, for example, Patent Document 1 and Patent Document 2). As a method for forming the i-type semiconductor layer, for example, a method in which an i-type semiconductor crystal layer is epitaxially grown on a crystal plane forming the surface of the p-type semiconductor layer is used.
特許第５２３２９８１号公報Japanese Patent No. 5232981 特開２０１１－１８１８７４号公報JP 2011-181874 A
　ｐｉｎ構造の受光素子において光電変換効率を向上させるために、ｉ型半導体層が良好な結晶性を有していることが望まれる。ｐ型半導体層の表面をなす結晶面上にｉ型半導体の結晶層をエピタキシャル成長させる場合、結晶性の良好なｉ型半導体層を得るには、下地層であるｐ型半導体層の不純物濃度を低くすることが必要である。その理由は、ｉ型半導体層を成長させる前の前処理として、下地層であるｐ型半導体層の表面に形成される自然酸化膜をフッ酸（ＨＦ）で除去することで、シリコン（ｐ型半導体層）表面のダングリングボンドを水素終端する処理を行うが、ｐ型半導体層の不純物濃度が高いとシリコン表面が水素終端しにくく、酸化膜が残りやすい傾向となって、この残った酸化膜がｉ型半導体層のエピタキシャル成長を阻害するからである。しかしながら、ｐ型半導体層の不純物濃度を低くすると、電極層としての電気抵抗が大きくなり、受光素子の高周波での動作特性が低下してしまう。 In order to improve photoelectric conversion efficiency in a light receiving element having a pin structure, it is desirable that the i-type semiconductor layer has good crystallinity. In the case where an i-type semiconductor crystal layer is epitaxially grown on a crystal plane forming the surface of the p-type semiconductor layer, in order to obtain an i-type semiconductor layer having good crystallinity, the impurity concentration of the p-type semiconductor layer which is a base layer is lowered. It is necessary to. The reason for this is that as a pretreatment before growing the i-type semiconductor layer, the natural oxide film formed on the surface of the p-type semiconductor layer which is the base layer is removed with hydrofluoric acid (HF), so that silicon (p-type) is formed. Semiconductor layer) The surface of the dangling bond on the surface is hydrogen-terminated. However, if the impurity concentration of the p-type semiconductor layer is high, the silicon surface is less likely to be hydrogen-terminated and the oxide film tends to remain. This is because it inhibits the epitaxial growth of the i-type semiconductor layer. However, if the impurity concentration of the p-type semiconductor layer is lowered, the electrical resistance as the electrode layer increases, and the operating characteristics at high frequencies of the light receiving element are degraded.
　本発明は、上記の点に鑑みてなされたものであり、その目的の１つは、高い光電変換効率を有するとともに高周波での動作特性に優れた受光素子を提供することにある。 The present invention has been made in view of the above points, and one of its purposes is to provide a light receiving element having high photoelectric conversion efficiency and excellent operating characteristics at high frequencies.
　上述した課題を解決するために、本発明の一態様は、第１領域及び前記第１領域の下部に位置する第２領域を有するｐ型半導体層と、前記ｐ型半導体層の前記第１領域上に形成された第１ＳｉＧｅ層よりなるｉ型半導体層と、前記ｉ型半導体層上に形成されたｎ型半導体層と、を備え、前記第１領域の不純物濃度が前記第２領域の不純物濃度よりも低濃度である、ことを特徴とするＳｉＧｅフォトダイオードである。 In order to solve the above-described problem, one embodiment of the present invention provides a p-type semiconductor layer including a first region and a second region located below the first region, and the first region of the p-type semiconductor layer. And an n-type semiconductor layer formed on the i-type semiconductor layer, wherein the impurity concentration of the first region is the impurity concentration of the second region. This is a SiGe photodiode characterized in that the concentration is lower than that of the SiGe photodiode.
　また、本発明の他の一態様は、上記一態様において、前記ｐ型半導体層は、前記第１領域の側部に金属電極と接続するための第３領域を有し、前記第３領域の不純物濃度が前記第１領域の不純物濃度よりも高濃度である、ことを特徴とするＳｉＧｅフォトダイオードである。 According to another aspect of the present invention, in the above aspect, the p-type semiconductor layer includes a third region connected to a metal electrode on a side portion of the first region, The SiGe photodiode is characterized in that the impurity concentration is higher than the impurity concentration of the first region.
　また、本発明の他の一態様は、上記一態様において、前記第３領域のうち前記金属電極と接する表層部の不純物濃度が前記第１領域の不純物濃度よりも高濃度であることを特徴とするＳｉＧｅフォトダイオードである。 According to another aspect of the present invention, in the above aspect, the impurity concentration of a surface layer portion in contact with the metal electrode in the third region is higher than the impurity concentration of the first region. This is a SiGe photodiode.
　また、本発明の他の一態様は、上記一態様において、前記ｐ型半導体層は、前記第２領域の下部に第４領域を有し、前記第４領域の不純物濃度が前記第２領域の不純物濃度よりも低濃度である、ことを特徴とするＳｉＧｅフォトダイオードである。 According to another aspect of the present invention, in the above aspect, the p-type semiconductor layer includes a fourth region below the second region, and the impurity concentration of the fourth region is equal to that of the second region. The SiGe photodiode is characterized by having a lower concentration than the impurity concentration.
　また、本発明の他の一態様は、上記一態様において、前記第１領域の不純物濃度は、１×１０１９ｃｍ－３以下であることを特徴とするＳｉＧｅフォトダイオードである。 Another embodiment of the present invention is the SiGe photodiode according to the above embodiment, wherein the impurity concentration of the first region is 1 × 10 19 cm −3 or less.
　また、本発明の他の一態様は、上記一態様において、前記ｐ型半導体層における前記第１領域の厚さは、５０ｎｍ以下であることを特徴とするＳｉＧｅフォトダイオードである。 Another aspect of the present invention is the SiGe photodiode according to the above aspect, wherein the thickness of the first region in the p-type semiconductor layer is 50 nm or less.
　また、本発明の他の一態様は、上記一態様において、前記第３領域の不純物濃度は、１×１０１９ｃｍ－３以上であることを特徴とするＳｉＧｅフォトダイオードである。 Another embodiment of the present invention is the SiGe photodiode according to the above embodiment, wherein the impurity concentration of the third region is 1 × 10 19 cm −3 or more.
　また、本発明の他の一態様は、上記一態様において、前記ｎ型半導体層は、前記第１ＳｉＧｅ層を覆うように形成された第２ＳｉＧｅ層よりなる保護膜のうち前記第１ＳｉＧｅ層の上面部分にｎ型不純物がドープされた半導体層であることを特徴とするＳｉＧｅフォトダイオードである。 According to another aspect of the present invention, in the above aspect, the n-type semiconductor layer is an upper surface portion of the first SiGe layer in a protective film made of a second SiGe layer formed to cover the first SiGe layer. This is a SiGe photodiode characterized in that it is a semiconductor layer doped with an n-type impurity.
　また、本発明の他の一態様は、上記一態様において、ｎ型不純物が更に前記第１ＳｉＧｅ層の表層にドープされたことを特徴とするＳｉＧｅフォトダイオードである。 Another aspect of the present invention is the SiGe photodiode according to the above aspect, wherein an n-type impurity is further doped in a surface layer of the first SiGe layer.
　また、本発明の他の一態様は、上記一態様において、前記第２ＳｉＧｅ層のＳｉの組成は、前記第１ＳｉＧｅ層のＳｉの組成よりも大きいことを特徴とするＳｉＧｅフォトダイオードである。 Another aspect of the present invention is the SiGe photodiode according to the above aspect, wherein the Si composition of the second SiGe layer is larger than the Si composition of the first SiGe layer.
　また、本発明の他の一態様は、上記一態様において、前記ｐ型半導体層は、埋め込み酸化膜層上のＳＯＩ層にｐ型不純物がドープされた半導体層であることを特徴とするＳｉＧｅフォトダイオードである。 According to another aspect of the present invention, in the above aspect, the p-type semiconductor layer is a semiconductor layer in which an SOI layer over a buried oxide film layer is doped with a p-type impurity. It is a diode.
　また、本発明の他の一態様は、上記一態様において、前記埋め込み酸化膜層からなる下部クラッド層、前記ＳＯＩ層からなるコア層、及び前記コア層を覆う上部クラッド層により構成された導波路を備え、前記導波路は、前記ｐ型半導体層に光学的に接続されている、ことを特徴とするＳｉＧｅフォトダイオードである。 According to another aspect of the present invention, in the above aspect, the waveguide includes the lower clad layer made of the buried oxide film layer, the core layer made of the SOI layer, and the upper clad layer covering the core layer. The SiGe photodiode is characterized in that the waveguide is optically connected to the p-type semiconductor layer.
　また、本発明の他の一態様は、上記一態様において、前記導波路は、前記コア層上にテーパ形状のシリコン層を有し、前記ｉ型半導体層に光学的に接続されていることを特徴とするＳｉＧｅフォトダイオードである。 According to another aspect of the present invention, in the above aspect, the waveguide includes a tapered silicon layer on the core layer and is optically connected to the i-type semiconductor layer. This is a characteristic SiGe photodiode.
　本発明によれば、高い光電変換効率を有するとともに高周波での動作特性に優れたＳｉＧｅフォトダイオードを実現することができる。 According to the present invention, a SiGe photodiode having high photoelectric conversion efficiency and excellent operating characteristics at high frequencies can be realized.
第１実施形態に係るＳｉＧｅフォトダイオード１００の模式的な断面構成を示した図である。It is the figure which showed the typical cross-sectional structure of the SiGe photodiode 100 which concerns on 1st Embodiment. 第２実施形態に係るＳｉＧｅフォトダイオード２００のＸＺ断面における模式的な断面構成を示した図である。It is the figure which showed the typical cross-sectional structure in the XZ cross section of the SiGe photodiode 200 which concerns on 2nd Embodiment. 第２実施形態に係るＳｉＧｅフォトダイオード２００のＹＺ断面における模式的な断面構成を示した図である。It is the figure which showed the typical cross-sectional structure in the YZ cross section of the SiGe photodiode 200 which concerns on 2nd Embodiment. 第２実施形態に係るＳｉＧｅフォトダイオード２００の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the SiGe photodiode 200 which concerns on 2nd Embodiment. 第２実施形態に係るＳｉＧｅフォトダイオード２００の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the SiGe photodiode 200 which concerns on 2nd Embodiment. 第２実施形態に係るＳｉＧｅフォトダイオード２００の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the SiGe photodiode 200 which concerns on 2nd Embodiment. 第２実施形態に係るＳｉＧｅフォトダイオード２００の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the SiGe photodiode 200 which concerns on 2nd Embodiment. 第３実施形態に係るＳｉＧｅフォトダイオード３００の模式的な断面構成を示した図である。It is the figure which showed the typical cross-sectional structure of the SiGe photodiode 300 which concerns on 3rd Embodiment. 第４実施形態に係るＳｉＧｅフォトダイオード４００のＸＺ断面における模式的な断面構成を示した図である。It is the figure which showed the typical cross-sectional structure in the XZ cross section of the SiGe photodiode 400 which concerns on 4th Embodiment. 第４実施形態に係るＳｉＧｅフォトダイオード４００のＹＺ断面における模式的な断面構成を示した図である。It is the figure which showed the typical cross-sectional structure in the YZ cross section of the SiGe photodiode 400 which concerns on 4th Embodiment. 第４実施形態に係るＳｉＧｅフォトダイオード４００の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the SiGe photodiode 400 which concerns on 4th Embodiment. 第４実施形態に係るＳｉＧｅフォトダイオード４００の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the SiGe photodiode 400 which concerns on 4th Embodiment. 第４実施形態に係るＳｉＧｅフォトダイオード４００の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the SiGe photodiode 400 which concerns on 4th Embodiment. 第４実施形態に係るＳｉＧｅフォトダイオード４００の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the SiGe photodiode 400 which concerns on 4th Embodiment. 第４実施形態に係るＳｉＧｅフォトダイオード４００の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the SiGe photodiode 400 which concerns on 4th Embodiment. 第４実施形態に係るＳｉＧｅフォトダイオード４００の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the SiGe photodiode 400 which concerns on 4th Embodiment.
　以下、図面を参照しながら本発明の実施形態について詳しく説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
　図１は、本発明の第１実施形態に係るＳｉＧｅフォトダイオード１００の模式的な断面構成を示した図である。ＳｉＧｅフォトダイオード１００は、基板１０１上に形成されたｐ型半導体層１０２と、ｐ型半導体層１０２上に形成されたｉ型半導体層１０３と、ｉ型半導体層１０３上に形成されたｎ型半導体層１０４とを備えている。ｐ型半導体層１０２は、ｐ型の不純物がドープされた半導体層である。ｉ型半導体層１０３は、不純物がドープされていないシリコンゲルマニウム（ＳｉｘＧｅ１－ｘ）層である。ｎ型半導体層１０４は、ｎ型の不純物がドープされた半導体層である。このように、ＳｉＧｅフォトダイオード１００は、ｐ型の半導体層とｎ型の半導体層とによってｉ型（真性）のシリコンゲルマニウム層を挟み込んだｐｉｎ構造を有している。 FIG. 1 is a diagram showing a schematic cross-sectional configuration of a SiGe photodiode 100 according to the first embodiment of the present invention. The SiGe photodiode 100 includes a p-type semiconductor layer 102 formed on a substrate 101, an i-type semiconductor layer 103 formed on the p-type semiconductor layer 102, and an n-type semiconductor formed on the i-type semiconductor layer 103. Layer 104. The p-type semiconductor layer 102 is a semiconductor layer doped with p-type impurities. The i-type semiconductor layer 103 is a silicon germanium (Si x Ge 1-x ) layer that is not doped with impurities. The n-type semiconductor layer 104 is a semiconductor layer doped with n-type impurities. Thus, the SiGe photodiode 100 has a pin structure in which an i-type (intrinsic) silicon germanium layer is sandwiched between a p-type semiconductor layer and an n-type semiconductor layer.
　ｐ型半導体層１０２は、ｉ型半導体層１０３側の上部領域である第１領域１０２ａと、基板１０１側の下部領域である第２領域１０２ｂとから構成されている。第１領域１０２ａは、ｐ型半導体層１０２の表層（最上部層）をなしており、ｉ型半導体層１０３と接している。即ち、ｉ型半導体層１０３は、ｐ型半導体層１０２の第１領域１０２ａ上に形成されている。第２領域１０２ｂは、第１領域１０２ａの下部に位置しており、基板１０１と接している。 The p-type semiconductor layer 102 includes a first region 102a that is an upper region on the i-type semiconductor layer 103 side and a second region 102b that is a lower region on the substrate 101 side. The first region 102 a forms the surface layer (uppermost layer) of the p-type semiconductor layer 102 and is in contact with the i-type semiconductor layer 103. That is, the i-type semiconductor layer 103 is formed on the first region 102 a of the p-type semiconductor layer 102. The second region 102b is located below the first region 102a and is in contact with the substrate 101.
　ｐ型半導体層１０２において、第１領域１０２ａにドープされているｐ型の不純物の濃度は、第２領域１０２ｂにドープされているｐ型の不純物の濃度よりも、低濃度である。具体的には、第１領域１０２ａには、第１領域１０２ａ上にｉ型半導体層１０３を形成する前のプロセス途中において第１領域１０２ａの表面が酸化しないような十分な低濃度で、ｐ型の不純物がドープされている。これにより、結晶性の良好なｉ型半導体層１０３（シリコンゲルマニウム層）をｐ型半導体層１０２上にエピタキシャル成長させることが可能である。一方、第２領域１０２ｂには、ｐ型半導体層１０２が十分大きな電気伝導度を有するように、第１領域１０２ａより高濃度でｐ型の不純物がドープされている。これにより、ｐ型半導体層１０２の抵抗値が低下し、ＳｉＧｅフォトダイオード１００を高速動作させることが可能である。 In the p-type semiconductor layer 102, the concentration of the p-type impurity doped in the first region 102a is lower than the concentration of the p-type impurity doped in the second region 102b. Specifically, in the first region 102a, the p-type is sufficiently low in concentration so that the surface of the first region 102a is not oxidized during the process before forming the i-type semiconductor layer 103 on the first region 102a. The impurities are doped. Thereby, the i-type semiconductor layer 103 (silicon germanium layer) with good crystallinity can be epitaxially grown on the p-type semiconductor layer 102. On the other hand, the second region 102b is doped with p-type impurities at a higher concentration than the first region 102a so that the p-type semiconductor layer 102 has a sufficiently large electrical conductivity. As a result, the resistance value of the p-type semiconductor layer 102 decreases, and the SiGe photodiode 100 can be operated at high speed.
　図２は、本発明の第２実施形態に係るＳｉＧｅフォトダイオード２００のＸＺ断面における模式的な断面構成を示した図である。ＳｉＧｅフォトダイオード２００は、ＳｉＧｅフォトダイオード１００のより詳細な構成を示したものである。ＳｉＧｅフォトダイオード２００は、埋め込み酸化膜層（ＢＯＸ層）２０２上に形成されたｐ型シリコン層２０３と、ｐ型シリコン層２０３上に形成されたｉ型ゲルマニウム層２０４と、ｉ型ゲルマニウム層２０４上に形成されたｎ型シリコンゲルマニウム層２０５とを備えており、ｐ型シリコン層２０３、ｉ型ゲルマニウム層２０４、及びｎ型シリコンゲルマニウム層２０５によるｐｉｎ構造を有している。ｐ型シリコン層２０３、ｉ型ゲルマニウム層２０４、及びｎ型シリコンゲルマニウム層２０５は、それぞれ、図１に示されたＳｉＧｅフォトダイオード１００のｐ型半導体層１０２、ｉ型半導体層１０３、ｎ型半導体層１０４に対応する。ＳｉＧｅフォトダイオード２００は、シリコン基板２０１、ＢＯＸ層２０２、及びＢＯＸ層２０２上のＳＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）層からなる、ＳＯＩ基板を利用して作製されている。 FIG. 2 is a diagram showing a schematic cross-sectional configuration in the XZ cross section of the SiGe photodiode 200 according to the second embodiment of the present invention. The SiGe photodiode 200 shows a more detailed configuration of the SiGe photodiode 100. The SiGe photodiode 200 includes a p-type silicon layer 203 formed on a buried oxide film layer (BOX layer) 202, an i-type germanium layer 204 formed on the p-type silicon layer 203, and an i-type germanium layer 204. The n-type silicon germanium layer 205 is formed, and has a pin structure of the p-type silicon layer 203, the i-type germanium layer 204, and the n-type silicon germanium layer 205. The p-type silicon layer 203, the i-type germanium layer 204, and the n-type silicon germanium layer 205 are respectively the p-type semiconductor layer 102, the i-type semiconductor layer 103, and the n-type semiconductor layer of the SiGe photodiode 100 shown in FIG. 104. The SiGe photodiode 200 is manufactured using an SOI substrate including a silicon substrate 201, a BOX layer 202, and an SOI (Silicon On Insulator) layer on the BOX layer 202.
　ｐ型シリコン層２０３は、ｐ型の不純物がドープされたシリコン（Ｓｉ）からなる層である。ｐ型の不純物として、例えばホウ素（Ｂ）を用いることができる。ｐ型シリコン層２０３は、ＢＯＸ層２０２上のＳＯＩ層にｐ型不純物をドープすることによって形成されている。 The p-type silicon layer 203 is a layer made of silicon (Si) doped with p-type impurities. For example, boron (B) can be used as the p-type impurity. The p-type silicon layer 203 is formed by doping a SOI layer on the BOX layer 202 with a p-type impurity.
　ｐ型シリコン層２０３は、ｉ型ゲルマニウム層２０４側の上部領域である第１領域２０３ａと、ＢＯＸ層２０２側の下部領域である第２領域２０３ｂとを有している。第１領域２０３ａ及び第２領域２０３ｂは、平面視においてｐ型シリコン層２０３の部分的な領域であり、当該領域上にｉ型ゲルマニウム層２０４が結晶成長することとなる領域である。第１領域２０３ａは、ｐ型シリコン層２０３の表層（最上部層）をなしており、ｉ型ゲルマニウム層２０４と接している。第２領域２０３ｂは、第１領域２０３ａの下部に位置しており、ＢＯＸ層２０２と接している。 The p-type silicon layer 203 has a first region 203a that is an upper region on the i-type germanium layer 204 side and a second region 203b that is a lower region on the BOX layer 202 side. The first region 203a and the second region 203b are partial regions of the p-type silicon layer 203 in plan view, and are regions where the i-type germanium layer 204 will grow on the regions. The first region 203 a forms the surface layer (uppermost layer) of the p-type silicon layer 203 and is in contact with the i-type germanium layer 204. The second region 203b is located below the first region 203a and is in contact with the BOX layer 202.
　第１領域２０３ａにドープされているｐ型不純物の濃度は、第２領域２０３ｂにドープされているｐ型不純物の濃度よりも、低濃度である。具体的には、第１領域２０３ａには、第１領域２０３ａの表面が酸化しないような十分な低濃度でｐ型不純物がドープされている。例えば、第１領域２０３ａにおけるｐ型不純物の濃度は、１×１０１９ｃｍ－３以下であることが好ましく、更には、１×１０１８ｃｍ－３程度とすることがより好適である。このような不純物濃度であれば、第１領域２０３ａの表面がプロセスの途中で酸素を含む雰囲気に露出した場合にも、第１領域２０３ａの表面の酸化を防止する効果が得られる。一方、第２領域２０３ｂには、ｐ型シリコン層２０３が十分大きな電気伝導度を有するように、第１領域２０３ａより高濃度でｐ型不純物がドープされている。例えば、第２領域２０３ｂにおけるｐ型不純物の濃度は、１×１０１９ｃｍ－３以上であることが好ましく、更には、１×１０２０ｃｍ－３程度とすることがより好適である。また、第２領域２０３ｂにおけるｐ型不純物の濃度は、ｐ型シリコン層２０３内でのキャリアプラズマ吸収を避けるために、５×１０１９ｃｍ－３ｃｍ－３以下であることが好ましい。 The concentration of the p-type impurity doped in the first region 203a is lower than the concentration of the p-type impurity doped in the second region 203b. Specifically, the first region 203a is doped with a p-type impurity at a sufficiently low concentration so that the surface of the first region 203a is not oxidized. For example, the concentration of the p-type impurity in the first region 203a is preferably 1 × 10 19 cm −3 or less, and more preferably about 1 × 10 18 cm −3 . With such an impurity concentration, the effect of preventing the oxidation of the surface of the first region 203a can be obtained even when the surface of the first region 203a is exposed to an oxygen-containing atmosphere during the process. On the other hand, the second region 203b is doped with p-type impurities at a higher concentration than the first region 203a so that the p-type silicon layer 203 has a sufficiently large electric conductivity. For example, the concentration of the p-type impurity in the second region 203b is preferably 1 × 10 19 cm −3 or more, and more preferably about 1 × 10 20 cm −3 . In addition, the concentration of the p-type impurity in the second region 203b is preferably 5 × 10 19 cm −3 cm −3 or less in order to avoid carrier plasma absorption in the p-type silicon layer 203.
　第１領域２０３ａの厚さは、できるだけ薄いことが望ましい。ｐ型シリコン層２０３の表層の非常に薄い領域の電位が、ｐ型シリコン層２０３の表面電位、即ちｐ型シリコン層２０３の表面における水素終端のしやすさに影響を与えると考えられるからである。例えば、第１領域２０３ａの厚さは、５０ｎｍ以下とすればよい。 It is desirable that the thickness of the first region 203a be as thin as possible. This is because the potential of a very thin region of the surface layer of the p-type silicon layer 203 is considered to affect the surface potential of the p-type silicon layer 203, that is, the ease of hydrogen termination on the surface of the p-type silicon layer 203. . For example, the thickness of the first region 203a may be 50 nm or less.
　ｐ型シリコン層２０３は、更に、第１領域２０３ａ及び第２領域２０３ｂの側部に第３領域２０３ｃを有している。第３領域２０３ｃは、平面視においてｐ型シリコン層２０３の部分的な領域であり、第１領域２０３ａ及び第２領域２０３ｂの端部から側方に延設されている領域である。第３領域２０３ｃにドープされているｐ型不純物の濃度は、第１領域２０３ａにドープされているｐ型不純物の濃度よりも、高濃度である。具体的には、第２領域２０３ｂと同様、第３領域２０３ｃには、ｐ型シリコン層２０３が十分大きな電気伝導度を有するように、第１領域２０３ａより高濃度でｐ型不純物がドープされている。例えば、第３領域２０３ｃにおけるｐ型不純物の濃度は、１×１０１９ｃｍ－３以上であることが好ましく、更には、１×１０２０ｃｍ－３程度とすることがより好適である。なお、第３領域２０３ｃのうち表層のみがｐ型不純物を高濃度に含んだ構成としてもよい。 The p-type silicon layer 203 further has a third region 203c on the side of the first region 203a and the second region 203b. The third region 203c is a partial region of the p-type silicon layer 203 in plan view, and is a region extending laterally from the end portions of the first region 203a and the second region 203b. The concentration of the p-type impurity doped in the third region 203c is higher than the concentration of the p-type impurity doped in the first region 203a. Specifically, like the second region 203b, the third region 203c is doped with p-type impurities at a higher concentration than the first region 203a so that the p-type silicon layer 203 has a sufficiently large electrical conductivity. Yes. For example, the concentration of the p-type impurity in the third region 203c is preferably 1 × 10 19 cm −3 or more, and more preferably about 1 × 10 20 cm −3 . Note that only the surface layer of the third region 203c may include a p-type impurity at a high concentration.
　ｉ型ゲルマニウム層２０４は、不純物がドープされていないゲルマニウム（Ｇｅ）からなる層である。ゲルマニウム層はシリコンゲルマニウム（ＳｉｘＧｅ１－ｘ）層の一例（即ちｘ＝０）である。ＳｉＧｅフォトダイオード２００のｉ型半導体層は、シリコンゲルマニウム層の一種であるゲルマニウム層から構成されている。以下、状況に応じて、ｉ型ゲルマニウム層２０４を第１シリコンゲルマニウム（ＳｉＧｅ）層とも称する。ｉ型ゲルマニウム層２０４は、ｐ型シリコン層２０３の第１領域２０３ａ上にゲルマニウムの結晶層をエピタキシャル成長させることによって形成されている。より詳細には、ｉ型ゲルマニウム層２０４は、その最下部が低温成長ゲルマニウム層２０４ａで構成されている。低温成長ゲルマニウム層２０４ａは、エピタキシャル成長時にｉ型ゲルマニウム層２０４のバッファ層（結晶歪緩和層）となる層である。上述したように、ｐ型シリコン層２０３の第１領域２０３ａは低濃度で不純物がドープされており、その表面は酸化されずにシリコンの結晶面が現れている。そのため、結晶性の良好な低温成長ゲルマニウム層２０４ａ及びｉ型ゲルマニウム層２０４をエピタキシャル成長させることが可能である。 The i-type germanium layer 204 is a layer made of germanium (Ge) that is not doped with impurities. The germanium layer is an example of a silicon germanium (Si x Ge 1-x ) layer (ie, x = 0). The i-type semiconductor layer of the SiGe photodiode 200 is composed of a germanium layer which is a kind of silicon germanium layer. Hereinafter, depending on the situation, the i-type germanium layer 204 is also referred to as a first silicon germanium (SiGe) layer. The i-type germanium layer 204 is formed by epitaxially growing a germanium crystal layer on the first region 203 a of the p-type silicon layer 203. More specifically, the i-type germanium layer 204 is configured with a low-temperature grown germanium layer 204a at the bottom. The low-temperature grown germanium layer 204a is a layer that becomes a buffer layer (crystal strain relaxation layer) of the i-type germanium layer 204 during epitaxial growth. As described above, the first region 203a of the p-type silicon layer 203 is doped with impurities at a low concentration, and the surface of the first region 203a is not oxidized and a silicon crystal plane appears. Therefore, the low temperature growth germanium layer 204a and the i-type germanium layer 204 with good crystallinity can be epitaxially grown.
　ｎ型シリコンゲルマニウム層２０５は、ｎ型の不純物がドープされたシリコンゲルマニウム（ＳｉｘＧｅ１－ｘ）からなる層である。ｎ型の不純物として、例えばリン（Ｐ）やヒ素（Ａｓ）等を用いることができる。ｎ型シリコンゲルマニウム層２０５の不純物濃度は、ｎ型シリコンゲルマニウム層２０５が十分大きな電気伝導度を有するように、例えば１×１０１９ｃｍ－３以上であることが好ましく、更には、１×１０２０ｃｍ－３程度とすることがより好適である。ｎ型シリコンゲルマニウム層２０５は、ｉ型ゲルマニウム層（第１シリコンゲルマニウム層）２０４の上面及び側面を覆うようにシリコンゲルマニウムの結晶層である第２シリコンゲルマニウム（ＳｉＧｅ）層２０５ａをエピタキシャル成長させ、更にこの第２シリコンゲルマニウム層２０５ａのうちｉ型ゲルマニウム層２０４の上面部分にｎ型不純物をドープすることによって形成されている。なお、ｉ型ゲルマニウム層２０４の側面を覆っている部分の第２シリコンゲルマニウム層２０５ａは、ｉ型ゲルマニウム層２０４の表面に存在する結晶欠陥に起因して生じるリーク電流を低減させるための保護膜として機能する。 The n-type silicon germanium layer 205 is a layer made of silicon germanium (Si x Ge 1-x ) doped with n-type impurities. For example, phosphorus (P), arsenic (As), or the like can be used as the n-type impurity. The impurity concentration of the n-type silicon germanium layer 205 is preferably 1 × 10 19 cm −3 or more, for example, so that the n-type silicon germanium layer 205 has a sufficiently large electric conductivity, and more preferably 1 × 10 20 More preferably, it is about cm −3 . The n-type silicon germanium layer 205 is obtained by epitaxially growing a second silicon germanium (SiGe) layer 205a, which is a silicon germanium crystal layer, so as to cover the upper surface and side surfaces of the i-type germanium layer (first silicon germanium layer) 204. Of the second silicon germanium layer 205a, the upper surface portion of the i-type germanium layer 204 is doped with an n-type impurity. The portion of the second silicon germanium layer 205a covering the side surface of the i-type germanium layer 204 serves as a protective film for reducing leakage current caused by crystal defects existing on the surface of the i-type germanium layer 204. Function.
　ＳｉＧｅフォトダイオード２００の表面は、絶縁膜２０６によって覆われている。絶縁膜２０６は、例えばＳｉＯ２膜である。絶縁膜２０６のうちｎ型シリコンゲルマニウム層２０５の上部には、ｎ型シリコンゲルマニウム層２０５の表面にまで達する開口が設けられており、当該開口内には第１金属電極２０７が形成されている。更に、絶縁膜２０６のうちｐ型シリコン層２０３の第３領域２０３ｃの上部（一部分）には、ｐ型シリコン層２０３の表面にまで達する開口が設けられており、当該開口内には第２金属電極２０８が形成されている。第１金属電極２０７及び第２金属電極２０８は、受光素子２００から電流を取り出すための電極である。 The surface of the SiGe photodiode 200 is covered with an insulating film 206. The insulating film 206 is, for example, a SiO 2 film. In the insulating film 206, an opening reaching the surface of the n-type silicon germanium layer 205 is provided above the n-type silicon germanium layer 205, and a first metal electrode 207 is formed in the opening. Furthermore, an opening reaching the surface of the p-type silicon layer 203 is provided in an upper part (a part) of the third region 203c of the p-type silicon layer 203 in the insulating film 206, and the second metal is contained in the opening. An electrode 208 is formed. The first metal electrode 207 and the second metal electrode 208 are electrodes for taking out current from the light receiving element 200.
　図３は、上述した本発明の第２実施形態に係るＳｉＧｅフォトダイオード２００のＹＺ断面における模式的な断面構成を示した図である。図３において、図２と同一の構成要素には同一の符号を付した。ＹＺ断面において、ＳｉＧｅフォトダイオード２００は、ＢＯＸ層２０２によって構成された下部クラッド層と、ＢＯＸ層２０２上のＳＯＩ層によって構成されたコア層２０９と、絶縁膜２０６によって構成された上部クラッド層とからなる、導波路２１０を備えている。下部クラッド層を構成するＢＯＸ層２０２、及び上部クラッド層を構成する絶縁膜２０６は、図２に示されたＢＯＸ層２０２及び絶縁膜２０６と共通のものである。コア層２０９を構成するＳＯＩ層は、図２に示されたｐ型シリコン層２０３を構成している不純物ドープ前のＳＯＩ層と共通のものである。コア層２０９は、共通のＳＯＩ層によりｐ型シリコン層２０３とシームレスに形成されている。このように、導波路２１０は、図２に示されたＳｉＧｅフォトダイオード２００のｐｉｎ構造が形成されているのと同じＳＯＩ基板を利用して、当該ｐｉｎ構造に隣接して形成されている。 FIG. 3 is a diagram showing a schematic cross-sectional configuration in the YZ cross section of the SiGe photodiode 200 according to the second embodiment of the present invention described above. In FIG. 3, the same components as those in FIG. In the YZ cross section, the SiGe photodiode 200 includes a lower clad layer constituted by the BOX layer 202, a core layer 209 constituted by the SOI layer on the BOX layer 202, and an upper clad layer constituted by the insulating film 206. A waveguide 210 is provided. The BOX layer 202 constituting the lower cladding layer and the insulating film 206 constituting the upper cladding layer are the same as the BOX layer 202 and the insulating film 206 shown in FIG. The SOI layer constituting the core layer 209 is the same as the SOI layer before impurity doping constituting the p-type silicon layer 203 shown in FIG. The core layer 209 is seamlessly formed with the p-type silicon layer 203 by a common SOI layer. Thus, the waveguide 210 is formed adjacent to the pin structure using the same SOI substrate on which the pin structure of the SiGe photodiode 200 shown in FIG. 2 is formed.
　ＳｉＧｅフォトダイオード２００は、導波路２１０のコア層２０９をＹ方向に伝搬してきた光がｐ型シリコン層２０３の側端部を介してｐ型シリコン層２０３へ入射するように構成されている。ｐ型シリコン層２０３へ入射した光は、ｐ型シリコン層２０３からｉ型ゲルマニウム層２０４へ次第に光のフィールドが移りながらｐｉｎ構造内をＹ方向に伝搬していき、ｉ型ゲルマニウム層２０４に光吸収される。ｉ型ゲルマニウム層２０４では、吸収した光に応じてキャリア（電子及びホール）が生成され、生成されたキャリアがそれぞれｐ型シリコン層２０３とｎ型シリコンゲルマニウム層２０５へ移動することによって、光電流が流れる。光電流は、第１金属電極２０７及び第２金属電極２０８から外部へ取り出される。ＳｉＧｅフォトダイオード２００は、ｐ型シリコン層２０３の第２領域２０３ｂと第３領域２０３ｃ、及びｎ型シリコンゲルマニウム層２０５の不純物濃度が高濃度であり大きな電気伝導度を有しているため、高周波で優れた動作特性を示すことができる。 The SiGe photodiode 200 is configured such that light propagating in the Y direction through the core layer 209 of the waveguide 210 is incident on the p-type silicon layer 203 via the side end portion of the p-type silicon layer 203. The light incident on the p-type silicon layer 203 propagates in the Y direction in the pin structure while the light field gradually moves from the p-type silicon layer 203 to the i-type germanium layer 204, and the i-type germanium layer 204 absorbs light. Is done. In the i-type germanium layer 204, carriers (electrons and holes) are generated according to the absorbed light, and the generated carriers move to the p-type silicon layer 203 and the n-type silicon germanium layer 205, respectively. Flowing. The photocurrent is extracted from the first metal electrode 207 and the second metal electrode 208 to the outside. In the SiGe photodiode 200, the second region 203b and the third region 203c of the p-type silicon layer 203 and the n-type silicon germanium layer 205 have a high impurity concentration and a large electric conductivity. Excellent operating characteristics can be shown.
　図４乃至図７は、上述した本発明の第２実施形態に係るＳｉＧｅフォトダイオード２００の製造方法を示す工程図である。以下、ＳｉＧｅフォトダイオード２００の製造方法について説明する。 4 to 7 are process diagrams showing a method of manufacturing the SiGe photodiode 200 according to the second embodiment of the present invention described above. Hereinafter, a method for manufacturing the SiGe photodiode 200 will be described.
　まず、図４に示されるように、ＳＯＩ基板のＳＯＩ層にｐ型シリコン層２０３の第１領域２０３ａ及び第２領域２０３ｂを形成する。具体的には、シリコン基板２０１、ＢＯＸ層２０２、及びＳＯＩ層２１１からなるＳＯＩ基板を用意し、ＳＯＩ層２１１上にレジスト膜２１２を形成する。レジスト膜２１２は、第１領域２０３ａとなる部分に開口を有するように露光・現像によって加工される。この開口を通して、ｐ型不純物（例えばホウ素（Ｂ））がＳＯＩ層２１１の内部へドープされて、ｐ型シリコン層２０３の第１領域２０３ａと第２領域２０３ｂが形成される。ｐ型不純物は、イオン注入によってドープされる。この時、イオン（Ｂ＋）の加速エネルギーでイオンが注入される深さを制御することができる。具体的には、加速エネルギーは、注入されたイオンの濃度のピークが第２領域２０３ｂにくるようなエネルギーに設定される。これにより、不純物濃度が低濃度である第１領域２０３ａと、不純物濃度が高濃度である第２領域２０３ｂとを有したｐ型シリコン層２０３が形成される。その後、レジスト膜２１２を除去する。 First, as shown in FIG. 4, the first region 203a and the second region 203b of the p-type silicon layer 203 are formed in the SOI layer of the SOI substrate. Specifically, an SOI substrate including a silicon substrate 201, a BOX layer 202, and an SOI layer 211 is prepared, and a resist film 212 is formed on the SOI layer 211. The resist film 212 is processed by exposure / development so as to have an opening in a portion to be the first region 203a. Through this opening, a p-type impurity (for example, boron (B)) is doped into the SOI layer 211 to form the first region 203 a and the second region 203 b of the p-type silicon layer 203. The p-type impurity is doped by ion implantation. At this time, the depth at which ions are implanted can be controlled by the acceleration energy of ions (B + ). Specifically, the acceleration energy is set to such an energy that the peak of the concentration of implanted ions comes to the second region 203b. As a result, a p-type silicon layer 203 having a first region 203a having a low impurity concentration and a second region 203b having a high impurity concentration is formed. Thereafter, the resist film 212 is removed.
　なお、図４はＸＺ断面を示しており、そのため図４にはコア層２０９が描かれていないが、図４の工程に先立って、又は図４の工程の後に、ＳＯＩ層２１１をフォトリソグラフィ及びエッチングによって所望のパターンに加工することによって、ＳＯＩ層２１１からコア層２０９（図３参照）が形成される。 Note that FIG. 4 shows an XZ cross section, and thus the core layer 209 is not drawn in FIG. 4. However, prior to or after the step of FIG. A core layer 209 (see FIG. 3) is formed from the SOI layer 211 by processing into a desired pattern by etching.
　次に、図５に示されるように、ＳＯＩ基板のＳＯＩ層にｐ型シリコン層２０３の第３領域２０３ｃを形成する。具体的には、図４の工程と同様に、第３領域２０３ｃとなる部分に開口を有するレジスト膜２１３をＳＯＩ層２１１上に形成し、レジスト膜２１３の開口を通してイオン注入によりｐ型不純物をＳＯＩ層２１１の内部へドープすることによって、ｐ型シリコン層２０３の第３領域２０３ｃが形成される。その後、レジスト膜２１３を除去する。 Next, as shown in FIG. 5, the third region 203c of the p-type silicon layer 203 is formed in the SOI layer of the SOI substrate. Specifically, as in the step of FIG. 4, a resist film 213 having an opening in the portion to be the third region 203c is formed on the SOI layer 211, and p-type impurities are doped by ion implantation through the opening of the resist film 213. By doping into the layer 211, the third region 203c of the p-type silicon layer 203 is formed. Thereafter, the resist film 213 is removed.
　次に、図６に示されるように、ｐ型シリコン層２０３の第１領域２０３ａ上にｉ型ゲルマニウム層２０４を形成する。具体的には、まずｐ型シリコン層２０３上にＳｉＯ２膜を成膜し、第１領域２０３ａに開口を有するようにこのＳｉＯ２膜をフォトリソグラフィ及びエッチングによって加工することにより、ＳｉＯ２マスク２１４を作成する。次いで、ＳｉＯ２マスク２１４の開口部分に、エピタキシャル成長によって低温成長ゲルマニウム層２０４ａ及びｉ型ゲルマニウム層２０４を順次形成する。前述したように、ｐ型シリコン層２０３の第１領域２０３ａの表面は酸化されずにシリコンの結晶面が現れているため、結晶性の良好な低温成長ゲルマニウム層２０４ａ及びｉ型ゲルマニウム層２０４をエピタキシャル成長させることが可能である。 Next, as shown in FIG. 6, an i-type germanium layer 204 is formed on the first region 203 a of the p-type silicon layer 203. Specifically, the SiO 2 film is formed first on a p-type silicon layer 203, by the SiO 2 film so as to have an opening in the first region 203a is processed by photolithography and etching, SiO 2 mask 214 Create Next, the low temperature growth germanium layer 204a and the i-type germanium layer 204 are sequentially formed in the opening portion of the SiO 2 mask 214 by epitaxial growth. As described above, since the surface of the first region 203a of the p-type silicon layer 203 is not oxidized and the silicon crystal plane appears, the low-temperature grown germanium layer 204a and the i-type germanium layer 204 with good crystallinity are epitaxially grown. It is possible to make it.
　次に、図７に示されるように、ｉ型ゲルマニウム層２０４上にｎ型シリコンゲルマニウム層２０５を形成する。具体的には、まず低温成長ゲルマニウム層２０４ａ及びｉ型ゲルマニウム層２０４からなる第１シリコンゲルマニウム層を覆うように、第２シリコンゲルマニウム層２０５ａをエピタキシャル成長させる。次いで、ｉ型ゲルマニウム層２０４の上部に開口を有するレジスト膜２１５を形成し、このレジスト膜２１５の開口を通してｉ型ゲルマニウム層２０４の上面部分の第２シリコンゲルマニウム層２０５ａへイオン注入によりｎ型不純物（例えばリン（Ｐ）やヒ素（Ａｓ）等）をドープすることによって、ｎ型シリコンゲルマニウム層２０５が形成される。 Next, as shown in FIG. 7, an n-type silicon germanium layer 205 is formed on the i-type germanium layer 204. Specifically, first, the second silicon germanium layer 205a is epitaxially grown so as to cover the first silicon germanium layer composed of the low-temperature grown germanium layer 204a and the i-type germanium layer 204. Next, a resist film 215 having an opening is formed on the i-type germanium layer 204, and an n-type impurity (by ion implantation into the second silicon germanium layer 205 a on the upper surface portion of the i-type germanium layer 204 through the opening of the resist film 215. For example, the n-type silicon germanium layer 205 is formed by doping phosphorus (P), arsenic (As), or the like.
　最後に、第１金属電極２０７及び第２金属電極２０８を形成する（図２参照）。具体的には、まずｎ型シリコンゲルマニウム層２０５及びｐ型シリコン層２０３を覆うように絶縁膜２０６を成膜する。次いで、成膜した絶縁膜２０６のうちｎ型シリコンゲルマニウム層２０５の上部及びｐ型シリコン層２０３の第３領域２０３ｃの上部（一部分）に、フォトリソグラフィ及びエッチングによって、それぞれｎ型シリコンゲルマニウム層２０５の表面及びｐ型シリコン層２０３の表面にまで達する開口を形成する。そして、これらの開口の内部を金属材料で充填することによって、第１金属電極２０７及び第２金属電極２０８が形成される。 Finally, the first metal electrode 207 and the second metal electrode 208 are formed (see FIG. 2). Specifically, first, an insulating film 206 is formed so as to cover the n-type silicon germanium layer 205 and the p-type silicon layer 203. Next, the n-type silicon germanium layer 205 is formed on the upper part of the n-type silicon germanium layer 205 and the upper part (a part) of the third region 203c of the p-type silicon layer 203 by photolithography and etching, respectively. An opening reaching the surface and the surface of the p-type silicon layer 203 is formed. Then, the first metal electrode 207 and the second metal electrode 208 are formed by filling the inside of these openings with a metal material.
　以上の工程により、図２及び図３に示されるＳｉＧｅフォトダイオード２００が完成する。 Through the above steps, the SiGe photodiode 200 shown in FIGS. 2 and 3 is completed.
　図８は、本発明の第３実施形態に係るＳｉＧｅフォトダイオード３００の模式的な断面構成を示した図である。ＳｉＧｅフォトダイオード３００は、ＸＺ断面及びＹＺ断面において同一の構造を有する。図８において、前述した第２実施形態に係るＳｉＧｅフォトダイオード２００と同一の構成要素には同一の符号を付した。ＳｉＧｅフォトダイオード３００は、ｎ型シリコンゲルマニウム層２０５の上部において第１金属電極３０１の中央部にｎ型シリコンゲルマニウム層２０５の表面にまで達する開口が設けられており、当該開口内に透明な保護膜３０２が形成されている点が、第２実施形態に係るＳｉＧｅフォトダイオード２００と異なる。保護膜３０２は、例えばＳｉＯ２膜である。ＳｉＧｅフォトダイオード３００のその他の部分の構成は、第２実施形態に係るＳｉＧｅフォトダイオード２００と同一である。 FIG. 8 is a diagram showing a schematic cross-sectional configuration of a SiGe photodiode 300 according to the third embodiment of the present invention. The SiGe photodiode 300 has the same structure in the XZ cross section and the YZ cross section. In FIG. 8, the same components as those of the SiGe photodiode 200 according to the second embodiment described above are denoted by the same reference numerals. In the SiGe photodiode 300, an opening reaching the surface of the n-type silicon germanium layer 205 is provided at the center of the first metal electrode 301 above the n-type silicon germanium layer 205, and a transparent protective film is formed in the opening. The point where 302 is formed is different from the SiGe photodiode 200 according to the second embodiment. The protective film 302 is a SiO 2 film, for example. The configuration of other parts of the SiGe photodiode 300 is the same as that of the SiGe photodiode 200 according to the second embodiment.
　ＳｉＧｅフォトダイオード３００は、ｎ型シリコンゲルマニウム層２０５の上方向からの光が保護膜３０２とｎ型シリコンゲルマニウム層２０５を介してｉ型ゲルマニウム層２０４へ入射するように構成されている。入射した光はｉ型ゲルマニウム層２０４に吸収されて、ＳｉＧｅフォトダイオード２００の場合と同様に、ｉ型ゲルマニウム層２０４では、吸収した光に応じてキャリア（電子及びホール）が生成され、生成されたキャリアがそれぞれｐ型シリコン層２０３とｎ型シリコンゲルマニウム層２０５へ移動することによって、光電流が流れる。光電流は、第１金属電極３０１及び第２金属電極２０８から外部へ取り出される。 The SiGe photodiode 300 is configured such that light from above the n-type silicon germanium layer 205 is incident on the i-type germanium layer 204 via the protective film 302 and the n-type silicon germanium layer 205. The incident light is absorbed by the i-type germanium layer 204, and similarly to the SiGe photodiode 200, the i-type germanium layer 204 generates and generates carriers (electrons and holes) according to the absorbed light. The carriers move to the p-type silicon layer 203 and the n-type silicon germanium layer 205, respectively, and a photocurrent flows. The photocurrent is extracted from the first metal electrode 301 and the second metal electrode 208 to the outside.
　図９は、本発明の第４実施形態に係るＳｉＧｅフォトダイオード４００のＸＺ断面における模式的な断面構成を示した図である。図１０は、当該ＳｉＧｅフォトダイオード４００のＹＺ断面における模式的な断面構成を示した図である。図９及び図１０において、前述した第２実施形態に係るＳｉＧｅフォトダイオード２００と同一の構成要素には同一の符号を付した。ＳｉＧｅフォトダイオード４００は、ｉ型ゲルマニウム層２０４の側部にエピタキシャル成長によって形成されたシリコン層４０１及び４０２を有している点が、第２実施形態に係るＳｉＧｅフォトダイオード２００と異なる。ＳｉＧｅフォトダイオード４００のその他の部分の構成は、第２実施形態に係るＳｉＧｅフォトダイオード２００と同一である。 FIG. 9 is a diagram showing a schematic cross-sectional configuration in the XZ cross section of the SiGe photodiode 400 according to the fourth embodiment of the present invention. FIG. 10 is a diagram showing a schematic cross-sectional configuration of the SiGe photodiode 400 in the YZ cross section. 9 and 10, the same components as those in the SiGe photodiode 200 according to the second embodiment described above are denoted by the same reference numerals. The SiGe photodiode 400 is different from the SiGe photodiode 200 according to the second embodiment in that the SiGe photodiode 400 includes silicon layers 401 and 402 formed by epitaxial growth on the side portion of the i-type germanium layer 204. The structure of other parts of the SiGe photodiode 400 is the same as that of the SiGe photodiode 200 according to the second embodiment.
　シリコン層４０２は、導波路２１０のコア層２０９上に形成されている。シリコン層４０２の側面のうち絶縁膜２０６（上部クラッド層）との界面をなしている側面４０２ａは、基板面（ＸＹ面）に対して傾斜した斜面として構成されている。これにより、コア層２０９とシリコン層４０２とからなる導波路２１０の実質的なコア層の厚さは、図１０においてＹ方向に行くほど厚くなっている。即ち、シリコン層４０２は、導波路２１０の実質的なコア層の厚さを変化させるテーパ型コア層である。このように、導波路２１０は、高さ方向（Ｚ方向）にコア層の厚さが変化するテーパ型導波路を構成している。 The silicon layer 402 is formed on the core layer 209 of the waveguide 210. Of the side surfaces of the silicon layer 402, a side surface 402a that forms an interface with the insulating film 206 (upper cladding layer) is configured as an inclined surface that is inclined with respect to the substrate surface (XY plane). Thus, the substantial core layer thickness of the waveguide 210 composed of the core layer 209 and the silicon layer 402 becomes thicker in the Y direction in FIG. That is, the silicon layer 402 is a tapered core layer that changes the thickness of the substantial core layer of the waveguide 210. Thus, the waveguide 210 constitutes a tapered waveguide whose thickness of the core layer changes in the height direction (Z direction).
　ＳｉＧｅフォトダイオード４００において、導波路２１０のコア層２０９をＹ方向に伝搬してきた光は、コア層２０９とシリコン層４０２とからなるテーパ型導波路の部分で光のフィールドがシリコン層４０２の側へ拡大して、Ｙ方向に更に進む。このフィールドが拡大した光は、ｐ型シリコン層２０３の側端部を介してだけでなく、ｉ型ゲルマニウム層２０４の側端部からも直接、ｉ型ゲルマニウム層２０４へと入射される。よって、ＳｉＧｅフォトダイオード４００は、導波路２１０のコア層２０９をＹ方向に伝搬してきた光を効率良くｉ型ゲルマニウム層２０４へ入射させることが可能である。ｉ型ゲルマニウム層２０４では、ＳｉＧｅフォトダイオード２００の場合と同様に、入射された光が吸収されてキャリア（電子及びホール）が生成され、生成されたキャリアがそれぞれｐ型シリコン層２０３とｎ型シリコンゲルマニウム層２０５へ移動することによって、光電流が流れる。光電流は、第１金属電極２０７及び第２金属電極２０８から外部へ取り出される。 In the SiGe photodiode 400, the light propagating in the Y direction in the core layer 209 of the waveguide 210 is a portion of the tapered waveguide composed of the core layer 209 and the silicon layer 402, and the light field is directed to the silicon layer 402 side. Zoom in and go further in the Y direction. The light whose field is expanded is incident not only on the side end portion of the p-type silicon layer 203 but also directly on the i-type germanium layer 204 from the side end portion of the i-type germanium layer 204. Therefore, the SiGe photodiode 400 can efficiently make the light propagating in the Y direction through the core layer 209 of the waveguide 210 incident on the i-type germanium layer 204. In the i-type germanium layer 204, as in the case of the SiGe photodiode 200, incident light is absorbed to generate carriers (electrons and holes), and the generated carriers are respectively converted into the p-type silicon layer 203 and the n-type silicon. By moving to the germanium layer 205, a photocurrent flows. The photocurrent is extracted from the first metal electrode 207 and the second metal electrode 208 to the outside.
　図１１乃至図１６は、上述した本発明の第４実施形態に係るＳｉＧｅフォトダイオード４００の製造方法を示す工程図である。以下、ＳｉＧｅフォトダイオード４００の製造方法について説明する。 11 to 16 are process diagrams showing a method of manufacturing the SiGe photodiode 400 according to the fourth embodiment of the present invention described above. Hereinafter, a method for manufacturing the SiGe photodiode 400 will be described.
　はじめに、図１１に示されるように、ＢＯＸ層２０２上にｐ型シリコン層２０３及びコア層２０９を形成する。これは、第２実施形態に係るＳｉＧｅフォトダイオード２００の製造方法で説明した図４及び図５の工程と同じ工程である。ｐ型シリコン層２０３は、第１領域２０３ａの不純物濃度が低濃度、第２領域２０３ｂの不純物濃度が高濃度になるように形成される。なお、図１１はＹＺ断面を示しているため、図１１にはｐ型シリコン層２０３の第３領域２０３ｃは描かれていない。 First, as shown in FIG. 11, a p-type silicon layer 203 and a core layer 209 are formed on the BOX layer 202. This is the same process as the process of FIGS. 4 and 5 described in the method of manufacturing the SiGe photodiode 200 according to the second embodiment. The p-type silicon layer 203 is formed so that the impurity concentration of the first region 203a is low and the impurity concentration of the second region 203b is high. 11 shows a YZ cross section, the third region 203c of the p-type silicon layer 203 is not drawn in FIG.
　次に、図１２に示されるように、コア層２０９の一部分及びｐ型シリコン層２０３の第１領域２０３ａを覆うようにシリコン層４０３を形成する。具体的には、まずコア層２０９及びｐ型シリコン層２０３の全面にＳｉＯ２膜を成膜し、コア層２０９の一部分及びｐ型シリコン層２０３の第１領域２０３ａが露出するようにこのＳｉＯ２膜をフォトリソグラフィ及びエッチングによって加工することにより、ＳｉＯ２マスク４０４を作成する。次いで、ＳｉＯ２マスク４０４の開口部分に、エピタキシャル成長によってシリコン層４０３を形成する。この時、成長したシリコン層４０３の結晶面（ファセット）により、斜面４０２ａが形作られる。斜面４０２ａは、上述したように、テーパ型コア層を構成する面である。 Next, as shown in FIG. 12, a silicon layer 403 is formed so as to cover a part of the core layer 209 and the first region 203 a of the p-type silicon layer 203. Specifically, first, an SiO 2 film is formed on the entire surface of the core layer 209 and the p-type silicon layer 203, and this SiO 2 is exposed so that a part of the core layer 209 and the first region 203a of the p-type silicon layer 203 are exposed. A SiO 2 mask 404 is formed by processing the film by photolithography and etching. Next, a silicon layer 403 is formed in the opening portion of the SiO 2 mask 404 by epitaxial growth. At this time, an inclined surface 402 a is formed by the crystal plane (facet) of the grown silicon layer 403. As described above, the slope 402a is a surface constituting the tapered core layer.
　次に、図１３に示されるように、シリコン層４０３を覆うように絶縁膜２０６を成膜し、成膜した絶縁膜２０６のうちｐ型シリコン層２０３の第１領域２０３ａの上部をフォトリソグラフィ及びエッチングによって除去して開口を形成する。 Next, as shown in FIG. 13, an insulating film 206 is formed so as to cover the silicon layer 403, and the upper part of the first region 203a of the p-type silicon layer 203 in the formed insulating film 206 is subjected to photolithography and An opening is formed by etching.
　次に、図１４に示されるように、絶縁膜２０６の開口からシリコン層４０３の一部分をエッチングして、ｐ型シリコン層２０３の第１領域２０３ａを露出させる。シリコン層４０３のエッチングには、例えば、アルカリ溶液による異方性ウェットエッチングが適用される。エッチングで残ったシリコン層４０３のうちコア層２０９の上部の部分は、テーパ型コア層４０２となる。 Next, as shown in FIG. 14, a part of the silicon layer 403 is etched from the opening of the insulating film 206 to expose the first region 203 a of the p-type silicon layer 203. For the etching of the silicon layer 403, for example, anisotropic wet etching with an alkaline solution is applied. Of the silicon layer 403 remaining after etching, the upper part of the core layer 209 becomes a tapered core layer 402.
　次に、図１５に示されるように、露出したｐ型シリコン層２０３の第１領域２０３ａ上にｉ型ゲルマニウム層２０４を形成する。具体的には、絶縁膜２０６の開口を通して、エピタキシャル成長によって低温成長ゲルマニウム層２０４ａ及びｉ型ゲルマニウム層２０４を順次形成する。低温成長ゲルマニウム層２０４ａ及びｉ型ゲルマニウム層２０４は、絶縁膜２０６の開口内のテーパ型コア層４０２及びシリコン層４０１をマスクとして、結晶成長する。前述したように、ｐ型シリコン層２０３の第１領域２０３ａの表面は酸化されずにシリコンの結晶面が現れているため、結晶性の良好な低温成長ゲルマニウム層２０４ａ及びｉ型ゲルマニウム層２０４をエピタキシャル成長させることが可能である。 Next, as shown in FIG. 15, an i-type germanium layer 204 is formed on the exposed first region 203 a of the p-type silicon layer 203. Specifically, the low-temperature grown germanium layer 204a and the i-type germanium layer 204 are sequentially formed by epitaxial growth through the opening of the insulating film 206. The low-temperature grown germanium layer 204a and the i-type germanium layer 204 are crystal-grown using the tapered core layer 402 and the silicon layer 401 in the opening of the insulating film 206 as masks. As described above, since the surface of the first region 203a of the p-type silicon layer 203 is not oxidized and the silicon crystal plane appears, the low-temperature grown germanium layer 204a and the i-type germanium layer 204 with good crystallinity are epitaxially grown. It is possible to make it.
　次に、図１６に示されるように、ｉ型ゲルマニウム層２０４上にｎ型シリコンゲルマニウム層２０５を形成する。具体的には、まずｉ型ゲルマニウム層２０４（第１シリコンゲルマニウム層）上にエピタキシャル成長によってシリコンゲルマニウムの結晶層（第２シリコンゲルマニウム層）を成長させる。次いで、このシリコンゲルマニウム結晶層にイオン注入によりｎ型不純物（例えばリン（Ｐ）やヒ素（Ａｓ）等）をドープすることによって、ｎ型シリコンゲルマニウム層２０５が形成される。 Next, as shown in FIG. 16, an n-type silicon germanium layer 205 is formed on the i-type germanium layer 204. Specifically, first, a silicon germanium crystal layer (second silicon germanium layer) is grown on the i-type germanium layer 204 (first silicon germanium layer) by epitaxial growth. Next, an n-type silicon germanium layer 205 is formed by doping the silicon germanium crystal layer with an n-type impurity (for example, phosphorus (P) or arsenic (As)) by ion implantation.
　最後に、第１金属電極２０７及び第２金属電極２０８を形成する（図９及び図１０参照）。具体的には、絶縁膜２０６のうちｐ型シリコン層２０３の第３領域２０３ｃの上部（一部分）に、フォトリソグラフィ及びエッチングによってｐ型シリコン層２０３の表面にまで達する開口を形成し、この開口の内部、及び図１３の工程で形成した絶縁膜２０６の開口の内部を金属材料で充填することによって、第１金属電極２０７及び第２金属電極２０８が形成される。 Finally, the first metal electrode 207 and the second metal electrode 208 are formed (see FIGS. 9 and 10). Specifically, an opening reaching the surface of the p-type silicon layer 203 is formed by photolithography and etching in an upper part (a part) of the third region 203c of the p-type silicon layer 203 in the insulating film 206. A first metal electrode 207 and a second metal electrode 208 are formed by filling the inside and the inside of the opening of the insulating film 206 formed in the step of FIG. 13 with a metal material.
　以上の工程により、図９及び図１０に示されるＳｉＧｅフォトダイオード４００が完成する。 Through the above steps, the SiGe photodiode 400 shown in FIGS. 9 and 10 is completed.
　以上、本発明の実施形態を説明したが、本発明はこれに限定されず、その要旨を逸脱しない範囲内において様々な変更が可能である。変形例のいくつかを以下に述べる。 As mentioned above, although embodiment of this invention was described, this invention is not limited to this, A various change is possible within the range which does not deviate from the summary. Some of the modifications will be described below.
　第１実施形態乃至第４実施形態において、ｐ型半導体層１０２の第１領域１０２ａ及びｐ型シリコン層２０３の第１領域２０３ａは、均一な不純物濃度を有する領域であってもよいし、不純物の濃度分布（濃度勾配）を有する領域であってもよい。同様に、ｐ型半導体層１０２の第２領域１０２ｂ及びｐ型シリコン層２０３の第２領域２０３ｂは、均一な不純物濃度を有する領域であってもよいし、不純物の濃度分布（濃度勾配）を有する領域であってもよい。即ち、第１実施形態乃至第４実施形態において、ｐ型半導体層１０２及びｐ型シリコン層２０３は、ｉ型半導体層１０３及びｉ型ゲルマニウム層２０４と接する側の表面における不純物濃度が、内部（即ち当該表面よりも下部側）の不純物濃度よりも低濃度となるように形成されていることが必要であるが、第１領域（１０２ａ、２０３ａ）及び第２領域（１０２ｂ、２０３ｂ）の各領域内における濃度分布は不問である。一例として、ｐ型半導体層１０２及びｐ型シリコン層２０３は、表面からの深さが深くなるにつれて次第に不純物濃度が高くなるように形成されていてもよい。また、ｐ型半導体層１０２及びｐ型シリコン層２０３は、表面からの深さが深くなるにつれて次第に不純物濃度が高くなり、深さの中央付近において不純物濃度が最大となり、深さがそれよりも深くなると次第に不純物濃度が低くなるように形成されていてもよい。 In the first to fourth embodiments, the first region 102a of the p-type semiconductor layer 102 and the first region 203a of the p-type silicon layer 203 may be regions having a uniform impurity concentration, It may be a region having a concentration distribution (concentration gradient). Similarly, the second region 102b of the p-type semiconductor layer 102 and the second region 203b of the p-type silicon layer 203 may be regions having a uniform impurity concentration or have an impurity concentration distribution (concentration gradient). It may be a region. That is, in the first to fourth embodiments, the p-type semiconductor layer 102 and the p-type silicon layer 203 have an internal impurity concentration (that is, an impurity concentration on the surface in contact with the i-type semiconductor layer 103 and the i-type germanium layer 204). It is necessary that the impurity concentration be lower than the impurity concentration on the lower side of the surface), but in each region of the first region (102a, 203a) and the second region (102b, 203b). The concentration distribution in is unquestioned. As an example, the p-type semiconductor layer 102 and the p-type silicon layer 203 may be formed so that the impurity concentration gradually increases as the depth from the surface increases. In addition, the p-type semiconductor layer 102 and the p-type silicon layer 203 gradually increase in impurity concentration as the depth from the surface becomes deeper, the impurity concentration becomes maximum near the center of the depth, and the depth is deeper than that. Then, the impurity concentration may be gradually decreased.
　第１実施形態乃至第４実施形態において、ｐ型半導体層１０２及びｐ型シリコン層２０３は、第２領域１０２ｂ、２０３ｂの下部に、第２領域１０２ｂ、２０３ｂよりも不純物濃度が低濃度である第４領域を更に備えていてもよい。即ち、ｐ型半導体層１０２及びｐ型シリコン層２０３は、下から順に低濃度の第４領域、高濃度の第２領域１０２ｂ、２０３ｂ、低濃度の第１領域が積層した３層構造であってもよい。 In the first to fourth embodiments, the p-type semiconductor layer 102 and the p-type silicon layer 203 are lower in impurity concentration than the second regions 102b and 203b below the second regions 102b and 203b. Four regions may be further provided. That is, the p-type semiconductor layer 102 and the p-type silicon layer 203 have a three-layer structure in which a low-concentration fourth region, high-concentration second regions 102b and 203b, and a low-concentration first region are stacked in order from the bottom. Also good.
　第２実施形態乃至第４実施形態において、ｐ型シリコン層２０３の第３領域２０３ｃは、その上層側（第２金属電極２０８と接する側）が不純物濃度の高い層で構成され、下層側が不純物濃度の低い層で構成されてもよい。 In the second to fourth embodiments, the third region 203c of the p-type silicon layer 203 is composed of a layer having a high impurity concentration on the upper layer side (side in contact with the second metal electrode 208), and the impurity concentration on the lower layer side. May be composed of a low layer.
　第２実施形態乃至第４実施形態において、ｉ型ゲルマニウム層２０４に代えて、シリコンとゲルマニウムの組成比ｘが例えば０＜ｘ≦０．５の範囲のｉ型シリコンゲルマニウム（ＳｉｘＧｅ１－ｘ）層を採用してもよい。使用波長に応じて、最適な組成比ｘを選択してもよい。 In the second to fourth embodiments, instead of the i-type germanium layer 204, i-type silicon germanium (Si x Ge 1-x) in which the composition ratio x of silicon and germanium is in the range of 0 <x ≦ 0.5, for example. ) Layer may be employed. The optimum composition ratio x may be selected according to the wavelength used.
　第２実施形態乃至第４実施形態において、ｎ型シリコンゲルマニウム層２０５に代えて、ｎ型シリコン層を採用してもよい。 In the second to fourth embodiments, an n-type silicon layer may be employed instead of the n-type silicon germanium layer 205.
　第２実施形態乃至第４実施形態において、ｉ型の第１シリコンゲルマニウム層２０４におけるシリコンとゲルマニウムの組成比と、ｎ型の第２シリコンゲルマニウム層２０５におけるシリコンとゲルマニウムの組成比は、異なっていてもよいし、同じであってもよい。例えば、第１シリコンゲルマニウム層２０４におけるシリコンの組成よりも、第２シリコンゲルマニウム層２０５におけるシリコンの組成を大きくしてもよい。第１シリコンゲルマニウム層２０４を保護する保護膜（第２シリコンゲルマニウム層２０５）としては、純粋なシリコン層の方が安定で好ましいが、第１シリコンゲルマニウム層２０４上にシリコンを結晶性良く成長させることは、シリコンとシリコンゲルマニウムとで結晶格子定数の相違が大きいことから難しい。また、第２シリコンゲルマニウム層２０５が純粋なシリコン層である場合、ｎ型不純物をドーピングした後に必要な活性化アニール温度が高くなり、ドープされた不純物が拡散しやすくなってしまう。活性化アニール温度を低くすることにより、不純物の拡散を抑制することができるが、不純物の活性化が不十分となったり、イオン注入による結晶欠陥の回復が不十分となったりしてしまう。これらのことから、第２シリコンゲルマニウム層２０５は、純粋なシリコン層ではなく、シリコンゲルマニウム層とした方がよい。 In the second to fourth embodiments, the composition ratio of silicon and germanium in the i-type first silicon germanium layer 204 is different from the composition ratio of silicon and germanium in the n-type second silicon germanium layer 205. Or the same. For example, the silicon composition in the second silicon germanium layer 205 may be larger than the silicon composition in the first silicon germanium layer 204. As the protective film (second silicon germanium layer 205) for protecting the first silicon germanium layer 204, a pure silicon layer is more stable and preferable, but silicon is grown on the first silicon germanium layer 204 with good crystallinity. Is difficult because of the large difference in crystal lattice constant between silicon and silicon germanium. In addition, when the second silicon germanium layer 205 is a pure silicon layer, the activation annealing temperature required after doping the n-type impurity becomes high, and the doped impurity is likely to diffuse. Although the diffusion of impurities can be suppressed by lowering the activation annealing temperature, the activation of the impurities becomes insufficient and the recovery of crystal defects due to ion implantation becomes insufficient. For these reasons, the second silicon germanium layer 205 is preferably not a pure silicon layer but a silicon germanium layer.
　第２実施形態乃至第４実施形態において、第１シリコンゲルマニウム層２０４の表層部（第２シリコンゲルマニウム層２０５と接している領域）にｎ型の不純物がドープされた構成としてもよい。この構成では、第１シリコンゲルマニウム層２０４の表層部の抵抗が下がるので、ＳｉＧｅフォトダイオードの高周波における動作特性を更に向上させることができる。第１シリコンゲルマニウム層２０４の表層部へのｎ型不純物のドーピングは、第２シリコンゲルマニウム層２０５へｎ型不純物をドーピングする工程（第２実施形態で説明した図７の工程及び第４実施形態で説明した図１６の工程）で行うことができる。例えば、第２シリコンゲルマニウム層２０５の厚さが薄い場合には、第２シリコンゲルマニウム層２０５へイオン注入でｎ型不純物をドーピングする際に、ｎ型不純物の一部は、第２シリコンゲルマニウム層２０５を通り抜けて第１シリコンゲルマニウム層２０４の表層へドープされる。または、イオン注入の加速エネルギーを変えて、第２シリコンゲルマニウム層２０５へのイオン注入と第１シリコンゲルマニウム層２０４へのイオン注入を２段階で行ってもよい。 In the second embodiment to the fourth embodiment, the surface layer portion of the first silicon germanium layer 204 (region in contact with the second silicon germanium layer 205) may be doped with n-type impurities. In this configuration, since the resistance of the surface layer portion of the first silicon germanium layer 204 is lowered, the operating characteristics at high frequencies of the SiGe photodiode can be further improved. The doping of the n-type impurity into the surface layer portion of the first silicon germanium layer 204 is performed by the step of doping the second silicon germanium layer 205 with the n-type impurity (the process of FIG. 7 and the fourth embodiment described in the second embodiment). This can be performed in the step shown in FIG. For example, when the thickness of the second silicon germanium layer 205 is thin, when the n-type impurity is doped into the second silicon germanium layer 205 by ion implantation, a part of the n-type impurity is part of the second silicon germanium layer 205. And doped into the surface layer of the first silicon germanium layer 204. Alternatively, by changing the acceleration energy of ion implantation, ion implantation into the second silicon germanium layer 205 and ion implantation into the first silicon germanium layer 204 may be performed in two stages.
　ｎ型シリコンゲルマニウム層２０５を形成するための不純物のドーピング方法として、イオン注入ではなく、シリコンゲルマニウム層をエピタキシャル成長させる際に、原料ガスであるシラン（ＳｉＨ４）とゲルマン（ＧｅＨ４）にホスフィン（ＰＨ３）を混合するｉｎ－ｓｉｔｕドーピングを採用してもよい。 As an impurity doping method for forming the n-type silicon germanium layer 205, phosphine (PH) is added to silane (SiH 4 ) and germane (GeH 4 ) which are source gases when the silicon germanium layer is epitaxially grown instead of ion implantation. 3 ) In-situ doping with mixing may be employed.
１００　ＳｉＧｅフォトダイオード
１０１　基板
１０２　ｐ型半導体層
１０３　ｉ型半導体層
１０４　ｎ型半導体層
２００　ＳｉＧｅフォトダイオード
２０１　シリコン基板
２０２　埋め込み酸化膜層（ＢＯＸ層）
２０３　ｐ型シリコン層
２０４　ｉ型ゲルマニウム層
２０５　ｎ型シリコンゲルマニウム層
２０６　絶縁膜
２０７　第１金属電極
２０８　第２金属電極
２０９　コア層
２１０　導波路
２１１　ＳＯＩ層
２１２　レジスト膜
２１３　レジスト膜
２１４　ＳｉＯ２マスク
２１５　レジスト膜
３００　ＳｉＧｅフォトダイオード
３０１　第１金属電極
３０２　保護膜
４００　ＳｉＧｅフォトダイオード
４０１　シリコン層
４０２　テーパ型コア層
４０３　シリコン層
４０４　ＳｉＯ２マスク
  100 SiGe photodiode 101 substrate 102 p-type semiconductor layer 103 i-type semiconductor layer 104 n-type semiconductor layer 200 SiGe photodiode 201 silicon substrate 202 buried oxide layer (BOX layer)
203 p-type silicon layer 204 i-type germanium layer 205 n-type silicon germanium layer 206 insulating film 207 first metal electrode 208 second metal electrode 209 core layer 210 waveguide 211 SOI layer 212 resist film 213 resist film 214 SiO 2 mask 215 resist Film 300 SiGe photodiode 301 First metal electrode 302 Protective film 400 SiGe photodiode 401 Silicon layer 402 Tapered core layer 403 Silicon layer 404 SiO 2 mask

Claims (15)

  1. 　第１領域及び前記第１領域の下部に位置する第２領域を有するｐ型半導体層と、
    　前記ｐ型半導体層の前記第１領域上に形成された第１ＳｉＧｅ層よりなるｉ型半導体層と、
    　前記ｉ型半導体層上に形成されたｎ型半導体層と、を備え、
    　前記第１領域の不純物濃度が前記第２領域の不純物濃度よりも低濃度である、
    　ことを特徴とするＳｉＧｅフォトダイオード。     A p-type semiconductor layer having a first region and a second region located below the first region;
    An i-type semiconductor layer comprising a first SiGe layer formed on the first region of the p-type semiconductor layer;
    An n-type semiconductor layer formed on the i-type semiconductor layer,
    The impurity concentration of the first region is lower than the impurity concentration of the second region;
    The SiGe photodiode characterized by the above-mentioned.
  2. 　前記ｐ型半導体層は、前記第１領域の側部に金属電極と接続するための第３領域を有し、
    　前記第３領域の不純物濃度が前記第１領域の不純物濃度よりも高濃度である、
    　ことを特徴とする請求項１に記載のＳｉＧｅフォトダイオード。     The p-type semiconductor layer has a third region for connecting to a metal electrode on a side portion of the first region,
    The impurity concentration of the third region is higher than the impurity concentration of the first region;
    The SiGe photodiode according to claim 1.
  3. 　前記第３領域のうち前記金属電極と接する表層部の不純物濃度が前記第１領域の不純物濃度よりも高濃度であることを特徴とする請求項２に記載のＳｉＧｅフォトダイオード。 The SiGe photodiode according to claim 2, wherein an impurity concentration of a surface layer portion in contact with the metal electrode in the third region is higher than an impurity concentration of the first region.
  4. 　前記ｐ型半導体層は、前記第２領域の下部に第４領域を有し、
    　前記第４領域の不純物濃度が前記第２領域の不純物濃度よりも低濃度である、
    　ことを特徴とする請求項１から請求項３のいずれか１項に記載のＳｉＧｅフォトダイオード。     The p-type semiconductor layer has a fourth region below the second region,
    The impurity concentration of the fourth region is lower than the impurity concentration of the second region;
    The SiGe photodiode according to any one of claims 1 to 3, wherein the SiGe photodiode is provided.
  5. 　前記第１領域の不純物濃度は、１×１０１９ｃｍ－３以下であることを特徴とする請求項１から請求項４のいずれか１項に記載のＳｉＧｅフォトダイオード。 5. The SiGe photodiode according to claim 1, wherein an impurity concentration of the first region is 1 × 10 19 cm −3 or less.
  6. 　前記ｐ型半導体層における前記第１領域の厚さは、５０ｎｍ以下であることを特徴とする請求項１から請求項５のいずれか１項に記載のＳｉＧｅフォトダイオード。 6. The SiGe photodiode according to claim 1, wherein a thickness of the first region in the p-type semiconductor layer is 50 nm or less.
  7. 　前記第３領域の不純物濃度は、１×１０１９ｃｍ－３以上であることを特徴とする請求項２又は請求項３に記載のＳｉＧｅフォトダイオード。 4. The SiGe photodiode according to claim 2, wherein the impurity concentration of the third region is 1 × 10 19 cm −3 or more.
  8. 　前記ｎ型半導体層は、前記第１ＳｉＧｅ層を覆うように形成された第２ＳｉＧｅ層よりなる保護膜のうち前記第１ＳｉＧｅ層の上面部分にｎ型不純物がドープされた半導体層であることを特徴とする請求項１から請求項７のいずれか１項に記載のＳｉＧｅフォトダイオード。 The n-type semiconductor layer is a semiconductor layer in which an upper surface portion of the first SiGe layer is doped with an n-type impurity in a protective film made of a second SiGe layer formed to cover the first SiGe layer. The SiGe photodiode according to any one of claims 1 to 7.
  9. 　ｎ型不純物が更に前記第１ＳｉＧｅ層の表層にドープされたことを特徴とする請求項８に記載のＳｉＧｅフォトダイオード。 The SiGe photodiode according to claim 8, wherein an n-type impurity is further doped on a surface layer of the first SiGe layer.
  10. 　前記第２ＳｉＧｅ層のＳｉの組成は、前記第１ＳｉＧｅ層のＳｉの組成よりも大きいことを特徴とする請求項７又は請求項８に記載のＳｉＧｅフォトダイオード。 The SiGe photodiode according to claim 7 or 8, wherein a composition of Si in the second SiGe layer is larger than a composition of Si in the first SiGe layer.
  11. 　前記ｐ型半導体層は、埋め込み酸化膜層上のＳＯＩ層にｐ型不純物がドープされた半導体層であることを特徴とする請求項１から請求項１０のいずれか１項に記載のＳｉＧｅフォトダイオード。 11. The SiGe photodiode according to claim 1, wherein the p-type semiconductor layer is a semiconductor layer in which an SOI layer on a buried oxide film layer is doped with a p-type impurity. .
  12. 　前記埋め込み酸化膜層からなる下部クラッド層、前記ＳＯＩ層からなるコア層、及び前記コア層を覆う上部クラッド層により構成された導波路を備え、
    　前記導波路は、前記ｐ型半導体層に光学的に接続されている、
    　ことを特徴とする請求項１１に記載のＳｉＧｅフォトダイオード。     A waveguide composed of a lower cladding layer made of the buried oxide film layer, a core layer made of the SOI layer, and an upper cladding layer covering the core layer;
    The waveguide is optically connected to the p-type semiconductor layer;
    The SiGe photodiode according to claim 11.
  13. 　前記導波路は、前記コア層上にテーパ形状のシリコン層を有し、前記ｉ型半導体層に光学的に接続されていることを特徴とする請求項１２に記載のＳｉＧｅフォトダイオード。 The SiGe photodiode according to claim 12, wherein the waveguide has a tapered silicon layer on the core layer and is optically connected to the i-type semiconductor layer.
  14. 　ｐ型半導体層と、
    　前記ｐ型半導体層上に形成されたｉ型半導体層と、
    　前記ｉ型半導体層上に形成されたｎ型半導体層と、を備え、
    　前記ｐ型半導体層の前記ｉ型半導体層側の表面における不純物濃度が、前記ｐ型半導体層の内部における不純物濃度よりも低濃度である、
    　ことを特徴とするＳｉＧｅフォトダイオード。     a p-type semiconductor layer;
    An i-type semiconductor layer formed on the p-type semiconductor layer;
    An n-type semiconductor layer formed on the i-type semiconductor layer,
    The impurity concentration on the surface of the p-type semiconductor layer on the i-type semiconductor layer side is lower than the impurity concentration inside the p-type semiconductor layer.
    The SiGe photodiode characterized by the above-mentioned.
  15. 　前記ｐ型半導体層は、前記ｐ型半導体層の内部において最大の不純物濃度を有することを特徴とする請求項１４に記載のＳｉＧｅフォトダイオード。
          The SiGe photodiode according to claim 14, wherein the p-type semiconductor layer has a maximum impurity concentration inside the p-type semiconductor layer.
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