JP2014003229A - Semiconductor light-emitting element and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element capable of achieving a window region in a simple configuration, and a method for manufacturing the same.SOLUTION: A semiconductor light-emitting element 1 comprises: a substrate 11; an active layer 21 having a region which emits light when current is supplied thereto; a lower clad layer 24 disposed closer to the substrate 11 side than the active layer 21 and having a first conductivity type; an upper clad layer 25 disposed across the active layer 21 from the lower clad layer 24 and having a second conductivity type; contact layers 26 and 27 formed on the upper clad layer 25 and doped with an impurity of the second conductivity type; and an insulating layer 28 formed on the contact layers 26 and 27. In the active layer 21, window regions A1 and A2 changed into a mixed crystal due to vacancy diffusion are formed near an emission end face. An impurity concentration of a first region of the contact layers 26 and 27 corresponding to the window regions A1 and A2 is smaller than an impurity concentration of a second region of the contact layers 26 and 27 not corresponding to the window regions A1 and A2.

Description

  The present invention relates to a semiconductor light emitting device and a method for manufacturing the semiconductor light emitting device.

  2. Description of the Related Art Conventionally, in order to prevent deterioration of a light emitting end face, a semiconductor light emitting element is known in which a window region that absorbs less laser light compared to the inside of an active layer is provided only in the vicinity of the end face of the active layer (for example, Patent Documents). 1 and 2). In the GaAs-based semiconductor light-emitting devices described in Patent Documents 1 and 2, the window region is formed by intermixing the crystal film using IFVD (impurity free vacancy disordering), which is a mixed crystallization technique by vacancy diffusion. .

Specifically, on a GaAs-based crystal film that forms a window region in a part thereof, an accelerating film formed corresponding to the window region to promote diffusion of Ga, and a region other than the window region (non-window region) A suppression film that is formed correspondingly and suppresses the diffusion of Ga is deposited. Thereafter, a predetermined heat treatment is performed, and a part of the GaAs crystal film located below the promotion film is mixed. In other words, vacancies are generated by absorption of Ga present in the region below the accelerating film into the active layer by diffusing into the active layer region located below the accelerating film. A window region is formed. In Patent Document 1, sparse SiN having a small N composition ratio is used as the promotion film, and dense SiN having a large Si composition ratio is used as the suppression film. In Patent Document 2, SiO ₂ is used as the promotion film, and SiN is used as the suppression film.

JP 2007-242718 A Japanese Patent Laid-Open No. 7-122816

  In the semiconductor light emitting devices described in Patent Documents 1 and 2, since it is necessary to form two types of insulating films, ie, an accelerating film and a suppressing film, the structure of the element and the manufacturing process may be complicated. In the present technical field, a semiconductor light emitting device in which a window region of an active layer is realized with a simple configuration and a manufacturing method thereof are desired.

  The present inventors have found that the diffusion rate of vacancies increases as the impurity concentration in the crystal film decreases, leading to an invention applied to the formation of the window region of the active layer.

  A semiconductor light emitting device according to one aspect of the present invention includes a substrate, an active layer, a first cladding layer, a second cladding layer, a contact layer, and an insulating layer. The active layer is formed on the substrate and has a region that emits light when supplied with current. The first cladding layer has a first conductivity type and is disposed closer to the substrate than the active layer. The second cladding layer has a second conductivity type, and is disposed with an active layer interposed between the second cladding layer and the first cladding layer. The contact layer is formed on the second cladding layer and is doped with a second conductivity type impurity. The insulating layer is formed on the contact layer. In the active layer, a window region mixed by vacancies is formed in the vicinity of the emission end face. The impurity concentration of the first region of the contact layer corresponding to the window region is lower than the impurity concentration of the second region of the contact layer not corresponding to the window region.

  In this semiconductor light emitting device, the impurity concentration of the contact layer interposed between the insulating layer and the cladding layer varies from region to region. That is, the impurity concentration of the first region corresponding to the window region is lower than the impurity concentration of the second region not corresponding to the window region. The lower the impurity concentration in the crystal film, the higher the diffusion rate of vacancies. Therefore, the diffusion rate of vacancies in the first region is higher than that in the second region. That is, according to this semiconductor light emitting device, by controlling the impurity concentration of the contact layer, it is possible to diffuse the vacancies in the first region compared to the second region, and to form the window region below the first region. it can. For this reason, the window region of the active layer can be formed using one or one kind of insulating film. Therefore, the window region of the active layer can be formed with a simple configuration.

  In one embodiment, the contact layer may be composed of two layers having different impurity concentrations. By using two layers having different impurity concentrations, the first region and the second region can be easily formed.

  In one embodiment, in the contact layer, the impurity concentration of the first region is changed from the impurity concentration of the first region toward the second region between the first region and the second region. A third region provided with a concentration gradient of impurity concentration may be formed. With such a configuration, the discontinuity of the band gap can be relaxed between the window region and the non-window region, so that it is possible to suppress the deterioration of the characteristics of the boundary portion.

  In one embodiment, the first conductivity type may be n-type and the second conductivity type may be p-type. Further, the impurity may contain Zn.

  A manufacturing method according to another aspect of the present invention is a method for manufacturing a semiconductor light emitting device. In this semiconductor light emitting device, a window region is formed in the vicinity of the emission end face of the active layer that emits light when current is supplied. The manufacturing method includes a semiconductor layer forming step, a contact layer forming step, an insulating layer forming step, and a heat treatment step. In the semiconductor layer forming step, a plurality of semiconductor layers including a first cladding layer having a first conductivity type, the active layer, and a second cladding layer having a second conductivity type are sequentially formed on the substrate from the substrate side. In the contact layer forming step, a contact layer doped with an impurity of the second conductivity type is formed on the second cladding layer. In the insulating layer forming step, an insulating layer is formed on the contact layer. In the heat treatment step, the window region is formed by heat treatment. Here, in the contact layer forming step, a contact layer having a first region corresponding to the window region and a second region not corresponding to the window region is formed, and the impurity concentration of the first region is higher than the impurity concentration of the second region. The contact layer is formed so as to be small.

  In this manufacturing method, the contact layer interposed between the insulating layer and the clad layer is formed so that the impurity concentration differs from region to region. That is, the impurity concentration of the first region corresponding to the window region is made smaller than the impurity concentration of the second region not corresponding to the window region. The lower the impurity concentration in the crystal film, the higher the diffusion rate of vacancies. Therefore, the diffusion rate of vacancies in the first region is higher than that in the second region. That is, according to this manufacturing method, by controlling the impurity concentration of the contact layer, it is possible to diffuse holes in the first region compared to the second region, and to form a window region below the first region. . For this reason, the window region of the active layer can be formed using one or one kind of insulating film. Therefore, the window region of the active layer can be formed with a simple configuration.

  In one embodiment, the contact layer forming step may include a first contact layer forming step, a second contact layer forming step, and an etching step. In the first contact layer forming step, a first contact layer doped with impurities is formed. In the second contact layer forming step, a second contact layer having an impurity concentration higher than that of the first contact layer is formed on the first contact layer. In the etching step, the region of the second contact layer corresponding to the window region is removed by etching. With this configuration, the region removed by etching becomes the first region, and the region not removed by etching becomes the second region. That is, the first region and the second region can be formed only by etching.

  In one embodiment, in the etching step, the second contact layer may be etched such that the thickness of the second contact layer increases in a slope from a region corresponding to the window region to a region not corresponding to the window region. With this configuration, since a concentration gradient can be provided at the boundary between the first region and the second region, the discontinuity of the band gap can be reduced between the window region and the non-window region. it can.

  In one embodiment, the contact layer forming step may include a first contact layer forming step, an etching step, and a second contact layer forming step. In the contact layer forming step, a first contact layer doped with impurities is formed. In the etching step, a region not corresponding to the window region of the first contact layer is removed by etching. In the second contact layer forming step, a second contact layer having an impurity concentration higher than that of the first contact layer is formed in the etched region. By forming the contact layer in this way, the portion where only the first contact layer is formed can be the first region, and the portion where the second contact layer is formed can be the second region.

  According to the present invention, the window region of the active layer can be realized with a simple configuration.

1 is a perspective view showing a configuration of a semiconductor light emitting element according to a first embodiment. It is a sectional side view in the II-II line | wire of the semiconductor light-emitting device shown in FIG. 2 is a flowchart showing a manufacturing process of the semiconductor light emitting device shown in FIG. It is a schematic diagram explaining the manufacturing process of the semiconductor light-emitting device shown in FIG. It is a sectional side view in the VV line of the semiconductor light-emitting device shown in FIG. It is a schematic diagram explaining the manufacturing process of the semiconductor light-emitting device shown in FIG. It is a schematic diagram explaining the manufacturing process of the semiconductor light-emitting device shown in FIG. It is a sectional side view in the VIII-VIII line of the semiconductor light-emitting device shown in FIG. It is a schematic diagram which shows the heat processing temperature dependence of band gap energy variation | change_quantity. It is a schematic diagram explaining the manufacturing process of the semiconductor light-emitting device shown in FIG. It is a schematic diagram explaining the manufacturing process of the semiconductor light-emitting device shown in FIG. It is a schematic diagram explaining the manufacturing process of the semiconductor light-emitting device concerning 2nd Embodiment. It is a schematic diagram explaining the manufacturing process of the semiconductor light-emitting device concerning 3rd Embodiment. It is a schematic diagram explaining the manufacturing process of the semiconductor light-emitting device concerning 4th Embodiment. It is a schematic diagram explaining the manufacturing process of the semiconductor light-emitting device concerning 5th Embodiment. It is a schematic diagram explaining the manufacturing process of the conventional semiconductor light-emitting device.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. Further, the dimensional ratios in the drawings do not necessarily match those described.

(First embodiment)
FIG. 1 is a perspective view showing a configuration of a semiconductor light emitting device according to an embodiment of the present invention, and FIG. 2 is a side sectional view taken along line II-II of the semiconductor light emitting device shown in FIG. The semiconductor light emitting device 1 shown in FIGS. 1 and 2 is a single emitter broad area semiconductor laser.

  As shown in FIGS. 1 and 2, the semiconductor light emitting device 1 includes a substrate 11 and a stacked body formed on the substrate. In the following description, it is assumed that the stacking direction of the stack is the Z direction, the light emission direction is the X direction, and the direction orthogonal to the stacking direction and the light emission direction is the Y direction.

  The substrate 11 is a semiconductor substrate, and for example, an n-type (first conductivity type) GaAs substrate is used. Further, the stacked body formed on the substrate 11 is formed of a multilayer film including the active layer 21. The active layer 21 is a light emitting layer that emits light with a predetermined emission spectrum when supplied with current. As such an active layer 21, for example, a quantum well active layer formed of AlInGaAs can be used. When AlInGaAs is used, the active layer 21 outputs light having a wavelength of 915 nm. The laminate constitutes all or part of a horizontal resonator that resonates light emitted from the active layer 21 in the horizontal direction (X direction).

  A lower guide layer 22 is formed in contact with the active layer 21 on the substrate 11 side of the active layer 21. The lower guide layer 22 is made of, for example, n-type AlGaAs. An upper guide layer 23 is formed on the active layer 21 in contact with the active layer 21. The upper guide layer 23 is made of, for example, p-type AlGaAs. The lower guide layer 22 and the upper guide layer 23 are disposed to confine light in the active layer 21.

  On the substrate 11 side of the lower guide layer 22, a lower clad layer (first clad layer) 24 is formed in contact with the lower guide layer 22. The lower cladding layer 24 is made of, for example, n-type AlGaAs. Further, an upper clad layer (second clad layer) 25 is formed on the upper guide layer 23 in contact with the upper guide layer 23. The upper cladding layer 25 is made of, for example, p-type (second conductivity type) AlGaAs. The lower cladding layer 24 and the upper cladding layer 25 are arranged to increase the electron density and hole density of the active region of the active layer 21 and to confine light in the active layer 21. Thus, in the semiconductor light emitting device 1, the active layer 21 is interposed between the lower clad layer 24 and the upper clad layer 25, and a horizontal resonator is formed in which light generated in the active layer 21 resonates in the horizontal direction. The

  A first contact layer 26 is formed on the upper surface of the upper cladding layer 25. For example, the first contact layer 26 is formed by doping p-type GaAs with a p-type impurity (Zn in this case).

  In the laminated body, window regions A1 and A2 are formed at both ends in the X direction, which is the light emitting direction. The window regions A1 and A2 include at least both ends of the active layer 21 in the X direction. In other words, the window regions A1 and A2 are formed at least at both ends in the X direction of the active layer 21. The window regions A1 and A2 are regions in which vacancies are diffused, and the region where the active layer 21 and the window regions A1 and A2 overlap is mixed with the diffusion of the vacancies. That is, the window regions A1 and A2 of the active layer 21 are regions that absorb less light compared to regions (non-window regions) where the window regions A1 and A2 in the active layer 21 are not formed. The window regions A1 and A2 are formed using IFVD, which is a mixed crystallization technique by hole diffusion. In FIG. 1 and FIG. 2, the window regions A1 and A2 extend over the lower cladding layer 24, the lower guide layer 22, the active layer 21, the upper guide layer 23, the upper cladding layer 25, and the first contact layer 26 as an example. Is formed. That is, vacancies are diffused in the vicinity of both ends in the X direction of the lower cladding layer 24, the lower guide layer 22, the active layer 21, the upper guide layer 23, the upper cladding layer 25, and the first contact layer 26. A region where the window regions A1 and A2 overlap is mixed. Thereby, melting deterioration of the emission end face of the active layer 21 is prevented.

  Further, a second contact layer 27 is formed on the first contact layer 26 in contact with the first contact layer 26. That is, the contact layer is formed of a multilayer film (here, a two-layer structure). The second contact layer 27 is formed on the non-window region of the first contact layer 26. For example, the second contact layer 27 is formed by doping p-type GaAs with a p-type impurity (Zn in this case).

The impurity concentration of the first contact layer 26 is smaller than the impurity concentration of the second contact layer 27. The impurity concentration of the first contact layer 26 is, for example, 1.0 × 10 ¹⁸ cm ⁻³ , and the impurity concentration of the second contact layer 27 is, for example, 1.8 × 10 ²⁰ cm ⁻³ .

  An insulating layer 28 is formed on the upper surface of the second contact layer 26. The insulating layer 28 has a function of absorbing Ga during heat treatment. For example, SiN is used as the insulating layer 28. A groove 28a extending in the X direction is formed in the insulating layer 28. The bottom of the groove 28 a reaches the upper surface of the first contact layer 26. An anode electrode member 30 is disposed on the upper surface of the insulating layer 28. The anode electrode member 30 is in contact with the first contact layer 26 through the groove 28a. A cathode electrode member 31 is disposed below the substrate 11. The anode electrode member 30 and the cathode electrode member 31 are made of a metal such as Au.

  As described above, in the semiconductor light emitting device 1 according to the first embodiment, the impurity concentration of the contact layer interposed between the insulating layer 28 and the upper cladding layer 25 differs for each region. In the conventional structure using IFVD, as shown in FIG. 16, for example, different types of insulating layers 51 and 52 are formed on the contact layer 50 formed with the same impurity concentration to diffuse the holes. The speed is controlled. In contrast, in the semiconductor light emitting device 1 according to the first embodiment, the contact layer has a two-layer structure of the first contact layer 26 and the second contact layer 27, and the overlap in the stacking direction of the two-layer structure is changed for each region. Has been. With such a layer structure, the region where only the first contact layer 26 is formed (first region) has an impurity concentration of the region where the first contact layer 26 and the second contact layer 27 are formed (second region). ) Is smaller than the impurity concentration. That is, the impurity concentration of the first region, which is a region corresponding to the window regions A1, A2, is smaller than the impurity concentration of the second region, which is a region not corresponding to the window regions A1, A2. The lower the impurity concentration in the crystal film, the higher the diffusion rate of vacancies. Therefore, the diffusion rate of vacancies in the first region is higher than that in the second region. That is, according to the semiconductor light emitting device 1, by controlling the impurity concentration of the first contact layer 26 and the second contact layer 27, the vacancies are diffused in the first region as compared with the second region, and the first region A window region can be formed below the window. Therefore, the window regions A1 and A2 of the active layer 21 can be formed using one or one kind of insulating layer 28. Therefore, the window regions A1 and A2 of the active layer 21 can be formed with a simple configuration.

  Next, a method for manufacturing the semiconductor light emitting device 1 according to the first embodiment will be described with reference to FIGS. FIG. 3 is a flowchart for explaining a manufacturing process of the semiconductor light emitting device 1 according to the first embodiment. 4 to 11 are perspective views or cross-sectional views of the semiconductor light emitting device 1 in each manufacturing process.

First, as shown in FIG. 3, a laminate manufacturing process is performed (S10: semiconductor layer forming step, contact layer forming step). In the process of S10, a laminated body is manufactured using MOCVD or the like. As shown in FIGS. 4 and 5, the lower cladding layer 24, the lower guide layer 22, the active layer 21, the upper guide layer 23, the upper cladding layer 25, the first contact layer 26 and the second contact layer 27 are formed on the substrate 11. Are laminated in order to produce a laminate. For example, an n-type GaAs substrate is used as the substrate 11, the lower cladding layer 24 is n-type AlGaAs, the lower guide layer 22 is n-type AlGaAs, the active layer 21 is AlInGaAs, the upper guide layer 23 is p-type AlGaAs, the upper The clad layer 25 is produced using p-type AlGaAs. The first contact layer 26 is p-type GaAs and is formed by doping so that the impurity concentration of Zn is 1.0 × 10 ¹⁸ cm ⁻³ (first contact layer forming step). The second contact layer 27 is p-type GaAs and is formed by doping so that the impurity concentration of Zn is 1.8 × 10 ²⁰ cm ⁻³ (second contact layer forming step).

  Next, a partial etching process is performed on the second contact layer 27 formed on the upper surface of the stacked body (S12: etching step). In the process of S12, a partial region of the second contact layer 27 corresponding to the window regions A1 and A2 is etched by an etching technique such as wet etching. As shown in FIG. 6, the vicinity (width L1, L2) of both ends in the X direction of the second contact layer 27 is removed by etching. The width L1 corresponds to the width of the window region A1, and the width L2 corresponds to the width of the window region A2. Thus, the etching region corresponds to the window regions A1 and A2. By the etching shown in S12, the upper surface 26a of the first contact layer 26 is exposed. The width L1 and the width L2 are, for example, 25 μm.

  Next, the insulating layer 28 is formed (S14: insulating layer forming step). In the process of S14, the insulating layer 28 is formed using plasma CVD or the like. As shown in FIG. 7, an insulating layer 28 is formed on the exposed upper surface 26 a of the first contact layer 26 and the upper surface of the second contact layer 27. For example, SiN having a thickness of 100 nm is formed as the insulating layer 28. The composition of SiN is determined by the thickness and carrier concentration of the first contact layer 26 and the second contact layer 27. Here, as an example, a composition of SiN having a refractive index of 1.9 is used.

  Next, heat treatment is performed (S16: heat treatment step). By heat treatment, Si contained in the insulating layer 28 is absorbed with Ga contained in the first contact layer 26 and the second contact layer 27, and voids are generated in the first contact layer 26 and the second contact layer 27. The vacancies diffuse into the laminated body by heat energy. At this time, since the Zn impurity concentration of the first contact layer 26 is smaller than the Zn impurity concentration of the second contact layer 27, the vacancy diffusion rate of the first contact layer 26 is larger than that of the second contact layer 27. Becomes larger. That is, as shown in FIG. 8, the vacancies diffuse below the region where the upper surface 26a of the first contact layer 26 and the insulating layer 28 are in contact (regions corresponding to the window regions A1, A2). Both ends of 21 are mixed. On the other hand, in the region where the upper surface of the second contact layer 27 and the insulating layer 28 are in contact with each other (the region not corresponding to the window regions A1 and A2), the diffusion of holes is suppressed, and the region other than the window regions A1 and A2 (Non-window region) is not mixed. Thus, by controlling the impurity concentration of Zn, only the window regions A1 and A2 can be selectively mixed.

  The heat treatment temperature is set such that the band gap energy of the window regions A1, A2 and the non-window region is different before and after the heat treatment. FIG. 9 is a measurement result showing the heat treatment temperature dependence of the band gap energy variation. The horizontal axis is the heat treatment temperature, and the vertical axis is the amount of change in the band gap energy. The graph shown in FIG. 9 was obtained by photoluminescence measurement performed before and after the heat treatment of the semiconductor light emitting device employing SiN having a refractive index of 1.9 as the insulating layer 28. Specifically, the photoluminescence measurement is performed before the heat treatment, the photoluminescence measurement is performed again after the heat treatment is performed for 60 s, and the change amount before and after the heat treatment is plotted for each heat treatment temperature as shown in FIG. For this reason, it can be said that the degree of mixed crystallization increases as the amount of change in band gap energy increases. As shown in FIG. 9, it can be seen that mixed crystallization occurs at 820 ° C. or higher. Since the amount of change in the band gap energy is sharply increased from 860 ° C., the set temperature may be 860 ° C. or higher. In S16, as an example, the heat treatment temperature is set to 900 ° C. The heat treatment time is 60 s as an example. In this case, the change amount of the band gap energy is 59 meV in the window region and 3.5 meV in the non-window region, and a sufficient band gap energy difference is obtained.

  Next, a current injection region forming step is performed (S18). In the process of S18, as shown in FIG. 10, the insulating layer 28 is removed in a stripe shape by etching. For example, it is striped with a width of 100 μm. As a result, the upper surface 26a of the first contact layer 26 and the upper surface 27a of the second contact layer 27 are exposed, and a current injection region is formed.

  Next, an electrode formation process is performed (S20). In the process of S20, as shown in FIG. 11, the anode electrode member 30 is formed on the upper surface of the laminate. For example, the anode electrode member 30 is formed by vacuum deposition. Thereafter, the back surface of the substrate 11 is polished and thinned, and then the cathode electrode member 31 is formed. Then, a resonator is formed by cleavage, and coating is applied to the emission end face and the reflection end face, whereby the chip of the semiconductor light emitting element 1 is completed.

  As described above, in the method for manufacturing the semiconductor light emitting device 1 according to the first embodiment, the impurity concentration of the contact layer interposed between the insulating layer 28 and the upper clad layer 25 is formed to be different for each region. For example, the contact layer has a two-layer structure of the first contact layer 26 and the second contact layer 27, and the overlap in the stacking direction of the two-layer structure is changed for each region. For example, only the first contact layer 26 is formed in the first region corresponding to the window regions A1 and A2, and the first contact layer 26 and the second contact region 26 are not formed in the second region corresponding to the window region. Two contact layers 27 are formed. Thereby, the impurity concentration of the first region, which is a region corresponding to the window regions A1, A2, can be made lower than the impurity concentration of the second region, which is a region not corresponding to the window regions A1, A2. The lower the impurity concentration in the crystal film, the higher the diffusion rate of vacancies. Therefore, the diffusion rate of vacancies in the first region is higher than that in the second region. That is, according to the semiconductor light emitting device 1, by controlling the impurity concentration of the first contact layer 26 and the second contact layer 27, the vacancies are diffused in the first region as compared with the second region, and the first region The window regions A1 and A2 can be formed below. Therefore, the window regions A1 and A2 of the active layer 21 can be formed using one or one kind of insulating layer 28. Therefore, the window regions A1 and A2 of the active layer 21 can be formed with a simple configuration.

  Furthermore, in the above-described embodiment, the insulating layer 28 formed on the first region is closer to the active layer 21 by the thickness of the second contact layer 27 than the insulating layer 28 formed on the second region. Is arranged. With such a configuration, the lower part of the first region is more likely to be mixed with crystals than the lower part of the second region. That is, the selectivity of mixed crystallization can be improved by the above configuration.

(Second Embodiment)
The semiconductor light emitting device 1 and the manufacturing method according to the second embodiment are configured in substantially the same manner as the semiconductor light emitting device 1 and the manufacturing method according to the first embodiment, and only the configuration and manufacturing process of the contact layer are different. Below, it demonstrates centering around difference with 1st Embodiment, and the overlapping description is abbreviate | omitted.

  FIG. 12 is a side cross-sectional view of the stacked body before the heat treatment in the semiconductor light emitting device 1 according to the second embodiment. FIG. 12 corresponds to FIG. 8 described in the first embodiment. As shown in FIG. 12, the contact layers do not overlap in the stacking direction, the first contact layer 26 is formed in the first region, and the second contact layer 27 is formed in the second region. For example, after the second contact layer 27 is formed on the upper cladding layer 25, both end portions are etched, and then the first contact layer 26 is selectively grown, whereby the first contact layer 26 and the second contact shown in FIG. Layer 27 can be formed. Alternatively, after forming the first contact layer 26 on the upper cladding layer 25, the central portion may be etched, and then the second contact layer 27 may be selectively grown. Other structures are the same as those in the first embodiment.

  As described above, according to the semiconductor light emitting device 1 and the manufacturing method according to the second embodiment, the same effects as the semiconductor light emitting device 1 and the manufacturing method according to the first embodiment can be obtained, and the top surface of the multilayer body can be formed flat. Therefore, the chip surface can be flattened. For this reason, for example, when the chip upper surface is mounted on a heat sink, no gap is formed between the chip and the heat sink, so that temperature control can be appropriately performed.

  Further, the material of the contact layer at the time of selective growth may be n-type GaAs. Since the film to be selectively grown in this way is a high resistance film or a film having an n-type conductivity type, it is difficult for current to flow in the vicinity of the light emitting end face, so that temperature rise due to Joule heat can be suppressed. Therefore, it is possible to improve the effect of suppressing end face deterioration.

(Third embodiment)
The semiconductor light emitting device 1 and the manufacturing method according to the third embodiment are configured in substantially the same manner as the semiconductor light emitting device 1 and the manufacturing method according to the first embodiment, and only the configuration and manufacturing process of the contact layer are different. Below, it demonstrates centering around difference with 1st Embodiment, and the overlapping description is abbreviate | omitted.

  FIG. 13 is a side cross-sectional view of the stacked body before the heat treatment in the semiconductor light emitting device 1 according to the third embodiment. FIG. 13 corresponds to FIG. 8 described in the first embodiment. As shown in FIG. 13, the contact layer is formed of the first contact layer 26, and a high Zn impurity concentration region 29, which is a region higher than the surrounding Zn impurity concentration, is formed at the center thereof. The high Zn impurity concentration region 29 is formed by using, for example, a Zn diffusion method. Other structures are the same as those in the first embodiment.

  As described above, according to the semiconductor light emitting device 1 and the manufacturing method according to the third embodiment, the same effects as those of the semiconductor light emitting device 1 and the manufacturing method according to the first embodiment and the second embodiment are obtained.

(Fourth embodiment)
The semiconductor light emitting device 1 and the manufacturing method according to the fourth embodiment are configured in substantially the same manner as the semiconductor light emitting device 1 and the manufacturing method according to the first embodiment, and only the configuration and manufacturing process of the contact layer are different. Below, it demonstrates centering around difference with 1st Embodiment, and the overlapping description is abbreviate | omitted.

  FIG. 14 is a side cross-sectional view of the stacked body before the heat treatment in the semiconductor light emitting device 1 according to the fourth embodiment. FIG. 14 corresponds to FIG. 8 described in the first embodiment. As shown in FIG. 14, the contact layer has a two-layer structure of a first contact layer 26 and a second contact layer 27. The second contact layer 27 is inclined at both end portions 27b. That is, the film thickness is configured to increase gradually from the region corresponding to the window regions A1 and A2 toward the region not corresponding to the window regions A1 and A2. By providing slopes at both end portions 27b of the second contact layer 27, the first contact layer 26 and the second contact layer 27 are provided between the first region and the second region, from the first region to the second region. A third region provided with a concentration gradient of the impurity concentration is formed so that the impurity concentration of the first region is changed from the impurity concentration of the first region toward the second region. This inclination is provided by etching, for example. Other structures are the same as those in the first embodiment.

  As described above, according to the semiconductor light emitting device 1 and the manufacturing method according to the fourth embodiment, the same effects as those of the semiconductor light emitting device 1 and the manufacturing method according to the first embodiment are obtained, and the window regions A1 and A2 and the regions that are not the window regions Since the discontinuity of the band gap can be relaxed between the two, it is possible to suppress the deterioration of the characteristics of the boundary portion.

(Fifth embodiment)
The semiconductor light emitting device 1 and the manufacturing method according to the fifth embodiment are configured in substantially the same manner as the semiconductor light emitting device 1 and the manufacturing method according to the first embodiment, and only the configuration and manufacturing process of the contact layer are different. Below, it demonstrates centering around difference with 1st Embodiment, and the overlapping description is abbreviate | omitted.

  FIG. 15 is a side cross-sectional view of the stacked body before the heat treatment in the semiconductor light emitting device 1 according to the fifth embodiment. FIG. 15 corresponds to FIG. 8 described in the first embodiment. As shown in FIG. 15, the contact layer 40 is formed so that the Zn concentration differs depending on the region. The first region 40a is a region corresponding to the window regions A1 and A2, and has a Zn impurity concentration similar to that of the first contact layer 26 of the first embodiment, for example. The second region 40b is a region that does not correspond to the window regions A1 and A2, and has a Zn impurity concentration similar to that of the second contact layer 27 of the first embodiment, for example. As in the fourth embodiment, the boundary between the first region 40a and the second region 40b is changed from the impurity concentration of the first region to the impurity concentration of the second region as it goes from the first region to the second region. A third region provided with a concentration gradient of impurity concentration may be formed. Other structures are the same as those in the first embodiment.

  As described above, according to the semiconductor light emitting device 1 and the manufacturing method according to the fifth embodiment, the same effects as those of the semiconductor light emitting device 1 and the manufacturing method according to the first embodiment, the second embodiment, and the fourth embodiment are obtained.

  In addition, embodiment mentioned above shows an example of the semiconductor light-emitting device based on this invention. The semiconductor light emitting device according to the present invention is not limited to the semiconductor light emitting device according to the embodiment, and the semiconductor light emitting device according to the embodiment may be modified or applied to other devices.

  For example, in the above-described embodiment, the case where AlInGaAs is used as the material of the active layer 21 has been described as an example, but other materials may be used. Further, it may be a narrow stripe type single mode semiconductor laser. In addition, a buffer layer or the like may be interposed between layers (including between the substrate 11 and the layer) constituting the semiconductor light emitting device.

  In the above-described embodiment, the example in which Zn is used as the p-type impurity has been described. However, a general p-type impurity such as Mg or C may be used. Further, Zn may be contained as a p-type impurity in combination with another p-type impurity.

  Further, in the above-described embodiment, the semiconductor light-emitting element chip is extracted and outlined, but as in the actual manufacturing process, it is performed in the wafer state, and the resonator is manufactured (bar state) by cleavage, and then the end face After coating, it may be cut into chips.

  Furthermore, in the above-described embodiment, the semiconductor light-emitting element 1 using the n-type substrate 11 has been described. However, the semiconductor light-emitting element configured by switching the n-type and the p-type of the embodiment using a p-type substrate. Even when the present invention is applied to the device, the element resistance can be reduced.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor light-emitting device, 11 ... Substrate, 21 ... Active layer, 24 ... Lower clad layer (first clad layer), 25 ... Upper clad layer (second clad layer), 26 ... First contact layer, 27 ... Second Contact layer, 28 ... insulating layer, 29 ... high Zn impurity concentration region, 40 ... contact layer.

Claims (11)

A substrate,
An active layer formed on the substrate and having a region that emits light when supplied with current;
A first cladding layer disposed on the substrate side of the active layer and having a first conductivity type;
A second cladding layer having a second conductivity type, wherein the active layer is interposed between the first cladding layer and the first cladding layer;
A contact layer formed on the second cladding layer and doped with an impurity of a second conductivity type;
An insulating layer formed on the contact layer;
With
In the active layer, a window region mixed by vacancies is formed in the vicinity of the emission end face,
A semiconductor light emitting element, wherein an impurity concentration of a first region of the contact layer corresponding to the window region is smaller than an impurity concentration of a second region of the contact layer not corresponding to the window region.   The semiconductor light-emitting element according to claim 1, wherein the contact layer includes two layers having different impurity concentrations.   In the contact layer, the impurity concentration of the first region is changed from the impurity concentration of the first region toward the second region between the first region and the second region. The semiconductor light emitting device according to claim 1, wherein a third region provided with a concentration gradient of impurity concentration is formed. The first conductivity type is n-type;
The semiconductor light emitting element according to claim 1, wherein the second conductivity type is a p-type.   The semiconductor light emitting element according to claim 4, wherein the impurity contains Zn. A method of manufacturing a semiconductor light emitting device in which a window region is formed in the vicinity of an emission end face of an active layer that emits light by being supplied with current,
A semiconductor layer forming step of sequentially forming a plurality of semiconductor layers including a first clad layer having a first conductivity type, an active layer and a second clad layer having a second conductivity type on the substrate from the substrate side;
Forming a contact layer doped with an impurity of a second conductivity type on the second cladding layer;
An insulating layer forming step of forming an insulating layer on the contact layer;
A heat treatment step for forming the window region;
With
In the contact layer forming step,
A contact layer having a first region corresponding to the window region and a second region not corresponding to the window region is formed, and an impurity concentration of the first region is made smaller than an impurity concentration of the second region. A method of manufacturing a semiconductor light emitting device for forming the contact layer. The contact layer forming step includes
A first contact layer forming step of forming a first contact layer doped with impurities;
A second contact layer forming step of forming a second contact layer having an impurity concentration higher than the impurity concentration of the first contact layer on the first contact layer;
An etching step of removing a region of the second contact layer corresponding to the window region by etching;
The manufacturing method of the semiconductor light-emitting device of Claim 6 which has these.   8. The semiconductor according to claim 7, wherein in the etching step, the thickness of the second contact layer is etched so as to increase in a slope from a region corresponding to the window region to a region not corresponding to the window region. Manufacturing method of light emitting element. The contact layer forming step includes
A first contact layer forming step of forming a first contact layer doped with impurities;
An etching step of removing, by etching, a region not corresponding to the window region of the first contact layer;
A second contact layer forming step of forming a second contact layer having an impurity concentration higher than that of the first contact layer in the region;
The manufacturing method of the semiconductor light-emitting device of Claim 6 which has these. The first conductivity type is n-type;
The method for manufacturing a semiconductor light-emitting element according to claim 6, wherein the second conductivity type is a p-type.   The method of manufacturing a semiconductor light emitting element according to claim 10, wherein the impurity contains Zn.

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