JP2013526739A5 - - Google Patents

Download PDF

Info

Publication number
JP2013526739A5
JP2013526739A5 JP2013510258A JP2013510258A JP2013526739A5 JP 2013526739 A5 JP2013526739 A5 JP 2013526739A5 JP 2013510258 A JP2013510258 A JP 2013510258A JP 2013510258 A JP2013510258 A JP 2013510258A JP 2013526739 A5 JP2013526739 A5 JP 2013526739A5
Authority
JP
Japan
Prior art keywords
processor
power
ways
operating point
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2013510258A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013526739A (ja
JP5735638B2 (ja
Filing date
Publication date
Priority claimed from US12/777,657 external-priority patent/US8412971B2/en
Application filed filed Critical
Publication of JP2013526739A publication Critical patent/JP2013526739A/ja
Publication of JP2013526739A5 publication Critical patent/JP2013526739A5/ja
Application granted granted Critical
Publication of JP5735638B2 publication Critical patent/JP5735638B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2013510258A 2010-05-11 2011-05-10 キャッシュ制御のための方法および装置 Active JP5735638B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/777,657 US8412971B2 (en) 2010-05-11 2010-05-11 Method and apparatus for cache control
US12/777,657 2010-05-11
PCT/US2011/035975 WO2011143256A1 (en) 2010-05-11 2011-05-10 Method and apparatus for cache control

Publications (3)

Publication Number Publication Date
JP2013526739A JP2013526739A (ja) 2013-06-24
JP2013526739A5 true JP2013526739A5 (enExample) 2014-06-26
JP5735638B2 JP5735638B2 (ja) 2015-06-17

Family

ID=44303932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013510258A Active JP5735638B2 (ja) 2010-05-11 2011-05-10 キャッシュ制御のための方法および装置

Country Status (6)

Country Link
US (2) US8412971B2 (enExample)
EP (1) EP2569680B1 (enExample)
JP (1) JP5735638B2 (enExample)
KR (1) KR101673500B1 (enExample)
CN (1) CN102934046B (enExample)
WO (1) WO2011143256A1 (enExample)

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9311245B2 (en) 2009-08-13 2016-04-12 Intel Corporation Dynamic cache sharing based on power state
US20110055610A1 (en) * 2009-08-31 2011-03-03 Himax Technologies Limited Processor and cache control method
US9043533B1 (en) * 2010-06-29 2015-05-26 Emc Corporation Sizing volatile memory cache based on flash-based cache usage
KR101661111B1 (ko) * 2010-11-23 2016-09-30 한국전자통신연구원 멀티 코어 프로세서의 전력 제어 장치 및 방법
US8972707B2 (en) 2010-12-22 2015-03-03 Via Technologies, Inc. Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin
US9201677B2 (en) * 2011-05-23 2015-12-01 Intelligent Intellectual Property Holdings 2 Llc Managing data input/output operations
JP5653315B2 (ja) * 2011-07-28 2015-01-14 株式会社東芝 情報処理装置
US8769316B2 (en) 2011-09-06 2014-07-01 Intel Corporation Dynamically allocating a power budget over multiple domains of a processor
JP5674613B2 (ja) 2011-09-22 2015-02-25 株式会社東芝 制御システム、制御方法およびプログラム
JP5674611B2 (ja) * 2011-09-22 2015-02-25 株式会社東芝 制御システム、制御方法およびプログラム
US9074947B2 (en) 2011-09-28 2015-07-07 Intel Corporation Estimating temperature of a processor core in a low power state without thermal sensor information
US8954770B2 (en) 2011-09-28 2015-02-10 Intel Corporation Controlling temperature of multiple domains of a multi-domain processor using a cross domain margin
US9026815B2 (en) 2011-10-27 2015-05-05 Intel Corporation Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor
US8832478B2 (en) 2011-10-27 2014-09-09 Intel Corporation Enabling a non-core domain to control memory bandwidth in a processor
US8943340B2 (en) 2011-10-31 2015-01-27 Intel Corporation Controlling a turbo mode frequency of a processor
US9158693B2 (en) * 2011-10-31 2015-10-13 Intel Corporation Dynamically controlling cache size to maximize energy efficiency
US20130145101A1 (en) * 2011-12-06 2013-06-06 Lisa Hsu Method and Apparatus for Controlling an Operating Parameter of a Cache Based on Usage
US8924758B2 (en) * 2011-12-13 2014-12-30 Advanced Micro Devices, Inc. Method for SOC performance and power optimization
CN107220029B (zh) 2011-12-23 2020-10-27 英特尔公司 掩码置换指令的装置和方法
US9619236B2 (en) * 2011-12-23 2017-04-11 Intel Corporation Apparatus and method of improved insert instructions
US9946540B2 (en) * 2011-12-23 2018-04-17 Intel Corporation Apparatus and method of improved permute instructions with multiple granularities
JP5458132B2 (ja) * 2012-03-13 2014-04-02 株式会社東芝 キャッシュ装置
US8943274B2 (en) * 2012-05-22 2015-01-27 Seagate Technology Llc Changing power state with an elastic cache
US8972665B2 (en) * 2012-06-15 2015-03-03 International Business Machines Corporation Cache set selective power up
US9292283B2 (en) * 2012-07-11 2016-03-22 Intel Corporation Method for fast large-integer arithmetic on IA processors
US9261945B2 (en) * 2012-08-30 2016-02-16 Dell Products, L.P. Dynanmic peak power limiting to processing nodes in an information handling system
US9218040B2 (en) 2012-09-27 2015-12-22 Apple Inc. System cache with coarse grain power management
US8977817B2 (en) * 2012-09-28 2015-03-10 Apple Inc. System cache with fine grain power management
US9734548B2 (en) * 2012-10-26 2017-08-15 Nvidia Corporation Caching of adaptively sized cache tiles in a unified L2 cache with surface compression
US9183144B2 (en) * 2012-12-14 2015-11-10 Intel Corporation Power gating a portion of a cache memory
JP6116941B2 (ja) * 2013-02-28 2017-04-19 株式会社東芝 情報処理装置
US10642735B2 (en) 2013-03-15 2020-05-05 Oracle International Corporation Statement cache auto-tuning
JP6038699B2 (ja) * 2013-03-22 2016-12-07 シャープ株式会社 電子機器
US9400544B2 (en) 2013-04-02 2016-07-26 Apple Inc. Advanced fine-grained cache power management
US8984227B2 (en) * 2013-04-02 2015-03-17 Apple Inc. Advanced coarse-grained cache power management
US9396122B2 (en) 2013-04-19 2016-07-19 Apple Inc. Cache allocation scheme optimized for browsing applications
KR102027573B1 (ko) * 2013-06-26 2019-11-04 한국전자통신연구원 캐시 메모리 제어 방법 및 그 장치
JP6130750B2 (ja) 2013-07-16 2017-05-17 株式会社東芝 メモリ制御回路およびプロセッサ
US9612961B2 (en) 2013-08-29 2017-04-04 Empire Technology Development Llc Cache partitioning in a multicore processor
US9430434B2 (en) 2013-09-20 2016-08-30 Qualcomm Incorporated System and method for conserving memory power using dynamic memory I/O resizing
KR101490072B1 (ko) * 2014-01-28 2015-02-06 한양대학교 산학협력단 캐시의 전력 제어를 위한 장치 및 방법
US20150310902A1 (en) * 2014-04-23 2015-10-29 Texas Instruments Incorporated Static Power Reduction in Caches Using Deterministic Naps
US9494997B2 (en) 2014-06-16 2016-11-15 Apple Inc. Hierarchical clock control using hysterisis and threshold management
US9886207B2 (en) * 2014-09-16 2018-02-06 Mediatek Inc. Memory-access method using batch command queue and associated controller
CN105793832B (zh) * 2014-09-18 2018-12-18 上海兆芯集成电路有限公司 处理器及其操作方法、以及计算机可读存储介质
US10928882B2 (en) * 2014-10-16 2021-02-23 Futurewei Technologies, Inc. Low cost, low power high performance SMP/ASMP multiple-processor system
US10248180B2 (en) * 2014-10-16 2019-04-02 Futurewei Technologies, Inc. Fast SMP/ASMP mode-switching hardware apparatus for a low-cost low-power high performance multiple processor system
US9952650B2 (en) * 2014-10-16 2018-04-24 Futurewei Technologies, Inc. Hardware apparatus and method for multiple processors dynamic asymmetric and symmetric mode switching
CN105849707B (zh) * 2014-11-28 2019-12-17 华为技术有限公司 一种多级缓存的功耗控制方法、装置及设备
US9734072B2 (en) 2015-03-24 2017-08-15 Macom Connectivity Solutions, Llc Main memory prefetch operation and multiple prefetch operation
US10268262B2 (en) 2015-08-02 2019-04-23 Dell Products, L.P. Dynamic peak power limiting to processing nodes in an information handling system
US11068401B2 (en) 2015-09-25 2021-07-20 Intel Corporation Method and apparatus to improve shared memory efficiency
US10255190B2 (en) * 2015-12-17 2019-04-09 Advanced Micro Devices, Inc. Hybrid cache
CN105404591B (zh) * 2015-12-18 2019-02-26 杭州士兰微电子股份有限公司 处理器系统及其存储器控制方法
US10073787B2 (en) * 2016-04-18 2018-09-11 Via Alliance Semiconductor Co., Ltd. Dynamic powering of cache memory by ways within multiple set groups based on utilization trends
JP2018005667A (ja) * 2016-07-05 2018-01-11 富士通株式会社 キャッシュ情報出力プログラム、キャッシュ情報出力方法及び情報処理装置
EP3491740B1 (en) * 2016-08-01 2021-07-21 Tsvlink Corporation A multiple channel cache memory and system memory device
US10255181B2 (en) * 2016-09-19 2019-04-09 Qualcomm Incorporated Dynamic input/output coherency
US10424107B2 (en) 2017-04-01 2019-09-24 Intel Corporation Hierarchical depth buffer back annotaton
US10241921B2 (en) * 2017-04-17 2019-03-26 Intel Corporation Avoid cache lookup for cold cache
US20180300238A1 (en) * 2017-04-17 2018-10-18 Balaji Vembu Adaptive cache sizing per workload
US11010953B2 (en) 2017-04-21 2021-05-18 Intel Corporation Dedicated fixed point blending for energy efficiency
CN108805276B (zh) * 2017-06-16 2020-09-22 上海兆芯集成电路有限公司 处理器、用于操作处理器的方法和计算机可用介质
KR102462507B1 (ko) * 2017-06-29 2022-11-02 삼성전자주식회사 프로세서, 이를 포함하는 컴퓨팅 장치 및 프로세서 저전력 모드 진입 방법
US10178619B1 (en) 2017-09-29 2019-01-08 Intel Corporation Advanced graphics power state management
US20190332166A1 (en) * 2018-04-27 2019-10-31 Qualcomm Incorporated Progressive power-up scheme for caches based on occupancy state
US20200103956A1 (en) * 2018-09-28 2020-04-02 Qualcomm Incorporated Hybrid low power architecture for cpu private caches
US11106261B2 (en) 2018-11-02 2021-08-31 Nvidia Corporation Optimal operating point estimator for hardware operating under a shared power/thermal constraint
US10540802B1 (en) 2019-01-31 2020-01-21 Advanced Micro Devices, Inc. Residency map descriptors
KR102740370B1 (ko) 2019-03-28 2024-12-06 에스케이하이닉스 주식회사 메모리 시스템, 메모리 컨트롤러 및 그 동작 방법
US11307987B2 (en) * 2019-05-24 2022-04-19 Texas Instmments Incorporated Tag update bus for updated coherence state
CN112540796B (zh) * 2019-09-23 2024-05-07 阿里巴巴集团控股有限公司 一种指令处理装置、处理器及其处理方法
US11385693B2 (en) 2020-07-02 2022-07-12 Apple Inc. Dynamic granular memory power gating for hardware accelerators
US12182317B2 (en) 2021-02-13 2024-12-31 Intel Corporation Region-based deterministic memory safety
US12235791B2 (en) 2021-08-23 2025-02-25 Intel Corporation Loop driven region based frontend translation control for performant and secure data-space guided micro-sequencing
US20230094030A1 (en) * 2021-09-30 2023-03-30 Advanced Micro Devices, Inc. Cache resizing based on processor workload
KR20230047823A (ko) * 2021-10-01 2023-04-10 삼성전자주식회사 시스템 온 칩 및 어플리케이션 프로세서
US12462331B2 (en) * 2023-02-28 2025-11-04 Qualcomm Incorporated Adaptive caches for power optimization of graphics processing
US20250190225A1 (en) * 2023-12-08 2025-06-12 Qualcomm Incorporated A processor-based system including a processing unit for dynamically reconfiguring micro-architectural features of the processing unit in response to workload being processed on the processing unit

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6845432B2 (en) * 2000-12-28 2005-01-18 Intel Corporation Low power cache architecture
GB2378778B (en) 2001-08-13 2005-03-23 Ibm Computer system with heap and card table
US7290093B2 (en) * 2003-01-07 2007-10-30 Intel Corporation Cache memory to support a processor's power mode of operation
US7051221B2 (en) * 2003-04-28 2006-05-23 International Business Machines Corporation Performance throttling for temperature reduction in a microprocessor
US7127560B2 (en) * 2003-10-14 2006-10-24 International Business Machines Corporation Method of dynamically controlling cache size
US7395372B2 (en) * 2003-11-14 2008-07-01 International Business Machines Corporation Method and system for providing cache set selection which is power optimized
JP3834323B2 (ja) * 2004-04-30 2006-10-18 日本電気株式会社 キャッシュメモリおよびキャッシュ制御方法
JP2006059068A (ja) 2004-08-19 2006-03-02 Matsushita Electric Ind Co Ltd プロセッサ装置
US20070083783A1 (en) * 2005-08-05 2007-04-12 Toru Ishihara Reducing power consumption at a cache
US7647514B2 (en) * 2005-08-05 2010-01-12 Fujitsu Limited Reducing power consumption at a cache
US20070043965A1 (en) * 2005-08-22 2007-02-22 Intel Corporation Dynamic memory sizing for power reduction
US7516274B2 (en) 2005-11-15 2009-04-07 Sun Microsystems, Inc. Power conservation via DRAM access reduction
US7752474B2 (en) 2006-09-22 2010-07-06 Apple Inc. L1 cache flush when processor is entering low power mode
US7606976B2 (en) * 2006-10-27 2009-10-20 Advanced Micro Devices, Inc. Dynamically scalable cache architecture
US7966457B2 (en) 2006-12-15 2011-06-21 Microchip Technology Incorporated Configurable cache for a microprocessor
JP5231867B2 (ja) * 2008-05-23 2013-07-10 株式会社東芝 キャッシュメモリシステム
US8271732B2 (en) * 2008-12-04 2012-09-18 Intel Corporation System and method to reduce power consumption by partially disabling cache memory
US8156357B2 (en) * 2009-01-27 2012-04-10 Freescale Semiconductor, Inc. Voltage-based memory size scaling in a data processing system
US9311245B2 (en) * 2009-08-13 2016-04-12 Intel Corporation Dynamic cache sharing based on power state
US8412885B2 (en) * 2009-11-12 2013-04-02 Intel Corporation Searching a shared cache by using search hints and masked ways
US8352683B2 (en) * 2010-06-24 2013-01-08 Intel Corporation Method and system to reduce the power consumption of a memory device

Similar Documents

Publication Publication Date Title
JP2013526739A5 (enExample)
JP2013542530A5 (enExample)
TWI455022B (zh) 提高處理器中渦輪加速模式之操作的電源效率之設備、方法及系統
EP2270625B1 (en) System and method for processor utilization adjustment to improve deep c-state use
WO2013102532A3 (en) Providing logical partitions with hardware-thread specific information reflective of exclusive use of a processor core
US9438624B2 (en) Detection of side channel attacks between virtual machines
JP2013542494A5 (enExample)
US20140067293A1 (en) Power sub-state monitoring
JP2013504127A5 (enExample)
TW201205322A (en) Computer component power-consumption database
JP2014203106A5 (enExample)
CN106662909A (zh) 操作系统中的启发式处理器电力管理
EP2972826B1 (en) Multi-core binary translation task processing
WO2013126066A1 (en) Wear-leveling cores of a multi-core processor
US9208755B2 (en) Low power application execution on a data processing device having low graphics engine utilization
US8972763B2 (en) Method, apparatus, and system for energy efficiency and energy conservation including determining an optimal power state of the apparatus based on residency time of non-core domains in a power saving state
TWI512629B (zh) 用於表格驅動之多重被動跳脫平台被動熱管理之設備及方法、計算系統及電腦可讀媒體
US10719107B2 (en) Method and apparatus to maintain node power budget for systems that share a power supply
JP5881198B2 (ja) 優先度ベースのインテリジェントプラットフォームの受動的熱管理
US9213585B2 (en) Controlling sprinting for thermal capacity boosted systems
CN107003954B (zh) 用于计算设备中的同步的方法、系统、设备和装置
TW201626228A (zh) 待機異常耗電偵測系統及方法
US10552167B2 (en) Clock-gating for multicycle instructions
CN105426229A (zh) 虚拟机迁移方法及装置
Koolwal Investigating latency effects of the Linux real-time Preemption Patches (PREEMPT RT) on AMD’s GEODE LX Platform