JP2013521557A5 - - Google Patents

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Publication number
JP2013521557A5
JP2013521557A5 JP2012555487A JP2012555487A JP2013521557A5 JP 2013521557 A5 JP2013521557 A5 JP 2013521557A5 JP 2012555487 A JP2012555487 A JP 2012555487A JP 2012555487 A JP2012555487 A JP 2012555487A JP 2013521557 A5 JP2013521557 A5 JP 2013521557A5
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Japan
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processing circuit
processing
transfer
circuit
data processing
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JP2012555487A
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Japanese (ja)
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JP2013521557A (ja
JP5823987B2 (ja
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Priority claimed from US12/659,234 external-priority patent/US8418187B2/en
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JP2012555487A 2010-03-01 2011-02-17 第１の処理回路と第２の処理回路との間で作業負荷を切り替えるためのデータ処理装置および方法 Active JP5823987B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/659,234 US8418187B2 (en) 2010-03-01 2010-03-01 Virtualization software migrating workload between processing circuitries while making architectural states available transparent to operating system
US12/659,234 2010-03-01
PCT/GB2011/050317 WO2011107776A1 (en) 2010-03-01 2011-02-17 A data processing apparatus and method for switching a workload between first and second processing circuitry

Publications (3)

Publication Number Publication Date
JP2013521557A JP2013521557A (ja) 2013-06-10
JP2013521557A5 true JP2013521557A5 (enExample) 2015-08-13
JP5823987B2 JP5823987B2 (ja) 2015-11-25

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JP2012555487A Active JP5823987B2 (ja) 2010-03-01 2011-02-17 第１の処理回路と第２の処理回路との間で作業負荷を切り替えるためのデータ処理装置および方法

Country Status (10)

Country Link
US (1) US8418187B2 (enExample)
JP (1) JP5823987B2 (enExample)
KR (1) KR101802140B1 (enExample)
CN (1) CN102782671B (enExample)
BR (1) BR112012021102B1 (enExample)
DE (1) DE112011100744T5 (enExample)
GB (1) GB2490823B (enExample)
IL (1) IL221270A (enExample)
RU (1) RU2520411C2 (enExample)
WO (1) WO2011107776A1 (enExample)

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US11150907B2 (en) 2015-01-13 2021-10-19 International Business Machines Corporation Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries

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US10775859B2 (en) * 2016-09-23 2020-09-15 Hewlett Packard Enterprise Development Lp Assignment of core identifier
JP2018101256A (ja) * 2016-12-20 2018-06-28 ルネサスエレクトロニクス株式会社 データ処理システム及びデータ処理方法
US10579575B2 (en) * 2017-02-24 2020-03-03 Dell Products L.P. Systems and methods of management console user interface pluggability
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10545762B2 (en) 2014-09-30 2020-01-28 International Business Machines Corporation Independent mapping of threads
US11144323B2 (en) 2014-09-30 2021-10-12 International Business Machines Corporation Independent mapping of threads
US10983800B2 (en) 2015-01-12 2021-04-20 International Business Machines Corporation Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices
US11150907B2 (en) 2015-01-13 2021-10-19 International Business Machines Corporation Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries

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