JP2013516846A - Integrated circuit integrated microphone - Google Patents

Abstract

  The integrated circuit (1000) includes a capacitive microphone with a backside cavity (1026) disposed within the substrate (1002) of the integrated circuit. Access holes (1006) can be formed in the substrate surface through the dielectric support layer (1004) to allow the etchant to access the substrate, thereby forming a backside cavity (1026). The backside cavity (1026) may be etched by providing an etchant to the substrate through the permeable membrane and access holes after the capacitive microphone fixation plate (1010) and permeable membrane (1018) are formed.

Description

  This application relates to the field of integrated circuits. More particularly, this application relates to integrating a microphone into an integrated circuit.

  In order to integrate a microphone into an integrated circuit, it may be necessary to form a back cavity to obtain the desired level of microphone sensitivity. Forming a sufficient volume of the back cavity may increase manufacturing costs and integrated circuit complexity.

  An integrated circuit that includes a capacitive microphone with a backside cavity may be formed such that the backside cavity is disposed within the substrate of the integrated circuit. Access holes can be formed through a dielectric support layer on the surface of the substrate so that the etchant can access the substrate, providing access to the etchant's substrate to form a backside cavity. The backside cavity can be etched by supplying an etchant through the permeable membrane and through the access hole to the substrate after forming the fixed plate and permeable membrane of the capacitive microphone.

  Exemplary embodiments will be described with reference to the accompanying drawings.

1 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a first embodiment, showing successive stages of manufacture. 1 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a first embodiment, showing successive stages of manufacture. 1 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a first embodiment, showing successive stages of manufacture. 1 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a first embodiment, showing successive stages of manufacture. 1 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a first embodiment, showing successive stages of manufacture. 1 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a first embodiment, showing successive stages of manufacture. 1 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a first embodiment, showing successive stages of manufacture. 1 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a first embodiment, showing successive stages of manufacture. 1 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a first embodiment, showing successive stages of manufacture.

FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a second embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a second embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a second embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a second embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a second embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a second embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a second embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a second embodiment, showing successive stages of manufacture.

FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a third embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a third embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a third embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a third embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a third embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a third embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a third embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a third embodiment, showing successive stages of manufacture.

FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a fourth embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a fourth embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a fourth embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a fourth embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a fourth embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a fourth embodiment, showing successive stages of manufacture. FIG. 6 is a cross-sectional view of an integrated circuit including a capacitive microphone formed in accordance with a fourth embodiment, showing successive stages of manufacture.

1 is a cross-sectional view of an integrated circuit including a capacitive microphone with a backside cavity including two or more cavity chambers. FIG.

  Capacitive microphones can be formed in an integrated circuit by etching a back cavity in the substrate of the integrated circuit such that the cavity does not extend to the bottom surface of the substrate. Further, the cavity etching can be performed on the top surface of the integrated circuit. A dielectric support layer can be formed on the top surface of the substrate, and an access hole can be formed in the dielectric support layer that provides access to the substrate from the top surface of the integrated circuit of the cavity etchant.

  1A-1I illustrate successive stages in the manufacture of an integrated circuit including a capacitive microphone according to a first exemplary embodiment.

As shown in FIG. 1A, an integrated circuit 1000 is formed in and on a substrate 1002. The substrate 1002 is usually a single crystal silicon wafer, but is a silicon on insulator (SOI) wafer, a HOT (hybrid orientation) having regions of different crystal plane orientations
technology) A wafer or other structure with a semiconductor region on the top surface of a substrate 1002 suitable for the manufacture of the IC 1000 may be used. A dielectric support layer 1004 is formed on the upper surface of the substrate 1002. In this embodiment, the dielectric support layer 1004 is substantially made of STI (shallow trench).
field) 1004 using an isolation process. In STI, trenches are etched into integrated circuit 1000, typically to a depth of 200-500 nanometers, and are typically electrically passivated by growing a thermal oxide layer on the sidewalls of the trench, typically a high density plasma. The trench is filled with an insulating material, typically silicon dioxide, by a thermal chemical vapor deposition (CVD) process with ozone, also known as an (HDP) process or a high aspect ratio process (HARP). It is within the scope of alternative embodiments to form a field oxide dielectric support layer using a local oxidation of silicon (LOCOS) process. An access hole 1006 is formed in the field oxide 1004 to provide access to the substrate 1002 in a subsequent cavity etch step. Field oxide 1004 is continuous in the area defined for the capacitive microphone. One or more optional silicide blocking layers 1008 may be formed over the top surface of the substrate 1002 over the access holes 1006 to prevent metal silicide from being formed on the substrate 1002 during subsequent manufacturing steps. . The silicide blocking layer 1008 may be silicon nitride having a thickness of 10 to 100 nanometers in one example, and silicon dioxide having a thickness of 250 to 200 nanometers in an alternative example. When forming the silicide blocking layer 1008, the silicide blocking layer 1008 may be removed during subsequent manufacturing steps.

  In FIG. 1B, a fixed plate 1010 is formed on the field oxide 1004 adjacent to the access hole 1006. The fixed plate 1010 provides one condenser plate for the capacitive microphone. The optional membrane terminal 1012 may be formed simultaneously with the fixed plate 1010 as shown in FIG. 1B, or may be formed in other manufacturing steps. In one example of this embodiment, the fixed plate 1010 and, if formed, optional membrane terminal 1012 may be fully silicided polycrystalline silicon. In other examples of this embodiment, the fixed plate 1010 and, if formed, the optional membrane terminal 1012 may be a metal such as tungsten or aluminum. In one example, fixed plate 1010 may be less than 100 microns wide. A protective layer (not shown), possibly an electrically insulating layer, may optionally be formed on the fixed plate 1010 to isolate the fixed plate 1010 during the operational lifetime of the capacitive microphone.

  In FIG. 1C, an optional interconnect / dielectric level 1014 may be formed on the substrate 1002. These dielectric levels may be low-k dielectric materials such as silicon dioxide, organosilicate glass (OSG), carbon-doped silicon oxide (SiCO or CDO), or methylsilsesquioxane (MSQ). The interconnect level can include aluminum or copper.

  In FIG. 1D, a capacitor cavity sacrificial layer 1016 is formed on the fixed plate 1010. Capacitor cavity sacrificial layer 1016 includes a sacrificial material such as photoresist or polyimide. In one example of this embodiment, the capacitor cavity sacrificial layer 1016 is formed, for example, by forming a layer of photosensitive sacrificial material on an existing top surface of the integrated circuit 1000 by a photolithography process, such as a photo of a wafer stepper or wafer scanner. It can be formed by exposing a pattern of photosensitive sacrificial material using a lithographic apparatus and developing the photosensitive sacrificial material to leave a capacitor cavity sacrificial layer 1016. In an alternative embodiment, a layer of sacrificial material is formed on the existing top surface of integrated circuit 1000, and a photoresist pattern is formed on the sacrificial material layer to define an area for capacitor cavity sacrificial layer 1016, which is not required. The sacrificial material may be removed to leave the capacitor cavity sacrificial layer 1016. Other processes for forming the capacitor cavity sacrificial layer 1016 are also within the scope of this embodiment.

  In FIG. 1E, a continuous permeable membrane 1018 is formed on the capacitor cavity sacrificial layer 1016. The permeable membrane 1018 provides a second condenser plate for the capacitive microphone. In one example of this embodiment, the permeable membrane 1018 may be formed of a metal used for the interconnect level in the integrated circuit 1000. A membrane hole 1020 is formed in the permeable membrane 1018. In one example of this embodiment, the vertical separation between the bottom surface of the permeable membrane 1018 and the top surface of the fixed plate 1010 is less than 200 nanometers. In an alternative example of this embodiment, the vertical separation between the bottom surface of the permeable membrane 1018 and the top surface of the fixed plate 1010 is less than 100 nanometers.

  In FIG. 1F, a sacrificial layer removal process 1022 is performed to remove the sacrificial material from the capacitor cavity sacrificial layer 1016. In one example of this embodiment, as shown in FIG. 1F, the sacrificial layer removal process 1022 diffuses through the film hole 1020 to remove reactive molecules, atoms, or atoms that remove the sacrificial material from the capacitor cavity sacrificial layer 1016. Provides radicals. In one example of this embodiment, the sacrificial layer removal process 1022 generates reactive oxygen species and possibly reactive fluorine species in a remote plasma and diffuses the reactive oxygen species into the integrated circuit 1000 in the field-free region. Means for providing are provided. In an alternative example of this embodiment, the sacrificial layer removal process 1022 provides ozone to the integrated circuit 1000. In an alternative example of this embodiment, the sacrificial layer removal process 1022 provides the integrated circuit with an elevated temperature, eg, 300-500 ° C., and possibly a reactive atmosphere, eg, oxygen, thereby within the capacitor cavity sacrificial layer 1016. The sacrificial material will decompose.

In FIG. 1G, a cavity formation process 1024 is performed to provide reactive species through the film hole 1020 to the substrate 1002 in the access hole 1006. In one example of this embodiment, the cavity formation process 1024 provides a fluorine-containing reactive species to the substrate 1002 using a plasma-like SF ₆ gas. The reactive species provided by the cavity formation process 1024 removes the semiconductor material from the exposed surface of the substrate 1002. The etching rate of field oxide 1004 is much slower than the etching rate of substrate 1002 by cavity formation process 1024, for example, less than 5%.

  FIG. 1H shows the integrated circuit 1000 during a later stage of the cavity formation process 1024. Reactive species from the cavity formation process 1024 diffuse through the access hole 1006 and remove semiconductor material from the substrate 1002 under the field oxide 1004 adjacent to the access hole 1006.

  FIG. 1I shows the integrated circuit 1000 after the formation of the capacitive microphone is substantially complete. A backside cavity 1026 is formed in the substrate 1002 below the fixed plate 1010 of the capacitive microphone so that the bottom of the backside cavity 1026 is in the substrate 1002. A protective coating (not shown) may optionally be formed on the exposed surfaces of the membrane 1018 and backside cavity 1026 for protection during the operational life of the capacitive microphone. The backside cavity is connected to the space between the fixed plate 1010 and the membrane 1018 via the access hole 1006. In one example of this embodiment, the backside cavity 1026 may extend laterally beyond the membrane 1018. In one example of this embodiment, the volume of the backside cavity 1026 is greater than 100 times the volume of the space between the fixed plate 1010 and the membrane 1018. In an alternative embodiment, the volume of the backside cavity 1026 is greater than 1000 times the volume of the space between the fixed plate 1010 and the membrane 1018.

  2A-2H illustrate the steps of manufacturing an integrated circuit including an integrated capacitive microphone according to a second exemplary embodiment.

  FIG. 2A shows an integrated circuit 2000 formed in and on the substrate 2002. In this embodiment, as described with reference to FIG. 1A, a continuous dielectric support layer of STI field oxide 2004 is formed on the top surface of substrate 2002 along with access holes 2006 in field oxide 2004. In one example of the present embodiment, as described with reference to FIG. 1A, metal silicide is not formed on the upper surface of the substrate 2002 in the access hole 2006. An interconnect region 2008 including a dielectric layer 2010 and a metal interconnect component 2012 is formed on the substrate 2002 and field oxide 2004. In some examples of this embodiment, no metal interconnect component 2012 is placed in the area defined for the capacitive microphone. In the present embodiment, the metal interconnect component 2012 is not disposed immediately above the access hole 2006.

  In FIG. 2B, a fixed plate 2014 is formed over the interconnect region 2008. In one example of this embodiment, the fixation plate 2014 is formed of the same material as the metal interconnect component 2012 in the interconnect region 2008. In the present embodiment, the fixing plate 2014 is not disposed immediately above the access hole 2006. The optional membrane terminal 2016 may be formed at the same time as the fixed plate 2014 as shown in FIG. 2B, or may be formed in other manufacturing steps. In one example of this embodiment, the fixation plate 2014, and optional membrane terminal 2016, if present, includes aluminum. In an alternative example of this embodiment, the fixed plate 2014, and optional membrane terminal 2016, if present, includes copper. A protective layer (not shown), possibly an electrical insulating layer, may optionally be formed on the fixed plate 2014 so as to isolate the fixed plate 2014 during the operational lifetime of the capacitive microphone. In FIG. 2B and subsequent figures of this embodiment, the boundaries between the dielectric layers in the interconnect region 2008 are not shown for clarity.

  In FIG. 2C, an access via photoresist pattern 2018 is formed on the existing top surface of the integrated circuit 2000 to define an area for the access via 2020 in the interconnect region 2008. Access via etch process 2022 removes dielectric material from interconnect region 2008 to form access via 2020. In one example of this embodiment, the access via etch process 2022 may be performed using a reactive ion etch (RIE) process. In the RIE process, reactive ions are sent toward the top surface of the integrated circuit 2000. In one example, the RIE process can include a fluorine-containing plasma. Access via 2020 extends to the semiconductor material of substrate 2002 in access hole 2006 through field oxide 2004. After the formation of the access via 2020 is completed, the access via photoresist is removed, for example, by exposing the integrated circuit 2000 to an oxygen-containing plasma and then performing a wet clean to remove any organic residues from the top surface of the integrated circuit 2000. The pattern 2018 is removed.

  In FIG. 2D, the capacitor cavity sacrificial layer 2024 is formed on the fixed plate 2014 as described with reference to FIG. 1D. Other processes for forming the capacitor cavity sacrificial layer 2024 are also within the scope of this embodiment. Capacitor cavity sacrificial layer 2024 includes a sacrificial material such as photoresist or polyimide. In one example of this embodiment, additional sacrificial material 2026 may be formed outside the area defined for the capacitive microphone. As shown in FIG. 2D, the sacrificial material of the capacitor cavity sacrificial layer 2024 may extend into the access via 2020 and fill the access via 2020.

  In FIG. 2E, a continuous permeable membrane 2028 is formed on the capacitor cavity sacrificial layer 2024 as described with reference to FIG. 1E. As described with reference to FIG. 1E, a film hole 2030 is formed in the permeable film 2028. In one example of this embodiment, the vertical separation between the bottom surface of the permeable membrane 2028 and the top surface of the fixed plate 2014 is less than 200 nanometers. In an alternative example of this embodiment, the vertical separation between the bottom surface of the permeable membrane 2028 and the top surface of the fixed plate 2014 is less than 100 nanometers.

  In FIG. 2F, a sacrificial layer removal process 2032 is performed to remove the sacrificial material from the capacitor cavity sacrificial layer 2024 as described with reference to FIG. 1F. In this embodiment, the sacrificial material is removed from the access via 2020.

  In FIG. 2G, as described with reference to FIG. 1G, a cavity formation process 2034 is performed to provide reactive species to the substrate 2002 through the film hole 2030. As described with reference to FIGS. 1G and 1H, reactive species from the cavity formation process 2034 diffuse through the access via 2020 and remove semiconductor material from the substrate 2002.

  FIG. 2H shows the integrated circuit 2000 after the formation of the capacitive microphone is substantially complete. A backside cavity 2036 is formed in the substrate 2002 below the field oxide 2004 of the integrated circuit 2000 such that the bottom of the backside cavity 2036 is in the substrate 2002. A protective coating (not shown) may optionally be formed on the exposed surfaces of the membrane 2028 and backside cavity 2036 for protection during the operational life of the capacitive microphone. The backside cavity is connected to the space between the fixed plate 2014 and the membrane 2028 via the access hole 2006 and the access via 2020. In one example of this embodiment, the backside cavity 2036 may extend laterally beyond the membrane 2028. In one example of this embodiment, the sum of the volume of the backside cavity 2036 and the volume of the access via 2020 is greater than 100 times the volume of the space between the fixed plate 2014 and the membrane 2028. In an alternative embodiment, the sum of the volume of the backside cavity 2036 and the volume of the access via 2020 is greater than 1000 times the volume of the space between the fixed plate 2014 and the membrane 2028.

  3A-3H illustrate the fabrication steps of an integrated circuit that includes a capacitive microphone formed in accordance with a third exemplary embodiment.

  As shown in FIG. 3A, an integrated circuit 3000 is formed in and on the substrate 3002, as described with reference to FIG. 1A. In this embodiment, a dielectric support layer 3004 is formed on the top surface of the substrate 3002 in the area defined for the capacitive microphone. In one example of this embodiment, the dielectric support layer 3004 can extend across the entire top surface of the integrated circuit 3000. A fixing plate 3006 is formed on the dielectric support layer 3004. Fixed plate 3006 provides one condenser plate for the capacitive microphone. The optional membrane terminal 3008 may be formed at the same time as the fixed plate 3006 as shown in FIG. 3A, or may be formed in other manufacturing steps. In one example of this embodiment, the fixed plate 3006 and, if formed, the optional film terminal 3008 may be fully silicided polycrystalline silicon. In other examples of this embodiment, the fixed plate 3006 and, if formed, the optional membrane terminal 3008 may be a metal such as tungsten or aluminum. In one example, the fixation plate 3006 may be less than 100 microns wide. A protective layer (not shown), possibly an electrically insulating layer, may optionally be formed on the fixed plate 3006 so as to isolate the fixed plate 3006 during the operational lifetime of the capacitive microphone.

  In FIG. 3B, an access hole photoresist pattern 3010 is formed on the existing top surface of the integrated circuit 3000 to define an area for the access hole 3012 adjacent to the fixed plate 3006 and through the dielectric support layer 3004. . The access hole etch process 3014 removes the dielectric material from the dielectric support layer 3004 to expose the substrate 3002 in the access hole 3012. In one example of this embodiment, the access hole etch process 3014 may include an RIE process using a fluorine-containing plasma. In an alternative embodiment, the access hole etching process 3014 may be performed using wet etching, for example with a dilute solution of hydrofluoric acid, perhaps a buffer solution. After the access hole 3012 is formed, the access hole photoresist pattern 3010 is formed by exposing the integrated circuit 3000 to an oxygen-containing plasma, for example, and then removing any organic residue from the top surface of the integrated circuit 3000 by wet cleaning. Removed.

  In FIG. 3C, an optional interconnect and dielectric level 3016 may be formed on the substrate 3002, as described with reference to FIG. 1C. As described with reference to FIG. 1D, a capacitor cavity sacrificial layer 3018 is formed on the fixed plate 3006. Other processes for forming the capacitor cavity sacrificial layer 3018 are also within the scope of this embodiment. Capacitor cavity sacrificial layer 3018 includes a sacrificial material such as photoresist or polyimide. This sacrificial material extends into the access hole 3012.

  In FIG. 3D, a continuous capacitor cavity sacrificial layer 3018 is formed as described with reference to FIG. 1E. The permeable membrane 3020 provides the second condenser plate of the capacitive microphone. A film hole 3022 is formed in the permeable film 3020. In one example of this embodiment, the vertical separation between the bottom surface of the permeable membrane 3020 and the top surface of the fixed plate 3006 is less than 200 nanometers. In an alternative example of this embodiment, the vertical separation between the bottom surface of the permeable membrane 3020 and the top surface of the fixed plate 3006 is less than 100 nanometers.

  In FIG. 3E, a sacrificial layer removal process 3024 is performed to remove the sacrificial material from the capacitor cavity sacrificial layer 3018, as described with reference to FIG. 1F. The sacrificial material removal process 3024 continues until substantially all of the sacrificial material is removed from the capacitor cavity sacrificial layer 3018, as shown in FIG. 3F.

  In FIG. 3G, as described with reference to FIG. 1G, a cavity formation process 3026 is performed to provide reactive species to the substrate 3002 through the film hole 3022. As described with reference to FIGS. 1G and 1H, the cavity formation process 3026 diffuses reactive species through the access hole 3012 to remove semiconductor material from the substrate 3002.

  FIG. 3H shows the integrated circuit 3000 after the formation of the capacitive microphone is substantially complete. A backside cavity 3028 is formed in the substrate 3002 below the dielectric support layer 3004 so that the bottom of the backside cavity 3028 is in the substrate 3002. A protective coating (not shown) may optionally be formed on the exposed surfaces of the membrane 3020 and backside cavity 3028 for protection during the operational life of the capacitive microphone. The backside cavity is connected to the space between the fixed plate 3006 and the membrane 3020 via the access hole 3012. In one example of this embodiment, the backside cavity 3028 may extend laterally beyond the membrane 3020. In one example of this embodiment, the volume of the backside cavity 3028 is greater than 100 times the volume of the space between the fixed plate 3006 and the membrane 3020. In an alternative embodiment, the volume of the backside cavity 3028 is greater than 1000 times the volume of the space between the fixed plate 3006 and the membrane 3020.

  4A-4G illustrate the fabrication steps of an integrated circuit that includes a capacitive microphone formed in accordance with a fourth exemplary embodiment.

  Referring to FIG. 4A, an integrated circuit 4000 is formed in and on the substrate 4002, as described with reference to FIG. 1A. In this embodiment, a dielectric support layer 4004 is formed on the top surface of the substrate 4002 in the area defined for the capacitive microphone. In one example of this embodiment, the dielectric support layer 4004 may extend over the entire top surface of the integrated circuit 4000. An interconnect region 4006 is formed on the dielectric support layer 4004 including the dielectric layer 4008 and the metal interconnect component 4010. In some examples of this embodiment, no metal interconnect component 4010 is placed in the area defined for the capacitive microphone. In FIG. 4A and subsequent figures of this embodiment, the boundary lines between the dielectric layers in the interconnect region 4006 are not shown for clarity. A fixed plate 4012 is formed over the interconnect area 4006 in the area defined for the capacitive microphone. In one example of this embodiment, the fixation plate 4012 is formed of the same material as the metal interconnect component 4010 in the interconnect region 4006. An optional membrane terminal 4014 may be formed at the same time as the stationary plate 4012 as shown in FIG. 4A, or may be formed in other manufacturing steps. In one example of this embodiment, the fixation plate 4012 and optional membrane terminal 4014, if present, includes aluminum. In an alternative embodiment, the fixation plate 4012 and optional membrane terminal 4014, if present, includes copper. A protective layer (not shown), possibly an electrically insulating layer, may optionally be formed on the fixed plate 4012 so as to isolate the fixed plate 4012 during the operational lifetime of the capacitive microphone.

  In FIG. 4B, access via photoresist pattern 4016 is formed on an existing top surface of integrated circuit 4000 to define a region for access hole 4022 through access via 4018 and dielectric support layer 4004 in interconnect region 4006. It is formed. Access via etch process 4020 removes dielectric material from interconnect region 4006 and dielectric support layer 4004 to form access via 4018 through interconnect region 4006 and access hole 4022 through dielectric support layer 4004. The In one example of this embodiment, the access via etch process 4020 may be performed using an RIE process using a fluorine-containing plasma. Access via 4018 extends through dielectric support layer 4004 to the semiconductor material of substrate 4002. After the formation of the access via 4018 is complete, the access via photoresist pattern 4016 is removed as described with reference to FIG. 2G.

  In FIG. 4C, a capacitor cavity sacrificial layer 4024 is formed on the stationary plate 4012 as described with reference to FIG. 2D. Capacitor cavity sacrificial layer 4024 includes a sacrificial material such as photoresist or polyimide. In one example of this embodiment, additional sacrificial material 4026 may be formed outside the area defined for the capacitive microphone. The sacrificial material of the capacitor cavity sacrificial layer 4024 may extend into the access via 4018 and fill the access via 4018 as shown in FIG. 4C.

  In FIG. 4D, a continuous permeable membrane 4028 is formed on the capacitor cavity sacrificial layer 4024 as described with reference to FIG. 1E. As described with reference to FIG. 1E, a film hole 4030 is formed in the permeable film 4028. In one example of this embodiment, the vertical separation between the bottom surface of the permeable membrane 4028 and the top surface of the fixed plate 4012 is less than 200 nanometers. In an alternative embodiment, the vertical separation between the bottom surface of the permeable membrane 4028 and the top surface of the stationary plate 4012 is less than 100 nanometers.

  In FIG. 4E, as described with reference to FIG. 1F, a sacrificial layer removal process 4032 is performed to remove the sacrificial material from the capacitor cavity sacrificial layer. In this embodiment, the sacrificial material is removed from the access via 4018.

  In FIG. 4F, a cavity formation process 4034 is performed to provide reactive species to the substrate 4002 through the film hole 4030 as described with reference to FIG. 1G. As described with reference to FIGS. 1G and 1H, reactive species from the cavity formation process 4034 diffuse through the access via 4018 and remove semiconductor material from the substrate 4002.

  FIG. 4G shows the integrated circuit 4000 after the formation of the capacitive microphone is substantially complete. A backside cavity 4036 is formed in the substrate 4002 below the dielectric support layer 4004 so that the bottom of the backside cavity 4036 is in the substrate 4002. A protective coating (not shown) may optionally be formed on the exposed surfaces of the membrane 4028 and backside cavity 4036 for protection during the operational life of the capacitive microphone. The backside cavity 4036 is connected to the space between the fixed plate 4012 and the membrane 4028 through the access via 4018. In one example of this embodiment, the backside cavity 4036 may extend laterally beyond the membrane 4028. In one example of this embodiment, the sum of the volume of the backside cavity 4036 and the volume of the access via 4018 is greater than 100 times the volume of the space between the fixed plate 4012 and the membrane 4028. In an alternative embodiment, the sum of the volume of backside cavity 4036 and the volume of access via 4018 is greater than 1000 times the volume of the space between fixed plate 4012 and membrane 4028.

  FIG. 5 shows an integrated circuit that includes a capacitive microphone with a backside cavity that includes two or more cavity chambers. The integrated circuit 5000 is built in and on the substrate 5002, as described with reference to FIG. 1A. In one embodiment, a field oxide 5004 may be formed with an access hole 5006 on the top surface of the substrate 5002, as described with reference to FIG. 1A. In an alternative embodiment, a dielectric support layer may be formed on the top surface of the substrate 5002, as described with reference to FIG. 3A, and access holes in the dielectric support layer as described with reference to FIG. 3B. 5006 may be formed. In some embodiments, an interconnect region 5008 may be formed over the substrate 5002 and field oxide 5004 or dielectric support layer, as described with reference to FIGS. 2A and 4A. In such an embodiment, an access via 5010 is formed through the interconnect region 5008 as described with reference to FIGS. 2C and 4B. According to this particular embodiment, a capacitive microphone fixation plate 5012 is formed on the substrate, as described with reference to FIGS. 1B, 2B, 3A, or 4A. According to this particular embodiment, only the space above the fixed plate 5012 is above the fixed plate 5012 as described with reference to FIGS. 1D-1F, 2D-2F, 3C-3E, or 4C-4E. Separately, a permeable membrane 5014 of a capacitive microphone is formed.

  In accordance with this particular embodiment, as described with reference to FIGS. 1G-1I, FIGS. 2G and 2H, FIGS. 3G and 3H, or FIGS. 4F and 4G, a backside cavity 5016 with a plurality of cavity chambers 5018 includes: Formed in the substrate 5002 below the fixed plate. In some implementations, a membrane 5014 can be supported over the substrate region between the cavity chambers 5018, as shown in FIG. In some examples of embodiments including multiple cavity chambers, the backside cavity 5016 can extend laterally beyond the membrane 5014.

  In some embodiments, the sum of the volume of the backside cavity 5016 and the volume of the access via 5010, if present, is greater than 100 times the volume of the space between the fixed plate 5012 and the membrane 5014. In an alternative embodiment, the sum of the volume of the backside cavity 5016 and the volume of the access via 5010, if present, is greater than 1000 times the volume of the space between the fixed plate 5012 and the membrane 5014.

  Embodiments having different combinations of one or more features or steps described in the context of an exemplary embodiment having all or part of the features or steps described in the context of the exemplary embodiment are also encompassed herein. Is intended. Those skilled in the art will appreciate that many other embodiments and variations are possible within the scope of the claims of the present invention.

Claims (10)

An integrated circuit including a capacitive microphone,
A substrate having a semiconductor region, wherein the semiconductor region extends to a surface of the substrate;
A dielectric support layer formed on the surface of the substrate, the dielectric support layer having an access hole penetrating the dielectric support layer;
A fixed plate of the capacitive microphone, the fixed plate disposed on the dielectric support layer;
A permeable membrane of the capacitive microphone, wherein the permeable membrane is disposed on the fixed plate so that the permeable membrane is separated from the fixed plate by a certain space; and
A backside cavity formed in the substrate, and connected to the space between the permeable membrane and the fixing plate through the access hole so that a bottom portion of the cavity is disposed in the substrate. The backside cavity,
An integrated circuit.   The integrated circuit of claim 1, wherein the dielectric support layer comprises a field oxide formed by a shallow trench isolation process.   The integrated circuit according to claim 1, wherein the fixed plate contacts the dielectric support layer.   The integrated circuit of claim 1, wherein the fixed plate is separated from the dielectric support layer by an interconnect area.   2. The integrated circuit according to claim 1, wherein the volume of the backside cavity is greater than 100 times the volume of the space between the permeable membrane and the fixed plate. A process for forming an integrated circuit including a capacitive microphone, comprising:
Providing a substrate, wherein the substrate includes a semiconductor region extending to a surface of the substrate;
Forming a dielectric support layer on the surface of the substrate;
Forming an access hole through the dielectric support layer;
Forming a fixed plate of the capacitive microphone on the dielectric support layer;
Forming a capacitor cavity sacrificial layer including a sacrificial material on the fixed plate;
Forming a permeable membrane on the capacitor cavity sacrificial layer;
Removing the sacrificial material from the capacitor cavity sacrificial layer such that the permeable membrane is separated from the fixed plate by a certain space;
Performing a cavity formation process, wherein a backside cavity is formed in the substrate by providing an etchant to the substrate through the permeable membrane, through the access hole, and thereby the backside The step of connecting a cavity to the space between the permeable membrane and the fixed plate via the access hole such that the bottom of the cavity is disposed in the substrate;
Including processes.   The process of claim 6, wherein the dielectric support layer comprises a field oxide formed by a shallow trench isolation process.   8. The process of claim 7, further comprising forming one or more silicide blocking layers over the access holes on the surface of the substrate.   7. The process of claim 6, wherein an interconnect region is formed on the dielectric support layer before the step of forming the anchor plate is performed, so that the anchor plate is in the interconnect region. The system further comprising a step disposed on. A process according to claim 6, wherein the step of performing the cavity formation process, further comprises fluorine-containing reactive species to form a plasma containing SF ₆ gas is provided to the substrate, the process.