JP2013512511A - 複数メモリ特定用途向けデジタル信号プロセッサ - Google Patents

複数メモリ特定用途向けデジタル信号プロセッサ Download PDF

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JP2013512511A
JP2013512511A JP2012541208A JP2012541208A JP2013512511A JP 2013512511 A JP2013512511 A JP 2013512511A JP 2012541208 A JP2012541208 A JP 2012541208A JP 2012541208 A JP2012541208 A JP 2012541208A JP 2013512511 A JP2013512511 A JP 2013512511A
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digital signal
data unit
signal processors
memory
instruction
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JP2013512511A5 (enExample
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ジュニア クレイ エス グロスター
ワンダ ディー ゲイ
マイケラ イー アモー
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ハワード ユニバーシティ
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G06F15/7885—Runtime interface, e.g. data exchange, runtime control

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Microcomputers (AREA)
  • Complex Calculations (AREA)
JP2012541208A 2009-11-25 2010-11-24 複数メモリ特定用途向けデジタル信号プロセッサ Pending JP2013512511A (ja)

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US26433409P 2009-11-25 2009-11-25
US61/264,334 2009-11-25
PCT/US2010/058100 WO2011066459A2 (en) 2009-11-25 2010-11-24 Multiple-memory application-specific digital signal processor

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JP2013512511A true JP2013512511A (ja) 2013-04-11
JP2013512511A5 JP2013512511A5 (enExample) 2014-01-16

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US (1) US9111068B2 (enExample)
EP (1) EP2504767A4 (enExample)
JP (1) JP2013512511A (enExample)
WO (1) WO2011066459A2 (enExample)

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JP2017506406A (ja) * 2014-02-20 2017-03-02 スティルウォーター スーパーコンピューティング，インク． アフィン従属による単一割当プログラムを実行するための実行エンジン

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WO2011066459A2 (en) 2009-11-25 2011-06-03 Howard University Multiple-memory application-specific digital signal processor
US9703538B2 (en) * 2011-06-08 2017-07-11 Hyperion Core, Inc. Tool-level and hardware-level code optimization and respective hardware modification
CN103186501A (zh) * 2011-12-29 2013-07-03 中兴通讯股份有限公司 一种多处理器共享存储方法及系统
CN103577266B (zh) * 2012-07-31 2017-06-23 国际商业机器公司 用于对现场可编程门阵列资源进行分配的方法及系统
CN104424128B (zh) * 2013-08-19 2019-12-13 上海芯豪微电子有限公司 变长指令字处理器系统和方法
EP2843616A1 (de) * 2013-08-29 2015-03-04 Sick Ag Optoelektronische Vorrichtung und Verfahren zur Aufnahme entzerrter Bilder
US10320390B1 (en) 2016-11-17 2019-06-11 X Development Llc Field programmable gate array including coupled lookup tables
US20190050263A1 (en) * 2018-03-05 2019-02-14 Intel Corporation Technologies for scheduling acceleration of functions in a pool of accelerator devices

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JP2004533672A (ja) * 2001-03-03 2004-11-04 マルコニ ユーケイ インテレクチュアル プロパティー リミテッド コンフィギュラブルロジックデバイス上の進化プログラミング
US20060004997A1 (en) * 2001-05-04 2006-01-05 Robert Keith Mykland Method and apparatus for computing
JP4188233B2 (ja) * 2001-07-12 2008-11-26 アイピーフレックス株式会社 集積回路装置

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JP2001500682A (ja) * 1996-09-03 2001-01-16 ザイリンクス・インコーポレイテッド プログラム可能なワード長および幅を有するｒａｍブロックと専用アドレスおよびデータラインとを有するｆｐｇａアーキテクチャ
JP2004533672A (ja) * 2001-03-03 2004-11-04 マルコニ ユーケイ インテレクチュアル プロパティー リミテッド コンフィギュラブルロジックデバイス上の進化プログラミング
US20060004997A1 (en) * 2001-05-04 2006-01-05 Robert Keith Mykland Method and apparatus for computing
JP4188233B2 (ja) * 2001-07-12 2008-11-26 アイピーフレックス株式会社 集積回路装置

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JPN6014042520; Ｃｌａｙ　ＧＬＯＳＴＥＲ，　Ｊｒ．: '"Ｆｌｏａｔｉｎｇ　Ｐｏｉｎｔ　Ｆｕｎｃｔｉｏｎａｌ　Ｃｏｒｅｓ　ｆｏｒ　Ｒｅｃｏｎｆｉｇｕｒａｂｌｅ　Ｃｏｍｐｕｔｉｎｇ　Ｓｙｓｔｅｍｓ"' Ｔｈｅ　ｔｈｉｒｄ　ａｎｎｕａｌ　Ｅａｒｔｈ　Ｓｃｉｅｎｃｅ　Ｔｅｃｈｎｏｌｏｇｙ　Ｃｏｎｆｅｒｅｎｃｅ　（ＥＳＴＣ），２００３ , 20030625, ｐａｇｅｓ：１-５, ＮＡＳＡ　Ｅａｒｔｈ　Ｓｃｉｅｎｃｅ　Ｔｅｃｈｎｏｌｏｇｙ　Ｏｆｆｉｃｅ *
JPN6014042525; Ｃｌａｙ　ＧＬＯＳＴＥＲ，　Ｊｒ．　ｅｔ　ａｌ．: '"Ｏｐｔｉｍｉｚｉｎｇ　ｔｈｅ　Ｄｅｓｉｇｎ　ｏｆ　ａ　Ｃｏｎｆｉｇｕｒａｂｌｅ　Ｄｉｇｉｔａｌ　Ｓｉｇｎａｌ　Ｐｒｏｃｅｓｓｏｒ　ｆｏｒ　Ａｃｃｅｌｅｒａｔｅｄ　Ｅｘｅｃｕｔｉｏｎ　ｏｆ　ｔｈｅ　２' ＨＩＣＳＳ　'０６．　Ｐｒｏｃｅｅｄｉｎｇｓ　ｏｆ　ｔｈｅ　３９ｔｈ　Ａｎｎｕａｌ　Ｈａｗａｉｉ　Ｉｎｔｅｒｎａｔｉｏｎａｌ　Ｃｏｎｆｅｒｅｎｃｅ　ｏｎ　Ｓｙｓｔｅｍ　Ｓｃｉｅｎｃｅｓ，　２００６． , 20060107, ｐａｇｅｓ：１-８, ＩＥＥＥ *
JPN6016024450; '"Ｂｅｎｅｆｉｔｓ　ｏｆ　Ｅｍｂｅｄｄｅｄ　ＲＡＭ　ｉｎ　ＦＬＥＸ　１０Ｋ　Ｄｅｖｉｃｅｓ"' Ｐｒｏｄｕｃｔ　Ｉｎｆｏｒｍａｔｉｏｎ　Ｂｕｌｌｅｔｉｎ　２０　（ＰＩＢ　２０） , 199601, １頁〜８頁, Ａｌｔｅｒａ　Ｃｏｒｐｏｒａｔｉｏｎ *
JPN6016024451; 山口 耕作: '［ＦＰＧＡの非論理機能を使いこなす 乗算器，メモリ・ブロック，クロック・マネージャの活用 第２章 デ' Ｄｅｓｉｇｎ Ｗａｖｅ ＭＡＧＡＺＩＮＥ 第１０巻 第４号, 20050401, ９７頁〜１０４頁, ＣＱ出版株式会社 *
JPN6016024452; '「ブロックＲＡＭの使い方」' ［ｏｎｌｉｎｅ］ , 20021012, １頁〜８頁 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017506406A (ja) * 2014-02-20 2017-03-02 スティルウォーター スーパーコンピューティング，インク． アフィン従属による単一割当プログラムを実行するための実行エンジン

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EP2504767A2 (en) 2012-10-03
WO2011066459A3 (en) 2011-09-22
WO2011066459A2 (en) 2011-06-03
US20110167225A1 (en) 2011-07-07
EP2504767A4 (en) 2015-05-20
US9111068B2 (en) 2015-08-18

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