JP2013500660A - Information encoding and decoding - Google Patents

Abstract

  Methods, systems, and apparatus are provided that include a computer program encoded on a computer storage medium for encoding and decoding information. In one aspect, a method of encoding information in an encoder includes an operation of receiving a signal representing information using a collection of discrete numbers, an operation of converting the received signal into a time-based code, and a time. Operation to output a base code. Time-based codes are divided into time intervals. Each time interval of the time-based code corresponds to a number in the received signal. Each number of the first state of the received signal is represented as an event that occurs at a first time within a corresponding time interval of the time-based code. Each second state number of the received signal is represented as an event occurring at a second time within a corresponding time interval of the time-based code, the first time being identifiable from the second time. All numeric states in the received signal are represented by events in a time-based code.

Description

BACKGROUND This specification relates to the encoding and decoding of information.

  An encoder is a device that converts information from a first representation to a second representation. Encoders can be included in many different systems and devices, including data communication devices, data storage devices, data compression devices, data encryption devices, and combinations of these and other devices. The encoder can be paired with a decoder that can recover the information. The encoded information and the decoded information can be communicated by signals and / or stored in a data storage device.

  Biological neurons and other biological nervous systems can communicate by encoding information using electrochemical signaling. For example, the living nervous system can encode information with action potentials of approximately equal amplitude. The living nervous system includes synapses that act as electrochemical transducers that convert electrochemical signals into electrical conductance changes. Even a single neuron can receive thousands of electrochemical signals as input on its branches (referred to as “dendrites”). These inputs result in voltage changes across the cell membrane synthesized in a time-dependent manner. The composition of this input follows the laws of passive (linear), active (non-linear), cable (decay over time), and electrochemical (diffusion). Under some circumstances, such inputs can be combined into a series of consecutive action potentials.

Overview This specification describes techniques for encoding and decoding information.

  In general, one innovative aspect of the subject matter described in this specification can be embodied in a method of encoding information at an encoder, and receives a signal representing information using a collection of discrete numbers. An operation, an operation of converting a received signal into a time-based code by an encoder, and an operation of outputting a time-based code. Time-based codes are divided into time intervals. Each time interval of the time-based code corresponds to a number in the received signal. Each digit of the first state of the received signal is represented as an event that occurs at a first time within a corresponding time interval of the time-based code. Each digit of the second state of the received signal is represented as an event that occurs at a second time within a corresponding time interval of the time-based code. The first time can be identified from the second time. All numeric states in the received signal are represented by events in a time-based code.

  Other embodiments of this aspect include corresponding systems, devices and computer programs encoded on a computer storage device and configured to perform the operations of the methods described above.

  Another innovative aspect of the subject matter described in this specification includes an input for receiving a signal representing information using a collection of discrete numbers, an encoder for encoding the received signal, and a time-based code. And an output for supplying to another system or device. The encoder includes a state detector configured to detect a numeric state in the received signal and a translator configured to translate the numeric state in the received signal into a time-based code, where the time-based code is a time Each of the time intervals is assigned a respective number in the received signal, each of the time intervals includes an event, and the timing of the event within each time interval is the number of the assigned number Characterize the condition.

  Other embodiments of this aspect include corresponding methods and computer programs encoded on a computer storage device and configured to perform the operations of the methods described above.

  Another innovative aspect of the subject matter described in this specification can be embodied in a method for decoding a time-based code signal, the operation of receiving a time-based code signal at a decoder, and An operation for detecting the timing of an event within a time interval, and an operation for outputting a signal representing information represented by a time-based code signal using a collection of discrete numbers. The time-based code signal is divided into time intervals, each time interval of the time-based code signal includes an event, and the timing of the event within the time interval represents the information content of the time-based code signal.

  Other embodiments of this aspect include corresponding systems, devices and computer programs encoded on a computer storage device and configured to perform the operations of the methods described above.

  Another innovative aspect of the subject matter described in this specification can be embodied in a system for decoding a time-based code signal, an input for receiving a time-based code signal, a time An event detector configured to detect the timing of an event within a time interval of a base code signal and a translator configured to translate the timing of the event within a time interval of the time based code into a state of a collection of numbers And an output configured to provide a signal including a number. The time-based code signal is divided into time intervals, each time interval of the time-based code signal includes an event, and the timing of the event within the time interval represents the information content of the time-based code signal.

  Other embodiments of this aspect include corresponding methods and computer programs encoded on a computer storage device and configured to perform the operations of the methods described above.

  The details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the following description, the accompanying drawings, and the appended claims.

1 is a schematic diagram of an encoder / decoder system. FIG. 6 is a flowchart illustrating a process for encoding and decoding information. 1 is a schematic diagram illustrating a system capable of encoding information. FIG. It is the schematic which shows the implementation example of a time encoder. FIG. 3 is a schematic diagram illustrating a process of time encoding. It is the schematic which shows another implementation example of a time encoder. FIG. 2 is a schematic diagram illustrating time encoding using a time encoder to detect the beginning and end of data transmission on a signal. It is the schematic which shows another implementation example of a time encoder. FIG. 2 is a schematic diagram illustrating encoding of a header at the beginning of data transmission with a signal. It is the schematic which shows another implementation example of a time encoder. FIG. 3 is a schematic diagram illustrating time encoding of a signal including three or more states. It is the schematic which shows the implementation example of the system which can encode information. It is the schematic which shows the implementation example of a multi-channel encoder. FIG. 1 is a schematic diagram illustrating a system capable of encoding, compressing, storing / transmitting information, and accessing / receiving, decoding and decompressing information. It is the schematic which shows the implementation example of a decoder. FIG. 6 is a schematic diagram illustrating a signal decoding process in which information is encoded according to the timing of occurrence of an event within a time interval. FIG. 7 is a schematic diagram illustrating another example of implementation of a decoder. FIG. 2 is a schematic diagram illustrating decoding of a signal in which information is encoded according to the timing of the occurrence of an event within a time interval using a decoder that detects the beginning and end of data transmission on the signal. It is the schematic which shows the other implementation example of a decoder. It is the schematic which shows the other implementation example of a decoder. It is the schematic which shows decoding of the signal by which the information is encoded into the signal containing the state of 3 or more by the timing of the generation | occurrence | production of the event in a time interval. It is the schematic which shows the implementation example of a decoding system. 1 is a schematic diagram illustrating a multi-channel decoder system. FIG. It is the schematic which shows the implementation example of the system which can encode information. It is the schematic which shows one implementation example of a compression encoder. FIG. 6 is a schematic diagram for various implementations of an integrator. FIG. 6 is a schematic diagram for various implementations of an integrator. FIG. 6 is a schematic diagram for various implementations of an integrator. FIG. 6 is a schematic diagram for various implementations of an integrator. It is the schematic which shows a binary-analog converter. FIG. 4 is a schematic diagram illustrating weighting as a function of the timing of other events in the time series relative to the amplitude of individual events in the time series of events. It is the schematic which shows one implementation example of the signal which can be output from a compression encoder. It is the schematic which shows a data storage device. It is the schematic which shows the implementation example of the system which can decode information. It is the schematic which shows one implementation example of an extended decoder. It is the schematic which shows a weighting apparatus. FIG. 4 is a schematic diagram illustrating weighting as a function of the timing of other events in the time series relative to the amplitude of individual events in the time series of events. It is the schematic which shows a time series scanner. It is the schematic which shows an extended decoder. 1 is a schematic diagram illustrating an implementation example of a system capable of encoding and decoding information. FIG. FIG. 5 is a flowchart illustrating a process for building a collection of binary-to-analog converters. Figure 5 is a flow chart illustrating a process for calibrating a weighting device. Figure 5 is a flow chart illustrating a process for creating an encoder / decoder pair.

Like reference numbers and designations in the various drawings indicate like elements.
DETAILED DESCRIPTION FIG. 1A is a schematic diagram illustrating an encoder / decoder system 3. The encoder / decoder system 3 is a collection of components for encoding and decoding information. The encoder / decoder system 3 can be, for example, a data communication system, a data storage system, a data compression system, a data encryption system, or a combination of these or other systems. The encoder can be paired with a decoder that can recover the information. The encoded information and the decoded information can be signaled and / or stored in a data storage device.

  The encoder / decoder system 3 includes an encoding transmitter system 6 and a decoding receiver system 9. The encoded transmitter system 6 includes an input 8, an encoder / compressor 10, a transmitter 12, and an output 14. The input 8 of the encoded transmitter system 6 can be connected to receive information on the signal 21. Depending on the physical structure of the input 8 and the output 14, the signals are respectively received by the encoded transmitter system 6 and transferred from the encoded transmitter system 6. The signal 21 contains information. The encoder / compressor 10 is a component that encodes and compresses at least some of the information in the signal 21.

  The encoder / compressor 10 includes a state encoder 23, a time-based encoder 25, an amplitude weighting component 27, and a compressor 29. The state encoder 23 is a component that encodes at least some of the information in the signal 21 into a signal 24 that represents the information as a collection of discrete numbers. Numbers can represent information using various states. For example, signal 24 may represent information in binary or bits (ie, using a pair of states) or in decimal (ie, using 10 states). The state encoder 23 is connected to supply a signal 24 to a time-based encoder 25.

  The time-based encoder 25 is a component that encodes the signal 24 into a time-based code 26 that represents information according to the timing of events within the interval. One or both of the state encoder 23 and the time-based encoder 25 may include a segmenter that divides a single signal into a collection of smaller units. As a result of this division, the amplitude weighting component 27 receives a collection of time-based codes 26. The time-based encoder 25 is connected to provide a collection of time-based codes 26 to the amplitude weighting component 27.

  The amplitude weighting component 27 is configured to weight the amplitude of the event in each time-based code 26 according to the timing of at least some of the other events in that time-based code 26. It is a component. In some implementations, the amplitude weighting component 27 can weight the amplitude of the event according to the timing of the preceding event. The amplitude weighting component 27 does not need to add new information to the time-based code 26, but represents at least some of the existing information in each time-based code in another dimension, i.e., the amplitude of the event. be able to. Amplitude weighting component 27 is connected to provide compressor 29 with a collection of amplitude weighted time-based codes 28.

  The compressor 29 is a component configured to compress a collection of amplitude-weighted time-based codes 28. The compressor 29 can compress the amplitude-weighted time-based code 28 by integrating the amplitude-weighted time-based code 28 to generate a one-dimensional code 31. The one-dimensional code 31 can represent at least some of the information in one dimension with an amplitude-weighted time-based code 28. For example, the one-dimensional code 31 can represent information using event timing. In some implementations, the integral may be a non-linear integral. The compressor 29 is connected to provide a one-dimensional code 31 to the transmitter 12.

  The transmitter 12 is configured to transmit the one-dimensional code 31 with a signal 30 that can be stored or processed. For example, the signal 30 can be stored in a memory structure (not shown). Alternatively, the signal 30 can be transmitted to a receiving device that decodes the signal. In the example shown, the signal 30 is communicated from the output 14 of the encoding transmitter system 6 to the input 16 of the decoding receiver system 9.

  The decoding receiver system 9 includes an input 16, a receiver 32, an expander / decoder 34, and an output 20. The input 16 of the decoding receiver system 9 can be connected to receive the signal 30. The signal 30 includes a one-dimensional code 31. Depending on the physical structure of the input 16 and the output 20, the signal is received by the decoding receiver system 9 or transferred from the decoding receiver system 9. The receiver 32 is configured to receive the signal 30 and transmit the one-dimensional code 31 to the expander / decoder 34.

  The expander / decoder 34 is a component that expands and decodes at least some of the information in the signal 29. The expander / decoder 34 includes a weighting expander 37, an amplitude decoder 39, a time-based code decoder 41, and a state decoder 42. The weighting expander 37 is a component configured to extend the one-dimensional code 31 to one or more collections of weights 43. The collection of weights can be generated according to the dimensions used to represent the information in signal 29 (eg, the timing of events in signal 29). For example, a weight can be generated for each event in signal 29 according to the timing of the preceding event in signal 29. Each event in the one-dimensional code can be associated with a single weight in each collection of weights. In some implementations, the weighting expander 37 weights the amplitude of each event using weights and outputs an amplitude weighted version of the one-dimensional code 31 as a collection of weights 43. In other implementations, the weighting expander 37 outputs an ordered list of weights and discards the dimensions used to represent the information in the signal 29 as a collection of weights 43 (eg, an event in the signal 29). Discard timing). The weighting expander 37 is connected to transmit the collection of weights 43 to the amplitude decoder 39.

  The amplitude decoder 39 is a component configured to decode the collection of weights 43 into one or more collections of time-based codes 45, where the timing of events within the interval represents information. The amplitude decoder 39 is connected to communicate one or more time-based codes 45 to the time-based code decoder 41. The time-based code decoder 41 is a component that decodes at least some of the information in the one or more time-based codes 45 into one or more signals 47 that represent information in a collection of states. For example, signal 47 can represent information in binary (ie, using a pair of discrete states) or in decimal (ie, using 10 discrete states). The time-based code decoder 41 is connected to transmit the signal 47 to the state decoder 42. The state decoder 42 is a component configured to decode a signal 47 representing information as a collection of numbers into a signal 50. The signal 50 may include at least some of the information included in the signal 21.

  One or more of the amplitude decoder 39, the time-based code decoder 41, and the state decoder 42 may include an aggregator that assembles a smaller collection of numbers into a larger collection of numbers. For example, in some implementations, the amplitude decoder 39 may include a time-based code aggregator that assembles multiple time-based codes into a single time-based code 45. As another example, in some implementations, the time-based code decoder 41 assembles multiple signals that represent information in a collection of discrete numbers into a single signal 47 that represents information in a collection of discrete numbers. An aggregator may be included. As yet another example, in some implementations, the state decoder 42 may include an aggregator that assembles the signal into a single signal 50.

  FIG. 1B is a flowchart illustrating a process 70 for encoding and decoding information. Process 70 may be performed alone or in combination with other operations. For example, process 70 may be performed at stage 4130 in process 4100 (FIG. 41). Process 3900 may be performed by an encoder / decoder system, such as encoder / decoder system 3 (FIG. 1A).

  In process 70, data is encoded into a collection of numbers (stage 72) and numbers are encoded into a time-based code (stage 74). Time-based codes represent information using the timing of events within the interval. The amplitude of the event in the time-based code is weighted according to the timing of other events in the time-based code (stage 76). For example, events can be weighted according to the timing of previous events in their time-based code. Amplitude weighting does not need to add new information to the time-based code, but can represent at least some of the existing information in the time-based code in another dimension, i.e., the amplitude of the event.

  The amplitude weighted time-based code can be compressed into a one-dimensional code (stage 78). A one-dimensional code can represent at least some of the information in one dimension with an amplitude-weighted time-based code using, for example, event timing.

  In the receiving device, the one-dimensional code can be expanded into a collection of amplitudes (stage 80). Each event in the one-dimensional code can be associated with a single weight in each collection of weights. In some implementations, the collection of amplitudes can be a list of amplitudes that does not include any timing information. In other implementations, the one-dimensional code itself can be weighted by multiple collections of amplitudes to obtain multiple amplitude-weighted versions of (previous) one-dimensional code.

  The amplitude can be decoded into a time-based code (stage 82), which can further be decoded into one or more signals that represent the information as a collection of numbers (stage 84). One or more signals representing information as a collection of numbers may themselves be decoded into another representation (stage 86).

Time Encoder FIG. 2A is a schematic diagram illustrating a system 100 capable of encoding information. System 100 includes a time encoder 105 that includes an input 110 and an output 115. Depending on the physical structure of the input 110 and the output 115, signals are received by or transferred from the time encoder 105, respectively. The time encoder 105 is a component that encodes information by generating an event at a specific time within the time interval of the output signal. The time encoder 105 can substantially represent the information content of the input signal in an output format in which the timing of the event within the interval represents the information content of the input signal. The time encoder 105 can be used in combination with other devices. For example, the time encoder 105 can be used as the time-based encoder 25 (FIG. 1A).

  The input 110 of the time encoder 105 can be connected to receive information 120 with a signal 125 received from the data communication path. Signal 125 represents information 120 as an ordered finite set of discrete numbers. For example, in some implementations, the input information 120 can be represented in binary as a series of high (ie, “1”) and low (ie, “0”) states, as shown. Input 110 may be a serial or parallel binary data port. The signal 125 can be transmitted over a wired or wireless data communication path.

  The output 115 of the time encoder 105 can be connected to transfer information encoded in the signal 135 communicated to the system or medium 140. Information in signal 135 is represented by the time at which the event occurs within the interval of signal 135. The timing of events within these intervals represents all the information in signal 125. For example, as described further below, an event that occurs at a first time within a time interval may represent a number having a high state in signal 125, whereas it occurs at a second time within a time interval. An event may represent a number having a low state in signal 125. The first time can be identified from the second time.

  The system or medium 140 through which the signal 135 is transmitted varies depending on the operating conditions of the system 100. For example, if system 100 is part of a data transmission system, system or medium 140 may include a data transmitter. As another example, if system 100 is part of a data storage system, system or medium 140 may include a write head that can write information to the data storage device.

  In operation, time encoder 105 receives signal 125 via input 110. Time encoder 105 encodes information 120 in signal 125 by representing input information 120 in signal 135 that includes events timed to occur at identifiable times within different intervals. The time encoder 105 outputs a signal 135 containing the timed event to the system or medium 140.

  FIG. 2B is a schematic diagram illustrating an implementation example of the time encoder 105. The illustrated implementation of time encoder 105 includes a state detector 205, an event timing circuit 210 and an event generator 215. The state detector 205 is a component that detects the numerical state in the signal 125 representing the input information 120. For example, in an implementation in which input information 120 is represented by a series of binary digits, state detector 205 may be a bit detector that distinguishes between binary “1” and “0” states. . The state detector 205 is connected between the input 110 and the event timing circuit 210. An indication of the detected state 220 is transmitted to the event timing circuit 210.

  Event timing circuit 210 is a component configured to identify the timing of events within the interval of output signal 135. The event timing circuit 210 includes a clock 225, a counter 230, an interval reset 235, and a timing selector 240. The clock 225 supplies a clock output signal to the counter 230. The counter 230 is connected to receive the clock output signal 242 and output a dynamic count of the clock signal 245. Dynamic count 245 is coupled to interval reset 235 and timing selector 240. The interval reset 235 may include a comparator (not shown) that compares the dynamic count of the clock signal with a threshold count representing the interval period. Such a comparison makes it possible to determine when the interval has elapsed. The interval reset 235 supplies a reset signal 250 as the interval elapses. The counter 230 can receive the reset signal 250 and reset the count of the clock signal according to the reset signal. Thus, the interval of the threshold count period can be distinguished by resetting the counter 230.

  Timing selector 240 receives both a dynamic count of clock signal 245 and an indication of state 220 detected by state detector 205. The timing selector 240 can include a switch 255 and a comparator 260. Comparator 260 includes a pair of inputs 265 and 270. Input 265 receives a dynamic count of clock signal 245 output by counter 230. Input 270 receives switch output signal 275 from switch 255. Switch 255, and other switches described herein, can be implemented, for example, as an electromechanical switch, one or more transistors, or machine-readable instructions.

  Switch 255 includes a high reference 280 and a low reference 285. High reference 280 embodies the time within the interval at which the event representing the number having a high state represented by signal 125 will occur. The low reference 285 embodies the time within the interval at which the event representing the number having the low state represented by signal 125 will occur. Switch 255 receives an indication of state 220 detected by state detector 205. Switch 255 switches between a high reference 280 and a low reference 285 that are applied to input 270 of comparator 260 in response to an indication of the state detected by state detector 205. In particular, in response to an indication that the state detector 205 has detected a low state, the switch 255 switches to connect the low reference 285 to the input 270. In response to an indication that the state detector 205 has detected a high state, the switch 255 switches to connect the high reference 280 to the input 270.

  The comparator 260 compares the count of the clock signal output by the counter 230 with the given low reference 285 or high reference 280, and outputs a comparison result 290.

  Event generator 215 is a component configured to generate an event with output signal 135. The event generator 215 is connected to receive the comparison result 290 from the comparator 260 and time the generation of the event based on the comparison result. For example, event generator 215 is a pulse generator that generates a pulse in response to a transition in result 290 resulting from a clock signal output by counter 230 that transitions past a given low reference 285 or high reference 280. May be. The occurrence of such an event within an interval distinguished by interval reset 235 is thus timed to encode a numeric state in signal 125 and may therefore be referred to as a “data event”. The event generator 215 provides the generated event 295 to the output 115.

  Timing selector 240 is also connected to receive interval reset signal 250. The timing selector 240 can advance to the next number and reset the comparison by the comparator 260 in response to the reset signal 250. In some implementations, the state detector 205 is also connected to receive the interval reset signal 250 (see the dashed line input to the state detector 205). The state detector 205 can, for example, set a time for presenting a display of the detected state to the timing selector 240 in response to the reset signal 250, thereby proceeding to the next number.

  In operation, time encoder 105 receives signal 125 via input 110. The state detector 205 detects the state in the numbers of the signal 125 representing the input information 120 and outputs a signal characterizing those numbers (ie, an indication of the state 220). The timing selector 240 receives signals describing those numbers and produces an output that is timed to occur within the interval according to the state (ie, the result output 290). In particular, the first state in signal 125 causes a transition in result 290 that occurs at a first time within the corresponding time interval, and the second state in signal 125 is at a second time within the corresponding time interval. The resulting result 290 causes a transition. The timing of these transitions is set by a low reference 285 and a high reference 280.

  In response to the transition in result 290, event generator 215 generates event 295 that is provided at output 115. The event timing follows the transition timing in the result 290. Interval reset 235 breaks the interval and advances timing selector 240 from the state of one number in signal 125 to the next number and resets the comparison that causes a transition in result 290. All numbers in signal 125 (including the low “0” state) are thus represented by correspondingly timed events in the interval.

  FIG. 3 is a schematic diagram illustrating the process of time encoding. The illustrated time encoding can be performed by a time encoder, such as time encoder 105 (FIGS. 1 and 2). In the illustrated implementation, information 120 is represented in binary as a series of large numbers 305 and small numbers 310.

  With time encoding, information 120 is encoded into a time-based code signal 135. The time-based code signal 135 includes a collection of time intervals 320, each corresponding to the numbers 305 and 310 in the signal 125. Each time interval 320 includes a respective data event 325. The timing of the data event 325 within an individual time interval 320 indicates the state of the numbers 305 and 310 corresponding to that time interval 320. For example, in the illustrated implementation, a data event 325 at intervals 320 corresponding to large status numbers 305 occurs at a time 330 near the beginning of those intervals 320. The data event 325 in the interval 320 corresponding to the small status number 305 occurs at a time 335 near the middle of those intervals 320. The time 330 can be identified from the time 335.

  In various implementations, various features of the event, including data event 325, can be identified and processed as the time the event occurs. For example, in the illustrated implementation, data event 325 transitions from a baseline (ie, “resting” state 340 to a high (ie, “excited”) state 345, and then , A pulse returning to the baseline stop state 340. In some implementations, the first transition from the baseline state 340 to the high state 345 may be identified and processed as the time at which the data event 325 occurs. In implementations, the transition from high state 345 back to baseline state 340 may be identified and processed as the time at which data event 325 occurs, in some implementations, data event 325 may be the first transition and return For example, the time encoder 105 cannot identify because the time of the transition is very close The time at which the transient data event 325 occurs is identified based on the apparent coincidence of the occurrence of the first and return transitions.

  In the illustrated implementation, the shapes of the various data events 325 are indistinguishable from each other, and the various data events 325 can only be identified by their timing. Further, in some implementations, the data event 325 can be a “binary event” in that it occurs at one of just two possible times in the interval. If they occur at those times, the data events are at the same signal level (eg, high), but their timing within the interval is due to the numerical state they represent.

  In the illustrated implementation, the time intervals 320 all have the same duration and occur continuously. The sequence of time intervals 320 corresponds to the sequence of corresponding numbers 305 and 310 in signal 125. In other words, the first time interval 320 (and its event 325) of the time-based code signal 135 corresponds to the first number 305 in the signal 125 and the second time interval 320 ( And its data event 325) corresponds to the second number 310 in the signal 125, and so on. This correspondence is represented by a wavy arrow 350.

  FIG. 4 is a schematic diagram showing another implementation example of the time encoder 105. In addition to the state detector 205, event timing circuit 210 and event generator 215, the illustrated implementation for the time encoder 105 also includes a start / stop detector 405. Start / stop detector 405 is a component configured to detect the beginning and end of data transmission on signal 125. For example, start / stop detector 405 may recognize one or more headers or footers in signal 125.

  Start / stop detector 405 may be connected to input 110. The start / stop detector 405 outputs an indication 410 of the start and end of data transmission on the signal 125 to the event generator 215 and other parts of the time encoder 105 (eg, event generator 215). The event generator 215 can generate a start event and an end event (eg, as part of the event 295) in response to the display output by the start / stop detector 405. The first event is the event that occurs when distinguishing the beginning of the data output in the result 290 and allowing the timing of the first data event and the first interval to be determined. An end event is an event that occurs when distinguishing the end of the data output in result 290. In some implementations, one or both of the beginning event and the ending event can be used to reset a time-dependent process, as described further below. The first event and the last event generated by the event generator 215 are output as an event 295 and provided to the output 115.

  The start and end indications of the data transmission on the signal 125 output by the start / stop detector 405 are communicated to and used by the other parts of the time encoder 105 to start by the event generator 215. Set the output of events, end events, and data events. For example, one or more of clock 225, counter 230, and interval reset 235 are disabled for the interval associated with the initial event (eg, to allow processing / ignoring of headers in information 120). There is a possibility that. As another example, the transition of the timing selector 240 by number or the detection of a state by the state detector 205 may be disabled for the interval associated with the initial event.

  FIG. 5 is a schematic diagram illustrating time encoding with a time encoder that detects the start and end of data transmission on a signal. For example, the illustrated time encoding may be performed by a time encoder such as time encoder 105 that includes a start / stop detector 405 (FIG. 4). In the illustrated implementation, signal 125 includes a header 505 (shown as “X”) and a footer 510 (shown as “Y”). Header 505 and footer 510 thus build information 120 in signal 125.

  Time encoding encodes information 120 into a time-based code signal 135 as described above with reference to FIG. Time-based code signal 135 includes a header interval 515 and a footer interval 520. The header interval 515 includes a header event 525 that occurs at time 535 within the header interval 515. Footer interval 520 includes a footer event 530 that occurs at time 540 within footer interval 520. Header interval 515 and header event 525 distinguish the beginning of time-based code signal 135. Footer interval 520 and footer event 530 distinguish the end of time-based code signal 135. The distinction of the start of the time-based code signal 135 can be used to determine the timing of the first event 325 within the first interval 320. For example, the first event 325 occurs at time 545 after the header event 525. The timing of the first event 325 within the first interval 320 can be determined using the interval 515 and the time period 545. For example, in an implementation where the duration of interval 515 is the same as interval 320, detection of event 525 can be used as a reset signal to reset the interval.

  In the illustrated implementation, events 525 and 530 are pulses that transition from baseline state 340 to high state 345 and then back to baseline state 340. In some implementations, the shapes of events 525 and 530 are not distinguishable from each other and may not be distinguishable from the shape of data event 325. In these implementations, events 325, 525, 530 can only be identified by their timing and location. For example, the event 525 can be recognized as the first event. In some implementations, intervals 515 and 520 both have the same duration as each other and have the same duration as time interval 320.

  FIG. 6 is a schematic diagram illustrating another implementation example of the time encoder 105. In addition to the status detector 205, event timing circuit 210 and event generator 215, the illustrated implementation for the time encoder 105 also includes a header / footer encoder 605. The header / footer encoder 605 is configured to encode a header located at the beginning of data transmission on the signal 125 and a footer located at the end of data transmission on the signal 125, or both to encode with information. Component. In some implementations, the information in which the header or footer is encoded can be received, for example, in the header or footer of signal 125. For example, the header / footer encoder 605 may encode a header or footer that includes information identifying the signal received at the input 110, or information that characterizes aspects of the signal received at the input 110. it can. For example, the signal received at input 110 can be identified, for example, according to the source and destination of the received signal, the type of information in the received signal, and the relationship between the received signal and other signals. The aspects of the received signal that can be characterized include the floating point position in the received signal, the sign of the number in the received signal, and error checking information. The header / footer encoder 605 can encode a header or footer that includes such information by triggering the injection of one or more events to the header or footer region associated with the input signal 125.

  The header / footer encoder 605 can be connected to the input 110. The header / footer encoder 605 outputs one or more signals 610 that identify or characterize information in the header or footer and provides the signal 610 to the event generator 215. Event generator 215 can generate an event that is timed to occur within the header or footer of signal 125 in response to the display output by header / footer encoder 605. The event 295 generated by the event generator 215 is supplied to the output 115.

  In some implementations, identification or characterization information in signal 610 can also be output to other portions of time encoder 105. This information can be used in a variety of ways including, for example, error checking and triggering and / or resetting of interval differentiation and data event generation.

  FIG. 7 is a schematic diagram illustrating encoding of a header at the beginning of data transmission with a signal. For example, the illustrated encoding may be performed by a time encoder 105, such as a time encoder that includes a header / footer encoder 605 (FIG. 6). Information may be encoded by one or more events occurring within header interval 515 or footer interval 520 in signal 135.

  In the illustrated implementation, header interval 515 includes header event 705. Header event 705 occurs at time 710 within header interval 515. The timing of header event 705 within header interval 515 can be determined, for example, by measuring a time span 710 between time 535 and time 710.

  In some implementations, the header interval 515 can itself be divided into multiple subintervals, each of which can include one or more information events. Different sub-intervals can be assigned to encode different identification and characterization information. For example, the first sub-interval may include an event, the timing of which indicates whether the number encoded in signal 135 is positively or negatively signed. As another example, a collection of small intervals may include an informational event whose timing is determined by the signal 135 within the larger collection of information (eg, after segmentation, as described further below). Indicates the position of the information encoded by.

  In the illustrated implementation, header event 705 is a pulse that transitions from baseline state 340 to high state 345 and back to baseline state 340. In some implementations, the shape of the header event 705 is indistinguishable from each other and may not be distinguishable from the shape of the events 525, 530 and the shape of the data event 325. In these implementations, events 705, 325, 525, 530 can only be identified by their timing and location.

  In some implementations, the footer at the end of data transmission on the signal can be encoded with one or more information events. In some implementations, both the header and footer can be encoded with one or more information events.

  FIG. 8 is a schematic diagram showing another implementation example of the time encoder 105. The illustrated implementation of the time encoder 105 includes a state detector 205 and an event timing circuit 210 suitable for operation with a signal 125 that encodes information with numbers having three or more possible states. For example, signal 125 may encode information in quaternary or decimal numbers.

  The state detector 205 is configured to detect a numerical state in the signal 125 and communicate an indication of the detected state to the event timing circuit 210. The event timing circuit 210 receives these indications and includes a timing selector 240 connected to configure the switch 255 in response. In particular, the switch 255 includes a collection of three or more criteria 805, each associated with a respective state (ie, the time within the interval at which the event representing the numerical corresponding state by the signal 125 occurs). For example, the first criterion 805 can be associated with a first time within the interval, the second criterion 805 can be associated with a second time within the interval, and the Nth criterion 805 is an interval. Can be associated with the Nth time.

  The switch 255 is configured to apply an appropriate reference 805 to the input 270 of the comparator 260 in response to an indication of the state detected by the state detector 205. The comparator 260 compares the count of the clock signal output by the counter 230 with an appropriate reference 805 and outputs a comparison result 290. Thus, the various states of the numbers in signal 125 result in transitions occurring at identifiable times within the corresponding time interval at the timing of these transitions set by reference 805.

  FIG. 9 is a schematic diagram illustrating time encoding of a signal including numbers having more than two possible states. The illustrated time encoding can be performed by a time encoder, such as time encoder 105 (FIG. 8). In the illustrated implementation, the information 120 includes four different possible states: a number 905 having a first state (ie, “A”) and a number 910 having a second state (ie, “B”). )), A number 915 having a third state (ie, “C”), and a number 920 having a fourth state (ie, “D”). In other implementations, the information 120 is a number having a different number of possible states (eg, a number having ten different possible states representing the information 120 in decimal), or very It can be represented by a number having many realizable states or realizable continuums (eg, an almost analog or analog continuum of realizable states). In some implementations, numbers having four possible states can be used to represent genetic information and represent four nucleic acids.

  With time encoding, information 120 is encoded into a time-based code signal 135. Time-based code signal 135 includes a collection of time intervals 320, each corresponding to a number 905, 910, 915, 920 in signal 125. Each time interval 320 includes a respective data event 325. The timing of the data event 325 within an individual time interval 320 indicates the state of the numbers 905, 910, 915, 920 corresponding to that time interval 320. For example, in the illustrated implementation, a data event 325 in interval 320 corresponding to the first state number 905 occurs at time 930 near the end of interval 320. A data event 325 in interval 320 corresponding to the second state number 910 occurs at time 935 near the middle of interval 320. A data event 325 in interval 320 corresponding to a third state number 915 occurs at time 940 prior to the middle of interval 320. A data event 325 in interval 320 corresponding to the fourth state number 920 occurs at time 945 near the beginning of interval 320. Times 930, 935, 940 and 945 are distinguishable from each other.

  In another implementation, the time encoder can be implemented as a digital circuit that receives as input a series of codes from a predetermined set of codes and generates a time-coded output signal as an output. In this case, each time interval in the time-encoded output signal contains a single pulse at a time within the interval determined by the corresponding input code. The digital circuit can be controlled by a programmed computer or can include an embedded computer. In some implementations, each input code is mapped to a unique character having a binary (ie, bit) N length that is the same as the number of different possible input codes, in this case , All bits are the same except for one, so the position of a separate bit in a character identifies the code to which the character corresponds. Thus, the code input sequence is mapped to the character input sequence, which can be input to the shift register. The output of the shift register is clocked so that N bits appear in every time interval 320. This output is coupled to a pulse generator so that the appearance of a separate bit will generate an output pulse at the output of the time encoder. In some such implementations, the time encoder includes circuitry that converts the analog input signal into a series of codes. When headers, footers and synchronization are desired in the output signal, the corresponding input code is the actual to be transmitted, possibly as a prefix or suffix, according to conventions or protocols adopted by the encoder and downstream decoder. Can be added to the signal.

  FIG. 10 is a schematic diagram illustrating an implementation example of the system 100, that is, a system 1000 capable of encoding information. System 1000 includes a neural processing component 1005 in which signal 135 is transmitted from time encoder 105. Neural processing component 1005 is a component that is composed of neural tissue or has a design that is suggested by the design and function of the neural tissue. Thus, the neural processing component 1005 is implemented using “wet” nerves and other neural components (eg, as a biological neural network or brain, or other neural tissue in the body). Alternatively, the neural processing component 1005 can be implemented using a semiconductor device (eg, as an artificial neural network implemented using hardware or software). In some implementations, the neural processing component 1005 can be implemented by a combination of semiconductor elements and wet neural components.

  As shown, the time encoder 105 outputs a signal 135 containing the timed event to the neural processing component 1005. In implementations where the neural processing component 1005 is implemented using a “wet” neural component, the characteristics of the signal 135 can be adjusted to match the wet neural component. For example, events in signal 135 can be adjusted to mimic the amplitude and time characteristics of action potentials.

  In some implementations, the neural processing component 1005 may include multiple elements that receive the signal 135. For example, in a neural processing component 1005 implemented using “wet” neural components, multiple nerves may receive the signal 135. As another example, in neural processing component 1005 implemented using semiconductor components, multiple neural network inputs may receive signal 135.

  In operation, time encoder 105 may encode information 120 in signal 125 into a format understood by neural processing component 1005, i.e., timed so that an event occurs at a time that is identifiable within an interval in a series of intervals. Signal 135 is obtained. Thus, time encoder 105 can serve as an interface between binary (and other) digital data processing, statistical processing, and pattern recognition provided in neural processing component 1005. For example, the time encoder 105 may be included in a neural prosthesis that stimulates a nerve using, for example, auditory, visual or other sensory information encoded in the signal 135.

  FIG. 11 is a schematic diagram illustrating an implementation of the system 100, ie, a system including a multi-channel encoder 1100 that can encode information. System 1100 includes a collection of time encoders 105, a data segmenter 1105, an input 1110, and a collection of one or more outputs 1115.

  Input 1110 receives information 120 in signal 125 via a data communication path. Input 1110 provides a signal 1117 carrying information in signal 125 to input 1120 of data segmenter 1105. Data segmenter 1105 is a component that divides (or “fragments”) a signal into smaller units. Data segmenter 1105 includes an input 1120 and one or more outputs 1125.

  Data segmenter 1105 divides the relatively large collection of numbers in signal 125 into a collection of numbers, each of which represents a smaller subset of information 120. In some implementations, the segment may be a contiguous portion of the number in signal 125. In other implementations, the segments may include non-consecutive numbers. In the illustrated example, signal 125 received by data segmenter 1105 represents information 120 in an ordered finite set of discrete numbers, eg, a collection of bits. The data segmenter 1105 divides the signal 125 into smaller collections of segments representing a true subset of the information 120 in a discrete number of finite sets, each ordered. The data segmenter 1105 provides a segment 1120 from one or more outputs 1125 to the corresponding input 110 of the time encoder 105. Each time encoder 105 encodes information in the received segment by timing the occurrence of events within the time interval of the respective output signal 135. The timing of the event within the interval in each output signal 135 represents all of the discrete numbers within each segment.

  The time encoder 105 outputs each output signal 135 from the output 1115 of the multi-channel encoder 1100. In some implementations, the output signal 135 is provided to a single system or medium 140 at the same time. For example, in an implementation in which the time-based code of the output signal 135 each includes a header interval 515 and a header event 525, header events 525 in each output signal occur simultaneously. System or medium 140 may include a collection of inputs, each of which is connected to a corresponding output 1115 to receive a corresponding output signal 135, as further described below.

  In operation, data segmenter 1105 receives signal 125 via input 1120. Data segmenter 1105 performs a data segmentation process via signal 125 to generate a collection of segments. Each segment is input to a respective input 110 of the time encoder 105. Each time encoder 105 encodes information in its respective segment by representing the information in events timed to occur at identifiable times within various intervals. Each signal 135 output by each time encoder 105 is communicated to the output 1115 of the multi-channel encoder 1100 and to the system or medium 140.

  FIG. 12 is a schematic diagram illustrating a system 1200 that can encode, compress, store / transmit information, and can also access / receive, decode and decompress. System 1200 can include one or more of the implementations of system 100 described above and a decoder 1205 that includes an input 1210 and an output 1215. Depending on the physical structure of the input 1210 and the output 1215, the signal is received by the decoder 1205 or transferred from the decoder 1205. The decoder 1205 is a component that decodes a signal in which information is encoded according to the timing of occurrence of an event within a time interval. The decoder 1205 essentially translates a time-based signal in which the timing of events within the interval represents information content into an output format that represents that information in an ordered finite set of discrete numbers.

  The input 1210 of the decoder 1205 can be connected to receive a signal 1220, where information is encoded according to the timing of the occurrence of an event within the time interval. Signal 1220 may be output on the data communication path from system or medium 140. The nature of transferring information from the system or medium 140 to the decoder 1205 via the signal 1220 depends on the operational context of the system 1200. For example, if system 1200 is part of a data transmission system, system or medium 140 may include a data transmitter that outputs signal 1220 to a data receiver in decoder 1205. As another example, if system 1200 is part of a data storage system, decoder 1205 can include, for example, a read head that can read information from data storage medium 140. The signal 1220 can be transmitted, for example, via a wired or wireless data communication path.

  After translation into the output format, the decoder 1205 outputs a signal 1230 that includes the decoded information 1225. Decoded information 1225 can be represented as an ordered finite set of discrete numbers, for example, in binary as a series of high and low states as shown. The output 1215 may be in the form of one or more binary data ports in series or parallel.

  In operation, decoder 1205 receives signal 1220 from system or medium 140 via input 1210. Signal 1220 represents information with events timed to occur at identifiable times within various intervals. The decoder 1205 decodes the information 1225 and outputs a signal 1230 including the decoded information 1225.

  The decoder 1205 can be used with other devices outside the system 1200. For example, the decoder 1205 can be used as the time-based decoder 41 (FIG. 1A).

  FIG. 13 is a schematic diagram illustrating an implementation example of the decoder 1205. The illustrated implementation of decoder 1205 includes event detector 1305, time-state translator circuit 1310, and state selector circuit 1315. Although a circuit is mentioned, one or more of the decoder components can be implemented in firmware or software. The event detector 1305 is a component that can detect events in the signal 1220 and their timing. The structure of the event detector 1305 can reflect the nature of the event in the signal 1220. For example, if the event in signal 1220 is a pulse, event detector 1305 can be a pulse detector. Event detector 1305 is connected to receive signal 1220 from input 1210 and a signal representative of time within interval 1325 from interval timing circuit 1320. Event detector 1305 is connected to output a time 1325 within the interval at which the event is detected.

  The interval timing circuit 1320 includes a clock 1330, a counter 1335, and an interval reset 1340. When clock 1330 provides output clock signal 1345 to counter 1335, counter 1335 then generates a dynamic count 1332 of the clock signal. A dynamic count 1332 is provided to both the event detector 1305 and the interval reset 1340. The interval reset 1340 may include a comparator (not shown) that compares the dynamic count of the clock signal with a threshold count representing the interval period. Such a comparison makes it possible to determine when the interval has elapsed. The interval reset 1340 supplies the reset signal 1350 as an output to the counter 1335. Counter 1335 is reset in response to reset signal 1350. By resetting the counter 1335, the range of the interval of the threshold count period is determined.

  The reset signal 1350 output by the interval reset 235 is communicated to and used by other parts of the decoder 1205 so that, for example, translation of events by the time-state translator 1310 and selection of numbers by the state selector 1315 and Output and time are set. For example, the time-state translator 1310 may include one or more switches that reset the translation and the output of the translation result in response to the reset signal 1350. As another example, state selector 1315 may ensure that a single number is selected and output for each interval by triggering reset signal 1350.

  In response to event detection, the event detector 1305 outputs a display of the time within the interval 1325 at which the event is detected. These indications are received by the time-state translator 1310. In the illustrated implementation, the time-state translator 1310 includes a high bit detector 1355 and a low bit detector 1360, both of which are adapted to receive an indication of time within an interval at which an event is detected. Connected.

  In some implementations, the high bit detector 1355 includes a pair of comparators 1356, 1358 and an AND gate 1359. The comparator 1356 is connected to compare the time within the interval at which the event is detected with the first reference ref_1. Comparator 1358 is connected to compare the time within the interval at which the event is detected with a second reference ref_2. The references ref_1 and ref_2 are threshold values indicating the earliest time and the latest time within an interval in which the detected event is considered to be in the first state (for example, high bit). If the bit is detected at a time later than the time indicated by ref_1 and a time before the time indicated by ref_2, the outputs of both comparators 1356 and 1358 are set. AND gate 1359 also generates an output 1365 (eg, a high signal) that indicates that the timing of the event detected by event detector 1305 is within the interval.

  In the illustrated implementation, the low bit detector 1360 includes a pair of comparators 1361, 1363 and an AND gate 1364. The comparator 1361 is connected to compare the time within the interval at which the event is detected with the first reference ref_3. The comparator 1363 is connected to compare the time within the interval at which the event is detected with the second reference ref_4. The references ref_3 and ref_4 are threshold values indicating the earliest time and the latest time within an interval in which the detected event is considered to be in the second state (eg, low bit). If an event is detected at a time after the time indicated by ref_3 and a time before the time indicated by ref_4, the outputs of both comparators 1361 and 1363 are set. AND gate 1364 also provides an output 1370 indicating that the timing of the event detected by event detector 1305 is within the interval.

  Status selector 1315 is a component configured to select a numeric status for the output of signal 1230 via output 1215. In some implementations, the number may be a binary bit. The state selector 1315 is connected to receive translations (ie, outputs 1365 and 1370). Based on the received translation, state selector 1315 outputs state information 1215. The numbers can be output in parallel or in series.

  In operation, event detector 1305 receives signal 1220. In this case, the information 1225 is encoded according to the occurrence timing of the event within the time interval. The event detector 1305 detects the timing of the event within each interval and outputs a description of the timing 1325. The time-state translator circuit 1310 compares the time at which the event was detected by the event detector 1305 with the time assigned to the state, thereby determining the time within the interval from the decoder 1205 to the signal 1230 to be output. Translate to In particular, an event detected within a first range of times defined by the references ref_1, ref_2 results in a setting signal being obtained on the output 1365. An event detected within the second range of times defined by the references ref_3, ref_4 results in a setting signal on the output 1370. The state selector circuit 1315 receives the results of these comparisons and selects the numerical state to be output via the output 1215 according to those results.

  FIG. 14 is a schematic diagram illustrating decoding of a signal in which information is encoded according to the timing of occurrence of an event within a time interval. Decoding can be performed by a decoder such as, for example, decoder 1205 (FIG. 12).

  Decoding translates the information encoded with the time-based code signal 1220 into a signal 1230 representing the information 1225 in an ordered finite set of discrete digits. In the illustrated implementation, information 1225 is represented in signal 1230 in binary notation as a series of large binary numbers 1405 (ie, “1”) and small binary numbers 1410 (ie, “0”).

  Time-based code signal 1220 includes a collection of time intervals 1420, each corresponding to the numbers 1405 and 1410 in signal 1230. Each time interval 1420 includes a respective data event 1425. The timing of the data event 1425 within an individual time interval 1420 indicates the state of the numbers 1405 and 1410 corresponding to that time interval 1420. For example, in the illustrated implementation, a data event 1425 in intervals 1420 corresponding to high state numbers 1405 occurs at time 1430 near the beginning of those intervals 1420. The data event 1425 in the interval 1420 corresponding to the low number 1405 occurs at a time 1435 near the middle of those intervals 1420. The time 1430 can be identified from the time 1435.

  In the illustrated implementation, data event 1425 is a pulse that transitions from baseline (ie, “stop”) state 2140 to high (ie, “activity”) state 1445 and then back to baseline stop state 1440. is there. In some implementations, the first transition from the baseline state 2140 to the high state 1445 can be identified and processed as the time at which the data event 1425 occurs. In other implementations, the transition from high state 1445 back to baseline state 2140 can be identified and processed as the time at which data event 325 occurs. In some implementations, the data event 1425 is a transient pulse that is indistinguishable for the time encoder 1205, for example, because the first transition and the return transition are very close in time. The time at which the transient data event 1425 occurs is identified based on the apparent coincidence of the occurrence of the first transition and the return transition.

  In some implementations, the shapes of the various data events 1425 are indistinguishable from each other, and the various data events 1425 can only be identified by their timing. Further, in some implementations, the data event 1425 can be a binary event in that it occurs only at two feasible times, i.e., at a first time or a second time within an interval.

  In the illustrated implementation, the time intervals 1420 all have the same period and occur continuously. The sequence of time intervals 1420 corresponds to the sequence of corresponding numbers 1405 and 1410 in signal 1430. In other words, the first time interval 1420 (and its event 1425) of the time-based code signal 1220 corresponds to the first number 1405 in the signal 1230 and the second time interval 1420 ( And its data event 1425) corresponds to the second number 1410 in signal 1230, and so on. This correspondence is represented by a wavy arrow 1450.

  FIG. 15 is a schematic diagram illustrating another implementation example of the decoder 1005. In addition to event detector 1305, time-state translator circuit 1310, state selector circuit 1315, and interval timing circuit 1320, the illustrated implementation of decoder 1005 also includes a start / stop detector 1505. Start / stop detector 1505 is a component configured to detect one or both of the beginning and end of data transmission on signal 1220. For example, the start / stop detector 1505 can recognize one or more of a header event, header interval, footer event, and footer interval in the signal 1220.

  Start / stop detector 1505 may be connected to input 1210 to receive signal 1220 (as shown). In some implementations, start / stop detector 1505 detects one or both of the beginning and end of data transmission on signal 1220 by detecting the beginning and end events in signal 1220. Can be detected. The start / stop detector 1505 outputs an indication 1510 to the interval reset 1340 and other portions of the decoder 1205 that indicates one or both of the start and end of data transmission on the signal 1220. The interval reset 1340 can reset itself and the distinction between intervals in response to the display output by the start / stop detector 1505. The start / stop detector 1505 can thereby synchronize the interval reset 1340 with the interval and event timing in the signal 1220.

  In some implementations, an indication of the beginning and end of data transmission in the signal 1220 output by the start / stop detector 1505 can be communicated to other parts of the decoder 1205 and used by this part. For example, in some implementations, the state selector 1315 may use one or more of the beginning and end of the signal 1220 using header and footer events, depending on the indication output by the start / stop detector 1505. Both can be distinguished.

  FIG. 16 is a schematic diagram illustrating the decoding of a signal in which information is encoded according to the timing of the occurrence of an event within a time interval, using a decoder that detects the start and end of data transmission on the signal. For example, the illustrated decoding may be performed by a decoder such as decoder 1205 that includes a start / stop detector 1505 (FIG. 15). In the illustrated implementation, signal 1230 includes a header 1605 (shown as “X”) and a footer 1610 (shown as “Y”). Thus, the frame signal 1230 is constructed by the header 1605 and the footer 1610.

  By decoding, the time-based code signal 1220 is decoded into the signal 1230 as described above with reference to FIG. Time-based code signal 1220 includes a header interval 1615 and a footer interval 1620. The header interval 1615 includes a header event 1625 that occurs at time 1635 within the header interval 1615. Footer interval 1620 includes a footer event 1630 that occurs at time 1640 within footer interval 1620. Header interval 1615 and header event 1625 distinguish the start of time-based code signal 1220. Footer interval 1620 and footer event 1630 distinguish the end of time-based code signal 1220. By distinguishing the beginning of the time-based code signal 1220, the timing of the first event 1625 within the first interval 1620 can be determined. For example, the first event 1625 occurs in the period 1645 after the header event 1625. The timing of the first event 1625 within the first interval 1620 can be determined using the duration of the interval 1615 and the time 1645.

  In the illustrated implementation, events 1625, 1630 and 1425 are pulses that transition from baseline state 1640 to high state 1445 and then back to baseline state 1640. In some implementations, the shapes of events 1625 and 1630 are indistinguishable from each other and are also indistinguishable from the shape of data event 1425, and events 1425, 1625, and 1630 are dependent on their timing. Can only be identified. Further, in some implementations, intervals 1615 and 1620 both have the same duration as each other and have the same duration as time interval 1420.

  FIG. 17 is a schematic diagram illustrating another implementation example of the decoder 1205. In addition to event detector 1305, time-state translator circuit 1310, state selector circuit 1315, interval timing circuit 1320 and start / stop detector 1305, the illustrated implementation of decoder 1005 also includes a header / footer decoder 1705. The header / footer decoder 1705 is a component configured to decode information encoded in the header of the signal 1220, information encoded in the footer of the signal 1220, or both.

  The header / footer decoder 1705 is connected to the input 1210 to receive the signal 1220 and a header event or footer event included in the signal 1220. For example, in some implementations where the duration of the header interval and footer interval is the same as the duration of interval 1420, header / footer decoder 1705 may indicate either or both of the beginning and end of data transmission on signal 1220. 1510 and can be connected to the event detector 1305 to receive a dynamic count of times 1325 within an interval having a size specified by the interval reset. For example, in an implementation in which the duration of the header interval and footer interval is different from the duration of interval 1420, header / footer decoder 1705 can be connected to the output of another interval timing circuit or internal start / stop detection component. Or, in other cases, the time at which an informational event occurs in the header, footer, or both may be determined.

  The header / footer decoder 1705 outputs a display of the information content of the event of information that occurs as an output 1710 in the header or footer. The state selector 1315 may receive the display and output a discrete number 1015 according to the display. For example, in some implementations, the state selector 1315 selects a series of numbers that identify the source and destination of the signal 1230, the type of information in the signal 1230, and the relationship between the signal 1230 and other signals. can do.

  In some implementations, the display output by the header / footer decoder 1705 can be communicated to and used by other parts of the decoder 1205. For example, error check information may be communicated to and used by the error check component within decoder 1005. As another example, the display output by header / footer decoder 1705 can be communicated to translator circuit 1310, which can be used, for example, to set the number of digits to be detected, or The time within the interval where the detected event is considered to match a certain state can be changed.

  FIG. 18 is a schematic diagram illustrating another implementation example of the decoder 1205. The illustrated implementation of decoder 1205 includes a translator circuit 1310 and a state selector circuit 1315. These circuits are suitable for decoding a signal in which information is encoded according to the occurrence timing of an event within a time interval into a signal in which information is encoded with numbers having three or more realizable states. For example, the decoder 1205 can decode the time-based code signal 1220 into a signal 1230.

  In response to event detection, the event detector 1305 outputs a display of time within the interval at which the event is detected. These indications 1325 are received by the time-state translator 1310. The time-state translator 1310 includes a collection of state detectors 1805, 1810, 1815, 1820, all of which are connected to receive an indication of the time within the interval at which the event is detected. .

  State detectors 1805, 1810, 1815, 1820 each specify the time within the interval at which the event is detected, the earliest time and the latest time within the interval at which the detected event is considered to be in the corresponding state. Connected to compare with the standard to be. In response to detecting that the event timing within the interval is within the corresponding range, state detectors 1805, 1810, 1815, 1820 output displays 1825, 1830, 1835, 1840, respectively. Thus, the state detectors 1805, 1810, 1815, 1820 translate the time within the interval into one of the numerical states in the signal 1230 to be output from the decoder 1005.

  The state selector 1315 is connected to receive translations (eg, displays 1825, 1830, 1835, 1840), and based on the received translations, the state selector 1315 outputs a number having a state to the output 1215.

  In operation, event detector 1305 receives signal 1220, where information 120 is encoded according to the timing of the occurrence of the event within the time interval. The event detector 1305 detects the timing of the event within each interval, and outputs a description of the timing (eg, display 1325). The time-state translator circuit 1310 translates the time within the interval into a state to be output by the signal 1330 from the decoder 1305 by comparing the time at which the event was detected by the event detector 1305 with the time assigned to the state. To do. The state selector circuit 1315 receives the results of those comparisons (eg, indications 1825, 1830, 1835, 1840) and selects the output numerical state to be provided to the output 1215 according to those results.

  FIG. 19 is a schematic diagram illustrating decoding a signal in which information is encoded according to the timing of the occurrence of an event within a time interval into a signal including numbers having three or more feasible states. For example, the illustrated decoding may be performed by a decoder such as decoder 1205 shown in FIG. In the illustrated implementation, the time-based code signal 1220 includes a collection of time intervals 1420, each corresponding to a number 1905, 1910, 1915, 1920 in the signal 1230. Each time interval 1420 includes a respective data event 1425. The timing of the data event 1425 within an individual time interval 1420 indicates the state of the numbers 1905, 1910, 1915, 1920 corresponding to that time interval 1420. For example, in the illustrated implementation, the data event 1425 at interval 1420 corresponding to the first state number 1905 occurs at time 1930 near the end of interval 1420. Data event 1425 in interval 1420 corresponding to second state number 1910 occurs at time 1935 near the middle of interval 1420. Data event 1425 at interval 1420 corresponding to third state number 1925 occurs at time 1940 prior to the middle of interval 1420. Data event 1425 at interval 1420 corresponding to the fourth state number 1905 occurs at time 1945 near the beginning of interval 1420. Times 1930, 1935, 1940, 1945 are distinguishable from each other.

  In decoding, the time-based code signal 1220 is decoded into a signal 1230. The information includes numbers having four different discrete potential states: a number 1905 having a first state (ie “A”), a number 1910 having a second state (ie “B”), a third number The number 1915 having a state (ie, “C”) and the number 1920 having a fourth state (ie, “D”) are represented by signal 1230. In other implementations, the signal 1230 may be a number having a different number of possible states (eg, a number having 10 different possible states representing information in decimal), or a very large number Information can be represented by numbers having a feasible state or a feasible continuum (eg, a substantially analog or analog continuum). In some implementations, the signal 1230 can represent genetic information, ie, four nucleic acids, using four different realizable states.

  In other implementations, the decoder is implemented as a digital circuit that receives as input an ordered collection of bits grouped into binary characters having a predetermined length of N binary digits (ie, bits). be able to. In this case, only one bit is identified from the other bits, producing a series of output codes as output. The digital circuit can be controlled by a programmed computer or can include an embedded computer. In some such implementations, the decoder includes circuitry that converts the sequence of codes into an analog output signal.

  FIG. 20 is a schematic diagram illustrating an implementation example of the decoding system 2000. System 2000 may be a stand-alone system or part of a larger system, such as system 1200 (FIG. 12). System 2000 includes neural processing components 140 and 1005 from which signal 1220 is received by decoder 1205. The signal 1220 encodes information according to the occurrence timing of the event within the time interval. In some implementations, neural processing components 140 and 1005 may include multiple elements that contribute to events in signal 1220. For example, in neural processing components 140 and 1005 implemented using “wet” neural components, multiple nerves may contribute to an event in signal 1220. As another example, in neural processing components 140 and 1005 implemented using semiconductor elements, multiple neural network outputs can contribute to events in signal 1220.

  In operation, decoder 1205 can decode signal 1220 into signal 1230 to represent information 1225 as an ordered finite set of discrete numbers. The decoder 1205 can thus serve as an interface between pattern recognition functions and statistical processing provided by the neural processing component 1205 and binary (and other) digital data processing devices. For example, the decoder 1205 may be included in a motor or other prosthesis that receives a neural spike train encoded in the signal 1220 with control or other information, for example.

  FIG. 21 is a schematic diagram illustrating an implementation example of a signal decoding system in which information is encoded according to the timing of occurrence of an event within a time interval, that is, a multi-channel decoder system 2100. Multi-channel decoder system 2100 can be used alone or with other devices. For example, multi-channel decoder system 2100 can be used as time-based decoder 41 (FIG. 1A).

  System 2100 includes a collection of decoders 1205, a data aggregator 2105, a collection of inputs 2110, and an output 2115. Input 2110 receives a respective time-based code signal 1220. Each time-based code signal 1220 includes a collection of intervals, which themselves include events. Information is encoded according to the timing of events within these intervals. In some implementations, the various time-based code signals 1220 can all be received from the same single system or medium 140, as shown.

  A time-based code signal 1220 is provided from input 2110 to a corresponding input 1210 of decoder 1205. Each decoder 1205 is thus connected to receive a respective time-based code signal 1220. The decoder 1205 decodes the information with the signal 1220 and outputs a decoded signal 2125. In the decoded signal, at least some of the information content of signal 1220 is represented by an ordered finite set of discrete numbers, eg, a collection of high and low bits.

  Decoded signal 2125 is provided to one or more inputs 2130 of data aggregator 2105. Data aggregator 2105 also includes an output 2135. The data aggregator 2105 is a component that aggregates a relatively small collection of numbers into a larger collection of numbers. In the illustrated implementation, the data aggregator 2105 is connected to aggregate the received decoded signal into an output signal 1230 that represents information 1225 in an ordered finite set of discrete digits. Output signal 1230 is provided from output 2135 of data aggregator 2105 to output 2115 of system 2100.

  In operation, each decoder 1205 receives a respective time-based code signal 1220 from the system or medium 140. The decoder 1205 decodes each time-based code signal 1220 into a signal representing information content in an ordered finite set of discrete numbers. The data aggregator 2105 is connected to receive the signal 1220, aggregate these signals, and output the output signal 2145.

  FIG. 22 is a schematic diagram illustrating an implementation example of a system 2200 capable of encoding information. System 2200 includes a multi-channel encoder 1105 and a compression encoder 2205.

  The compression encoder 2205 is a component that compresses a plurality of input signals into a single output signal 2220. The compression encoder 2205 includes a collection of one or more inputs 2210 and outputs 2215. One or more inputs 2210 are connectable to receive a time-based code signal from output 1115 of multi-channel time encoder 1105. The compression encoder 2205 compresses the received time-based code signal and outputs the compressed signal 2220 to the system or medium 140 via the output 2215.

  System 2200 can be used alone or in conjunction with other devices. For example, system 2200 can be used as time-based encoder 25, amplitude weighting component 27, and compressor 29 (FIG. 1A).

  FIG. 23 is a schematic diagram illustrating an implementation example of the compression encoder 2205. The compression encoder 2205 is a component that encodes information from a collection of signals, and a signal that includes events whose information is time-series such as a signal 2220 (FIG. 22) depending on the timing of event occurrence within a time interval. Is encoded.

  In the illustrated implementation, encoder 2205 includes a collection of various binary-to-analog converters 2305, an integrator 2310, a collection of inputs 2315, and an output 2320. Each binary to analog converter 2305 includes a respective input 2325 and output 2330. The input 2325 of each binary to analog converter 2305 is connected to receive a respective signal 135. In this case, information is encoded from the corresponding input 2315 according to the timing of the occurrence of the event within the time interval.

  Each input 2315 and corresponding binary-to-analog converter 2305 pair forms an encoded channel 2340. The compression encoder 2205 thus forms a parallel combination of multiple encoded channels 2340. The signal 135 may have the same information, may have different information content, or may have a combination of the same information content and different information content.

  Each binary-to-analog converter 2305 is a component configured to weight the amplitude of individual events in the input time series of events as a function of the timing of other events in the input time series. In some implementations, events can be weighted using a non-linear function. In some implementations, the compression encoder 2205 includes at least two different binary-to-analog converters 2305. Different binary-to-analog converters 2305 can weight events using various time sensitivity parameters, various time sensitivities, or a combination of these or other factors. In some implementations, every binary to analog converter 2305 in encoder 2205 will be different from every other binary to analog converter 2305 in encoder 2205. In some implementations, the collection of binary-to-analog converters 2305 in encoder 2205 is a complete set of binary-to-analog converters constructed using a process such as process 3900 (FIG. 39). Because of this difference, as a result, when the same signal whose information is encoded by the timing of the occurrence of an event within the time interval is input to a different binary-to-analog converter 2305, it is weighted in the input signal. Different signals that include weighted events at relative times corresponding to the timing of the non-events will be output by different binary-to-analog converters 2305.

  Each binary-to-analog converter 2305 outputs a signal 2345 that may include a weighted event at a relative time corresponding to the timing of the unweighted event in the input signal across output 2330. Signal 2345 is provided to each input 2350 of integrator 2310. In implementations where the integrator 2310 is implemented using “wet” neural components, the characteristics of the signal 2345 can be adjusted to match the wet neural components. For example, events in signal 2345 can be adjusted to mimic the amplitude and time characteristics of action potentials.

  Integrator 2310 includes a collection of inputs 2350 and outputs 2355. Integrator 2310 is a component that integrates the signal received at input 2350 to generate the signal supplied to output 2355. By integrating these signals, these signals are combined and compressed into a single signal. In some implementations, integrator 2310 can be a non-linear integrator in that different signals received at different inputs 2350 contribute to varying degrees to the signal provided at output 2355. In some implementations, integrator 2310 can be a linear integrator in that different signals received at different inputs 2350 contribute to the same extent to the signal provided at output 2355. In some implementations, integrator 2310 is modeled on one or more neurons or nodes in a brain or other neural processing device, as described further below. For example, a single signal output 2360 provided on output 2355 of integrator 2310 can represent the overall interaction of the different signals received at input 2350.

  Output 2355 couples signal 2360 to output 2320 of compression encoder 2205. Output 2320 provides signal 2365 to system or medium 140.

  FIGS. 24, 25, 26, and 27 are schematic diagrams associated with various implementations of integrator 2310, namely integrator 2400, integrator 2500, integrator 2600, and integrator 2700. Integrator 2400 is a non-branching node of the neural processing system. Integrator 2500 is a node of a neural processing system having a plurality of branches. Integrators 2600 and 2700 are a network of nodes of a neural processing system. Integrators 2400, 2500, 2600, 2700 can be constructed of hardware, software, wet neural components, or a combination of these components.

  As shown, integrator 2500 includes a collection of branches 2505. In some implementations, branch 2505 has the same characteristics. In other implementations, different branches 2505 have different characteristics. For example, different branches 2505 may have different cable characteristics.

  As shown, integrators 2600 and 2700 each include a collection of nodes 2605 joined by a collection of links 2610. Link 2610 may include, for example, a feed forward link, a feedback link, a repetitive link, or a combination thereof. Integrator 2700 includes a pair of outputs 2355. Both outputs 2355 provide the result of combining and compressing the signal received at input 2350. In general, however, output 2355 will output various signals due to various combinations and compression of the signals received at input 2350. As a result, two different signals can be output from the compression encoder and transmitted to the system or medium 140. These two different signals can also be stored or decoded in parallel using the systems and techniques described above. Such parallel storage and decoding can reduce data storage density or require additional processing, but the fidelity of storage and decoding can be checked and required Accordingly, it can be improved by comparing the results of parallel decoding.

  In operation, integrators 2400, 2500, 2600, 2700 can integrate the input signal according to one or more models. For example, in some implementations, the integrator 2400 can integrate according to an integration-fire model. Such a model includes a capacitor C in parallel with a resistor R driven by a current I (t) and provides the following equation:

In this model, the signal on input 2350 is integrated by linearly summing the amplitude of each signal at any instant in time (ie, the voltage of each input signal (RxI (t)) is summed. ) The voltage signal decays exponentially with a time constant τ _m . A threshold voltage can be selected and a binary state can be signaled at output 2355 at a higher voltage.

  In other implementations, integrators 2400-2700 can integrate according to a conductance-based integration-firing neuron model given by the following equation:

g _j is a conductance for a specific ion species, V-V _j is a Nernst potential of conductance, and I _ext is a current applied from the outside.

In this model, the signal on input 2350 is integrated by nonlinearly summing the amplitude of each signal at any instant in time, which depends on the total voltage achieved at any instant in time. _Is achieved by one or more conductances g which scale the amplitude of the signal (I _ext ). The amplitude of each signal also decays exponentially with a time constant τ _m that can vary if the conductance is set to change. A threshold voltage can be selected and a binary state can be signaled at output 2355 at a higher voltage.

  In some implementations, the integrator 2500 may operate according to a model that is expanded such that the generation of a voltage conductance base includes the attenuation of the voltage in the cable. This is described by the telegraph equation given by:

Where λ is a length constant determined by the characteristics of the branch, χ is a counted unit of length along the branch, and V _L is the voltage at equilibrium.

  In this model, the signal on input 2350 is propagated to all other inputs 2350 using Equation 1 or Equation 2 above, and each signal on input 2350 along the physical branch of the system. It is integrated by summing more linearly to obtain. As the signal propagates, the amplitude attenuates according to the length constant λ, while each signal on the input 2350 contributes to amplitude to some extent at each input 2350. Thus, the amplitude of any one signal at input 2350 is inherently attenuated while propagating to the location of exemplary input 2350, and then the amplitude of that signal is reduced to that of all other signals on input 2350. The sum of the amplitudes is added. A threshold voltage can be selected and a binary state can be signaled at output 2355 at a higher voltage.

  In some implementations, integrators 2600 and 2700 may operate according to a neural network model in which all nodes are interconnected directly or indirectly through other nodes. In such an integrator, any node can function as an output. In some implementations, integrators 2600 and 2700 may operate according to a model given by:

I _i (t) is the current input by input i at time t, and there are n inputs to the neuron.

  In this model, the signal on input 2350 is integrated by networking processing elements 2605, each modeled by Equation 1, Equation 2 or Equation 3 above. This in turn provides an additional internal input 2610 to each element 2605, thus allowing all inputs 2350 to be arbitrarily non-linearly and in parallel to provide an output 2355. Any one of the processing elements 2605 may choose to signal the binary state of the network as output 2355.

  Integrators 2400, 2500, 2600, 2700 can be used as compressor 29 (FIG. 1A).

  FIG. 28 is a schematic diagram showing the binary-analog converter 2305. The binary-analog converter 2305 can be used in, for example, an encoder, a time series scanner, or a weighting device. Thus, the binary to analog converter 2305 may be a reference binary to analog converter in some implementations, as further described below.

  The binary-to-analog converter 2305 is a component configured to weight the amplitude of individual events in the input time series of events as a function of the timing of other events in the input time series. In some implementations, events can be weighted using a non-linear function. For example, the binary-to-analog converter 2305 can use a plurality of time sensitivity parameters to generate individual weights for each individual event based on the timing of previous events in the input signal. The binary to analog converter 2305 individually generates the weights generated by, for example, multiplying the events by weights and outputting weighted events at relative times corresponding to the timing of the unweighted events in the input signal. Can be added to any event.

  The binary to analog converter 2305 includes an input 2325 and an output 2330. Input 2325 receives a signal 2805 containing a time series of events. For example, input 2325 may receive a time-based code signal 135 or a signal output from compression encoder 2205. Output 2330 provides a signal 2810 that includes a weighted event at a relative time corresponding to the timing of the unweighted event in the input signal.

  In some implementations, the binary to analog converter 2305 may include a reset mechanism that resets the amplitude weighting of individual events to a known state. The reset mechanism may be triggered, for example, by the presence of a footer event 530 within the footer interval 520 of the signal 135 (FIG. 5). By resetting the weighting, the gradual change of the time sensitivity parameters can be stopped and these parameters can be returned to known values. In other implementations, the binary-to-analog converter 2305 can be stationary without triggering, for example, over time.

In some implementations, the parameters used by the binary to analog converter 2305 can be represented by a time dependent differential equation. For example, the binary-to-analog converter 2305 uses three time sensitivity parameters (U, τ _d , τ _t in the following equation) and one time sensitivity parameter (A in the following equation) to convert individual weights. Can be generated. In some implementations, the amplitude A _k of the kth event in a signal in which events (1,... K) are separated by time (Δ _k ,..., Δ _k−1 ) may be given by it can.

In this case, Ψ and μ _k are hidden dynamic variables (μ∈ [0,1]; (Ψ∈ [0,1]; with initial values of Ψ ₁ = 1 and μ ₁ = U for the first event). 1]), for example, the variable Ψ can represent the fractional part of the resources available at the time of each event, and the variable μ can represent, for example, the fractional part of the resources used by each event. In some implementations, both variables expand with each event so that the amplitude of the response to each event in the signal varies differently to reflect the temporal history of the event in that signal. Can be prescribed.

The manner in which these dynamic variables develop and the period in which each response accumulates information about the temporal history of the signal depends on the value of the time sensitivity parameters (U, τ _d , τ _f ). The parameter U can set the maximum resource available for the first event, thereby discriminating the maximum possible response (given by A). Thus, A ₁ = AU. The parameter τ _d is a time constant for recovering resources after use. The parameter τ _f is a time constant for recovering from the simplified μ _κ by a certain amount (typically μ).

By assigning different values to the parameters U, τ _d , τ _f , different binary-to-analog converters 2305 generate different sequence amplitudes according to the same input sequence of events. In some implementations, more complex time sensitivity can be achieved using a double or higher order exponential function for one or both of the parameters τ _d , τ _f . In some implementations, a time sensitivity function is used to provide one or both of τ _d , τ _f to create a more complex time sensitivity by creating a random variable or function linked to the parameter itself. can do.

  In some implementations, the binary-to-analog converter 2305 may be implemented as disclosed in one or more of the following: US Patent Publication 2003/0208451; US Patent 5,155,802; U.S. Patent 5,537,512; U.S. Patent 6,363,369; and U.S. Patent 4,962,342. The contents of all these publications are incorporated herein by reference. For example, the binary-to-analog converter 2305 dynamically adjusts the reaction intensity according to the temporal pattern of events in the signal 2805, thereby “dynamic synapses” as disclosed in US Pat. No. 6,363,369. Can be implemented as a device that includes a network of signal processors interconnected by one or more processing junctions. These processing junctions can generate post-join signals for a second signal processor in the network by receiving and processing pre-join signals from one signal processor in the network to generate a join signal. Each processing junction can be configured such that the junction signal is dynamically dependent on the pre-join signal.

  FIG. 29 is a schematic diagram showing the weighting of individual events in the time series of events as a function of the timing of other events in the time series. The illustrated weighting can be performed by a binary-to-analog converter, such as binary-to-analog converter 2305 (FIG. 28). In the illustrated implementation, signal 135 is a time-based code signal that encodes information according to the timing of the occurrence of an event within the time interval. For example, the signal 135 may be a time-based code signal output from the decoder 105 (FIGS. 1, 2, 4, 6, and 8). Signal 135 is weighted to form a weighted time signal 2900.

  The weighted time signal 2900 includes a series of time intervals 2905, each of which includes a respective event 2910. Event 2910 occurs at time 2915 within each interval 2905.

  In the illustrated implementation, event 2910 is a pulse that transitions from a baseline (ie, “stop”) state 2920 to a high (ie, “activity” state 2925, and then returns to the baseline stop state 2920. The level of the high state 2925 is different for various events 2910. The level of the high state 2925 is a result of the amplitude and weighting of the event 2910. The level of the high state 2925 (ie, the amplitude of each event 2910) is , Embody the timing of that event 2910 in signal 135 and the timing of other events 2910 in signal 135. In other words, the information encoded by the timing of two or more events 2910 in signal 135 is: For each event 2910 As it is the. Above embodied in width, in some implementations, the amplitude of each of the event 2910 may be embodied timing of only events 2910 preceding.

  In the illustrated implementation, event weighting in the time-based code signal 135 changes the amplitude of those events while retaining timing information within the interval and within the signal. In particular, the illustrated weighted time signal 2900 includes a collection of time intervals 2905, each corresponding to a respective interval 320 in the signal 135. This correspondence is represented by arrow 2930. In the illustrated implementation, several events 2910 are incremented with an amplitude for each corresponding event 205, and some events 2910 are decremented with an amplitude for each corresponding event 205.

  Corresponding time intervals 2905 and 320 each include a respective event 2910 and 325 encoding information. The locations of events 2910 and 320 within the corresponding time intervals 2905 and 325, respectively, are the same. For example, if event 320 occurs at the beginning of time interval 325, event 2910 at the corresponding time interval 2905 also occurs at the beginning of that interval. As another example, if event 320 occurs in the middle of time interval 325, event 2910 in the corresponding time interval 2905 also occurs in the middle of that interval. In the implementation shown, the corresponding intervals 2905 and 325 have the same duration. Further, the order of the corresponding intervals 2905 and 325 relative to the other intervals 2905 and 325 in the respective signals 2900 and 135 is the same.

  FIG. 30 is a schematic diagram illustrating one implementation example of the signal 2365. The signal 2365 may be output from a compression encoder 2205 of a device such as a mobile phone transmitter or a disk drive head. The signal 2365 may be a one-dimensional signal or the one-dimensional signal 29 (FIG. 1A).

  The signal 2365 includes a time-series event 3005. Events 3005 are separated from each other by a time span 3010. The time span 3010 period embodies the integration of an amplitude sequence that includes a weighted event, eg, a weighted time signal 2900.

  In the illustrated implementation, the event 3005 is a pulse that transitions from the baseline (ie, “stop”) state 3015 to the high (ie, “active” state 3020 and then back to the baseline stop state 3015. In some implementations, the shapes of the various events 3005 are indistinguishable from each other, and the various events 3005 can only be identified by their timing.

  The number of time spans 3010 for a given signal 2365 within a unit time can be selected to match a predetermined probability distribution. In some implementations, the probability distribution may be asymmetric, eg, tilted to the left of its center. In some implementations, the standard deviation of the probability distribution is approximately equal to the square root of the mean value of the probability distribution. For example, in some implementations, the number of time spans 3010 within a unit time may be Poisson distributed.

  In some implementations, the signal 2365 can be added to the additional information, superimposed on the additional information, or transmitted along with the additional information. For example, event 3005 can be added to a modulated or shifted analog or digital signal, and thus can be similar to noise in that signal. Such an implementation is particularly relevant to hidden or encrypted data communications. For example, event 3005 can be transmitted with a frequency modulated analog signal that itself conveys inconspicuous information, such as a radio broadcast. For an observer who has not received the notification, the event 3005 will look like noise on the second signal. In this way, the information content encoded by the event 3005 can be camouflaged.

  FIG. 31 is a schematic diagram showing the data storage device 3100. Data storage device 3100 is a component that can store information therein and access the information stored therein. For example, the data storage device 3100 may be an optical disk, a magnetic disk, a magnetic tape, a record album, a punch card, a bar code label, or other data storage device.

  Data storage device 3100 includes a collection of detectable physical representations 3105. The physical representation 3105 is a structural element that can be detected or sensed by a reader of the data storage device. For example, the physical representation 3105 may be an optical disc pit or bump detectable by an optical disc reader. As another example, the physical representation 3105 may be a magnetic disk or tape magnetizing element detectable by a magnetizing sensor. As another example, the physical representation 3105 may be a feature of a record album that can be detected by a record player's needle.

  The physical representation 3105 is sequentially placed and positioned along the path 3110. Path 3110 guides data storage and access and can be, for example, the length of a track, groove, magnetic tape, barcode. The physical representations 3105 along each path 3110 are separated from each other by a distance 3115. The length of the distance 3115 can be scaled to correspond to the time between events in the signal. For example, the length of the distance 3115 can be scaled to correspond to the duration of the time span 3010 in the signal 2365 (FIG. 30).

  During the writing of data to the data storage device 3100, the relative movement speed between the path 3110 of the data storage device 3100 and the writer of the data storage device follows the time between the events in such signals along the path 3110. It can be converted to a position in the physical representation 3105. During the reading of data from the data storage device 3100, the relative speed of movement between the path 3110 of the data storage device 3100 and the reader of the data storage device determines the position of the physical representation 3105 along the path 3110 as such. It can be converted back to the time between events in the signal. In some implementations, the relative speed of movement during reading and writing need not be constant, and may vary based on the location of path 3110 on data storage device 3100, for example.

  The number of lengths of the distance 315 within the unit length can be selected to match a predetermined probability distribution. In some implementations, the probability distribution may be asymmetric, eg, tilted to the left of its center. In some implementations, the standard deviation of the probability distribution can be approximately equal to the square root of the mean value of the probability distribution. For example, in some implementations, the number of lengths of the distance 315 within the unit length may be Poisson distributed.

  In operation, a writer of the data storage device can receive a signal characterizing a timed event, such as signal 2365. The data storage writer writes the physical representation 3105 along one or more paths 3110 on the data storage 3100 so that the length of the distance 3115 is scaled to correspond to the time between events in the signal. Can be included. The data storage device 3100 can maintain or “store” the physical representation 3105 and the length of the distance 3115 separating the physical representation 3105.

  In accessing the stored information, the reader of the data storage device can measure the length of the distance 3115 that separates the physical representation 3105 along one or more paths 3110 on the data storage device 3100. These measurements can be converted into signals characterizing time-series events, such as signal 2365 (FIG. 30). For example, the reader of the data storage device can output signal 2365 such that the duration of time span 3010 is scaled to correspond to the length of distance 3115. In some implementations, the reader of the data storage device and the writer of the data storage device may be the same device.

  FIG. 32 is a schematic diagram illustrating an implementation example of a system capable of decoding information, that is, a system 3200. System 3200 includes a multi-channel decoder 2100 and an extension decoder 3205.

  The extension decoder 3205 is a component that extends one or more input signals to a collection of output signals. Extended decoder 3205 includes an input 3210 and a collection of one or more outputs 3215. Input 3210 receives signal 2365 from system or medium 140. The extension decoder 3205 extends the signal 2365 and provides the multi-channel decoder 2100 with a collection of one or more signals whose information is encoded according to the timing of the occurrence of an event within a time interval on one or more outputs 3215. Output.

  System 3200 can be used alone or in conjunction with other devices. For example, system 3200 can be used as weighting expander 37, amplitude decoder 39, and time-based decoder 41 (FIG. 1A).

  FIG. 33 is a schematic diagram illustrating an implementation example of the extension decoder 3205. The decoder 3205 is a component that decodes information in a time-series signal including an event into a time-based code signal. In this case, the information is encoded according to the occurrence timing of the event within the time interval. Decoder 3205 can thus decode signals such as signal 2365 (FIG. 30) into signals such as signal 1220 (FIG. 12).

  In addition to input 3210 and one or more outputs 3215, decoder 3205 includes a weighting device 3310 and a time series scanner 3315. The weighting device 3310 is a component for weighting events in a signal including events that are time-series. The time series scanner 3315 is a component that scans a time series that, when input to an appropriately scaled binary-to-analog converter, results in a time-based code signal, in this case the occurrence of events within a time interval. Information is encoded according to timing.

  Input 3210 of extension decoder 3205 receives signal 2365. Signal 2365 includes time-series events. The weighting device 3310 is coupled to the input 3210 and includes an output 3335. Output 3335 provides the net series of amplitude event 3340.

  Time series scanner 3315 includes an input 3345 and is coupled to an output 3215 of decoder 3305. Input 3345 receives event 3340 and outputs a time-based code signal. In this case, information is encoded according to the occurrence timing of the event within the time interval. For example, output 3215 can provide signal 135 to a system or medium.

  The extension decoder can be used alone or with other devices. For example, the extended decoder can be used as a weighting expander 37 and an amplitude decoder 39 (FIG. 1A).

  FIG. 34 is a schematic diagram showing the weighting device 3310. The weighting device 3310 is a component for weighting events in a signal including events that are time-series. For example, the weighting device 3310 can weight the event 3005 of the signal 2365 (FIG. 30). As described further below, the weighting by which the weighting device 3310 weights events has succeeded in representing mathematical or other behavior on a particular signal on the input channel 2340 of the compression encoder 2205. Can be selected based on (FIG. 23). For example, in some implementations, the weighting device 3310 weights events for data compression and encryption operations on signals on input channel 2340, document processing operations on signals on input channel 2340, input One or more of a number processing operation on the signal on channel 2340, an image processing operation on the signal on input channel 2340, and a signal processing operation on the signal on input channel 2340 may be selected. The weighting device 3310 may be part of the extended decoder 3205 (FIG. 33).

  The weighting device 3310 includes an input 3210, an output 3335, a collection of binary-to-analog converters 2305, a collection of multipliers 3440, a collection of weights 3445, and an adder 3465. Input 3210 receives a signal 2365 that includes time-series events. Input 3210 distributes signal 2365 to input 2325 of binary to analog converter 2305. Each binary-to-analog converter 2305 weights the amplitude of individual events in the input time series of events as a function of the timing of other events in the input time series. For example, each binary-to-analog converter 2305 can use the time sensitivity parameter to generate individual weights for each individual event based on the timing of previous events in the signal 2365. In general, each binary-to-analog converter 2305 is generated, for example, by multiplying an event by a weight and outputting a weighted event at a relative time corresponding to the timing of the unweighted event in signal 2365. Add weight to individual events.

  In some implementations, the collection of binary-to-analog converters 2305 can be constructed using a process such as process 3900 (FIG. 39). In some implementations, the set of binary-to-analog converters 2305 in weighting device 3310 can be a complete set of binary-to-analog converters constructed using process 3900.

  Each binary to analog converter 2305 includes an output 2330 for which a weighted time series of events 3430 is output. Weighted time series events 3430 are provided as inputs to respective multipliers 3440. The multiplier 3440 is a component configured to multiply the weighted time series event by another weight. As described further below, the weight 3445 can be determined during the training process. For example, each of the weights 3445 can be determined in response to the corresponding binary-to-analog converter 2305 successfully displaying a particular signal 135 input to the channel 2340 of the compression encoder 2205. As another example, the weights 3445 are in response to each binary-to-analog converter 2305 successfully representing a mathematical or other operation with a particular signal 135 input to the channel 2340 of the compression encoder 2205. Can be determined.

  Each weight 3445 may be received by multiplier 3440 via a respective input 3450. The weight 3445 can be stored, for example, in one or more data storage devices. Multiplier 3440 is a component that scales the weighted time series of events 3430 received on input 3435 according to weight 3445. Multiplier 3440 can scale weighted and time series events linearly or non-linearly. For example, in some implementations, multiplier 3440 can multiply weight 3445 corresponding to the weighted event in each time series using weight 3445 as a scalar weight. In some implementations, multiplier 3440 can use weights 3445 to scale various weighted events in each time series to a non-linear or other form.

  Each multiplier 3440 outputs a scaled and weighted time series of events 3455 via an output 3450 coupled to an input 3460 of adder 3465. Adder 3465 is a component that sums these scaled and weighted events 3455 for each time in the input scaled and weighted time series to produce a net series of amplitude events 3470.

  In some implementations, the adder 3465 may include a dynamic threshold for generating an amplitude event in the net series 3470. A dynamic threshold is a variable threshold. The dynamic threshold may be a lower cutoff to include amplitude events in the net series 3470. In other words, if the sum of the scaled and weighted events at the first time is less than this lower cutoff, this sum is not included in the net series 3470, even if the sum is not zero. The dynamic threshold may be modified to control the number of amplitude events in the net series 3470. For example, the dynamic threshold can be changed to ensure that the number of amplitude events in the net series 3470 is equal to the number of events in the input signal 2365. In some implementations, adder 3465 first sums the scaled and weighted events for each time in the input scaled and weighted time series, then the number of amplitude events in the net series 3470. The dynamic amplitude gradually decreases until is equal to the number of events in signal 2365. This allows the same dynamic threshold to be applied to the entire net series 3470.

  In the illustrated implementation, the amplitude events within the net series 3470 are separated by non-uniform periods. This is not necessarily true. Alternatively, adder 3465 can output an amplitude event in net series 3470 without timing information. Considering the dynamic threshold described above, adder 3465 can output a list of amplitudes of the largest amplitude event as a net series 3470, substantially without describing the timing between those events. . The order of amplitudes in such a list may correspond to the order in which such events occurred.

  FIG. 35 is a schematic diagram showing the weighting as a function of the timing of other events in the time series relative to the amplitude of individual events in the time series of events. The illustrated weighting can be performed by a binary-to-analog converter, such as binary-to-analog converter 2305 (FIG. 28). In the illustrated implementation, signal 2365 includes time series events 3005 that are separated from each other by a time span 3010. The time span 3010 period embodies the integration of an amplitude sequence that includes weighted events. Thus, signal 2365 can be output from one of the integrators 2310, 2400, 2500, 2600, 2700, etc., for example.

  Signal 2365 is weighted to form a weighted time signal 3500. Weighted time signal 3500 includes a collection of events 3505 separated from each other by a time span 3510.

  In the illustrated implementation, event 3505 is a pulse that transitions from a baseline (ie, “stop”) state 3520 to a high (ie, “activity”) state 3525 and then back to the baseline stop state 3520. . The level of the high state 3525 is different for various events 3505. The level of high state 3525 is a result of the amplitude and weighting of event 3505. The level of high state 3525 (ie, the amplitude of each event 3505) embodies the timing of that event 3505 in signal 2365 and at least some of the other events 3505 in signal 2365. In other words, information encoded by the timing of two or more events 3505 in signal 2365 is embodied within the amplitude of each event 3505. As described above, in some implementations, the amplitude of each event 3505 may embody the timing of the preceding event 3505 only.

  In the illustrated implementation, several events 3505 are incremented with an amplitude for each corresponding event 2365 and some events 3505 are decremented with an amplitude for each corresponding event 2365.

  The time span 3510 between occurrences of event 3505 within the weighted time signal 3500 is scaled to the time span 3010 between occurrences of event 3005 within 2365. In the illustrated implementation, the time span 3510 is scaled 1: 1 to the time span 3010. In other words, the time span 3010 separating the first pair of events 3005 is the same as the time span 3510 separating the pair of events 3505 corresponding to the first pair.

  FIG. 36 is a schematic diagram showing a time series scanner 3315. Time series scanner 3315 is a component that scans for a time series that, when input to an appropriately scaled binary-to-analog converter, results in a time-based code signal. In this case, information is encoded according to the occurrence timing of the event within the time interval. For example, the time series scanner 3315 can scan for a time-based code signal 135 that is similar to or the same as the time-based code signal 135 input to the channel 2340 (FIG. 23) of the compression encoder 2205. .

  Time series scanner 3315 includes an input 3345 and an output 3215. Input 3345 receives a net series 3470 of amplitudes or amplitude events. Input 3345 communicates net series 3470 to input 3620 of amplitude buffer 3625. The amplitude buffer 3625 is a component that buffers the amplitude in the net series 3470 for comparison by the comparator 3635. In some implementations, the amplitude buffer 3625 may include a cache or other memory that stores the magnitude of the net series 3470 or the magnitude of the amplitude event. In implementations where the net series 3470 includes timing information, the amplitude buffer 3625 may include components for removing timing information from the net series 3470 without losing amplitude information. Amplitude buffer 3615 includes an output 3630 that provides the buffered amplitude to input 3640 of comparator 3635.

  Comparator 3635 also includes an input 3645 and an output 3650. Comparator 3635 is a component that compares the amplitude on input 3640 with the amplitude on input 3645 and displays the result of the comparison on output 3650. As a result of the comparison, a difference in amplitude between the input 3640 and the input 3645 is realized. For example, if the difference in amplitude between input 3640 and input 3645 is very small, output 3650 can output a small signal.

  The comparator 3635 compares the amplitude buffered in the amplitude buffer 3615 with the amplitude output from the reference binary-analog converter 2305. Although shown as a single component, comparator 3635 may include a collection of comparators connected in parallel, for example, to compare individual amplitudes. In other words, the first comparator can compare the first amplitude buffered in the amplitude buffer 3625 with the first amplitude output from the reference binary-to-analog converter 2305, and the second comparator can The second amplitude buffered in buffer 3625 can be compared to the second amplitude output from reference binary-to-analog converter 2305, and so on. The results of individual comparisons by such a collection of comparators can be output to one or more output collections.

  The output 3660 of the comparator 3635 is provided to the input 3665 of the time-based code permuter 3670. The time-based code permuter 3670 is a component that rearranges the time-based code times in response to feedback from the output 3660. In particular, the time-based code permuter 3670 reorders the time-based code to minimize the amplitude difference between the input 3640 and the input 3645 of the comparator 3635. Time-based code permuter 3670 outputs candidate time-based code 3675 via output 3680. As described further below, candidate time-based codes are proposed as solutions that approximate the time-based code signal 135 input to channel 2340 (FIG. 23) of compression encoder 2205. For example, the time-based code permuter 3670 can generate candidate time-based code 3675 using a successive approximation method.

  Code 3675 is provided to input 2325 of reference binary-to-analog converter 2305. The reference binary-to-analog converter 2305 may use a plurality of time sensitivity parameters, for example, to generate individual weights for each individual event based on the timing of previous events in the time-based code. A component that can weight the amplitude of individual events in a candidate time-based code as a function of the timing of other events in the time-based code. The reference binary-to-analog converter 2305 can output the weighted event at a relative time corresponding to the timing of the unweighted event in the candidate time-based code or without timing information. In other words, the reference binary-to-analog converter 2305 can output an ordered list of amplitude weights without describing the timing between those events in the input candidate time-based code. In some implementations, the reference binary-to-analog converter 2305 may include a buffer, cache, or other memory that stores weighted or weighted amplitude magnitudes.

  In some implementations, the reference binary-to-analog converter 2305 may be identical to the binary-to-analog converter 2305 (FIG. 23) of the compression encoder 2205. For example, the time sensitivity parameter used by the reference binary-to-analog converter 2305 in the time series scanner 3315 may be the same as the time sensitivity parameter used by the binary-to-analog converter 2305 in the channel 2340.

  In some implementations, the time-based code permuter 3670 also implements the feedback provided by the output 3660 to account for an acceptable amount difference between the amplitudes of the inputs 3640 and 3645 of the comparator 3635. A comparator may be included that compares to the value level. The time-based code permuter 3670 can reorder candidate time-based codes until an acceptable amount of difference is reached. In other words, in implementations where fidelity is very important, the threshold level may be more stringent, and the difference in amplitude between input 3640 and input 3645 of comparator 3635 may be relatively small or zero. Is set to be necessary. Under such circumstances, the reordering that the time-based code permuter 3670 will perform will generally be relatively large. In implementations where fidelity is less important and factors such as speed are more important, the threshold level may not be so strict and the difference between the amplitudes of the input 3640 and the input 3645 of the comparator 3635 may be It can be set to be relatively large. Under such circumstances, there will generally be relatively little reordering that the time-based code permuter 3670 will perform. In some cases, an acceptable amount difference between the amplitudes of input 3640 and input 3645 of comparator 3635 may be achieved after performing more or less reordering than is generally required. . For example, the time-based code permuter 3670 may accidentally output a candidate time-based code with little substitution and meet even a very strict threshold level. In some implementations, the threshold stringency may be adjustable, for example by a user, for operation under various circumstances.

  In response to feedback from output 3660 reaching or exceeding the threshold level, time-based code permuter 3670 may output a selection signal 3585 via output 3690. Selection signal 3865 indicates that the difference in amplitude between input 3640 and input 3645 of comparator 3635 has reached an acceptable low level. The selection signal 3585 can be set to close the switch 3690 so that the output 3215 can be associated with the code 3675. This causes candidate time-based code 3675 to be transmitted to output 3215 and output to stem or medium 140 as signal 135.

  FIG. 37 is a schematic diagram showing an extension decoder 3205, that is, a multi-channel extension decoder 3700. The decoder 3700 is a component that decodes information in a signal including time-series events into a time-based code signal. In this case, information is encoded according to the timing of event occurrence within a time interval. Decoder 3700 can thus decode a signal, such as signal 2365 (FIG. 30), into a collection of signals 135. The decoder 3700 can be used alone or with other devices. For example, the decoder 3700 can be used as a weighting expander 37 and an amplitude decoder 39 (FIG. 1A).

  The decoder 3700 includes a collection of weighting devices 3310, a collection of time series scanners 3315, an input 3710, and a collection of one or more outputs 3715. Each weighting device 3310 is paired with a corresponding time series scanner 3315. These pairs may form a collection of decoding channels 3717 at decoder 3700. The decoder 3700 thus forms a parallel combination of multiple decoding channels 3717, each of which forms a separate enhanced decoder 3205.

  In decoder 3700, each weighting device 3310 can weight an event using an associated set of binary-to-analog converters 2305 and an associated set of weights 3445. In some implementations, at least some of the binary-to-analog converter 2305, at least some of the weights 3445 of the various weighting devices 3310, or both will be different. For example, in an implementation in which the set of binary-to-analog converters 2305 is a complete set of binary-to-analog converters 2305 constructed using a process such as process 3900 (FIG. 39), the same binary-to-analog converter 2305 can be All weighting devices 3310 in the extended decoder 3700 can be included. However, at least some of the weights 3445 of the various weighting devices 3310 will be different. For example, in some implementations, many of the weights 3445 of various weighting devices 3310 will be at or near zero, but some weights 3445 will not be zero. These differences result in each weighting device 3310 generally outputting various net series amplitude events when the same time series of events is input to different weighting devices 3310. . However, this is not always true. This is because, despite the fact that the binary-to-analog converter 2305 and the weight 3445 are different, by chance, different weighting devices 3310 may output the same net series of amplitude events. .

  In decoder 3700, each time series scanner 3315 may scan for time-based code signals using various components. For example, each time series scanner 3315 may include a different reference binary to analog converter 2305. For example, the reference binary to analog converter 2305 in each time series scanner 3315 may be the same as the binary to analog converter 2305 (FIG. 23) of the channel 2340 of the compression encoder 2205.

  Due to the different components in different time series scanners 3315, the result is that different time series scanners 3315 generally differ at different times, even in response to the same net series of amplitude events being received on input 3345. Output series. Further, since there are differences between different time series scanners 3315, even when the same time series is output by different time series scanners 3315 depending on the situation, different time series are provided. Also, different time series scanners 3315 may sometimes produce the same time series in response to different net series amplitude events being received on input 3345.

  Input 3710 of decoder 3700 receives signal 2365. Signal 2365 includes time-series events. Input 3700 distributes signal 2365 to input 3210 of weighting device 3310. Thus, the same single signal 2365 is input to different weighting devices 3310 included in the collection.

  One or more outputs 3215 of each time series scanner 3315 generate a time-based code signal 3725. In this case, information is encoded according to the occurrence timing of the event within the time interval. Each signal 3725 communicates a time-based code to a respective output 3715 of decoder 3700. One or more outputs 3715 provide, for example, a system or medium 140 with a time-based code signal 135 in which information is encoded according to the timing of the occurrence of an event within the time interval.

  FIG. 38 is a schematic diagram illustrating an implementation example of a system capable of encoding and decoding information, that is, a system 3800. System 3800 includes system 2200 (FIG. 22) and system 3200 (FIG. 32). System 3800 can be, for example, a data storage system, a communication system, and / or a data compression system. System 3800 can be used alone or in conjunction with other devices. For example, system 3800 can be used as time-based encoder 25, amplitude weighting component 27, compressor 29, weighting expander 37, amplitude decoder 39, and time-based decoder 41 (FIG. 1A).

  In system 3800, multi-channel time encoder 1105 receives signal 125 and outputs a collection of time-based code signals via output 1115. The time-based code signal is received by one or more inputs 2210 of a compression encoder that compresses the received time-based code signal and outputs the compressed signal 2220 to the system or medium 140 via output 2215. . Extended decoder 3205 receives signal 2365 from system or medium 140 at input 3210. The extended decoder 3205 extends the signal 2365 and further collects a collection of one or more signals whose information is encoded according to the timing of the occurrence of an event within the time interval via one or more outputs 3215. 2100 is output. Multi-channel decoder 2100 receives the signals, decodes these signals and bundles them into output signal 1230 to represent the information in an ordered finite set of discrete numbers.

  FIG. 39 is a flowchart of a process 3900 for building a collection of binary-to-analog converters. For example, process 3900 can be used to build binary-to-analog converter 2305 in weighting device 3310 (FIG. 34). As another example, process 3900 can be used to build a binary-to-analog converter in compression encoder 2205 (FIG. 23). As another example, process 3900 can be used to build a reference binary-to-analog converter in time series scanner 3315 (FIG. 26). Process 3900 may be performed alone or in conjunction with other operations. For example, process 3900 may form part of process 4100 (FIG. 41) for creating an encoder / decoder pair. Process 3900 may be performed by one or more data processing devices.

  As described above, a set of binary-analog converters uses a plurality of time sensitivity parameters to generate individual weights for each individual event in a time series of events based on the timing between events in the input signal. Can do. In some implementations, the weights can be generated based on the timing of previous events in the input signal. At stage 3905, a range of possible values for each time sensitivity parameter is assigned. For example, the time sensitivity parameter can be limited to be within the same normalized range, eg, between 0 and 1.

  Several discrete values within each range are identifiable (stage 3910). In some implementations, the discrete values can be distributed within each range such that they are all separated by a single distance from the nearest value. For example, for a time sensitivity parameter assigned a range of 0 to 1, five distinct values can be identified: 0, 0.25, 0.5, 0.75 and 1. In some implementations, the discrete values are not evenly distributed within each range, but are distributed depending on the application in the binary-to-analog converter. For example, the value of the time sensitivity parameter appearing in the nonlinear function can be distributed according to the position of the time sensitivity parameter in the nonlinear function. In some implementations, the number of discrete values in each range can be selected to be approximately the same as or greater than the number of weighting devices 3310, and the time series scanner 3315 is multi-channel. A pair is formed in the extension decoder 3700 (FIG. 37).

One of the identified discrete values for each parameter used by the binary-to-analog converter is selected (stage 3915). These values can be selected using a random process or a non-random process. In some implementations, a selected value of a given parameter can be excluded for that parameter selection. In effect, this requires that the constructed binary-to-analog converter has different values for each parameter. In these implementations, if there are N discrete values within each range of Y different parameters, several (N ^* Y) combinations of possible values can be selected.

In some implementations, the same value can be selected multiple times for multiple binary-to-analog converters. For example, a binary-to-analog converter can be constructed using an exhaustive combination of identified values. For example, if there are N discrete values within each range of Y different parameters, several (N ^Y ) possible value combinations can be selected.

In some implementations, the same value can be selected multiple times for multiple binary-to-analog converters, but the combination of identified values need not be exhaustive. For example, if there are N discrete values in each range of Y different parameters, a number of possible value combinations greater than (NY) but less than (N ^Y ) can be selected.

  A binary-to-analog converter can be constructed using the selected values (stage 3920). A check can be made to determine if the desired number of binary-to-analog converters have been built (stage 3930). In some implementations, the desired number of binary-to-analog converters can be applied to almost any feasible weighted for a given set of parameters and their ranges with respect to a single input time series for events. The time series will be large enough so that it can be generated by some linear superposition of one or more outputs of the binary-to-analog converter in the collection. If the desired number of binary-to-analog converters has not yet been built, the process returns to select additional parameter values to build an additional binary-to-analog converter (steps 3915 and 3920). If the desired number of binary-to-analog converters has been constructed, the constructed binary-to-analog converter can be used to assemble the device (stage 3935).

  FIG. 40 is a flowchart illustrating a process 4000 for calibrating the weighting device. For example, process 4000 can be used to calibrate a weighting device, such as weighting device 3310 (FIG. 34). Process 4000 can be used alone or in conjunction with other operations. For example, process 4000 may be part of process 4100 (FIG. 41) for creating an encoder / decoder pair. Process 4000 may be performed, for example, on one or more digital data processing devices.

  One or more known time-based code signals may be input to the channel of the multi-channel encoder (stage 4005). For example, the system can input one or more known time-based code signals 135 to the input 2315 (FIG. 23) of the compression encoder 2205. In some implementations, the same time-based code signal 135 can be input to all channels.

  Not only the output signal of the multi-channel encoder, but also the amplitude-weighted time series for each channel in the multi-channel encoder can be similarly identified (stage 4010). In some implementations, the system can store an amplitude weighted time series description and the output of the multi-channel encoder. For example, in some implementations, the system can store an output signal from a multi-channel encoder in data storage device 3100 (FIG. 31).

  The output signal from the multichannel encoder is provided as input to an uncalibrated multichannel extension decoder (step 4015). The multi-channel decoder is not calibrated in that it has not been calibrated to operate with the multi-channel encoder that generated the particular output signal (ie, the multi-channel encoder from which the output signal is received in step 4010). .

  The net series of amplitude events for each channel of the multi-channel extension decoder is identified and compared to the amplitude-weighted time series of the corresponding channel (stage 4020). In some implementations, such a comparison may include a measurement of the amplitude of the event, but for both the net series of amplitude events and the amplitude-weighted time series for a given channel. Event timing may be abandoned. For example, in some implementations, the system can form a series list of event amplitudes in an amplitude weighted time series and a series list of event amplitudes in a net series of amplitude events. . These lists do not describe the timing of events in an amplitude-weighted time series or the net series of amplitude events. However, the difference can be determined by comparing the amplitudes in the list. In general, the result of the comparison is represented for each channel. However, in some implementations, the result of the comparison can be represented by a value that embodies the comparison of multiple channels.

  In some implementations, the net series of amplitude events is compared to the results of mathematical or other operations performed on the amplitude-weighted time series of the corresponding channel. For example, if a weighting device is to be calibrated to multiply a particular channel by 2, it first multiplies that channel's amplitude weighted time series by 2 and compares the result of the multiplication with the net series of amplitude events. be able to. The weights can then be used to perform mathematical or other operations. For example, the weights can be selected to perform one or more of data compression and encryption operations, document processing operations, number processing operations, image processing operations, and signal processing operations. In some implementations, different channels in a single device can use weights to perform various operations.

  It is determined whether the difference between the net series of amplitude events and the corresponding amplitude-weighted time series of the channel is sufficiently small (stage 4025). For example, in some implementations, the system execution process 4000 may compare these differences to thresholds to materialize acceptable levels of differences for each channel. In some implementations, the threshold stringency may be adjustable, for example, by a user, for operation under various circumstances.

  In response to determining that the difference between the net series of amplitude events and the amplitude-weighted time series of the corresponding channel is not sufficiently small, the weight of the weighting device is adjusted (stage 4030). In some implementations, the weight is adjusted for each channel. For example, the system can identify weighted time series weights for events output by individual binary-to-analog converters 320 that most closely resemble amplitude weighted time series. The weights 345 associated with those weighted time series events can be increased. As another example, the system can identify the weights of the weighted time series events output by the individual binary-to-analog converter 320 that are most different from the amplitude weighted time series. The weights 345 associated with those weighted time series events can be reduced.

  In some implementations, the input of the output signal from the multi-channel encoder to the multi-channel decoder can be repeated after incrementally adjusting the weights. The comparison result of the continuous net series of amplitude events and the corresponding channel amplitude weighted time series can be considered as an indication of whether the incremental adjustment was appropriate. In other words, if the net series of amplitude events is very similar to the amplitude-weighted time series for a given channel, the adjustment for that channel can be considered suitable and further adjustments are made . For example, the weight may be further increased or decreased in some cases.

  On the other hand, if the difference between the net series of amplitude events and the amplitude-weighted time series becomes large, adjustments to the channel can be considered disadvantageous and the weights are either restored to their original values or in different directions. Can be changed. For example, the initially increased weight may be decreased and the initially decreased weight may be increased.

  One or more new time-based code signals are selected in response to determining that the difference between the net series of amplitude events and the amplitude-weighted time series of the corresponding channel is not sufficiently small (stage 4035). ). In some implementations, the new time-based code signal can be selected according to the difference between the new time-based code signal and the previous time-based code signal. For example, a new time-based code signal that differs significantly from the previous time-based code can be preferentially selected. In other implementations, a new time-based code signal can be selected at random. The process can continue and one or more new time-based codes can be input into the channel of the multi-channel encoder (stage 4005).

  In response to determining that the difference between the net series of amplitude events and the amplitude-weighted time series of the corresponding channel is sufficiently small, the weight of the weighting device can be fixed (stage 4040). After fixing the weights, the multi-channel decoder is calibrated to operate with the multi-channel encoder that generated the particular output signal (ie, the multi-channel encoder from which the output signal is received in step 4010).

  FIG. 41 is a flowchart illustrating a process 4100 for creating an encoder / decoder pair. Process 4100 can be used alone or in conjunction with other operations. For example, process 4100 may include one or more of process 3900 (FIG. 39) and process 4000 (FIG. 40). Process 4100 may be performed on one or more digital data processing devices.

  Process 4100 begins by building a collection of binary-to-analog converters (stage 4105). The binary-to-analog converter can be constructed in hardware, software, or a combination of hardware and software. The structure of the binary-to-analog converter may include a process such as process 3900 (FIG. 39).

  An encoder using a binary-analog converter is assembled (stage 4110). In some implementations, each channel of the assembled encoder may include a different one of the binary-to-analog converters.

  A collection of time series scanners is assembled using the same binary-to-analog converter (stage 4115). In some implementations, the time series scanners may each include one of the binary-to-analog converters that appear in the encoder channel. The binary-to-analog converter in the time series scanner can function as a reference binary-to-analog converter. Focusing on the correspondence between the binary-analog converter in the encoder channel and the binary-analog converter in each time series scanner, this correspondence can be used, for example, to calibrate the weight of the weighting device.

  A collection of weighting devices is assembled using a collection of binary-to-analog converters (stage 4120). In some implementations, the collection of weighting devices is assembled using the same binary-to-analog converter that is used to assemble the encoder and the collection of time series scanners. In other implementations, a collection of weighting devices is assembled using completely different binary-to-analog converters. In another implementation, a collection of weighting devices is assembled using a combination of the same binary-analog converter and a different binary-analog converter.

  In some implementations, a binary to analog converter (at least initially) may be present in each weighting device. For example, in some implementations, a complete set of constructed binary-to-analog converters exists in each weighting device. As described further below, the weight used to weight the output of the binary-to-analog converter can be calibrated to zero, thereby substantially removing the binary-to-analog converter from the weighting device. . In a hardware implementation, the binary-to-analog converter is one whose output is weighted to zero, but can be physically removed from the weighting device.

  The weights in the weighting device are calibrated (stage 4125). Calibration of weights in the weighting device may include processes such as process 4000 (FIG. 40).

  Process 4100 encodes, compresses, or stores information using a collection of encoders, time series scanners, and a collection of weighting devices (stage 4130).

  Examples of subject matter and operations described herein can be found in digital electronic circuits or in computer software, firmware or hardware that includes the structures disclosed herein and their structural equivalents. Or it can implement | achieve in the combination of 1 or more of these.

  Aspects of the subject matter described in this specification are encoded as one or more computer programs, ie, on a computer storage medium executed by a data processing device or to control operation of the data processing device. Can be implemented as one or more modules of computer program instructions. For example, lines and signals that convey information can be implemented as variables or objects that are passed between computer program components (eg, computer programs, software modules, subroutines, procedures, and functions) to convey information. Detectors, comparators, timers, switches and selectors can be implemented as computer program components that cooperate to perform operations.

  For example, the encoding / compression operation performed by encoder compressor 10 (FIG. 1A) may be performed according to the following instructions:

  Encoding-compression

  As another example, the expansion / decoding operation performed by expander decoder 34 (FIG. 1A) can be implemented according to the following instructions.

  Expansion and decryption

  The computer storage medium may be or be included in a computer readable storage device, a computer readable storage substrate, a random or serial access memory array or device, or a combination of one or more of these. A computer storage medium may also be or be included in one or more separate physical components or media (eg, multiple CDs, disks or other storage devices).

  The operations described herein may be implemented as operations performed by a data processing device on data stored in one or more computer readable storage devices or received from other sources. .

  The term “data processing apparatus” refers to any type of apparatus, device, and machine for processing data, including, by way of example, a programmable processor, a computer, a system on a chip, or a plurality of elements or combinations thereof. Is included. The device may include a special purpose logic circuit such as a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). In addition to hardware, the device also creates code that creates an execution environment for the computer program, eg, processor firmware, protocol stack, database management system, operating system, cross-platform runtime environment, virtual machine, or any of them Code comprising one or more combinations. Devices and execution environments can implement a variety of different computing model infrastructures such as web services, distributed computing and grid computing infrastructure.

  Computer programs (also known as programs, software, software applications, scripts or code) can be written in any form of programming language, including compiled or translated languages, declarative or procedural languages, stand-alone programs Or as a module, it can be deployed in any form including components, subroutines, objects or other units suitable for use in a computing environment. The computer program may correspond to a file in the file system, but need not correspond. A program can contain other programs or data (eg, marks) in a single file or multiple associated files (eg, files that store one or more modules, subprograms, or portions of code) dedicated to the program. One or more scripts stored in the up-language document) can be stored in a part of the file. A computer program runs on one computer or deploys to run on multiple computers located at one site or distributed across multiple sites and interconnected by a communications network Can do.

  The processes and logic flows described herein perform operations by one or more programmable processors executing one or more computer programs to operate on input data and generate output. Can be executed by. The process and logic flow can also be performed by an application specific logic circuit such as an FPGA (Field Programmable Gate Array) or ASIC (Application Specific IC), and the device can also be an application specific logic circuit such as an FPGA or ASIC. Can be realized.

  Processors suitable for executing computer programs that perform operations in the processes described herein include, by way of example, both general purpose and special purpose microprocessors, and any type of digital It also includes one or more processors of the computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. The essential elements of a computer correspond to a processor for performing operations according to instructions and one or more memory elements for storing instructions and data. Generally, a computer also includes one or more mass storage devices for storing data, such as a magnetic disk, magneto-optical disk or optical disk, or receives or mass data from these mass storage devices. It will be operably connected to send data to the storage device or send and receive data to and from the mass storage device. However, the computer need not include such a device. Further, a computer may be another device, such as a mobile phone, a personal digital assistant (PDA), a portable audio or video device, a game console, a global positioning system (GPS), to name a few. System) receiver, or portable storage device (eg, a universal serial bus (USB) flash drive). Suitable devices for storing computer program instructions include, by way of example, semiconductor storage devices such as EPROM, EEPROM and flash memory devices, magnetic disks such as internal hard disks or removable disks, magneto-optical disks, and CD-ROM and DVD- Includes all forms of non-volatile memory, media and memory elements, including ROM disks. The processor and memory may be supplemented by, or incorporated in, special purpose logic circuitry.

  This specification includes details of many specific implementations, but these should not be construed as limitations on the scope of the invention or what it may claim, but rather specific implementations of the invention. It should be interpreted as a description of features specific to the example. Certain features described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Further, although features have been described above as operating in several combinations and claimed at the outset as such, one or more features resulting from the claimed combination may be excluded from the combination in some cases. The claimed combinations may be directed to sub-combinations or variations of sub-combinations.

  Similarly, operations are described in a particular order in the drawings, such that such actions are performed in the particular order shown or sequentially to achieve the desired result. Or, it should not be understood as necessary so that all illustrated operations are performed. Under some circumstances, multitasking and parallel processing may be advantageous. Furthermore, the selection of the various system components in the embodiments described above should not be understood as requiring such a selection in all embodiments, and the program components and systems described above are generally a single software. It should be understood that it can be integrated into a product and packaged into multiple software products.

Embodiments A method, system, and apparatus for encoding and decoding information described herein, including a computer program encoded on a computer storage medium, is provided in one or more of the following embodiments. It can be embodied.

  Embodiment 1 A method for encoding information in an encoder by harmonizing digital data processing, statistical processing, and pattern recognition provided in a neural processing component is a method for generating a signal representing information using a collection of discrete numbers. Receiving and converting the received signal into a time-based code by an encoder, wherein the time-based code is divided into time intervals, each of the time-based code time intervals corresponding to a number in the received signal Each of the received signal first state numbers is represented as an event occurring at a first time within a corresponding time interval of the time-based code, and each of the received signal second state numbers is time Represented as an event occurring at a second time within a corresponding time interval of the base code, the first time being the second Is identifiable from time, all digits of the state in the received signal is represented by events in the time-based code, said method further comprising the step of outputting the time-based code to the neural processing elements. Embodiment 2: In the method of Embodiment 1, the received signal is a binary representation of information, and the number of the received signal includes bits in binary representation. Example 3: In any of the methods of Examples 1 and 2, each binary state first state number is represented as an event occurring in the middle of a corresponding time interval of a time-based code; Each binary representation of the second state number is represented as an event that occurs at one of the beginning or end of the corresponding time interval of the time-based code. Example 4: In any of the methods of Examples 1-3, an event representing a number in the first state is indistinguishable from an event representing a number in the second state, except for the time of occurrence. is there. Example 5: In any of the methods of Examples 1-4, each event includes a pair of transitions from low to high and from high to low. Example 6: In any of the methods of Examples 1-5, the event is a binary number. Example 7: In any of the methods of Examples 1-6, the step of outputting the time-based code comprises converting the time-based code into a neural processing component implemented using a wet neural component. Output step, and the characteristics of the time-based code can be adjusted to match the wet neural component. Example 8: In any of the methods of Examples 1-7, converting the received signal to a time-based code includes adding a start header to the time-based code, It distinguishes the start of the time-based code and corresponds to the header in the received signal. Example 9: In any of the methods of Examples 1-8, converting the received signal to a time-based code includes adding a stop footer to the time-based code, the stop footer being a time It distinguishes the end of the base code and corresponds to the footer in the received signal. Example 10: In any of the methods of Examples 1-9, the time interval is the entire single period. Example 11: In any of the methods of Examples 1-10, the time intervals are sequentially ordered in the same sequence as the corresponding numbers in the received signal. Embodiment 12: In any of the embodiments 1-11, the step of converting the received signal into a time-based code is an event that occurs at a first time for all digits of the first state of the received signal. And converting all numbers in the second state, which are binary representations, to events occurring at the second time.

  Embodiment 13: A system for reconciling digital data processing, statistical processing, and pattern recognition provided in a neural processing component, an input for receiving a signal representing information using a collection of discrete numbers; An encoder that encodes the received signal, the encoder configured to translate a numeric state in the received signal into a time-based code, and a state detector configured to detect a numeric state in the received signal The time-based code includes a collection of time intervals each assigned to a respective number in the received signal, each of the time intervals includes an event, and the timing of the event within each of the time intervals is Characterize the status of each assigned number, and the system further separates the time-based code Comprising an output for providing a system or apparatus, and a connection neural processing component to receive a time-based code. Example 14 In the system of Example 13, the neural processing component is implemented using a wet neural component, and the characteristics of the time-based code are adjusted to match the wet neural component. Example 15: In any of the systems of Examples 13 and 14, the received signal includes a binary signal and the state detector includes a bit detector configured to detect the state of the bits in the binary signal. . Example 16: In any of the systems of Examples 13-15, the translator includes an event generator, and the event generator is configured and connected to generate a time-based code event. Example 17: In the system of Example 16, the event generator includes a pulse generator, and the shape of the pulse representing the first state is indistinguishable from the shape of the pulse representing the second state. Example 18 In the system of Example 16, the event generator is further configured to distinguish the start of a time-based code and generate a header event corresponding to the header in the received signal. Example 19: The system of any of Examples 13-18 further includes a start / stop detector configured and connected to detect the beginning and end of the received signal. Example 20: The system of any of Examples 13-19 further includes an interval timing component that distinguishes the passage of time intervals in the time-based code. Example 21: In the system of Example 20, the interval timing component is configured to distinguish the course of a single time interval.

  Embodiment 22: A method for decoding a time-based code signal by reconciling statistical processing with a pattern recognition function provided by a neural processing component and a digital data processing device, the time from the neural processing device Receiving a base code signal at a decoder, wherein the time based code signal is divided into time intervals, each time interval of the time based code signal includes an event, and the timing of the event within the time interval is: Representing the information content of a time-based code signal, the method further comprising the step of detecting the timing of an event within the time interval and a signal representing the information represented by the time-based code signal using a collection of discrete digits Output. Example 23: The method of Example 22 further includes converting events occurring within a first time range of the time-based code signal interval to discrete numbers of a first state in the output signal; Converting events occurring within a second time range of the code signal interval to discrete numbers of a second state in the output signal. Example 24: In the method of Example 23, the output signal comprises a binary signal. Example 25: The method of any of Examples 22-24 further includes detecting the start of the data content of the time-based code signal. Example 26: In the method of Example 25, detecting the start of data content includes detecting a header event of a time-based code signal. Example 27: The method of Example 26 further includes determining a time between a header event and a first event after the header event. Example 28: The method of Example 25 further includes synchronizing the detection of the time at which an event occurs within the time interval with the start of the data content of the time-based code signal. Example 29: In any of the methods of Examples 22-28, the step of receiving a time-based code signal comprises receiving a time-based code signal from a neural processor implemented using a wet neural component. Receiving. Example 30: The method of any of Examples 22-29 further includes receiving a second time-based code signal at a second decoder, wherein the second time-based code signal is at a time interval. Each of the time intervals of the divided second time-based code signal includes an event, the timing of the event within the time interval represents the information content of the second time-based code signal, and the method further includes: Detecting a timing of an event within the time interval in the two decoders, and outputting a signal representing information represented by the second time-based code signal from the second decoder using the second set of discrete numbers. And aggregating a set of discrete numbers and a second set of discrete numbers into a second signal. Example 31 In any of the methods of Examples 22-30, the time-based code signal event has an indistinguishable shape.

  Example 32: A system for decoding statistical processing and a pattern recognition function provided by a neural processing component and a digital data processing device and decoding a time-based code signal, the neural processing component; A neural processing component is connected and includes an input for receiving a time-based code signal, the time-based code signal is divided into time intervals, each time interval of the time-based code signal includes an event, and the time interval The timing of the event in the information represents the information content of the time-based code signal, and the system further includes an event detector configured to detect the timing of the event within the time interval of the time-based code signal, and a time base A collection of numbers that indicate the timing of events within the time interval Including and translators configured to translate the state, and configured to provide a signal containing the numeric output. Example 33: In the system of Example 32, the translator includes a collection of comparators that receive the detected timing of the event and compare the timing of the detected event with a time range within the interval. Example 34: In any of the systems of Examples 32 and 33, the neural processing component is implemented using a wet neural component. Example 35: In any system of Examples 32-34, the translator is configured to translate events within a time interval of a time-based code into a binary signal. Example 36: In any of the systems of Examples 32-35, the event detector includes a pulse detector. Example 37: The system of any of Examples 32-36 further includes an interval timing component that distinguishes the passage of time intervals in a time-based code. Example 38: In the system of Example 37, the interval timing component includes a comparator configured to compare the time count to a reference. Example 39: In the system of Example 38, the criteria are constant and the time intervals are all the same single length. Example 40: The system of Example 37 further includes a start detector configured to detect the start of a time-based code signal. Example 41: In any of the systems of Examples 32-40, the start detector is coupled to the interval timing component and provides a reset signal to the interval timing component, the reset signal distinguishing the passage of time intervals. To reset.

  Thus, particular embodiments of the present invention have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve desirable results. In addition, the processes illustrated in the accompanying drawings do not necessarily require the particular order shown or sequential order to achieve the desired result. In some implementations, multitasking and parallel processing may be advantageous.

Claims (59)

A method,
Receiving a time-based code signal at an input, wherein the time-based code signal is divided into time intervals, each time interval of the time-based code signal includes an event, and the occurrence of the event within the interval is informational And the method further includes:
Weighting the amplitude of at least some of the events in the time-based code signal as a function of the timing of other events in the time-based code signal to generate an amplitude sequence including the weighted events; ,
Outputting an amplitude weighted time-based code.   The method of claim 1, wherein weighting the event amplitude does not add new information to the time-based code signal.   3. A method according to claim 1 or 2, wherein the step of weighting the amplitude of the input event comprises the step of weighting the first input event as a function of the weighted amplitude of the immediately preceding input event.   The step of weighting the amplitude of the input event comprises the step of weighting the amplitude of the first input event by multiplying the time elapsed from the directly preceding input event having a time sensitivity parameter. The method of crab.   5. A method according to any preceding claim, wherein the step of weighting the amplitude of the input event further comprises the step of weighting the amplitude of the input event as a function of a random variable.   6. A method according to any preceding claim, further comprising the step of resetting the weighting of the event amplitude to a known state in response to a footer event in the time-based code. A system,
A time encoder configured to encode the information into a collection of time-based code signals, each of the time-based code signals being divided into time intervals, each of the time intervals including an event, The occurrence is timed to represent information, and the system further includes:
A compression encoder, wherein the compression encoder includes a collection of converter devices, each of the converter devices receiving an amplitude of an event in a respective time-based code signal, and other event features in the respective time-based code. A system connected and configured to weight the amplitude of the received event as a function of.   The system of claim 7, wherein the encoder includes a reset mechanism, wherein the reset mechanism is configured to reset the weighting on the amplitude of the event in the converter device to a known state.   9. A system according to claim 7 or 8, wherein the encoder comprises an integrator connected and configured to integrate an amplitude weighted time-based code into the signal.   The system according to any of claims 7 to 9, wherein the integrator is configured to integrate the amplitude-weighted time-based code into a one-dimensional signal.   11. A system according to any of claims 7 to 10, wherein the integrator is configured to integrate an amplitude weighted time-based code into the signal, and several time spans between events within a unit time are Poisson distributed. .   12. A system according to any of claims 7 to 11, wherein the converter device weighting does not add new information to the time-based code signal.   13. A system according to any of claims 7 to 12, wherein the weighting of each event is a non-linear function of the time of occurrence of a preceding event in the time-based code signal. A method realized by a machine,
Receiving at the input a collection of amplitude weighted sequences of events, the amplitude weights being a function of the timing of other events in each sequence of events, the method further comprising:
Integrating the interactions between the time sequences to generate an integral representing those interactions;
Adjusting the threshold according to the number of events in an amplitude weighted sequence of events;
Outputting an output event at the output in response to the integration reaching a threshold, whereby the timing of each output event indicates the timing of the integration reaching a dynamic threshold. The number of input events in each amplitude-weighted sequence of events is the same,
The method of claim 14, further comprising adjusting a dynamic threshold such that the number of output events is equal to the number of input events.   16. A method according to claim 14 or 15, wherein the output events are indistinguishable from each other except for the timing of the output events.   17. A method according to any of claims 14 to 16, wherein each of the amplitude weighted sequences of events starts at the same time.   18. A method according to any of claims 14 to 17, wherein outputting an output event comprises transitioning from low to high and from high to low.   19. A method according to any of claims 14 to 18 in combination with any of methods 1 to 6. A system,
Includes integrators connected and configured to receive a collection of amplitude-weighted sequences of events, where amplitude weights are a function of the timing of other events in each sequence of events, and the integrator receives a signal that characterizes the integral A comparator connected to the comparator, the comparator comprising:
Compare the signal characterizing the integral with the dynamic threshold,
A system configured to output an output event and reset a comparison between the signal characterizing the integral and the dynamic threshold in response to the signal characterizing the integral reaching the dynamic threshold.   The system of claim 20, wherein the integrator further includes an event counter configured to count the number of input events in a time sequence.   The integrator further includes a threshold adjuster connected to receive a count of input events in a time sequence, the threshold adjuster dynamically depending on the count of the number of input events in the time sequence. 22. A system according to claim 20 or 21, connected and configured to adjust a threshold.   23. A system according to any of claims 20 to 22, wherein the output events are indistinguishable from each other except for the timing of the output events.   24. A system according to any of claims 20 to 23, further comprising a transmitter configured to transmit an output event output by the comparator.   25. A system according to any of claims 20 to 24, further comprising a data writer configured to write output events to a data storage device.   26. A system according to any of claims 20 to 25, in combination with any of systems 7 to 13.   A data storage device that includes a detectable physical representation that encodes information, the physical representation being spaced apart according to an encoding scheme, thereby encoding an interval between physical representations A data storage device representing the contents of the information.   28. The data storage device according to claim 27, wherein the interval between physical representations matches a predetermined probability distribution.   29. A data storage device according to claim 28, wherein the probability distribution is asymmetric and sloped.   30. The data storage device according to claim 29, wherein the probability distribution is inclined to the left of the center of the probability distribution.   The data storage device according to claim 30, wherein the standard deviation of the probability distribution is approximately equal to the mean square root of the probability distribution.   32. The data storage device according to claim 31, wherein the probability distribution is a Poisson distribution.   33. A data storage device according to any of claims 27 to 32, wherein the physical representations are indistinguishable from each other, except for the interval between the physical representations.   34. A data storage device according to any of claims 27 to 33, wherein the number of physical representations is equal to the number of bits stored in the data storage device.   Each physical representation includes a pair of transitions: a first transition from a first state to a second state, and a second transition from the second state back to the first state. Item 35. The data storage device according to any one of Items 27 to 34.   36. A data storage device according to any of claims 27 to 35, wherein the interval between physical representations is scaled to the time between output events output by the system according to any of claims 20 to 26. A method,
Receiving a time series of events, the events occur at non-uniform intervals in the input time series, and the information is encoded according to the timing of the input events in the input time series, the method further comprising:
Generating a plurality of collections of weights, wherein each weight in each collection corresponds to a respective input event in the input time series, and the weight in each collection is the timing of the plurality of events in the received time series And the method further comprises
Outputting a collection of weights.   38. The method of claim 37, wherein an interval between events in the received time series scales to an interval between physical representations of the data storage device according to any of claims 27-36. The method further includes multiplying an event in the input time series by an amplitude weight;
Converting the input time series into an amplitude weighted collection of weighted events;
Outputting a collection of weights, wherein said outputting includes outputting an amplitude-weighted time series collection of weighted events, at least some of the weights in each collection being non- 39. A method according to claim 37 or 38, wherein the method is different for each zero input time series.   40. A method according to any of claims 37 to 39, wherein outputting the collection of weights comprises outputting a list of weights without time information.   The step of generating a collection of weights includes generating a first weight corresponding to a first event in the time series as a non-linear function of a timing of an event preceding the first event in the time series. The method according to any one of 37 to 40.   42. A method according to any of claims 37 to 41, wherein the method further comprises calibrating the generation of a collection of amplitude weights. Resetting the generation of amplitude weights to a known state;
43. The method according to any of claims 37 to 42, further comprising receiving a second subsequent input time series.   44. A method according to any of claims 37 to 43, in combination with a method according to any of claims 1 to 6 or 14 to 19. A decoder device,
Including inputs connectable to receive an input time series of events, events in the input time series occur at non-uniform intervals, information is encoded according to the timing of the input events within the input time series, and the decoder device further includes ,
Each comprising a collection of converter devices configured to inherently convert an input time series into a collection of amplitudes, each amplitude being a function of the timing of a plurality of input events in the input time series, wherein the decoder device comprises: further,
Including a collection of outputs, each connectable to output a respective sequence of amplitudes, with different amplitudes, but the number of amplitudes is the same as the number of events in the input time series;
A decoder device, wherein at least some of the amplitudes generated by the different weight generators are different for each non-zero input time series.   45. The decoder of claim 44, further comprising a reset mechanism, wherein the reset mechanism is configured to reset the converter device to a known state. A collection of data storage devices for storing a collection of weights;
Each of the multipliers is connected and configured to multiply one of the amplitude collections by a respective weight;
46. A decoder according to claim 44 or 45, comprising an adder configured to sum the product of the amplitude collection and the respective second weight.   Each of the converter devices is a network of signal processors interconnected by one or more processing junctions that dynamically adjust the reaction intensity according to a temporal pattern of events in the input time series to generate a collection of amplitudes 48. A decoder according to any of claims 44 to 47, comprising:   49. A decoder according to any of claims 44 to 48, in combination with any of claims 7 to 13 or 20 to 26. A device,
An input connectable to receive an input string of amplitude;
A comparator connected to compare the amplitude input string with the second amplitude column to generate a signal indicative of the difference between the amplitude input string and the second amplitude string;
A converter device configured to convert a time series into a second column of amplitudes, each amplitude in the second column being a function of the timing of a plurality of events in the time series input to the converter device The device further comprises:
A permuter configured to rearrange the time series input to the converter device;
An apparatus comprising: an output connectable to output a time series input to a converter apparatus in response to a signal indicative of a difference between an amplitude input string and a second string of amplitudes below a threshold value.   The converter device includes a signal processor interconnected by one or more processing junctions that dynamically adjust the reaction intensity according to a temporal pattern of events in the input time series to generate a second column of amplitudes. 51. The apparatus of claim 50, comprising a network.   52. The apparatus of claim 50 or 51, further comprising a buffer for storing an amplitude input string.   53. The apparatus according to any of claims 50 to 52, further comprising a second buffer for storing a second column of amplitudes.   54. The comparator according to any of claims 50 to 53, wherein the comparators comprise a collection of comparators, each comparator being connected to compare a single amplitude of the input column with a single amplitude of the second column of amplitudes. Equipment.   55. Apparatus according to any of claims 50 to 54, in combination with any of claims 44 to 48, 7 to 13 or 20 to 26. A method,
Receiving an input sequence of amplitudes;
Comparing the amplitude of the input string with the amplitude of the second column of amplitudes to generate a signal indicative of the difference;
Rearranging a time series input to the device in response to the difference signal, wherein the device generates a second column of amplitudes in response to the input time series.   57. The method of claim 56, further comprising outputting a time series in response to the difference signal below a threshold value.   58. The method of claim 56 or 57, further comprising storing the input column amplitude and the second column amplitude in one or more buffers for comparison.   59. A method according to any of claims 56 to 58, in combination with a method according to any of claims 37 to 44, 1 to 6 or 14 to 19.