ES2823253T3 - Information encoding and decoding - Google Patents

Abstract

An encoding system implemented in digital electronic circuits or in computer software and hardware combinations, the encoding system comprising: a temporal encoder (105) configured to encode information in a set of time-function code signals (135), each including one of the time-function code signals (135) time intervals (320, 1420, 2905) and each of the time intervals (320, 1420, 2905) including one event (325, 1425, 2910), occurrences of the events (325, 1425, 2910) within the time intervals (320, 1420, 2905) that are synchronized to represent the information; and a compressor encoder (2205) comprising a set of converter devices (2305) each connected and configured to receive and weight the amplitudes of the events (325, 1425, 2910) in a respective one of the time-based code signals ( 135) as a function of the timing of other events (325, 1425, 2910) in the respective time-function code signal, and providing a signal (2345) that includes the amplitude-weighted events at relative times corresponding to the timing of the unweighted events within the respective time-based code signal.

Description

DESCRIPTION

Information encoding and decoding

BACKGROUND OF THE INVENTION

This specification refers to the encoding and decoding of information.

An encoder is a device that converts information from a first representation to a second representation. Encoders can be included in many different systems and devices, including data communication devices, data storage devices, data compression devices, data encryption devices, and combinations of these and other devices. An encoder can be paired with a decoder that can reconstruct the information. The encoded and decoded information can be communicated in signals and / or stored on a data storage device.

Biological neurons and other biological neural systems can encode information and communicate using electrochemical signaling. For example, biological neural systems can encode information in action potentials of approximately the same amplitude. Biological neural systems include synapses that act as electrochemical transducers that convert electrochemical signals into changes in electrical conductance. Even a single neuron can receive several thousand electrochemical signals as inputs to its branches (called "dendrites"). These inputs cause voltage changes across a cell membrane that fuse in a time-dependent manner. This fusion of inputs follows passive (linear), active (non-linear), wire (decreasing over time), and electrochemical (diffusion) laws. In certain circumstances, these inputs can merge into a train of successive action potentials.

SUMMARY

This specification describes technologies related to the encoding and decoding of information.

In general, an innovative aspect of the subject matter described in this specification can be incorporated into information encoding methods in an encoder that include the actions of receiving a signal representing information using a set of discrete digits, converting, by an encoder, the signal received in a time-based code and providing said time-based code. The time function code is divided into time intervals. Each of the time intervals of the time function code corresponds to one digit in the received signal. Each digit of a first state of the received signal is expressed as an event that occurs for the first time within it.

The Wikipedia entry for "Pulse Position Modulation" describes that Pulse Position Modulation (PPM) is a form of signal modulation where M message bits are encoded by transmitting a single pulse in one of 2M possible time offsets. .

US 2002/0190881 discloses a pulse position modulation signal with variable amplitude, whereby the amplitude encodes additional information.

The paper entitled "Reinforced learning through peak timing-dependent modulation of synaptic plasticity" by R. Florian describes that peak timing-dependent modulation of plasticity by a global reward signal leads to reinforcement learning .

SUMMARY OF THE INVENTION

This specification describes technologies related to the encoding and decoding of information.

An innovative aspect of the subject matter described in this specification can be embodied in an encoder system implemented in digital electronic circuits or in combinations of computer software and hardware, the encoder system comprising: a temporary encoder configured to encode information in a set. of code signals as a function of time, each of the code signals as a function of time including time intervals and in turn, each of the time intervals includes an event, occurrences of the events within the time intervals specified they synchronize to represent information; and a compressor encoder comprising a set of converter devices, each of which is connected and configured to receive and weight the amplitudes of the events in a respective one of the time-based code signals as a function of synchronization of other events in the respective time-function code signal, and providing a signal that includes the amplitude-weighted events at relative times corresponding to the timing of the unweighted events within the respective time-function code signal.

Another innovative aspect of the subject matter described in this specification can be embodied in a decoding device implemented in digital electronic circuits or in combinations of software and hardware. computer, the decoding device comprising: a connectable input to receive a time series of input events, the events occurring in the input time series at non-uniform intervals, the synchronization of the input events being within the encoding information of the input time series; a set of weight converting devices each configured to uniquely convert the input time series to a set of amplitudes, each amplitude being a function of the timing of multiple input events in the input time series; and a set of outputs, each included in a respective connectable weighting generator converter device to provide a respective series of amplitudes, wherein the amplitudes vary but the number of amplitudes is the same as the number of events in the time series of input, where at least some of the amplitudes generated by different weighting converter devices differ for each non-zero input time series.

Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and in the following description. Other features, aspects, and advantages of the matter will be apparent from the description, drawings, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1A is a schematic representation of an encoder / decoder system.

Figure 1B is a flow chart of a process for encoding and decoding information.

Figure 2A is a schematic representation of a system where information can be encoded.

Figure 2B is a schematic representation of an implementation of a time encoder.

Figure 3 is a schematic representation of a time encoding process.

Figure 4 is a schematic representation of another implementation of a time encoder.

Figure 5 is a schematic representation of time encoding with a time encoder that detects the start and end of data transmission in a signal.

Figure 6 is a schematic representation of another implementation of a time encoder.

Figure 7 is a schematic representation of the encoding of a header at the beginning of data transmission in a signal.

Figure 8 is a schematic representation of another implementation of a time encoder.

Figure 9 is a schematic representation of the temporal encoding of a signal that includes more than two states.

Figure 10 is a schematic representation of one implementation of a system where information can be encoded.

Figure 11 is a schematic representation of an implementation of a multichannel encoder.

Figure 12 is a schematic representation of a system where information can be encoded, compressed and stored / transmitted and then accessed / received, decoded and decompressed.

Figure 13 is a schematic representation of a decoder implementation.

Figure 14 is a schematic representation of a signal decoding process where the information is encoded by the timing of the occurrence of events within time intervals.

Figure 15 is a schematic representation of another implementation of a decoder.

Figure 16 is a schematic representation of the decoding of a signal where the information is encoded by synchronizing the occurrence of events within time intervals with a decoder that detects the start and end of data transmission in a signal. .

Figures 17 and 18 are schematic representations of other decoder implementations.

Figure 19 is a schematic representation of the decoding of a signal where the information is encoded by the timing of the occurrence of events within time intervals in a signal that includes more than two states.

Figure 20 is a schematic representation of a decoding system implementation.

Figure 21 is a schematic representation of a multichannel decoder system.

Figure 22 is a schematic representation of a system implementation where information can be encoded.

Figure 23 is a schematic representation of an implementation of a compressor encoder.

Figures 24, 25, 26, 27 are schematic representations related to different integrator implementations.

Figure 28 is a schematic representation of a binary to analog converter.

Figure 29 is a schematic representation of the weighting of the amplitude of individual events in a time series of events as a function of the timing of other events in the time series.

Figure 30 is a schematic representation of an implementation of a signal that can be provided from a compressor encoder.

Figure 31 is a schematic representation of a data storage device.

Figure 32 is a schematic representation of a system implementation where information can be decoded.

Figure 33 is a schematic representation of an implementation of an expander decoder.

Figure 34 is a schematic representation of a weighting device.

Figure 35 is a schematic representation of the weighting of the amplitude of individual events in a time series of events as a function of the timing of other events in the time series.

Figure 36 is a schematic representation of a time series scanner.

Figure 37 is a schematic representation of an expander decoder.

Figure 38 is a schematic representation of a system implementation where information can be encoded and decoded.

Figure 39 is a flow diagram of a process for constructing a set of binary to analog converters. Figure 40 is a flow chart of a process for calibrating a weighting device.

Figure 41 is a flow chart of a process for creating an encoder / decoder pair.

Like reference numerals and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION OF THE INVENTION

Figure 1A is a schematic representation of an encoder / decoder system 3. The encoder / decoder system 3 is a set of components for encoding and decoding information. The encoder / decoder system 3 can be, for example, a data communication system, a data storage system, a data compression system, a data encryption system or a combination of these or other systems. An encoder can be paired with a decoder that can reconstruct the information. The encoded and decoded information can be communicated in signals and / or stored on a data storage device.

The encoder / decoder system 3 includes an encoder transmitter system 6 and a decoder receiver system 9. The encoder transmitter system 6 includes an input 8, an encoder-compressor 10, a transmitter 12 and an output 14. The input 8 of the encoder transmitter system 6 can be connected to receive information in a signal 21. Input 8 and output 14 are physical structures through which signals are received and transferred, respectively, from encoder transmitter system 6. Signal 21 includes information. The encoder-compressor 10 is a component that encodes and compresses at least part of the information of the signal 21.

The encoder-compressor 10 includes a status encoder 23, a time function encoder 25, an amplitude weighting component 27, and a compressor 29. The status encoder 23 is a component that encodes at least part of the signal information. 21 into a signal 24 that represents information in a set of discrete digits. Digits can represent information using different states. For example, signal 24 can represent information in binary digits or bits (that is, using a pair of states) or in decimal digits (that is, using ten states). Status encoder 23 is connected to provide signal 24 to time function encoder 25.

The time function encoder 25 is a component that encodes the signal 24 into a time function code 26 wherein the timing of the events within the intervals represents information. One or both of the state encoder 23 and the time function encoder 25 may include a segmenter that splits a single signal into a set of smaller units. As a consequence of this division, the amplitude weighting component 27 receives a set of time-function codes 26. The time-function encoder 25 is connected to provide the time-function code set 26 to the amplitude weighting component 27 .

The amplitude weighting component 27 is a component that is configured to weight the amplitudes of the events within each time-function code 26 in accordance with the timing of at least some of the other events in that time-function code 26. In some implementations, the amplitude weighting component 27 may weight the amplitudes of the events according to the timing of the predecessor events. The amplitude weighting component 27 does not need to add new information to the time-function codes 26, but can represent at least part of the existing information in each time-function code in another dimension, namely the amplitudes of the events . The amplitude weighting component 27 is connected to provide a set of amplitude weighted time function codes 28 to the compressor 29.

Compressor 29 is a component that is configured to compress a set of amplitude-weighted time-function codes 28. Compressor 29 can compress the amplitude-weighted time-function codes 28 by integrating them to generate a one-dimensional code 31. One-dimensional code 31 can represent at least part of the information in amplitude-weighted time codes 28 in a single dimension. For example, one-dimensional code 31 can represent information using event synchronization. In some implementations, the integration may be a non-linear integration. Compressor 29 is connected to provide a one-dimensional code 31 to transmitter 12.

Transmitter 12 is configured to transmit a one-dimensional code 31 in a signal 30 that can be stored or otherwise processed. For example, signal 30 can be stored in a memory structure (not illustrated). Alternatively, signal 30 can be transmitted to a receiving device that decodes the signal. In the example shown, signal 30 is transported from output 14 of encoder transmitter system 6 to input 16 of decoder receiver system 9.

The decoding receiver system 9 includes an input 16, a receiver 32, an expander-decoder 34 and an output 20. The input 16 of the decoding receiver system 9 can be connected to receive the signal 30. The signal 30 includes the one-dimensional code 31 The input 16 and the output 20 are physical structures through which signals are received and transferred respectively from the decoding receiver system 9. The receiver 32 is configured to receive the signal 30 and transmit the one-dimensional code 31 to the expander. -decoder 34.

The expander-decoder 34 is a component that expands and decodes at least part of the information in the signal 29. The expander-decoder 34 includes a weighting expander 37, an amplitude decoder 39, a time-function code decoder 41 and a state decoder 42. Weight expander 37 is a component that is configured to expand one-dimensional code 31 into one or more sets of weighting weights 43. Sets of weighting weights can be generated in accordance with the dimension used to represent information on signal 29 (eg, timing of events on signal 29). For example, weighting weights can be generated for each event in signal 29 in accordance with the timing of the predecessor events within signal 29. Each event in the one-dimensional code can be associated with a single weighting weight in each set of weights. . In some implementations, the weighting expander 37 weights the amplitudes of each event using the weighting weights and generates amplitude-weighted versions of the one-dimensional code 31 as sets of weighting weights 43. In other implementations, the weighting expander 37 generates ordered lists of weight weights that discard the dimension used to represent information in signal 29 (for example, discard synchronization of events in signal 29) as sets of weight weights 43. Weight expander 37 is connected to transporting sets of weighting weights 43 to amplitude decoder 39.

Amplitude decoder 39 is a component that is configured to decode sets of weighting weights 43 into a set of one or more time-function codes 45 wherein timing of events within intervals represents information. The amplitude decoder 39 is connected to transmit one or more time-function codes 45 to the time-function code decoder 41. The time-function code decoder 41 is a component that decodes at least part of the information in the one or more codes function of time 45 in one or more signals 47 that represent information in a set of states. For example, signals 47 can represent information in binary (ie, using a pair of discrete states) or in decimal (ie, using ten discrete states). The time function code decoder 41 is connected to transmit signals 47 to the status decoder 42. The status decoder 42 is a component that is configured to decode signals 47 that represent information in a set of digits in a signal 50. The signal 50 may include at least part of the information included in signal 21.

One or more of the amplitude decoder 39, the time function code decoder 41, and the status decoder 42 may include an adder that assembles a set of smaller digits into a set of larger digits. For example, in some implementations, the amplitude decoder 39 may include a time-function code adder that assembles multiple time-function codes into a single time-function code 45. By way of another example, in some implementations , the time function code decoder 41 may include an adder that assembles multiple signals representing information in a set of discrete digits into a single signal 47 representing information in a set of discrete digits. By way of another example, in some implementations, the state decoder 42 may include an adder that assembles signals into a single signal 50.

Figure 1B is a flow diagram of a process 70 for encoding and decoding information. Process 70 can be performed in isolation or in conjunction with other activities. For example, process 70 can be performed at step 4130 in process 4100 (Figure 41). Process 3900 can be performed by an encoder / decoder system, such as encoder / decoder system 3 (Figure 1A).

In process 70, the data is encoded in a set of digits (step 72) and the digits are encoded in a code as a function of time (step 74). The function-of-time code represents information that is used by the synchronization of events within intervals. The amplitudes of the events within the time function code are weighted according to the timing of other events in the time function code (step 76). For example, the events can be weighted according to the timing of the predecessor events in that code as a function of time. Amplitude weighting does not need to add new information to the code as a function of time, but can represent at least some of the existing information in the code as a function of time in another dimension, namely the amplitudes of the events.

The amplitude-weighted time-function codes can be compressed into a one-dimensional code (step 78). The one-dimensional code may represent at least part of the information in amplitude-weighted time-function codes in a single dimension, for example, using event synchronization.

In a receiving device, the one-dimensional code can be expanded into sets of amplitudes (step 80). Each event in the one-dimensional code can be associated with a single weighting weight in each set of weights. In some implementations, the sets of amplitudes can be a list of amplitudes without any temporal information. In other implementations, the one-dimensional code itself may be weighted by multiple sets of amplitudes to provide multiple amplitude-weighted versions of the one-dimensional code (beforehand).

The amplitudes can be decoded into a time-function code (step 82) which in turn can be decoded into one or more signals representing information in a set of digits (step 84). The one or more signals representing information in one set of digits can themselves be decoded into another representation (step 86).

Temporal encoder

Figure 2A is a schematic representation of a system 100 where information can be encoded. The system 100 includes a time encoder 105 that includes an input 110 and an output 115. The input 110 and output 115 are physical structures through which signals are respectively received and transferred out of the time encoder 105. The time encoder 105 it is a component that encodes information that causes events to occur at particular times within the time intervals of an output signal. The time encoder 105 may, in effect, express the information content of an input signal in an output format where the timing of events within intervals represents the information content of the input signal. The temporary encoder 105 can be used in conjunction with other devices. For example, time encoder 105 can be used as time function encoder 25 (Figure 1A).

The input 110 of the time encoder 105 can be connected to receive information 120 on a signal 125 received from a data communication path. Signal 125 represents information 120 in an ordered finite set of discrete digits. For example, in some implementations, the input information 120 may be expressed in binary digits as a series of high-level (ie, "1") and low-level (ie, "0") states, such as it shows. Input 110 can be a serial or parallel binary data port. Signal 125 can be transmitted over a wired or wireless data communication path.

The output 115 of the temporal encoder 105 can be connected in order to transfer information encoded in a signal 135 transported to a system or support medium 140. The information in the signal 135 is expressed by the times when events occur within the intervals of signal 135. The timing of events within these intervals represents all the information within signal 125. For example, as described below, events that occur for the first time within time intervals may express digits that have high-level states within signal 125, while events occurring at the second moment within time intervals can express digits that have low-level states within signal 125. The first times can be distinguished from the seconds.

The support system or means 140 to which the signal 135 is transported varies depending on the operating context of the system 100. For example, if the system 100 is part of a data transmission system, the support system or means 140 may include a data transmitter. By way of another example, if the system 100 is part of a data storage system, the support system or means 140 may include a writing head that can write information to a data storage device.

In operation, time encoder 105 receives signal 125 at input 110. Time encoder 105 encodes information 120 into signal 125 by expressing input information 120 into signal 135 with events timed to occur at distinguishable times within different times. intervals. The time encoder 105 sends the signal 135, which includes the synchronized events, to the support system or means 140.

Figure 2B is a schematic representation of an implementation of the time encoder 105. The illustrated implementation of the time encoder 105 includes a status detector 205, an event synchronization circuit 210, and an event generator 215. The event detector state 205 is a component that detects digit states in signal 125 representing input information 120. For example, in implementations where input information 120 is expressed in a series of binary digits, state detector 205 may be a bit detector that distinguishes between binary states "1" and "0". The state detector 205 is connected between the input 110 and the event synchronization circuit 210. The indications of the detected states 220 are transmitted to the event synchronization circuit 210.

Event timing circuit 210 is a component that is configured to specify timing of events within intervals of an output signal 135. Event timing circuit 210 includes clock 225, counter 230, interval reset 235 and a timing selector 240. Clock 225 provides a clock output signal 242 to counter 230. Counter 230 is connected to receive clock output signal 242 and output a dynamic count of clock signal 245. The dynamic count 245 is coupled to the interval reset 235 and the timing selector 240. The interval reset 235 may include a comparator (not illustrated) that compares the dynamic count of the clock signal to a threshold count representative of the duration. of an interval. Such a comparison can determine when an interval has elapsed. The interval reset 235 provides a reset signal 250 in response to the step of an interval. The counter 230 receives the reset signal 250 and can reset the count of the clock signal in response to the reset signal. Resetting the counter 230 may therefore demarcate intervals of a threshold count duration.

Synchronization selector 240 receives both the dynamic count of the clock signal 245 and indications of the states 220 detected by state detector 205. Synchronization selector 240 may include a switch 255 and a comparator 260. Comparator 260 includes a pair of inputs 265, 270. Input 265 receives the dynamic count of the clock signal 245 provided by counter 230. Input 270 receives an output signal from switch 275 of switch 255. Switch 255, and the other switches described herein, they may be implemented as, for example, an electro-mechanical switch, one or more transistors, or machine-readable instructions.

Switch 255 includes a high reference 280 and a low reference 285. The high reference 280 incorporates the times within an interval where events representing digits that have high states in the signal 125 must occur. The low reference 285 incorporates the times within of an interval where events representing digits that have low states in signal 125 must occur. Switch 255 receives indications of the states detected 220 by state detector 205. Switch 255 toggles between applying high reference 280 and low reference 285 to input 270 of comparator 260 in response to indications of states detected by state detector 205. In particular, in response to an indication that state detector 205 has detected a low state, switch 255 switches to connect low reference 285 to input 270. In response to an indication that status detector 205 has detected a status high, switch 255 toggles to connect high reference 280 to input 270.

Comparator 260 compares the count of the clock signal provided by counter 230 to either the low reference 285 or the high reference 280 and provides the results of the comparison 290.

The event generator 215 is a component that is configured to generate events on the output signal 135. The event generator 215 is connected to receive the results 290 of the comparisons from the comparator 260 and to synchronize the generation of events based on the results of the comparisons. For example, him event generator 215 may be a pulse generator that generates pulses in response to transitions in results 290 arising from the clock signal output by counter 230 passing through the provided low reference 285 or through the high reference 280 The occurrence of such events within the intervals demarcated by the interval reset 235 are thus synchronized to encode the states of the digits within the signal 125 and can therefore be called "data events". Event generator 215 provides generated events 295 to output 115.

The timing selector 240 is also connected to receive the interval reset signal 250. The timing selector 240 may advance to the next digit and restart the comparison by the comparator 260 in response to the reset signal 250. In some implementations , the status detector 205 is also connected to receive the interval reset signal 250 (see dashed line input to the status detector 205). The status detector 205 may, for example, synchronize the provision of indications of the detected states to the synchronization selector 240 in response to the reset signal 250 and thus advance to the next digit.

In operation, the time encoder 105 receives the signal 125 at the input 110. The status detector 205 detects states in the digits of the signal 125 that represent the input information 120 and provides a signal that characterizes those digits (that is, the state indications 220). Synchronization selector 240 receives the signal describing those digits and generates outputs (ie, results output 290) that are synchronized to occur within intervals in correspondence with the states. In particular, the first states in signal 125 produce transitions in results 290 that occur for the first time within the corresponding time intervals and the second states in signal 125 produce transitions in results 290 that occur in a second moment within the corresponding time intervals. The timing of these transitions is established by the low reference 285 and the high reference 280.

In response to the transitions in the results 290, the event generator 215 generates events 295 that are provided to the output 115. The timing of the events follows the timing of the transitions in the results 290. The reset of the interval 235 demarcates the intervals to advance the timing selector 240 from the one digit state in signal 125 to the next and to reset the comparisons that generate transitions in the results 290. Each digit in signal 125 (including the low "0" states) is thus represented by a correspondingly synchronized event in an interval.

Figure 3 is a schematic representation of a time encoding process. The illustrated temporal encoding can be performed by a temporal encoder such as temporal encoder 105 (Figures 1 and 2). In the illustrated implementation, the information 120 is expressed in binary digits as a series of high digits 305 and low digits 310.

Time encoding encodes information 120 into a time-function code signal 135. Time-function code signal 135 includes a set of time slots 320, each of which corresponds to a digit 305, 310 within signal 125 Each time slot 320 includes a respective data event 325. Synchronization of data events 325 within individual time slots 320 indicates the status of a digit 305, 310 corresponding to that time slot 320. For example, in the In the illustrated implementation, data events 325 in intervals 320 corresponding to the high state digits 305 occur at times 330 near the start of those intervals 320. Data events 325 in intervals 320 corresponding to the low state digits 305, occur at times 335 about half of those 320 intervals. Times 330 are distinguished from times 335.

In different implementations, different event characteristics, including data events 325, can be identified and treated as the time when the events occur. For example, in the illustrated implementation, data events 325 are pulses that transition from a baseline state (ie, a "sleep" state) 340 to a high state (ie, an "excited" state. ) 345 and then return to the resting state of the baseline 340. In some implementations, the initial transitions from the baseline state 340 to the high state 345 can be identified and treated as the times when data events occur 325 In other implementations, the return transitions from high state 345 to baseline state 340 can be identified and treated as the times when data events 325 occur. In some implementations, data event 325 is transient pulses in the sense that the initial and return transitions are so close in time that they are indistinguishable, for example, from the temporal encoder 105. The moment where a transient data event 325 occurs is identified b roasting at the coincident occurrence of the initial and return transition.

In the illustrated implementation, the shapes of the different data events 325 are indistinguishable from each other and the different data events 325 can be distinguished only by virtue of their timing. Furthermore, in some implementations, the data events 325 may be "binary events" in the sense that they occur at one of only two possible times in the interval. When they occur at those times, they are at the same signal level (eg high) but their timing within the range is attributable to the states of the digits they represent.

In the illustrated implementation, the time intervals 320 are all the same duration and occur sequentially. The sequence of time intervals 320 corresponds to the sequence of the corresponding digits 305, 310 in signal 125. In other words, the first time interval 320 (and its event 325) of the time-function code signal 135 corresponds to the first digit 305 in signal 125, the second time slot 320 (and its data event 325) of the time function code signal 135 corresponds to the second digit 310 in signal 125, and so on. This correspondence is represented by dashed arrows 350.

Figure 4 is a schematic representation of another implementation of time encoder 105. In addition to status detector 205, event synchronization circuit 210, and event generator 215, the illustrated implementation of time encoder 105 also includes a start / stop detector 405. Start / stop detector 405 is a component that is configured to detect the start and end of data transmission on signal 125. For example, start / stop detector 405 can recognize a or more headers or feet at sign 125.

The start / stop detector 405 can be connected to input 110. The start / stop detector 405 outputs indications 410 of the start and end of data transmission on signal 125 to the event generator 215 and other parts of the time encoder 105 (for example, to event generator 215). Event generator 215 may generate start and end events (for example, as part of events 295) in response to indications issued by start / stop listener 405. A start event is an event that occurs at one time. which delimits the start of the data output in the results 290 and allows determining the timing of a first interval and a first data event. An end event is an event that occurs at a time that marks the end of the data output in the 290 results. In some implementations, one or both of the initial events and the final events can be used to reset time-dependent processes, such as outlined below. The start and end events generated by event generator 215 are issued as events 295 and provided to output 115.

The indications of the start and end of data transmission in the signal 125 emitted by the start / stop detector 405 can be transmitted and used by other parts of the time encoder 105 to synchronize the output of start events, end events, and stop events. data by event generator 215. For example, one or more of clock 225, counter 230, and interval reset 235 may be turned off during an interval that is associated with an initial event (for example, to allow processing / dismissal of a header in information 120). By way of another example, the progression of the timing selector 240 from digit to digit or the detection of states by the state detector 205 may be disabled during an interval that is associated with an initial event.

Figure 5 is a schematic representation of time encoding with a time encoder that detects the start and end of data transmission in a signal. For example, the illustrated time encoding can be performed by a time encoder such as time encoder 105 that includes a start / stop detector 405 (Figure 4). In the illustrated implementation, the sign 125 includes a header 505 (illustrated as an "X") and a foot 510 (illustrated as a "Y"). Header 505 and footer 510 thus frame information 120 within token 125.

Temporal encoding encodes information 120 into time-function code signal 135, as previously described with reference to Figure 3. Time-function code signal 135 includes header slot 515 and footer slot 520 The header interval 515 includes a header event 525 that occurs at a time 535 within the header interval 515. The foot interval 520 includes a foot event 530 that occurs at a time 540 within the foot interval 520. The The header interval 515 and the header event 525 mark the start of the time-function code signal 135. The foot-interval 520 and the foot-event 530 mark the end of the time-function code signal 135. The demarcation of the Start of the time function code signal 135 can be used to determine the timing of the first event 325 within the first interval 320. For example, the first event 325 occurs at a time 545 after the header event 525. The timing of the first event 325 within the first interval 320 can be determined using the duration of the interval 515 and the moment 545. For example, in implementations where the duration of the interval 515 is the same in the intervals 320 , the detection of event 525 can be used as a reset signal to reset an interval.

In the illustrated implementation, events 525, 530 are pulses that pass from the baseline state 340 to the high state 345 and then return to the baseline state 340. In some implementations, the forms of events 525, 530 may be indistinguishable from each other and from the shapes of the data events 325. In these implementations, the events 325, 525, 530 can be distinguished only by virtue of their timing and position. For example, event 525 can be recognized as the first event. In some implementations, the intervals 515, 520 have the same duration as each other and as the time intervals 320.

Figure 6 is a schematic representation of another implementation of time encoder 105. In addition to status detector 205, event synchronization circuit 210, and event generator 215, the illustrated implementation of time encoder 105 also includes a header / footer encoder 605. The header / footer encoder 605 is a component that is configured to encode a header located at the beginning of the data transmission on signal 125, and a foot located at the end of data transmission on signal 125, or both with information. In some implementations, the information that a header or footer is encoded with may be received, for example, in the header or footer of signal 125. For example, the header / footer encoder 605 may encode a header or footer. with information identifying the signal received at input 110 or with information characterizing aspects of the signal received at input 110. For example, the signal received at input 110 can be identified according to, for example, the source and destination of the received signal, the type of information in the received signal, and the relationship between the received signal and other signals. Aspects of the received signal that can be characterized include the location of a floating point within the received signal, the sign of a number within the received signal, and error checking information. Header / footer encoder 605 may encode a header or footer with such information by triggering the introduction of one or more events in a header or footer area associated with input signal 125.

The header / footer encoder 605 may be connected to input 110. The header / footer encoder 605 outputs one or more signals 610 that identify or characterize information in the header or footer and provides the signals 610 to the event generator 215. The Event generator 215 can generate events that are timed to occur within the header or footer of signal 125 in response to indications issued by header / footer encoder 605. Events 295 generated by event generator 215 are provided to exit 115.

In some implementations, the identification or characterization information in the signals 610 may also be sent to other parts of the temporal encoder 105. This information may be used in a variety of ways, including, for example, error checking and triggering and / or restoration of interval demarcation and generation of data events.

Figure 7 is a schematic representation of the encoding of a header at the beginning of data transmission in a signal. For example, the illustrated encoding can be performed by a time encoder such as time encoder 105 that includes a header / footer encoder 605 (Figure 6). The information can be encoded by one or more events that occur within the header interval 515 or the footer interval 520 in the signal 135.

In the illustrated implementation, the header interval 515 includes a header event 705. The header event 705 occurs at a time 710 within the header interval 515. The timing of the header event 705 within the header interval 515 may be determined, for example, by measuring the time interval 710 between time 535 and time 710.

In some implementations, the header interval 515 may itself be divided into multiple subranges, each of which may include one or more informational events. Different sub-ranges can be assigned to encode different identification and characterization information. For example, a first sub-interval may include an event, the timing of which indicates whether a number encoded in signal 135 has a positive or negative sign. By way of another example, a set of sub-ranges may include informational events, the timing of which indicates the position of the information encoded in signal 135 within a higher set of information (for example, after segmentation, as described below). continuation).

In the illustrated implementation, the header event 705 is a pulse that passes from the baseline state 340 to the high state 345 and then returns to the baseline state 340. In some implementations, the forms of the events of Header 705 can be indistinguishable from each other, from the forms of the events 525, 530 and the forms of the data events 325. In these implementations, the events 705, 325, 525, 530 can be distinguished only in by virtue of their timing and position.

In some implementations, a footer at the end of data transmission in a signal may be encoded with one or more informational events. In some implementations, both a header and a footer can be encoded with one or more informational events.

Figure 8 is a schematic representation of another implementation of the time encoder 105. The illustrated implementation of the time encoder 105 includes a status detector 205 and an event synchronization circuit 210 that are adapted to operate with signals 125 that encode information with digits that have more than two possible states. For example, signal 125 may encode information in quaternary or decimal digits.

The state detector 205 is configured to detect the states of the digits in the signal 125 and transmit the indications of the detected states to the event synchronization circuit 210. The event synchronization circuit 210 includes a synchronization selector 240 that is connected to receive these prompts and set switch 255 in response. In particular, the switch 255 includes a set of more than two references 805 that are associated, each one, with respective states (that is, times within an interval where events will occur that represent a corresponding state of the digits in the signal. 125). For example, the first reference 805 can be associated with a first moment within an interval, the second reference 805 can be associate with a second moment within an interval, and the N-th reference 805 can be associated with the N-th moment within an interval.

Switch 255 is configured to apply the appropriate reference 805 to input 270 of comparator 260 in response to indications of states detected by state detector 205. Comparator 260 compares the count of the clock signal emitted by counter 230 with the appropriate reference 805 and generates the results 290 of the comparisons. The various states of the digits in signal 125, therefore, result in transitions occurring at distinguishable times within corresponding time intervals, with the timing of these transitions established by references 805.

Figure 9 is a schematic representation of the time encoding of a signal that includes digits that have more than two possible states. The illustrated time encoding can be performed by a time encoder such as time encoder 105 (Figure 8). In the illustrated implementation, information 120 is expressed in signal 125 using digits that have four different possible states, namely, digits 905 that have a first state (ie, "A's"), digits 910 that have a second. state (that is, "B's"), the digits 915 have a third state (that is, "C's") and the digits 920 have a fourth state (that is, "D's"). In other implementations, the information 120 may be expressed in digits that have a different number of possible states (for example, digits that have 10 different possible states that express information 120 in decimal) or in digits that have a much greater number of possible states or a continuous set of possible states (for example, an analog or quasi-analog continuous set of possible states). In some implementations, digits having four possible states can be used to express genetic information and represent four nucleic acids.

Temporal encoding encodes information 120 into a time-function code signal 135. The time-function code signal 135 includes a set of time slots 320, each of which corresponds to a digit 905, 910, 915, 920 within signal 125. Each time slot 320 includes a respective data event 325. The timing of the data events 325 within the individual time slots 320 indicates the status of the digits 905, 910, 915, 920 corresponding to that time interval 320. For example, in the illustrated implementation, data events 325 in intervals 320 corresponding to the digits 905 of the first state occur at times 930 near the end of intervals 320. Data events 325 in the 320 intervals corresponding to the digits 910 of the second state occur at times 935 near the middle of the 320 intervals. The 325 data events at 320 intervals corresponding to the digits The 915s of the third state occur at times 940 before the middle of the 320 intervals. The 325 data events in 320 intervals corresponding to the digits 920 of the fourth state occur at times 945 near the start of the 320 intervals. The times 930, 935, 940, 945 can be distinguished from each other.

In other implementations, a time encoder may be implemented as a digital circuit that receives as input a sequence of symbols from a predetermined set of symbols and produces, as output, a time-coded output signal, where each time interval in the time-coded output signal includes a single pulse at a time within the interval determined by the corresponding input symbol. Digital circuits can be controlled by a programmed computer or include a built-in computer. In some implementations, each input symbol is assigned a single character that has a length in binary digits (that is, bits) N that is equal to the number of different possible input symbols, and where all bits are equal except one, so the position of the distinct bit in the character identifies the symbol to which the character corresponds. Therefore, the symbol input sequence is mapped to a character input sequence, which can be input to a shift register. The shift register output is clocked so that N bits appear in each time interval 320. This output is coupled to a pulse generator so that the occurrence of the different bit causes an output pulse to be generated at the output of the shift register. temporary encoder. In some of these implementations, the time encoder includes circuitry that transforms an analog input signal into a sequence of symbols. If headers, feet and synchronization are desired in the output signal, the corresponding input symbols can be added as a prefix or suffix, as the case may be, to the actual signal to be transmitted, in accordance with a convention or protocol adopted by the encoder. and decoders downstream.

Figure 10 is a schematic representation of an implementation of the system 100, that is, a system 1000 where information can be encoded. The system 1000 includes a neural processing component 1005 to which the signal 135 is transmitted from the temporal encoder 105. The neural processing component 1005 is a component constructed of neural tissue or having a design inspired by the design and function of neural tissue. . Thus, the neural processing component 1005 can be implemented using "wet" nerves and other neural components (eg, such as a biological neural network or the brain or other neural tissue of a living organism) or the Neural processing 1005 can be implemented using semiconductor devices (eg, such as an artificial neural network implemented using hardware or software). In some implementations, combinations of semiconductor devices and wet neural components can implement neural processing component 1005.

As shown, time encoder 105 sends signal 135, including synchronized events, to neural processing component 1005. In implementations where neural processing components 1005 are implemented using "wet" neural components, the properties signal 135 can be tailored for compatibility with wet neural components. For example, events within signal 135 can be customized to mimic the amplitude and time characteristics of action potentials.

In some implementations, neural processing component 1005 may include multiple elements that receive signal 135. For example, in neural processing components 1005 implemented using "wet" neural components, multiple nerves may receive signal 135. By way of another example, in neural processing component 1005 implemented using semiconductor components, multiple neural network inputs can receive signal 135.

In operation, time encoder 105 may encode information 120 in signal 125 in a way that is understood by neural processing component 1005, that is, signal 135 with events timed to occur at distinguishable times within intervals in a sequence of intervals. Temporal encoder 105 may act as an interface between binary digital data processing (and others) and statistical processing and pattern recognition provided in neural processing component 1005. For example, temporal encoder 105 may be included in a neural prosthesis that stimulates the nerves with, for example, auditory, visual, or other sensory information encoded in signal 135.

Figure 11 is a schematic representation of an implementation of the system 100, namely, one that includes a multi-channel encoder 1100 where information can be encoded. System 1100 includes a set of time encoders 105, a data slicer 1105, an input 1110, and a set of one or more outputs 1115.

Input 1110 receives information 120 on a signal 125 on a data communication path. Input 1110 provides a signal 1117 that transmits information in signal 125 to an input 1120 of data slicer 1105. Data slicer 1105 is a component that divides (or "chunks") a signal into smaller units. The data slicer 1105 includes an input 1120 and one or more outputs 1125.

The data segmenter 1105 divides the relatively larger set digits in signal 125 into a smaller set of digit set that each represent an appropriate subset of information 120. In some implementations, the segments may be a contiguous part of the digits in signal 125. In other implementations, the segments may include non-contiguous digits. In the illustrated example, signal 125 received by data slicer 1105 represents information 120 in an ordered finite set of discrete digits, eg, a set of bits. Data segmenter 1105 divides signal 125 into a set of smaller segments, each of which represents a suitable subset of information 120 in an ordered finite set of discrete digits. The data segmenter 1105 provides the segments 1120 from one or more outputs 1125 to the inputs 110 of the corresponding temporal encoders 105. Each temporal encoder 105 encodes the information in a received segment by synchronizing the occurrence of events within time intervals of a signal. respective output signal 135. The timing of events within the intervals on each output signal 135 represents all the discrete digits within each segment.

Temporal encoder 105 outputs respective output signals 135 from outputs 1115 of multichannel encoder 1100. In some implementations, output signals 135 are provided to a single support medium 140 at the same time. For example, in implementations where the time code of the output signals 135 each include a header interval 515 and a header event 525, the header events 525 in the respective output signals occur in the same moment in time. The support system or means 140 may include a set of inputs, each of which is connected to a corresponding output 1115 to receive a corresponding output signal 135, as described below.

In operation, data slicer 1105 receives signal 125 at input 1120. Data slicer 1105 performs a data slicing process on signal 125 and generates a set of slices. Each of the segments is input to a respective input 110 of a time encoder 105. Each time encoder 105 encodes the information in the respective segment by expressing the information with synchronized events to occur at distinguishable times within different intervals. Each time encoder 105 provides a respective signal 135 that transmits the signal 135 to the outputs 1115 of the multichannel encoder 1100 and to the support system or means 140.

Figure 12 is a schematic representation of a system 1200 where information can be encoded, compressed, and stored / transmitted and then accessed / received, decoded, and decompressed. System 1200 may include one or more of the implementations of system 100 described above, as well as a decoder 1205 that includes an input 1210 and an output 1215. Input 1210 and output 1215 are physical structures through which the signals are received and transferred respectively out of the decoder 1205. The decoder 1205 is a component that decodes a signal in which the information is encoded by timing the occurrence of events within time intervals. The decoder 1205, in effect, translates, a signal as a function of time, into where the synchronization of events, within intervals, represents the content of the information in an output format that represents said information in a finite ordered set of discrete digits.

The input 1210 of the decoder 1205 can be connected to receive a signal 1220 wherein the information is encoded by synchronizing the occurrence of events within time intervals. Signal 1220 may be output from the support system or means 140 to a data communication path. The exact nature of the information transfer from the system or support medium 140 to the decoder 1205 via signal 1220 depends on the operating context of the system 1200. For example, if the system 1200 is part of a data transmission system, Support system or means 140 may include a data transmitter that sends signal 1220 to a data receiver in set-top box 1205. By way of another example, if system 1200 is part of a data storage system, set-top box 1205 can include, for example, a read head that can read information from data storage medium 140. Signal 1220 can be carried, for example, over a wired or wireless data communication path.

After translation into an output format, the decoder 1205 provides a signal 1230 that includes the decoded information 1225. The decoded information 1225 can be expressed in an ordered finite set of discrete digits, for example, in binary digits as a series of states. highs and lows as illustrated. Output 1215 may be in the form of one or more serial or parallel binary data ports.

In operation, decoder 1205 receives signal 1220 from system or support means 140 at input 1210. Signal 1220 expresses information with events timed to occur at distinguishable times within different intervals. Decoder 1205 decodes information 1225 and provides signal 1230 that includes decoded information 1225.

Decoder 1205 can be used in conjunction with other devices, outside of system 1200. For example, decoder 1205 can be used as a time function decoder 41 (Figure 1A).

Figure 13 is a schematic representation of an implementation of the decoder 1205. The illustrated implementation of the decoder 1205 includes an event detector 1305, a time-to-state translator circuit 1310, and a state selector circuit 1315. Although it is done Reference to circuits, one or more of the decoder components can be implemented in firmware or software. Event listener 1305 is a component that can detect events - and their timing - on signal 1220. The structure of event listener 1305 can reflect the nature of events on signal 1220. For example, when events on signal 1220 are pulses, event detector 1305 may be a pulse detector. Event detector 1305 is connected to receive signal 1220 from input 1210 and a signal indicative of time within an interval 1325 from an interval synchronization circuit 1320. Event detector 1305 is connected to provide output to times 1325 within the intervals where the events are detected.

The interval synchronization circuit 1320 includes a clock 1330, a counter 1335, and an interval reset 1340. The clock 1330 provides an output clock signal 1345 to the counter 1335 which in turn produces a dynamic count 1332 of the clock signal. . The dynamic count 1332 is provided to both the event listener 1305 and the interval reset 1340. The interval reset 1340 may include a comparator (not shown) that compares the dynamic count of the clock signal to a threshold count representative of a interval duration. Such a comparison can determine when an interval has elapsed. The interval reset 1340 outputs a reset signal 1350 to the counter 1335. The counter 1335 is reset in response to the reset signal 1350. The reset of the counter 1335 delimits intervals of a threshold count duration.

The reset signal 1350 emitted by the interval reset 235 may be carried and used by other parts of the decoder 1205 in due course, for example, the translation of events by the time-to-state translator 1310 and the selection and output of digits. by the state selector 1315. For example, the time-to-state translator 1310 may include one or more switches that reset the translations and output the translation results in response to the reset signal 1350. By way of another example , the status selector 1315 can disable the reset signal 1350 to ensure that a single digit is selected and issued for each interval.

In response to the detection of an event, the event listener 1305 issues a time stamp within an interval 1325 where an event is detected. These indications are received by the time-to-state translator 1310. In the illustrated implementation, the time-to-state translator 1310 includes a high-bit detector 1355 and a low-bit detector 1360 that are both connected to receive the indications of the times within intervals where events are detected.

In some implementations, the high bit detector 1355 includes a pair of comparators 1356, 1358 and an AND gate 1359. The comparator 1356 is connected to compare the times within the intervals where events are detected with a first reference ref_1. The comparator 1358 is turned on to compare the times within the intervals where events are detected with a second reference ref_2. The references ref_1, ref_2, are thresholds indicating the earliest and most recent times within an interval where a detected event is considered to be in a first state (eg, a high bit). If one bit is detected at a time after the time indicated by ref_1 and before the time indicated by ref_2, the outputs of both comparators 1356, 1358 are set. The AND gate 1359 also produces an output 1365 (for example, a high signal) that indicates that the timing of the detected event by event listener 1305 is within a range.

In the illustrated implementation, the low bit detector 1360 includes a pair of comparators 1361, 1363 and an AND gate 1364. The comparator 1361 is connected to compare the times within the intervals where events are detected with a first reference ref_3 . The comparator 1363 is connected to compare the times within the intervals where events are detected with a second reference ref_4. The references ref_3, ref_4 are thresholds indicating the earliest and most recent time within an interval where a detected event is considered to be in a second state (eg, a low bit). If an event is detected at a time after the time indicated by ref_3 and before the time indicated by ref_4, the outputs of both comparators 1361, 1363 are set. The gate to Nd 1364 also provides an output 1370 that indicates that the timing of the event detected by event listener 1305 is within a range.

Status selector 1315 is a component that is configured to select the states of the digits for the output on signal 1230 at output 1215. In some implementations, the digits may be binary bits. Status selector 1315 is wired to receive translations (ie, outputs 1365, 1370). Based on the received translations, the status selector 1315 provides status information 1215. The digits can be output in parallel or serially.

In operation, event detector 1305 receives signal 1220 wherein information 1225 is encoded by timing the occurrence of events within time intervals. The event listener 1305 detects the timing of the events within their respective intervals and generates a description of that timing 1325. The time-to-state translator circuit 1310 translates the times within an interval into the discrete digits that will be output from the decoder. 1205 on signal 1230 by comparing the times where the events were detected by the event detector 1305 with the times assigned to the states. In particular, events detected within a first time range defined by references ref_1, ref_2 result in signals set at output 1365. Events detected within a second time range defined by references ref_3, ref_4 result in signals set at output 1370. Status selector circuit 1315 receives the results of those comparisons and selects digit states for output at output 1215 in accordance with those results.

Figure 14 is a schematic representation of the decoding of a signal where the information is encoded by the timing of the occurrence of events within time intervals. Decoding can be performed, for example, by a decoder such as decoder 1205 (Figure 12).

Decoding translates the information encoded in the time-code signal 1220 into a signal 1230 that represents the information 1225 in a finite ordered set of discrete digits. In the illustrated implementation, the information 1225 is expressed in the signal 1230 in binary as a series of high bits 1405 (ie, "1") and low bits 1410 (ie, "0").

Time function code signal 1220 includes a set of time slots 1420, each of which corresponds to a digit 1405, 1410 within signal 1230. Each time slot 1420 includes a respective data event 1425. Synchronization of data events 1425 within individual time intervals 1420 indicate the status of the digit 1405, 1410 corresponding to that time interval 1420. For example, in the illustrated implementation, data events 1425 in intervals 1420 corresponding to the high state digits 1405 occur at times 1430 near the start of those 1420 intervals. Data events 1425 in the 1420 intervals corresponding to the low state digits 1405 occur at times 1435 near the middle of those 1420 intervals. moments 1430 are distinguished from moments 1435.

In the illustrated implementation, data events 1425 are pulses that transition from a baseline state (ie, a "sleep" state) 2140 to a high state (ie, an "energized" state) 1445, and they then return to the rest state of the baseline 1440. In some implementations, the initial transitions from the initial state 2140 to the high state 1445 can be identified and treated as the times when data events 1425 occur. In other implementations , the return transitions from the high state 1445 to the initial state 2140 can be identified and treated as the times where the data events 325 occur. In some implementations, the data events 1425 are transient pulses in the sense that the Initial and return transitions are so close in time that they are indistinguishable, for example, for time encoder 1205. The time when a transient data event 1425 occurs is identified based on the appearance of the transitions. you coincident occurrence of the initial and return transition.

In some implementations, the shapes of different data events 1425 may be indistinguishable from each other and the different data events 1425 may be distinguished only by virtue of their timing. Furthermore, in some implementations, data events 1425 may be binary events in the sense that they occur only at two possible times, ie, at a first time or at a second time within an interval.

In the illustrated implementation, the time slots 1420 are all the same duration and occur sequentially. The sequence of time intervals 1420 corresponds to the sequence of the corresponding digits 1405, 1410 in signal 1430. In other words, the first time interval 1420 (and its event 1425) of the time-function code signal 1220 corresponds to the first digit 1405 in signal 1230, the second time slot 1420 (and its data event 1425) of the time function code signal 1220 corresponds to the second digit 1410 in signal 1230, and so on. This correspondence is represented by dotted arrows 1450.

Figure 15 is a schematic representation of another implementation of the decoder 1005. In addition to the event detector 1305, the time-to-state translator circuit 1310, the state selector circuit 1315, and the interval synchronization circuit 1320, the The illustrated practice of decoder 1005 also includes a start / stop detector 1505. The start / stop detector 1505 is a component that is configured to detect one or both of the start and end of data transmission on signal 1220. For example, the start / stop detector 1505 may recognize one or more of a header event, a header interval, a foot event, and a foot interval in signal 1220.

The start / stop detector 1505 can be connected to input 1210 to receive signal 1220 (as shown). In some implementations, the start / stop detector 1505 may detect one or both of the start and end of data transmission on signal 1220 by detecting start and end events on signal 1220. The start detector / stop 1505 provides indications 1510 of one or both of the start and end of data transmission on signal 1220 to the interval reset 1340 and other parts of the decoder 1205. The interval reset 1340 can be reset by itself - and interval demarcation - in response to prompts provided by the start / stop detector 1505. The start / stop detector 1505 can thus synchronize the interval reset 1340 with the timing of intervals and events within signal 1220.

In some implementations, the indications of the start and end of data transmission in the signal 1220 provided by the start / stop detector 1505 may be transmitted and used by other parts of the decoder 1205. For example, in some implementations In practice, the state selector 1315 may demarcate one or both of the start and end of signal 1220 using a header event and a foot event in response to prompts provided by the start / stop detector 1505.

Figure 16 is a schematic representation of the decoding of a signal where the information is encoded by synchronizing the occurrence of events within time intervals with a decoder that detects the start and end of data transmission in a signal. . For example, the illustrated decoding can be performed by a decoder such as decoder 1205 that includes a start / stop detector 1505 (Figure 15). In the illustrated implementation, the sign 1230 includes a header 1605 (illustrated as an "X") and a footer 1610 (illustrated as a "Y"). Header 1605 and footer 1610, therefore, serve as the structure for signal 1230.

Decoding decodes time-function code signal 1220 into signal 1230, as previously described with reference to Figure 14. Time-function code signal 1220 includes head slot 1615 and foot slot 1620. The header interval 1615 includes a header event 1625 that occurs at a time 1635 within the header interval 1615. The foot interval 1620 includes a foot event 1630 that occurs at a time 1640 within the foot interval 1620. The interval The header 1615 and the header event 1625 delimit the start of the time-function code signal 1220. The foot interval 1620 and the foot event 1630 mark the end of the time-function code signal 1220. The start demarcation of the time function code signal 1220 can be used to determine the timing of the first event 1625 within the first interval 1620. For example, the first event 1625 occurs in a period of time 1645 after the header event 1625. The timing of the first event 1625 within the first interval 1620 can be determined using the duration of the interval 1615 and the time period 1645.

In the illustrated implementation, events 1625, 1630, and 1425 are pulses that go from the baseline state 1640 to the high state 1445 and then return to the baseline state 1640. In some implementations, the forms of the events 1625, 1630 can be indistinguishable from each other and from the forms of data events 1425 and events 1425, 1625, 1630 can only be distinguished by virtue of their timing. Furthermore, in some implementations, the intervals 1615, 1620 are both the same duration as each other and as time intervals 1420.

Figure 17 is a schematic representation of another implementation of the decoder 1205. In addition to the event detector 1305, the time-to-state translator circuit 1310, the state selector circuit 1315, the interval synchronization circuit 1320, and the time-to-state detector. start / stop 1305, the illustrated implementation of decoder 1005 also includes a header / footer decoder 1705. The header / footer decoder 1705 is a component that is configured to decode information encoded in the header of a signal 1220, encoded information at the bottom of a 1220 sign or encoded information at both locations.

Header / footer decoder 1705 is connected to input 1210 to receive signal 1220 and any header events or footer events included in signal 1220. In some implementations, eg. For example, where the duration of the header interval and footer intervals is the same as the duration of intervals 1420, the decoder of header / footer 1705 can be connected to receive 1510 indications from one or both of the start and end of data transmission on signal 1220 and to event listener 1305 to receive a 1325 dynamic count of time within an interval of a magnitude specified by the interval reset. In implementations, for example, where the duration of the header interval and footer intervals differ from the duration of the intervals 1420, the header / footer decoder 1705 may be connected to the output of another interval synchronization circuit. , include internal start / stop detection components, or otherwise determine when informational events occur within a header, footer, or both.

The header / footer decoder 1705 generates indications of the informational content of informational events that occur within a header or footer such as an output 1710. The status selector 1315 may receive the indications and generate discrete digits 1015 in accordance with the indications. For example, in some implementations, the status selector 1315 may select a sequence of digits that identifies the source and destination of the signal 1230, the type of information in the signal 1230, and the relationship between the signal 1230 and other signals. .

In some implementations, the indications emitted by the header / footer decoder 1705 may be transmitted and used by other parts of the decoder 1205. For example, the error checking information may be transmitted and used by an error checking component. within decoder 1005. By way of another example, the indications emitted by the header / footer decoder 1705 can be transmitted to the translator circuit 1310 and used, for example, to set the number of digits to be detected or to change the numbers. times within an interval where a detected event is considered to correspond to a certain state.

Figure 18 is a schematic representation of another implementation of decoder 1205. The illustrated implementation of decoder 1205 includes a translator circuit 1310 and a state selector circuit 1315 that are suitable for decoding signals where information is encoded by the synchronization of the occurrence of events within time intervals in signals that encode information with digits that have more than two possible states. For example, decoder 1205 may decode a time-based code signal 1220 into a signal 1230.

In response to the detection of an event, the event listener 1305 issues a time stamp within an interval where an event is detected. These indications 1325 are received by the time-to-state translator 1310. The time-to-state translator 1310 includes a set of status detectors 1805, 1810, 1815, 1820 that are all connected to receive the indications of the moments within intervals in where events are detected.

Each status detector 1805, 1810, 1815, 1820 is connected to compare the moments within the intervals where events are detected with references that incorporate the earliest and most recent moments within an interval where a detected event is considered to be corresponding status. In response to detecting that the timing of an event within a range is within a corresponding range, each status detector 1805, 1810, 1815, 1820 provides an indication 1825, 1830, 1835, 1840. The status detectors 1805 , 1810, 1815, 1820 translate the moments within an interval into one of the digit states in signal 1230 to be output from decoder 1005.

The state selector 1315 is wired to receive the translations (for example, the indications 1825, 1830, 1835, 1840) and, based on the received translations, the state selector 1315 provides digits having the states to the output 1215.

In operation, event detector 1305 receives signal 1220 wherein information 120 is encoded by timing the occurrence of events within time intervals. Event listener 1305 detects the timing of events within their respective ranges and generates a description of that timing (eg, prompts 1325). The time-to-state translator circuit 1310 translates the moments within an interval to the states to be emitted from the decoder 1305 in the signal 1330 by comparing the moments where the events were detected by the event detector 1305 with the moments assigned to the state. State selector circuit 1315 receives the results of those comparisons (eg, indications 1825, 1830, 1835, 1840) and selects digit states for the output to be provided to output 1215 in accordance with those results.

Figure 19 is a schematic representation of the decoding of a signal where the information is encoded by the timing of the occurrence of events within time intervals in a signal that includes digits that have more than two possible states. For example, the illustrated decoding may be performed by a decoder such as the decoder 1205 illustrated in Figure 18. In the illustrated implementation, the time-function code signal 1220 includes a set of time slots 1420, each of which corresponds to a digit 1905, 1910, 1915, 1920 within signal 1230. Each time interval 1420 includes a respective data event 1425. Synchronization of data events 1425 within individual time intervals 1420 indicates the status of the digit 1905, 1910, 1915, 1920 corresponding to that time interval 1420. For example, in the illustrated implementation, data events 1425 in intervals 1420 corresponding to the digits 1905 of the first state, occur at times 1930 near the end of intervals 1420. Data events 1425 in intervals 1420 corresponding to the digits 1910 of the second state, occur at times 1935 near the middle of intervals 1420. Events of Data 1425 in intervals 1420 corresponding to the digits 1925 of the third state, occur in the times 1940 before the middle of the intervals 1420. The events of data 1425 in intervals 1420 corresponding to the digits 1905 of the fourth state, occur in the moments 1945 near the beginning of the 1420 intervals. The times 1930, 1935, 1940, 1945 are distinguished from each other.

Decoding decodes time-function code signal 1220 into signal 1230. Information is expressed in signal 1230 using digits that have four different discrete potential states, namely, digits 1905 that have the first state (ie, "A's "), digits 1910 that have the second state (that is," B's "), digits 1915 that have the third state (that is," C's "), and digits 1920 that have the fourth state (that is," D's ") . In other implementations, signal 1230 may express information in digits that have a different number of possible states (eg, digits that have 10 different possible states that express information in decimal) or in digits that have a much larger number. or a continuous set of possible states (eg, a continuum of analog or near-analog states). In some implementations, signal 1230 may express genetic information, namely four nucleic acids, using four different possible states.

In other implementations, a decoder can be implemented as a digital circuit that receives as input an ordered set of bits that are grouped into binary characters of a predetermined length of N binary digits (i.e., bits), where only one bit is distinct from the others and outputs a sequence of output symbols. Digital circuits can be controlled by a programmed computer or include a built-in computer. In some such implementations, the decoder includes circuitry that transforms the sequence of symbols into an analog output signal.

Figure 20 is a schematic representation of one implementation of decoding system 2000. System 2000 may be a stand-alone system or part of a larger system, such as system 1200 (Figure 12). System 2000 includes a neural processing component 140, 1005 from which signal 1220 is received by decoder 1205. Signal 1220 encodes information by timing the occurrence of events within time slots. In some implementations, neural processing component 140, 1005 may include multiple elements that contribute to events in signal 1220. For example, in neural processing components 140, 1005 implemented using "wet" neural components, Multiple nerves can contribute to events in signal 1220. By way of another example, in neural processing components 140, 1005 implemented using semiconductor devices, multiple outputs of the neural network can contribute to events in signal 1220 .

In operation, decoder 1205 can decode signal 1220 into a signal 1230 that expresses information 1225 in a finite ordered set of discrete digits. Decoder 1205 may act as an interface between statistical processing and pattern recognition functions provided by neural processing component 1205 and binary (and other) digital data processing devices. For example, decoder 1205 can be included in a motor or other prosthesis that receives nerve spike trains with, for example, control or other information, encoded in signal 1220.

Figure 21 is a schematic representation of an implementation of a system for decoding signals where the information is encoded by timing the occurrence of events within time slots, namely, a 2100 multi-channel decoder system. The system 2100 multichannel decoder can be used alone or in conjunction with other devices. For example, the multichannel decoder system 2100 can be used as a time function decoder 41 (Figure 1A).

System 2100 includes a set of decoders 1205, a data adder 2105, a set of inputs 2110, and an output 2115. The inputs 2110 receive a respective time-code signal 1220. The time function code signals 1220 each include a set of intervals that themselves include events. The timing of events within these intervals encodes the information. In some implementations, different time code signals 1220 may all be received from the same single system or support means 140, as illustrated.

Time-code signals 1220 are provided from inputs 2110 to corresponding inputs 1210 of decoders 1205. Decoders 1205 are therefore each connected to receive a respective time-code signal 1220. Decoders 1205 decode information into signals 1220 and decode signals 2125 are provided. In decoded signals, at least part of the information content of signals 1220 is expressed in a finite ordered set of discrete digits, for example, in a set of high and low bits.

Decoded signals 2125 are provided to one or more inputs 2130 of data adder 2105. Data adder 2105 also includes an output 2135. Data adder 2105 is a component that adds a relatively small set of digits into a larger set of digits. digits. In the illustrated implementation, the data adder 2105 is connected to aggregate the received decoded signals into an output signal 1230 that expresses the 1225 information in a finite ordered set of discrete digits. Output signal 1230 is provided from output 2135 of data adder 2105 to output 2115 of system 2100.

In operation, each decoder 1205 receives a respective time-code signal 1220 from the support system or means 140. The decoders 1205 decode their respective time-code signals 1220 into signals that express the information content in a finite set. ordered of discrete digits. The data adder 2105 is connected to receive signals 1220, aggregates them, and provides them on an output signal 2145.

Figure 22 is a schematic representation of a 2200 system implementation where information can be encoded. The 2200 system includes a 1105 multichannel encoder and a 2205 compressor encoder.

Compressor encoder 2205 is a component that compresses multiple input signals into a single output signal 2220. Compressor encoder 2205 includes a set of one or more inputs 2210 and one output 2215. One or more inputs 2210 can be connected to receive signals time-code code from the output 1115 of a multichannel time encoder 1105. Compressor encoder 2205 compresses the received time-code signals and provides a compressed signal 2220 at output 2215 to a support system or means 140.

The 2200 system can be used in isolation or in conjunction with other devices. For example, the 2200 system can be used as a time function encoder 25, amplitude weighting component 27, and compressor 29 (Figure 1A).

Figure 23 is a schematic representation of an implementation of a compressor encoder 2205. The compressor encoder 2205 is a component that encodes information from a set of signals where the information is encoded by the timing of the occurrence of events within intervals time in a signal that includes a synchronized series of events such as signal 2220 (Figure 22).

In the illustrated implementation, the encoder 2205 includes a set of different binary-to-analog converters 2305, an integrator 2310, a set of inputs 2315, and an output 2320. Each of the binary-to-analog converters 2305 includes a respective input 2325 and an output 2330. The input 2325 of each binary-to-analog converter 2305 is connected to receive a respective signal 135 wherein the information is encoded by timing the occurrence of events within time intervals from the corresponding input 2315.

Each input 2315 and the corresponding binary-to-analog converter pair 2305 form an encoding channel 2340. Compressor encoder 2205 is therefore a parallel combination of multiple encoding channels 2340. Signals 135 may have the same information, they may have different information content, or it may have combinations of the same and different information content.

Each binary-to-analog converter 2305 is a component that is configured to weight the amplitude of individual events in a time series of input events based on the timing of other events in the input time series. In some implementations, the events can be weighted using a non-linear function. In some implementations, the compressor encoder 2205 includes at least two different binary-to-analog converters 2305. A different binary-to-analog converter 2305 can weight events using different parameters as a function of time, different time dependencies, or combinations of these or other factors. . In some implementations, each binary-to-analog converter 2305 in encoder 2205 will be different from all other binary-to-analog converters 2305 in encoder 2205. In some implementations, set of binary-to-analog converters 2305 in encoder 2205 is the complete set of binary to analog converters built using a process such as the 3900 process (Figure 39). As a consequence of these differences, when the same signal where the information is encoded by the synchronization of the occurrence of events within time intervals is introduced into different binary-to-analog converters 2305, different signals that include the weighted events in relative moments that correspond to the synchronization of the unweighted events within the input signal will be output through the different binary to analog converters 2305.

Each binary-to-analog converter 2305 provides a signal 2345 that can include the weighted events at relative times corresponding to the timing of the unweighted events within the input signal on the output 2330. The signals 2345 are provided to a respective input 2350 of the integrator 2310. In implementations where the integrator 2310 is implemented using "wet" neural components, the properties of the signals 2345 can be tailored to be compatible with the wet neural components. For example, events within 2345 signals can be tailored to mimic the amplitude and time characteristics of action potentials.

The integrator 2310 includes a set of inputs 2350 and an output 2355. The integrator 2310 is a component that integrates the signals received at the inputs 2350 to generate a signal that is provided to the output 2355. The integration of these signals combines and compresses them in a single signal. In some implementations, the integrator 2310 may be a non-linear integrator in the sense that different signals received at different inputs 2350 contribute in different measures to the signal provided at output 2355. In some implementations, integrator 2310 may be a linear integrator in the sense of that different signals received at different inputs 2350 contribute to the same extent to the signal provided to output 2355. In some implementations, as will be described below, integrator 2310 is modeled from one or more neurons or nodes in the brain or other neural processing device. For example, the single signal output 2360 provided at the output 2355 of the integrator 2310 may represent the 'all to all' interactions of the different signals received at the inputs 2350.

Output 2355 couples signal 2360 to output 2320 of compressor encoder 2205. Output 2320 provides signal 2365 to a support system or means 140.

Figures 24, 25, 26, 27 are schematic representations related to different implementations of an integrator 2310, namely an integrator 2400, an integrator 2500, an integrator 2600, and an integrator 2700. The integrator 2400 is an unbranched node of a neural processing system. The integrator 2500 is a node in a neural processing system that has multiple branches. The integrators 2600, 2700 are a network of nodes in a neural processing system. The integrators 2400, 2500, 2600, 2700 can be built in hardware, in software, in wet neural components, or in combinations of these components.

As shown, integrator 2500 includes a set of legs 2505. In some implementations, legs 2505 have identical properties. In other implementations, different branches 2505 have different properties. For example, different branches 2505 may have different cable properties.

As shown, integrators 2600, 2700 each include a set of nodes 2605 joined by a set of links 2610. Links 2610 may include, for example, feed forward links, feedback links, recurring links, or their combinations. The integrator 2700 includes a pair of outputs 2355. Both outputs 2355 provide results of combining and compressing the signals received at inputs 2350. In general, however, outputs 2355 will output different signals that result from different combinations and compressions of the inputs. signals received at inputs 2350. As a result, two different signals can be output from a compressor encoder and transported to a support system or means 140. These two different signals can also be stored or decoded in parallel using the systems and techniques described. Although such parallel storage and decoding might decrease the data storage density or require additional processing, the fidelity of the storage and decoding can be verified and, if necessary, improved by comparing the results of parallel decoding.

In operation, integrators 2400, 2500, 2600, 2700 can integrate input signals according to one or more models. For example, in some implementations, the 2400 integrator may be integrated according to an integration and trigger model. Said model includes a capacitor C in parallel with a resistance R driven by a current I ( t) and that provides:

Ecuación 1

Equation 1

In this model, the signals at the 2350 inputs are made up of a linear summation of the amplitudes of each signal at any moment in time (that is, the voltages of each input signal are added (RxI (t)). voltage drops exponentially with a time constant im. A threshold voltage can be selected, above which a binary state can be signaled at output 2355.

In other implementations, the 2400-2700 integrators can be integrated in accordance with an integrating and firing neuron model based on conductance provided by:

where g ^j is the conductance for a particular ionic species, V-Vj is the Nernst potential of the conductance, and I ^ext is an external applied current.

In this model, the signals at the 2350 inputs are made up of a non-linear summation of the amplitudes of each signal at any moment in time, achieved by one or more conductances g that scale the amplitude of the signals ( I ^ext ) depending on the total tension reached in time. The amplitudes of each signal are also reduced, exponentially, with a time constant im that can vary if the conductance is varied. A threshold voltage can be selected, above which a binary state can be signaled at output 2355.

In some implementations, the integrator 2500 may operate in accordance with a model in which a conductance-based stress evolution is extended to include stress drop within the cables, which is described in the Telegraphy Equation provided by :

where X is a constant of length determined by the properties of the branches, x is a digitized unit of length along the branches and V ^l is the equilibrium voltage.

In this model, the signals at inputs 2350 are integrated using Equation 1 or Equation 2 above and by additional linear summation where each signal at inputs 2350 can propagate along the physical branches of the system to all other inputs. 2350. While reducing in amplitude in accordance with the length constant X as the signal propagates, each signal at inputs 2350 contributes, to some extent, to the amplitude at each input 2350. The amplitude of any signal at the Input 2350 is therefore the amplitude of that signal plus the sum of all the amplitudes of other signals at inputs 2350 after each of them has uniquely decreased while propagating to the location of the example input 2350. A threshold voltage can be selected, above which a binary state can be signaled at output 2355.

In some implementations, integrators 2600, 2700 may operate in accordance with a neural network model where all nodes are directly or indirectly interconnected through other nodes. In such integrators, any node can serve as an output. In some implementations, the 2600, 2700 integrators may operate according to a model provided by:

dV

c «'^ - = E M k _ ^ & ■ ('> Equation 4

1 = 1

where Ii ( t) is the current injected by input i at time t and where there are n inputs to a neuron.

In this model, the signals at inputs 2350 are made up of network processing elements 2605 that are modeled by Equations 1, 2 or 3 above, creating additional internal inputs 2610 for each element 2605, allowing a non-summation. -linear and parallel of all the inputs 2350 to obtain the output 2355. Any of the processing elements 2605 can be selected to signal binary states of the network as output 2355.

The integrators 2400, 2500, 2600, 2700 can be used as compressor 29 (Figure 1A).

Figure 28 is a schematic representation of a binary-to-analog converter 2305. The binary-to-analog converter 2305 can be used, for example, in an encoder, time series scanner, or weighting device. The binary-to-analog converter 2305 may, therefore, in some implementations, be a reference binary-to-analog converter as described below.

The binary-to-analog converter 2305 is a component that is configured to weight the amplitude of individual events in a time series of input events as a function of the timing of other events in the input time series. In some implementations, the events can be weighted using a non-linear function. For example, binary-to-analog converter 2305 can use multiple time-function parameters to generate individual weighting weights for each individual event based on the timing of predecessor events within an input signal. The binary-to-analog converter 2305 can apply the generated weights to individual events, for example, multiplying the events by the weights and generating the weighted events at relative times that correspond to the timing of the unweighted events within the input signal.

The binary-to-analog converter 2305 includes an input 2325 and an output 2330. The input 2325 receives a signal 2805 that includes a time series of events. For example, input 2325 may receive a time-function code signal 135 or a signal output from a compressor encoder 2205. Output 2330 provides a signal 2810 that includes the weighted events at relative times that correspond to the timing of the events. not weighted within the input signal.

In some implementations, the binary-to-analog converter 2305 may include a reset mechanism that resets the weighting of the amplitude of individual events to a known state. The reset mechanism can be triggered, for example, by the presence of a foot event 530 within a foot range 520 of a signal 135 (Figure 5). Resetting the weight can stop the evolution of parameters as a function of time and return these parameters to known values. In other implementations, the binary-to-analog converter 2305 may go idle without an initiator, for example, over time.

In some implementations, the parameters used by the binary-to-analog converter 2305 may appear in time-dependent differential equations. For example, the binary-to-analog converter 2305 can use three time-dependent parameters (U, id, if in the following equations) and one non-time-based parameter (A in the following equations) to generate individual weighting weights. In some implementations, the amplitude Ak of the k-th event in the signal where the events (1, ..., k) are separated by times (Ak, ..., Ak ^-1 ) can be given by:

Ak - A ■ uk - \ | / ¿Equation 5

- TO

ut = U (1 - U) exp (---—) Equation 6

where y and pk are hidden dynamic variables (pe [0,1]; (ye [0,1]) with initial values of y1 = 1 and p1 = U for the first event. The variable y can represent, for example, the fraction of resources available at the time of each event. The variable p can represent, for example, the fraction of resources used by each event. In some implementations, both variables can evolve with each event and provide that the amplitude of the response to each event in a signal is different and reflects the temporal record of events in that signal.

The way in which these dynamic variables evolve and the period of time during which each response accumulates information about the temporal register of the signal depends on the values of the parameters as a function of time (U, id, if). The U parameter can set the maximum resources available for the first event, which slices the maximum possible response (provided by A). Therefore, A ¹ = AU. The id parameter is a time constant for resource recovery after use. The if parameter is a time constant for recovery from a facilitation of pk in some magnitude (usually p).

By assigning different values to the parameters U, id, if, different binary-to-analog converters 2305 will generate different sequences of amplitudes in response to an identical sequence of input events. In some implementations, more complex time dependencies can be achieved by using double or higher order exponentials for one or both id, if parameters. In some implementations, more complex time dependencies can be achieved by using a time-dependent function to represent one or both of id, if, and making U a stochastic variable or function bound to the parameters themselves.

In some implementations, the binary-to-analog converters 2305 may be implemented as described in one or more of the following: US Patent Publication 2003/0208451; US Patent 5,155,802; US Patent 5,537,512; US Patent 6,363,369; and US Patent 4,962,342. For example, the 2305 binary-to-analog converters can be implemented as a device that includes a network of signal processors interconnected by one or more processing junctions that dynamically adjust the response intensity according to the time pattern of events on signal 2805 and thus simulates a "dynamic synapse" as described in US Patent 6,363,369. Processing junctions can receive and process a previous junction signal from a signal processor at the network to obtain a binding signal that generates a subsequent binding signal to a second signal processor in the network.Each processing junction can be configured so that the binding signal has a dynamic dependence on the pre-binding signal.

Figure 29 is a schematic representation of the weighting of the amplitude of individual events in a time series of events as a function of the timing of other events in the time series. The weighting illustrated can be performed by a binary-to-analog converter, such as a binary-to-analog converter 2305 (Figure 28). In the illustrated implementation, signal 135 is a time-function code signal that encodes information by timing the occurrence of events within time intervals. For example, signal 135 may be a time-code signal emitted from a decoder 105 (Figures 1, 2, 4, 6, 8). Signal 135 is weighted to form a time-weighted 2900 signal.

Weighted time signal 2900 includes a sequence of time slots 2905, each of which includes a respective event 2910. Events 2910 occur at times 2915 within respective slots 2905.

In the illustrated implementation, events 2910 are pulses that go from a baseline state (ie, a "sleep" state) 2920 to a high state (ie, an "energized" state) 2925 and then return. to the idle state of the baseline 2920. The high state level 2925 differs for different events 2910. The high state level 2925 is the amplitude of event 2910 and a result of the weighting. The high state level 2925 (that is, the amplitude of each event 2910) incorporates the timing of that event 2910 within signal 135 and the timing of other events 2910 within signal 135. In other words, the encoded information by timing two or more events 2910 within signal 135 are embedded within the amplitudes of each event 2910. As previously described, in some implementations, the amplitudes of each event 2910 may incorporate timing only of predecessor events 2910.

In the illustrated implementation, weighting the events in the time-function code signal 135 changes the amplitude of those events while retaining the timing information within the range and within the signal. In particular, the illustrated time-weighted signal 2900 includes a set of time intervals 2905, each of which corresponds to a respective interval 320 in signal 135. This correspondence is represented by arrows 2930. In the illustrated implementation, some 2910 events increase in amplitude with respect to the respective corresponding 205 events and some 2910 events decrease in amplitude with respect to the respective corresponding 205 events.

The corresponding time slots 2905, 320 each include a respective event 2910, 325 that encodes information. The position of the events 2910, 320 within the respective corresponding time slots 2905, 325 is the same. For example, when event 320 occurs at the start of a time interval 325, event 2910 in the corresponding time interval 2905 also occurs at the start of that interval. By way of another example, when an event 320 occurs in the middle of a time interval 325, event 2910 in the corresponding time interval 2905 also occurs in the middle of that interval. In the illustrated implementation, the duration of the corresponding intervals 2905, 325 is the same. Furthermore, the order of corresponding intervals 2905, 325 with respect to other intervals 2905, 325 within a respective signal 2900, 135 is the same.

Figure 30 is a schematic representation of a signal 2365 implementation. Signal 2365 may be output from a compressor encoder 2205 of a device such as a mobile phone transmitter or a disk drive head. Signal 2365 can be a one-dimensional signal and can be a one-dimensional signal 29 (Figure 1A).

The signal 2365 includes a synchronized series of events 3005. The events 3005 are separated from each other by time intervals 3010. The duration of the time intervals 3010 incorporates the integration of the amplitude sequences that include weighted events, for example, signal of time weighted 2900.

In the illustrated implementation, events 3005 are pulses that go from a baseline state (ie, a "sleep" state) 3015 to a high state (ie, an "energized" state) 3020 and then return. to the rest state of the baseline 3015. In some implementations, the shapes of the different events 3005 may be indistinguishable from each other and the different events 3005 may be distinguished only by virtue of their timing.

The number of time intervals 3010 for a provided signal 2365 within a unit of time can be selected to fit a predetermined probability distribution. In some implementations, the probability distribution may be skewed and skewed, for example, to the left of its median. In some implementations, the standard deviation of the probability distribution may be approximately equal to the square root of the mean of the probability distribution. For example, in some implementations, the number of time intervals 3010 within a time unit can be distributed according to the Poisson model.

In some implementations, signal 2365 may be added, overlaid, or otherwise transmitted along with additional information. For example, events 3005 can be added to a modulated or shifted analog or digital signal and thus resemble noise in that signal. Such implementations are particularly relevant for the communication of covert or encrypted data. For example, events 3005 can be transmitted along with a frequency modulated analog signal that transmits unimportant information such as, for example, a radio transmission. To the uninformed observer, events 3005 would appear to be noise on this second signal. The information content encoded by events 3005 can therefore be disguised.

Figure 31 is a schematic representation of a data storage device 3100. The data storage device 3100 is a component in which information can be stored and from which stored information can be accessed. For example, data storage device 3100 can be an optical disk, magnetic disk, magnetic tape, record album, punch card, barcode label, or other data storage device.

Data storage device 3100 includes a set of detectable physical manifestations 3105. Physical manifestations 3105 are structural elements that can be detected or discovered by a data storage device reader. For example, physical manifestations 3105 can be the holes or bumps on an optical disc that are detectable by an optical disc reader. By way of another example, physical manifestations 3105 may be magnetized magnetic disk or tape elements that are detectable by a magnetization sensor. By way of another example, physical manifestations 3105 may be the characteristics of a record album that are detectable by the stylus of a record player.

Physical manifestations 3105 are arranged and placed in sequence along routes 3110. Routes 3110 guide the storage and access of data and can be, for example, tracks, slots, a magnetic tape or the length of a code of bars. The physical manifestations 3105 along each route 3110 are separated from each other by distances 3115. The lengths of the distances 3115 can be scaled to correspond to the times between events in a signal. For example, the lengths of distances 3115 can be scaled to correspond to the duration of time intervals 3010 in signal 2365 (Figure 30).

During data writing to the data storage device 3100, the speed of relative movement between the paths 3110 of the data storage device 3100 and a writing apparatus of the data storage device can transform the times between events into said signals. at the position of 3105 physical manifestations along the routes. 3110. During data reading from data storage device 3100, the speed of relative movement between paths 3110 of data storage device 3100 and a reader of data storage device can transform the position of physical manifestations 3105 to along routes 3110 in times between events on those signals. In some implementations, the speed of relative movement during reading and writing need not be constant, but may vary, for example, based on the position of a path 3110 in the data storage device 3100.

The number of distance lengths 315 within a unit length can be selected to fit a predetermined probability distribution. In some implementations, the probability distribution may be skewed and skewed, for example, to the left of its median. In some implementations, the standard deviation of the probability distribution may be approximately equal to the square root of the mean of the probability distribution. For example, in some implementations, the number of lengths of distances 315 within a unit of length can be distributed according to the Poisson model.

In operation, a data storage device writer may receive a signal that characterizes a synchronized series of events, such as signal 2365. The data storage device writer may write physical manifestations 3105 along of one or more routes 3110 in the data storage device 3100 so that the lengths of the distances 3115 are scaled to correspond to the times between events in the signal. The data storage device 3100 can maintain or "store" the physical manifestations 3105 and the lengths of distances 3115 that separate the physical manifestations 3105.

By accessing the stored information, a data storage device reader can measure the lengths of the distances 3115 that separate physical manifestations 3105 along one or more routes 3110 in the data storage device 3100. The measurements are made. they can be converted into a signal that characterizes a synchronized series of events, such as signal 2365 (Figure 30). For example, the data storage device reader may output signal 2365 so that the duration of the time intervals are scaled 3010 to correspond to the lengths of the distances 3115. In some implementations, the device reader The data storage device and the writing apparatus of the data storage device may be the same device.

Figure 32 is a schematic representation of an implementation of a system where information can be decoded, namely, a 3200 system. The 3200 system includes a 2100 multichannel decoder and a 3205 expander decoder.

The expander decoder 3205 is a component that expands one or more input signals into a set of output signals. The expander decoder 3205 includes an input 3210 and a set of one or more outputs 3215. The input 3210 receives a signal 2365 from a support system or means 140. The expander decoder 3205 expands the signal 2365 and outputs a set of one or more signals where the information is encoded by synchronizing the occurrence of events within time intervals on one or more outputs 3215 to the multi-channel decoder 2100.

The 3200 system can be used in isolation or in conjunction with other devices. For example, the 3200 system can be used as a weight expander 37, amplitude decoder 39, and time function decoder 41 (Figure 1A).

Figure 33 is a schematic representation of an implementation of an expander decoder 3205. The decoder 3205 is a component that decodes information in a signal that includes a synchronized series of events in a time-based code signal where the information is encoded by the synchronization of the occurrence of events within time intervals. Decoder 3205 can thus decode a signal like signal 2365 (Figure 30) into a signal like signal 1220 (Figure 12).

In addition to input 3210 and one or more outputs 3215, decoder 3205 includes weighting device 3310 and time series scanner 3315. Weighting device 3310 is a component for weighting. events in a signal that includes a synchronized series of events. The 3315 time series scanner is a component that searches for a time series that, when input into a binary-to-analog converter with the appropriate reference, provides a time-function code signal where the information is encoded by the timing of the occurrence of events within the time intervals.

Input 3210 of expander decoder 3205 receives signal 2365. Signal 2365 includes a synchronized series of events. Weighting device 3310 is coupled to input 3210 and also includes output 3335. Output 3335 provides a net series of events of amplitude 3340.

The time series scanner 3315 includes an input 3345 and is coupled to the output 3215 of the decoder 3305. The input 3345 receives the events 3340 and provides a time-based code signal where the information is encoded by the timing of the occurrence of events within time intervals. For example, output 3215 can provide a signal 135 to a system or media.

The expander decoder can be used in isolation or in conjunction with other devices. For example, the expander decoder can be used as a weight expander 37 and an amplitude decoder 39 (Figure 1A).

Figure 34 is a schematic representation of a weighting device 3310. The weighting device 3310 is a component for weighting events in a signal that includes a synchronized series of events. For example, weighting device 3310 may weight events 3005 of signal 2365 (Figure 30). As described below, the weights with which the weighting device 3310 weights the events can be selected based on the success of rendering a mathematical or other operation on a particular signal on an input channel 2340 of a 2205 Compressor Encoder (Figure 23). For example, in some implementations, the weights with which the weighting device 3310 weights the events may be selected to perform one or more data compression and encryption operations on signals on the input channel 2340, data processing operations. text on signals on input channel 2340, number processing operations on signals on input channel 2340, image processing operations on signals on input channel 2340, and signal processing operations on signals on input channel 2340. Weighting device 3310 may be part of expander decoder 3205 (Figure 33).

Weighting device 3310 includes input 3210, output 3335, set of binary-to-analog converters 2305, set of multipliers 3440, set of weighting weights 3445, and adder 3465. Input 3210 receives signal 2365 which includes a synchronized series of events. Input 3210 distributes signal 2365 to inputs 2325 of binary-to-analog converters 2305. Each binary-to-analog converter 2305 weights the amplitude of individual events in a time series of input events as a function of the timing of other events in the input time series. For example, each binary-to-analog converter 2305 can use multiple time-function parameters to generate individual weighting weights for each individual event based on the timing of predecessor events within the 2365 signal. In general, each binary-to-analog converter 2305 applies the weights generated for individual events, for example, by multiplying the events by the weighting weights and providing the weighted events at relative times that correspond to the timing of the unweighted events within the 2365 signal.

In some implementations, the binary-to-analog converter assembly 2305 can be constructed using a process such as process 3900 (Figure 39). In some implementations, the set of binary-to-analog converters 2305 in the weighting device 3310 may be the full set of binary-to-analog converters constructed using the 3900 process.

Each binary-to-analog converter 2305 includes output 2330 where the weighted synchronized series of events 3430 is provided. The weighted synchronized series of events 3430 is provided as input to a respective multiplier 3440. Multipliers 3440 are components that are configured to multiply a weighted synchronized series of events by another weight 3445. As described below, weight weights 3445 can be determined during a training process. For example, each weighting weight 3445 can be determined according to the success of a corresponding binary-to-analog converter 2305 in representing a particular input signal 135 on a channel 2340 of a compressor encoder 2205. By way of another example, the weights Weights 3445 can be determined in accordance with the success of a respective binary-to-analog converter 2305 in representing a mathematical or other operation on a particular signal 135 input to a channel 2340 of a compressor encoder 2205.

Each weighting weight 3445 may be received by a multiplier 3440 at a respective input 3450. Weighting weights 3445 may be stored, for example, in one or more data storage devices. The multipliers 3440 are components that scale the weighted synchronized series of events 3430 received at input 3435 in accordance with the weighting weight 3445. The multipliers 3440 can scale the weighted synchronized series of events linearly or non-linearly. For example, in some implementations, multipliers 3440 may use weighting weights 3445 as scalar weights and multiply the weighted events in each synchronized series by a corresponding weight 3445. In some implementations, multipliers 3440 may use weighting weights 3445 to scale multiple weighted events at each nonlinear or other serial sync.

Each multiplier 3440 generates the series of scaled and weighted events 3455 synchronized on an output 3450 that is coupled to the inputs 3460 of an adder 3465. The adder 3465 is a component that adds these scaled and weighted events 3455 at each moment of the input of the weighted and scaled synchronized series to generate a net series of events of amplitude 3470.

In some implementations, the adder 3465 may include a dynamic threshold to generate an amplitude event in the net series 3470. A dynamic threshold is a threshold that changes. The dynamic threshold can be a lower limit for the inclusion of an amplitude event in the net series 3470. In other words, if the sum of the weighted and scaled events for the first time is below the lower limit, this sum is not calculated. includes in the net series 3470 even if the sum is not zero. The dynamic threshold can be changed to control the number of amplitude events in the 3470 net series. For example, the dynamic threshold can be changed to ensure that the number of amplitude events in the 3470 net series is identical to the number of events in input signal 2365. In some implementations, adder 3465 first adds the scaled and weighted events at each point in time of the input weighted and scaled synchronized series, and then the dynamic amplitude is gradually reduced until the number of amplitude events in the net series 3470 is identical to the number of events in signal 2365. The above allows the same dynamic threshold to be applied for the entire net series 3470.

In the illustrated implementation, the amplitude events within the net series 3470 are separated by non-uniform periods. This is not necessarily the case. Instead, the adder 3465 can generate the amplitude events within the net string 3470 without timing information. In light of the dynamic threshold described above, the adder 3465 may in effect generate a list of the amplitudes of the highest amplitude events as a net series 3470 without describing the time between those events. The order of the amplitudes in this list may correspond to the order in which these events occurred.

Figure 35 is a schematic representation of the weighting of the amplitude of individual events in a time series of events as a function of the timing of other events in the time series. The weighting illustrated can be performed by a binary-to-analog converter, such as a binary-to-analog converter 2305 (Figure 28). In the illustrated implementation, signal 2365 includes a synchronized series of events 3005 that are separated from each other by time intervals 3010. The duration of time intervals 3010 represents the integration of the amplitude sequences that include weighted events. Thus, signal 2365 can be output, for example, from an integrator such as one of integrators 2310, 2400, 2500, 2600, 2700.

Signal 2365 is weighted to form a time-weighted signal 3500. Time-weighted signal 3500 includes a set of events 3505 that are separated from each other by time intervals 3510.

In the illustrated implementation, events 3505 are pulses that go from a baseline state (ie, a "sleep" state) 3520 to a high state (ie, an "energized" state) 3525 and then return. to the idle reference state 3520. The level of the high state 3525 differs for different events 3505. The level of the high state 3525 is the amplitude of the event 3505 and a result of the weighting. The high state level 3525 (that is, the amplitude of each event 3505) incorporates the time of that event 3505 within signal 2365 and the time of at least some of the other events 3505 within signal 2365. In other words Thus, the information encoded by the timing of two or more events 3505 within signal 2365 is embedded within the amplitudes of each event 3505. As previously described, in some implementations, the amplitudes of each event 3505 may incorporate timing of predecessor events 3505 only.

In the illustrated implementation, some events 3505 increase in amplitude with respect to the respective corresponding events 2365 and some events 3505 decrease in amplitude with respect to the respective corresponding events 2365.

The time intervals 3510 between the occurrence of events 3505 within the weighted time signal 3500 are scaled to time intervals 3010 between the occurrence of events 3005 within 2365. In the illustrated implementation, the time intervals 3510 are scaled one by one at time intervals 3010. In other words, the time interval 3010 that separates a first pair of events 3005 is identical to the time interval 3510 that separates a pair of events 3505 that corresponds to the first pair.

Figure 36 is a schematic representation of a 3315 time series scanner. The 3315 time series scanner is a component that searches for a time series which, when input into a properly referenced binary-to-analog converter, provides a code signal as a function of the time where the information is encoded by the synchronization of the occurrence of events within time intervals. For example, time series scanner 3315 may scan a time-function code signal 135 that approximates or is the same as time-function code signal 135 input on a channel 2340 of a compressor encoder 2205 (Figure 23).

The time series scanner 3315 includes an input 3345 and an output 3215. The input 3345 receives the net series 3470 of amplitudes or amplitude events. Input 3345 transports the net string 3470 to an input 3620 of an amplitude buffer 3625. The amplitude buffer 3625 is a component that stores the amplitudes in the net string 3470 for comparison with a comparator 3635. In some implementations , the amplitude buffer 3625 may include a cache or other memory that stores the magnitudes of the amplitudes or amplitude events of the net series 3470. In implementations where the net series 3470 includes time information, the buffer of amplitude 3625 may include components to remove the time information from the net series 3470 without losing the amplitude information. The amplitude buffer 3615 includes an output 3630 that provides the buffered amplitudes to an input 3640 of the comparator 3635.

The comparator 3635 also includes an input 3645 and an output 3650. The comparator 3635 is a component that compares amplitudes at input 3640 with amplitudes at input 3645 and generates an indication of the result of the comparison at output 3650. The result of the comparison Comparison incorporates the differences between the amplitudes at the inputs 3640, 3645. For example, when the differences between the amplitudes at the inputs 3640, 3645 are very small, the output 3650 may generate a small signal.

The comparator 3635 compares the amplitudes stored in the amplitude buffer 3615 with the output amplitudes of a reference binary-to-analog converter 2305. Although shown as a single component, the comparator 3635 may include a set of comparators that are connected to compare individual amplitudes, e.g. eg in parallel. In other words, a first comparator may compare a first buffered amplitude of amplitude 3625 with a first amplitude output of the reference binary-to-analog converter 2305, a second comparator may compare a second buffered amplitude of amplitude 3625 with a second amplitude output from the reference binary-to-analog converter 2305, and so on. The results of individual comparisons of such a set of comparators can be converted into a set of one or more outputs.

The output (s) 3660 of the comparator 3635 are provided to an input 3665 of a time-code permutator 3670. The time-code permutator 3670 is a component that permutes a time-based code in response to feedback from the outputs. 3660. In particular, the time-based code permuter 3670 permutes a time-based code to minimize the differences between the amplitudes at the inputs 3640, 3645 of the comparator 3635. The time-based code permuter 3670 generates a time-based code candidate 3675 over a 3680 output. As described below, the candidate time function code is proposed as a solution that approximates a 135 time function code signal input to a channel 2340 of a 2205 compressor encoder (Figure 23) . For example, the time code permuter 3670 may use successive approximations to generate candidate time codes 3675.

Code 3675 is provided to an input 2325 of reference binary-to-analog converter 2305. Reference binary-to-analog converter 2305 is a component that can weight the amplitude of individual events of the candidate time function code as a function of timing. from other events in the candidate time function code, for example, using multiple time function parameters to generate individual weights for each individual event based on the timing of the predecessor events within the time function code. The reference binary-to-analog converter 2305 can generate weighted events at relative times corresponding to the timing of the unweighted events within the candidate time-function code or without timing information. In other words, the reference binary-to-analog converter 2305 can generate an ordered list of amplitude weights without describing the time between those events in the input candidate time code. In some implementations, the reference binary-to-analog converter 2305 may include a buffer, cache, or other memory that stores the magnitudes of the weights or weighted amplitudes.

In some implementations, the reference binary-to-analog converter 2305 may be identical to a binary-to-analog converter 2305 of the compressor encoder 2205 (Figure 23). For example, the time-function parameters used by reference binary-to-analog converter 2305 on time-series scanner 3315 may be identical to the time-function parameters, used by binary-to-analog converter 2305 on channel 2340.

In some implementations, the time code permutator 3670 may also include a comparator that compares the feedback provided by the outputs 3660 to a threshold level that incorporates an acceptable amount of difference between the amplitudes at the inputs 3640, 3645 of the comparator 3635. Time function code permutator 3670 may permute the candidate code based on time until the acceptable amount of difference is reached. In other words, in implementations where fidelity is very important, the threshold level may be stricter and set to require that the difference between the amplitudes at the inputs 3640, 3645 of the comparator 3635 be relatively small or null. In such circumstances, the time code permuter 3670 will generally perform relatively more permutations. In implementations where fidelity is less important and factors such as speed are more important, the threshold level may be less stringent and set to allow the difference between the amplitudes at inputs 3640, 3645 of comparator 3635 are relatively large. In such circumstances, the time-code permutator 3670 will generally perform relatively fewer permutations. In some cases, the acceptable magnitude of difference between the amplitudes at the inputs 3640, 3645 of the comparator 3635 can be reached after more or fewer permutations than are generally required. For example, the time-based code permuter 3670 may, by chance, generate a candidate time-based code after very few permutations that satisfy even a very strict threshold level. In some implementations, the threshold stringency may be tunable, for example, by a user, to operate in different contexts.

In response to feedback from outputs 3660 that reach or cross the threshold level, time-function code permutator 3670 may output a select signal 3685 on an output 3690. Select signal 3685 is an indication that the difference Between the amplitudes at the inputs 3640, 3645 of the comparator 3635 has reached an acceptably small level. Selection signal 3685 can be configured to close a 3690 breaker, thus connecting output 3215 to code 3675. The foregoing transmits candidate time function code 3675 to output 3215 for output to the system or media. stand 140 at sign 135.

Figure 37 is a schematic representation of a 3205 expander decoder, that is, a 3700 multi-channel expander decoder. The 3700 decoder is a component that decodes information in a signal that includes a synchronized series of events in a time-dependent code signal in where the information is encoded by the synchronization of the occurrence of events within time intervals. Decoder 3700 can thus decode a signal such as signal 2365 (Figure 30) into a set of signals 135. Decoder 3700 can be used in isolation or in conjunction with other devices. For example, decoder 3700 can be used as a weight expander 37 and an amplitude decoder 39 (Figure 1A).

Decoder 3700 includes a set of weighting devices 3310, a time series scanner set 3315, an input 3710, and a set of one or more outputs 3715. Each weighting device 3310 is paired with a corresponding time series scanner 3315. These pairs can form a set of decoding channels 3717 in decoder 3700. Decoder 3700 is thus a parallel combination of multiple decoding channels 3717, each of which forms a separate expander decoder 3205.

In decoder 3700, each weighting device 3310 can weight events using an associated set of binary-to-analog converters 2305 and an associated set of weights 3445. In some implementations, at least some of the binary-to-analog converters 2305, at least some of the weighting weights 3445 of different weighting devices 3310, or both, will be different. For example, in implementations where the 2305 binary-to-analog converter set is a complete 2305 binary-to-analog converter set constructed using a process such as the 3900 process (Figure 39), the same 2305 binary-to-analog converters can be included. in all weighting devices 3310 in the multi-channel expander decoder 3700. However, at least some of the weighting weights 3445 of different weighting devices 3310 will be different. For example, in some implementations, many 3445 weight weights from different 3310 weight devices will be zero or close to zero, but some 3445 weight weights will not. As a consequence of these differences, when the same synchronized series of events is input to different weighting devices 3310, each weighting device 3310 will generally generate different net series of amplitude events. However, this is not necessarily the case, as chance can result in different 3310 weighting devices providing the same net series of amplitude events despite different 2305 binary-to-analog converters and 3445 weighting weights.

In the 3700 decoder, each 3315 time series scanner can scan a time code signal using different components. For example, each 3315 time series scanner may include a different reference binary-to-analog converter 2305. For example, the 2305 binary-to-analog reference converter in each 3315 time series scanner may be identical to the 2305 binary-to-analog converter of a Channel 2340 of a 2205 Compressor Encoder (Figure 23).

As a consequence of the different components in different 3315 time series scanners, different 3315 time series scanners generally generate different time series even in response to the same net series of amplitude events that are received on the 3345 inputs. Differences between different 3315 time series scanners will provide different time series even in cases where, due to circumstances, the same time series is generated by different 3315 time series scanners. In addition, different 3315 time series scanners can provide different Occasionally the same time series in response to different net series of amplitude events received at inputs 3345.

The input 3710 of the decoder 3700 receives a signal 2365. The signal 2365 includes a synchronized series of events. Input 3700 distributes signal 2365 to inputs 3210 of weighting devices 3310. The same single signal 2365 is thus input to different weighting devices 3310 in the array.

The one or more outputs 3215 of each time series scanner 3315 generate a time-function code signal 3725 wherein the information is encoded by timing the occurrence of events within time intervals. Each signal 3725 transmits a time-function code to a respective output 3715 of the 3700 decoder. One or more outputs 3715 provide time-function code signals 135 where the information is encoded by timing the occurrence of events within time intervals. to P. eg, a support system or means 140.

Figure 38 is a schematic representation of one implementation of a system where information can be encoded and decoded, namely a 3800 system. The 3800 system includes the 2200 system (Figure 22) and the 3200 system (Figure 32). . System 3800 can be, for example, a data storage system, a communication system, and / or a data compression system. The 3800 system can be used in isolation or in conjunction with other devices. For example, the 3800 system can be used as a time function encoder 25, amplitude weighting component 27, compressor 29, weight expander 37, amplitude decoder 39, and time function decoder 41 (Figure 1A).

In the 3800 system, the multichannel time encoder 1105 receives the signal 125 and provides a set of time-code signals at the outputs 1115. The time-code signals are received by one or more compression encoding inputs 2210, which compresses the received time-code signals and provides a compressed signal 2220 at the output 2215 to the support system or means 140. The expander decoder 3205 receives the signal 2365 from the support system or means 140 at the input 3210. The expander decoder 3205 expands signal 2365 and provides a set of one or more signals wherein the information is encoded by synchronizing the occurrence of events within time slots on one or more outputs 3215 to the multi-channel decoder 2100. The multi-channel decoder 2100 receives the signals and decodes them and adds them to the output signal 1230 which expresses information in a finite ordered set of digits. discreet coughs.

Figure 39 is a flow diagram of a process 3900 for building a set of binary to analog converters. For example, the 3900 process can be used to build 2305 binary-to-analog converters on a 3310 weighting device (Figure 34). As another example, process 3900 can be used to build binary-to-analog converters in a 2205 compressor encoder (Figure 23). As another example, process 3900 can be used to build reference binary-to-analog converters in time series scanner 3315 (Figure 26). The 3900 process can be done in isolation or in conjunction with other activities. For example, process 3900 can be part of a process 4100 (Figure 41) to create an encoder / decoder pair. Process 3900 can be performed by one or more data processing devices.

As previously described, a set of binary-to-analog converters can use multiple parameters as a function of time to generate individual weighting weights for individual events in a time series of events as a function of the timing of occurrence between events in an input signal. . In some implementations, the weights can be generated based on the timing of predecessor events within the input signal. At step 3905, a range of possible values is assigned for each time-function parameter. For example, time-function parameters can be constrained to be within the same normalized range, for example, between zero and one.

Several discrete values can be identified within each range (step 3910). In some implementations, the discrete values can be distributed within each range so that they are all separated from their nearest neighbor by a single distance. For example, for a time-function parameter assigned a margin between zero and one, five separate values of zero, 0.25, 0.5, 0.75, and one can be identified. In some implementations, the discrete values are not distributed evenly within each range, but rather are distributed according to their use in binary-to-analog converters. For example, the values of a time-dependent parameter appearing in a non-linear function can be distributed according to the position of the time-function parameter in the non-linear function. In some implementations, the number of discrete values within each range can be selected to be approximately equal to or greater than the number of pairs of the 3310 weighting device and 3315 time series scanner within a 3700 multichannel expander decoder (Figure 37).

One of the identified discrete values is selected for each parameter used by a binary-to-analog converter (step 3915). The values can be selected by a random or non-random process. In some implementations, a selected value of a given parameter may be excluded from being selected again for that parameter. To this end, this would require that the built-in binary-to-analog converters have different values for each parameter. In these implementations, if there are N discrete values within each range of Y different parameters, a number (N * Y) possible combinations of values can be selected.

In some implementations, the same value can be selected multiple times for multiple binary-to-analog converters. For example, binary-to-analog converters can be constructed using a comprehensive combinatorial set of the identified values. For example, if there are N discrete values within each range of Y different parameters, a number (NY) of possible combinations of values can be selected.

In some implementations, the same value can be selected multiple times for multiple binary-to-analog converters, but the combinatorial set of identified values need not be exhaustive. For example, if there are N discrete values within each range of Y different parameters, a number greater than (NY) but less than (NY) possible combinations of values can be selected.

A binary-to-analog converter can be constructed using the selected values (step 3920). A check can be performed to determine if the desired number of binary-to-analog converters have been built (step 3930). In some implementations, the desired number of binary-to-analog converters will be large enough that, for a single time series of input events, almost any weighted time series possible for a given set of parameters and their margins can be generated. by some linear superposition of one or more outputs of the binary-to-analog converters in the set. If the desired number of binary-to-analog converters have not yet been built, the process returns to select additional parameter values and build an additional binary-to-analog converter (steps 3915, 3920). If the desired number of binary-to-analog converters have been built, a device can be assembled using the built-in binary-to-analog converters (step 3935).

Figure 40 is a flow chart of a process 4000 for calibrating a weighting device. For example, process 4000 can be used to calibrate weighting devices such as weighting device 3310 (Figure 34). Process 4000 can be used in isolation or in conjunction with other activities. For example, process 4000 can be part of process 4100 (Figure 41) to create an encoder / decoder pair. Process 4000 can be performed, for example, by one or more digital data processing devices.

One or more known time-code signals can be input into the channels of a multichannel encoder (step 4005). For example, the system may input one or more known time-function code signals 135 (Figure 3) into inputs 2315 of compressor encoder 2205 (Figure 23). In some implementations, the same time function code signal 135 may be input to all channels.

The output signal of the multichannel encoder can be identified, as well as the amplitude-weighted time series for each channel in the multichannel encoder (step 4010). In some implementations, the system may store an amplitude-weighted time series description and the output of the multichannel encoder. For example, in some implementations, the system may store the output signal of the multichannel encoder in a data storage device 3100 (Figure 31).

The output signal from the multichannel encoder is provided as an input to an uncalibrated multichannel expander decoder (step 4015). The multichannel decoder is not calibrated because it has not been calibrated to work in conjunction with the multichannel encoder that generated the particular output signal (ie, the multichannel encoder from which the output signal is received in step 4010).

The net series of amplitude events for each channel of the multichannel expander decoder is identified and compared to the amplitude-weighted time series of a corresponding channel (step 4020). In some implementations, such comparisons may include measuring the amplitudes of the events, but disregarding the timing of the events for both the net amplitude event series and the amplitude-weighted time series for a given channel. For example, in some implementations, the system may form a sequential list of the amplitudes of the events in the amplitude-weighted time series and a sequential list of the amplitudes of the events in the net series of amplitude events. These lists do not describe the timing of events in either the amplitude-weighted time series or the net amplitude event series. However, the amplitudes in the list can be compared to determine the differences. In general, the results of the comparison are expressed on a channel-by-channel basis. However, in some implementations, the comparison results may be expressed in a value that incorporates the multi-channel comparison.

In some implementations, the net series of amplitude events is compared to the result of a mathematical or other operation performed on the amplitude-weighted time series of a corresponding channel. For example, if a weighting device is to be calibrated to multiply a particular channel by two, the amplitude-weighted time series for that channel can first be multiplied by two and the result of that multiplication can be compared to the net series of amplitude events. The weighting weights can then be used to perform mathematical or other operations. For example, weighting weights can be selected to perform one or more data compression and encryption operations, word processing operations, numerical processing operations, image processing operations, and signal processing operations. In some implementations, different channels in a single device may use weighting weights that perform different operations.

A determination is made as to whether the differences between the net amplitude event series and the amplitude-weighted time series of the corresponding channels are small enough (step 4025). For example, in some implementations, the system performing process 4000 may compare the differences to a threshold incorporating an acceptable level of differences on a channel-by-channel basis. In some implementations, the threshold stringency may be tunable, for example, by a user, to operate in different contexts.

In response to the determination that the differences between the net amplitude event series and the amplitude-weighted time series of the corresponding channels are not small enough, the weights of the weighting devices are adjusted (step 4030). In some implementations, the weights are adjusted on a channel-by-channel basis. For example, the system may identify the weights of the weighted synchronized series of events emitted by individual binary-to-analog converters 320 that most closely resemble the amplitude-weighted time series. The weighting weights 345 that are associated with those weighted synchronized series of events can be increased. By way of another example, the system may identify the weights of the weighted clock series of events emitted by individual binary-to-analog converters 320 that differ further from the amplitude-weighted time series. The weighting weights 345 that are associated with those weighted synchronized series of events can be decreased.

In some implementations, the input of the output signal from the multichannel encoder to the multichannel decoder may be repeated after incremental adjustments in the weighting weights. The results of comparisons between successive net series of amplitude events with the amplitude-weighted time series of a corresponding channel can be taken as an indication of whether the incremental adjustments have been appropriate. In other words, if the net series of amplitude events more closely resembles the amplitude-weighted time series for a given channel, adjustments to that channel can be viewed as favorable and further adjustments made. For example, the weighting weights can be further increased or decreased as the case may be.

On the other hand, if the differences between the net series of events of amplitude and the time series weighted in amplitude increase, the adjustments to a channel can be taken as unfavorable and the weights can be returned to their previous values or changed in a different sense. For example, the weight weights that were initially increased can be decreased and the weights that were initially decreased can be increased.

One or more new time-code signals are selected (step 4035) in response to determining that the differences between the net series of amplitude events and the amplitude-weighted time series of the corresponding channels are not small enough. In some implementations, the new time-based code signals may be selected in accordance with the differences between the new time-based code signals and the old time-based code signals. For example, new time-based code signals that differ greatly from the previous time-based code can be preferably selected. In other implementations, the new time-based code signals may be randomly selected. The process may continue and enter one or more new time-function codes into the channels of the multichannel encoder (step 4005).

In response to the determination that the differences between the net amplitude event series and the amplitude-weighted time series of the corresponding channels are sufficiently small, the weights of the weighting device can be set (step 4040). After setting the weights, the multichannel decoder is calibrated to work in conjunction with the multichannel encoder that generated the particular output signal (ie, the multichannel encoder from which the output signal is received in step 4010).

Figure 41 is a flow diagram of a process 4100 for creating an encoder / decoder pair. The 4100 process can be used in isolation or in conjunction with other activities. For example, process 4100 may include one or more of process 3900 (Figure 39) and process 4000 (Figure 40). The 4100 process can be performed by one or more digital data processing devices.

Process 4100 begins by building a set of binary-to-analog converters (step 4105). Binary-to-analog converters can be built in hardware, in software, or in combinations of hardware and software. Building binary-to-analog converters can include a process such as process 3900 (Figure 39).

The assembly of an encoder using the binary-to-analog converters is performed (step 4110). In some implementations, each channel of the assembled encoder may include a different one of the binary-to-analog converters.

A set of time series scanners is assembled using the same binary-to-analog converters (step 4115). In some implementations, each time series scanner may include one of the binary-to-analog converters that appear on one channel of the encoder. Time series scanners binary-to-analog converters can act as reference binary-to-analog converters. The correspondence between the binary-to-analog converters on the encoder channels and the binary-to-analog converter in each time series scanner can be noted and used, for example, to calibrate the weights of the weighting devices.

The assembly of a set of weighting devices is performed using the set of binary-to-analog converters (step 4120). In some implementations, the same binary-to-analog converters that are used to assemble the encoder and the set of time series scanners are used to assemble the set of weighting devices. In other implementations, completely different binary-to-analog converters are used to assemble the set of weighting devices. In other implementations, combinations of the same and different binary-to-analog converters are used to assemble the set of weighting devices.

In some implementations, binary-to-analog converters may appear (at least initially) in each weighting device. For example, in some implementations, the complete set of binary-to-analog converters that is built appears in each weighting device. As described below, the weights that are used to weight the output of a binary-to-analog converter can be calibrated to zero, which effectively removes the binary-to-analog converter from the weighting device. In hardware implementations, binary-to-analog converters whose output is zero-weighted can be physically removed from a weighting device.

The weights are calibrated on the weighting devices (step 4125). Calibrating the weights on the weighting devices may include a process such as process 4000 (Figure 40).

Process 4100 encodes, compresses, or stores information using the encoder, set of time series scanners, and set of weighting devices (step 4130).

The embodiments of the matter and the operations described in this specification can be practiced in digital electronic circuits, or in computer software, firmware or hardware, including the structures described in this specification and their structural equivalents, or in combinations of one or more of them.

Aspects of matter described in this specification may be implemented as one or more computer programs, that is, one or more computer program instruction modules, encoded on a computer storage medium for execution or to control operation. of data processing apparatus. For example, lines and signals that transmit information can be implemented as variables or objects that are passed between components of computer programs (eg, computer programs, software modules, subroutines, procedures, and functions) to transmit information. Detectors, comparators, timers, switches and selectors can be implemented as components of computer programs that cooperate to perform operations.

For example, the encoding / compression operations performed by the encoder-compressor 10 (Figure 1A) can be carried out in accordance with the following instructions.

CODING-COMPRESSION

// Convert a sequence of binary numbers to a wave vector with binary digits

(Binary Signal)

File2binary (str) function

String str

Make / o / n = (strlen (str)) in_BinarySignal

in_B inarySignal [] = str2num (str [p])

End

// Convert a single vector of binary numbers into a set of binary waves (Bytes)

Binary2bytes () function

NVAR numChannels = numChannels

WAVE in_BinarySignal

Variable / G numBits = numpnts (in_Binary_Signal)

Variable n, i

String in_Byte

//Initialize

numChannels = numBits / 8

i = 0; n = l

do

in_Byte = "in_Byte" + num2str (n) Duplicate / o / R = [i, (i + 7)] in_BinarySignal in_Byte_w Duplicate / o in_Byte_w $ in_Byte

i + = 8

n + = l

While (n <numChannels + 1)

End

// Convert Bytes to nBinary

Bytes2nBinary () function

NVAR timeInterval

NVAR numChannels = numChannels

NVAR dt = dt

Variable n, i, j

String in_Byte

String in_nBinary

//initialize

dt = timelnterval

n = l

do

// Input waves

in_Byte = "in_Byte" + num2str (n)

Duplicate / o $ in_Byte in_Byte_w

InsertPoints 0,1, in Byte w

in_Byte_w [0] = l // add start bit

InsertPoints 9.1, in_Byte_w

in_Byte_w [9] = 0 // add stop bit

// Output waves

in_nBinary = "in_nBinary" + num2str (n) Make / o / n = (numpnts (in_Byte_w) * 2) in_nBinary_out // Operation

in_nBinary_out = 0

i = 0

j = 0

do

if (in_Byte_w [i] == l)

in: nBinary_out [j] = 1

else; in_nBinary_out [j + l] = l

endif

i + = l

j + = 2

while (i <numpnts (in_Byte_w))

//Departure

Duplicate / o in_nBinary_out $ in_nBinary

SetScale / P x 0, (0.5 * dt), "", $ in_nBinary

n + = l

While (n <numChannels + 1)

End

// Convert nBinary to analog amplitudes in binary times (aAmps_bTimes) Function nBinary2iBAC_r ()

NVAR numChannels = numChannels

Variable n, i, j

Variable Ase, Use, u, D, F

Variable R, E

Variable elapsedTime

String in_nBinary

String iBAC

String iBAC_r

//Initialize

n = l

Do

// Input waves

in_nBinary = "in_nBinary" + num2str (n)

Duplicate / o $ in_nBinary in_nBinary_w, iBAC_r_w

iBAC = MiBAC "+ num2str (n)

Duplicate / o $ iBAC ibac_w

Make / o / n = 0 EventTimes

Findlevels / Q / D = EventTimes in_nBinary_w 1

// Output waves

iBAC_r = "IB AC_r" + num2str (n)

// Initialize BACs

Ase = ibac_w [0]; Use = ibac_w [l]; D = ibac_w [2]; F = ibac_w [3]; R = 1; u = Use // Operation

E = Ase * u * R

iBAC_r_w [0] = E

i = l; j = 0

do

if (in_nBinary_w [i] == 0)

iBAC_r_w [i] = 0; else

elapsedTime = (EventTimes [j + l] / 1000) - (EventTimesj] / 1000) u = Use + ((u * (l-Use)) * exp (-elapsedTime / F))

R = l + ((R-R * u-l) * exp (-elapsedTime / D))

E = Ase * u * R

iBAC_r_w [i] = E

j + = l

endif

i + = l

while (i <numpnts (in_nBinary_w))

// Departure

wavestats / q iBAC_r_w

iBAC_r_w = iBAC_r_w / v_max

Duplicate / o iBAC r w $ IBAC_r

n + = l

While (n <numChannels + 1)

End

//////////////////////////////////////////////////// ////////

// Integrate and compress iBAC responses

Compress () function

NVAR tau = tau

NVAR IntDep = IntDep

NVAR numChannels = numChannels

Variable dt

Variable i, n, m

// Get dt

in_nBinary = "in_nBinary" + num2str (l)

Duplicate / o $ in_nBinary temp_w

tempw = 0

dt = pnt2x (temp_w, l) -pnt2x (temp_w, 0)

// Activate analog device

i = l

Do

Analoglntegration ()

i + = l

While (i <numpnts (sumAmps))

Wavestats / Q sumAmps

sumAmps = sumAmps / v_max

// Output wave

aEventsMessage = sumAmps * thresholdFunction ()

End

By way of another example, the expansion / decoding operations performed by the expander-decoder 34 (Figure 1A) can be performed in accordance with the following instructions.

EXPAND AND DECODE

// Convert time events to analog amplitudes

AEventMessage2oBAC_r () function

NVAR numChannels = numChannels

NVAR num_oBACs

Variable n, i

Variable Ase, Use, u, D, F

Variable R, E

Variable elapsedTime

String oBAC

String oBAC_r

WAVE aEventMessage = aEventMessage

// Extract times

Findlevels / Q aEventMessage 1

Make / o / n = 0 aTimesMessage

Findlevels / Q / D = aTimesMessage, aEventMessage 1

Make / o / n = (V_LevelsFound) oBAC_r_w

// Calculate oBAC responses

n = l

Do

// load oBAC

oBAC = "oBAC" + num2str (n)

Duplicate / o $ oBAC oBAC w

// create an analog amp output waveform

oBACr = "oBAC_r" + num2str (n)

// Initialize oBAC

Ase = l; Use = oBAC_w [l]; D = oBAC_w [2]; F = oBAC_w [3]; u = Use; R = l // Calculate amplitudes

i = 0

do

if (i = 0)

E = Ase * u * R; oBAC_r_w [i] = E

else

elapsedTime = (aTimesMessage [i] / 1000) - (aTimesMessage [i-l] / 1000) u = Use + ((u * (l-Use)) * exp (-elapsedTime / F))

R = l + ((R-R * u-l) * exp (-elapsedTime / D))

E = Ase * u * R

oBAC_r_w [i] = E

endif

i + = l

while (i <numpnts (oBAC_r_w))

Duplicate / o oBAC_r_w $ oBAC_r

n + = l

While (n <num_oB ACs + 1)

End

//////////////////////////////////////////////////// //////////////////////////////

// Differentially scale the outputs

OBAC_r2oBAC_s () function

NVAR numChannels

NVAR num_oBACs

Variable n, m

String oBAC_r

String oBAC_r_error

String oBAC_r_s

//Initialize

oBAC_r = "oBAC_r" + num2str (l)

Duplicate / o $ oBAC_r oBAC_r_s_w

// Convert oBAC_r to oBAC_s

n = l

Do

oBAC_r_s = “oBAC_r_s" + num2str (n)

oBAC_r_s_w = 0

m = l

Do

oBACr = "oBAC_r" + num2str (m)

Duplicate / o $ oBAC_r oBAC_r_w

oBAC_r_error = "oBAC_r_error" + num2str (n) + "_" + num2str (m) Duplicate / o $ oBAC_r_error oBAC_r_error_w

Wavestats / Q oBAC_r_error_w

oB AC_r_w = oB AC_r_w / error_w oBAC_r_s_w = oBAC_r_s_w + oBAC_r_w

m + = l

While (m <num_oB ACs + 1)

Wavestats / Q oBAC_r_s_w

oBAC_r_s_w = oBAC_r_s_w / v_max

Duplicate / o oBAC_r_s_w $ oBAC_r_s

n + = l

While (n <numChannels + 1)

End

// Convert responses from oBAC to out_nBinary

OBAC_s2out_nBinary () function

NVAR numChannels = numChannels

NVAR dt = dt

Variable n, i

RTPL_l variable

RTPL_2 variable

TargetAmp variable

Variable Ase, Use, D, F

String rBAC

String oBAC_r_s

String out_nBinary

// Create output waves

oBAC_r_s = "oBAC_r_s" + num2str (l)

Duplicate / o $ oBAC_r_s oBAC_s_w

Make / o / n = (numpnts (oBAC_s_w)) rBAC_r_w, out_nBinary_w

// Convert all output channels

n = l

Do

// Initialize waves

rBAC = MrBAC "+ num2str (n)

Duplicate / o $ rBAC rBAC_w

oBAC_r_s = "oBAC_r_s" + num2str (n)

Duplicate / o $ oBAC_r_s oBAC_s_w

out_nBinary = "out_nBinary" + num2str (n)

// Initialize rBAC parameters

Ase = l; Use = rBAC_w [l]; D = rBAC_w [2]; F = rBAC_w [3]

// Assign start bit

out_nBinary_w [0] = 1

// loop for each time interval

i = 2

Do

out_nBinary_w [i] = l

out_nBinary_w [i] = 0

rBACResponse (Use, D, F)

rTPL_l = rBAC_r_w [i]

out_nBinary_w [i] = 0

out_nBinary_w [i] = 1

rBACResponse (Use, D, F)

rTPL_2 = rBAC_r_w [i]

// target amplitude

targetAmp = oBAC_s_w [i]

// select tpl for closest amp match if (abs (targetAmp-rTPL_l) <abs (targetAmp-rTPL_2))

out_nBinary_w [i] = 1

out_nBinary_w [i] = 0

else

out_nBinary_w [i] = 0

out_nBinary_w [i] = 1

endif

i + = 2

While (i <numpnts (out_nBinary_w))

// Assign end bit

out_nBinary_w [numpnts (out_nBinary_w) -2] = l

// nBinary output

Duplicate / o out_nBinary_w $ out_nBinary

// set the scale to the same as the input

SetScale / P x 0, dt, "", $ out_nBinary

n + = l

While (n <numChannels + 1)

End

///////////////////////////////////

// Get rBAC response

RBACResponse function (Use, D, F)

Variable Use, D, F

NVAR numChannels = numChannels

Variable n, i

Variable R, E, Ase, u

Variable elapsedTime

WAVE out_nBinaryw = out_nBinary_w

WAVE rBAC_r_w = rBAC_r_w

// get time wave out_nBinary

Make / o / n = 0 out_times_w

Findlevels / Q / D = out times w, out_nBinary_w 1

// Initialize oBAC

Ase = l; u = Use, R = l

// Initialize the rBAC response waveform

rBAC_r_w = 0

// Calculate amplitudes

i = 0

Do

if (i = 0)

E = Ase * u * R

rBAC_r_w [i] = E

else

elapsedTime = (out_times_w [i]) - (out_times_w [i-l]) u = Use + ((u * (l-Use)) * exp (-elapsedTime / F))

R = l + ((R-R * u-l) * exp (-elapsedTime / D))

E = Ase * u * R

rBAC_r_w [i] = E

endif

i + = l

while (i <numpnts (out_times_w))

End

///////////////////////////////////////////

// Convert to bytes

Out_nBinary2out_Byte () function

NVAR numChannels = numChannels

Variable n

String out_nBinary

String out_Byte

//Initialize

n = l

Do

out_Byte = "out_Byte" + num2str (n)

out_nBinary = "out_nBinary" + num2str (n)

Duplicate / o $ out_nBinary out_nBinary_w

DeletePoints 0, l, out_nBinary_w

DeletePoints numpnts (out_nBinaryw) -1,1, out_nBinary_w

Duplicate / or out_nBinary_w, $ out_Byte

n + = l

While (n <numChannels + 1)

End

////////////////////////////////////

// Convert bytes to binary signal

Out_out_Byte2out_BinarySignal () function

NVAR numChannels = numChannels

Variable n

String out_Byte

String out_BinarySignal

ConcatBytes ()

End

A computer storage medium may be, or be included in, a computer-readable storage device, a computer-readable storage substrate, a serial or random access memory device or array, or a combination of one or more of they. The medium can also be, or be included in, one or more physical components or separate media (eg, multiple CDs, disks, or other storage devices).

The operations described in this document can be implemented as operations performed by a data processing apparatus on data stored in one or more computer-readable storage devices or received from other sources.

The term "data processing apparatus" encompasses all types of apparatus, devices and machines for processing data, including, by way of example, a programmable processor, a computer, a system on an integrated circuit, or multiple, or combinations, of the above. The apparatus may include special purpose logic circuits, for example an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). The apparatus may also include, in addition to hardware, code that creates an execution environment for the computer program in question, for example, code that constitutes the processor firmware, a protocol stack, a database management system, a operating system, a cross-platform runtime environment, a virtual machine, or a combination of one or more of these. The appliance and runtime environment can realize various different computing model infrastructures, such as web services, distributed computing, and grid computing infrastructures.

A computer program (also referred to as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be implement in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program can, but need not, correspond to a file on a file system. A program can be stored in a part of a file that contains other programs or data (for example, one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in several coordinated files (for example, files that store one or more modules, applets, or pieces of code). A computer program can be implemented to run on one computer or on several computers located at one site or distributed over multiple sites and interconnected by a communication network.

The processes and logical flows described in this document can be performed by one or more programmable processors that execute one or more computer programs to perform actions operating with input data and generating output. Processes and logic flows can also be realized and the apparatus can also be implemented as a special purpose logic circuit, for example an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). ).

Suitable processors for executing a computer program that perform activities in the processes described herein include, by way of example, general and special purpose microprocessors, and one or more processors of any type of digital computer. Typically, a processor will receive instructions and data from read-only memory or random access memory, or both. The essential elements of a computer are a processor to perform actions in accordance with instructions and one or more memory devices to store instructions and data. Generally, a computer will also include, or be operably coupled to receive or transfer data to, or both, one or more mass storage devices for storing data, eg, magnetic discs, magneto-optical discs, or optical discs. However, a computer does not need to have such devices. In addition, a computer can be integrated into another device, for example, a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System receiver. (GPS) or on a portable storage device (for example, a universal serial bus (USB) flash drive), to name just a few. Suitable devices for storing computer program instructions and data include all forms of non-volatile memory, memory media and devices, including, by way of example, semiconductor memory devices, for example EPROM, EEPROM, and flash memory devices. ; magnetic drives, for example internal hard drives or removable drives; magneto-optical discs; and CD-ROM and DVD-ROM discs. The processor and memory can be supplemented or incorporated into special-purpose logic circuits.

Although this specification contains many specific implementation details, these should not be construed as limitations on the scope of the invention or what can be claimed, but rather as descriptions of specific features of particular embodiments of the invention. Certain features that are described in this invention within the context of separate embodiments can also be practiced in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple separate embodiments or in any suitable sub-combination. Furthermore, although the characteristics may be previously described as acting in certain combinations and even initially claimed as such, one or more characteristics of a claimed combination may in some cases be removed from the combination, and the claimed combination may be directed to a sub-combination or variation. of a subcombination.

Similarly, although the operations are represented in the drawings in a particular order, this should not be understood as requiring that said operations be performed in the particular illustrated order or sequential order, or that all illustrated operations be performed, in order to achieve desirable results. In certain circumstances, multitasking and parallel processing can be advantageous. Furthermore, the separation of various components of the system in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the components and systems of the program described generally can be integrated together into a single software product or bundled into multiple software products.

WAYS OF REALIZATION

The methods, systems and apparatus, including computer programs encoded on a computer storage medium, for encoding and decoding the information described herein can be performed in one or more of the following embodiments.

Embodiment 1. An interface method between digital data processing and statistical processing and pattern recognition provided in a neural processing component and encoding information in an encoder, comprising: receiving a signal representing information using a set of discrete digits; converting, by means of an encoder, the received signal into a code as a function of time, where: the code as a function of time is divided into time intervals, each of the time intervals of the code as a function of time corresponds to a digit in the signal received, each digit of a first state of the received signal is expressed as an event that occurs at a first moment within the corresponding time interval of the code as a function of time, each digit of a second state of the received signal expressed as an event that it occurs in a second time within the corresponding time intervals of the time-function code, the first moment being distinguishable from the second moment, and all the states of the digits in the received signal are represented by events in the time-function code; and place the code as a function of time in the neural processing component.

Embodiment 2. The method according to embodiment 1, wherein: the received signal is a binary representation of the information; and the digits of the received signal comprise bits in the binary representation.

Embodiment 3. The method according to any one of embodiments 1 to 2, wherein: each digit of the first state of the binary representation is expressed as an event that occurs in the middle of the corresponding time interval of the code as a function of time ; and each digit of the second state of the binary representation is expressed as an event that occurs at the beginning or end of the corresponding time interval of the code as a function of time.

Embodiment 4. The method according to any one of embodiments 1 to 3, wherein, except at times of occurrence, the events expressing the digits of the first state are indistinguishable from the events expressing the digits of the second state.

Embodiment 5. The method according to any of embodiments 1 to 4, wherein the events each comprise a pair of transitions from low to high and from high to low.

Embodiment 6. The method according to any one of embodiments 1 to 5, wherein the events are binary.

Embodiment 7. The method according to any one of embodiments 1 to 6, wherein the time-function code output comprises the time-function code output to a neural processing component implemented using wet neural components, in where the properties of the time function code are designed for compatibility with wet neural components.

Embodiment 8. The method according to any of embodiments 1 to 7, wherein converting the received signal into the time-function code comprises adding a start header to the time-function code, the start header delimiting the start of the time code and the one corresponding to a header in the received signal.

Embodiment 9. The method according to any one of embodiments 1 to 8, wherein the conversion of the received signal into the time-function code comprises adding a stop foot to the time-function code, the stop foot demarking the end of the code as a function of time and the one corresponding to one foot in the received signal.

Embodiment 10. The method according to any one of embodiments 1 to 9, wherein the time intervals are all of a single duration.

Embodiment 11. The method according to any one of embodiments 1 to 10, wherein the time intervals are ordered serially in the same sequence as the corresponding digits in the received signal.

Embodiment 12. The method according to any of the embodiments 1 to 11, wherein converting the received signal into the code as a function of time comprises: converting each digit of the first state of the received signal into events that occur in the first moment ; and converting each digit of the second state of the binary representation into events that occur in the second beat.

Embodiment 13. A system to interface between digital data processing and statistical processing and pattern recognition provided in a neural processing component, the system comprising: an input for receiving a signal representing information using a set discrete digits; an encoder that encodes the received signal, the encoder comprising: a state detector configured to detect the states of the digits in the received signal, and a translator configured to translate the states of the digits in the received signal into a code as a function of time , the time-function code comprising a set of time intervals to each of which a respective digit is assigned in the received signal, each of the time intervals comprising an event, the timing of the event within each of the time intervals characterizing the status of a respective assigned digit; an output to provide the code as a function of time to another system or device; a neural processing component wired to receive the code as a function of time.

Embodiment 14. The system according to embodiment 13, wherein the neural processing component is implemented using wet neural components and the properties of the time-function code are adapted for compatibility with the wet neural components.

Embodiment 15. The system according to any one of embodiments 13 to 14, wherein: the received signal comprises a binary signal; and the state detector comprises a bit detector configured to detect the state of bits in the binary signal.

Embodiment 16. The system according to any of the embodiments 13 to 15, wherein the translator comprises an event generator, the event generator being configured and connected to generate the code events as a function of time.

Embodiment 17. The system according to embodiment 16, wherein the event generator comprises a pulse generator, wherein the forms of the pulses that express the first states are indistinguishable from the forms of the pulses that express the second state.

Embodiment 18. The system according to embodiment 16, wherein the event generator is further configured to generate a header event that delimits the start of the code as a function of time and corresponds to a header in the received signal.

Embodiment 19. The system according to any of embodiments 13 to 18, further comprising a start / stop detector configured and connected to detect the start and end of the received signal.

Embodiment 20. The system according to any one of embodiments 13 to 19, further comprising a slot synchronization component, the slot synchronization component demarcating the time slot stage of the time-based code.

Embodiment 21. The system according to embodiment 20, wherein the interval synchronization component is configured to demarcate the stage of time intervals of a single duration.

Embodiment 22 A method to interface between the statistical processing and pattern recognition functions provided by the neural processing component and the devices for processing digital data and decoding a time-based code signal, said method comprising : receive a time-based code signal from a neural processing device in a decoder, where: the time-based code signal is divided into time slots, each of the time slots of the time-based code signal time comprises an event, and the timing of the events within the time intervals expresses the information content of the code signal as a function of time; detect timing of events within time intervals; and providing a signal representing the information expressed in the time-code signal using a set of discrete digits.

Embodiment 23. The method according to embodiment 22, further comprising: converting events occurring within a first time range of the time-based code signal intervals into a discrete digit of a first state in the exit sign; and converting events occurring within a second time frame of the time-code signal intervals into a discrete second-state digit in the output signal.

Embodiment 24. The method according to embodiment 23, wherein the output signal comprises a binary signal.

Embodiment 25. The method according to any of embodiments 22 to 24, further comprising detecting an onset of the data content of the time-based code signal.

Embodiment 26. The method according to embodiment 25, wherein detecting the start of the data content comprises detecting a header event of the time-based code signal.

Embodiment 27. The method according to embodiment 26, further comprising determining a time between the header event and the first event after the header event.

Embodiment 28. The method according to embodiment 25, further comprising synchronizing the detection of the moments where the events occur within the time intervals with the start of the data content of the code signal as a function of the weather.

Embodiment 29. The method according to any one of embodiments 22 to 28, wherein receiving the time-based code signal comprises receiving the time-based code signal from a neural processing device implemented using wet neural components. .

Embodiment 30. The method according to any of embodiments 22 to 29, further comprising: receiving a second time-based code signal in a second decoder, wherein: the second time-based code signal is divided In time intervals, each of the time intervals of the second code signal as a function of time comprises an event, and the synchronization of the events within the time intervals expresses the information content of the second code signal as a function of the weather; detecting, in the second decoder, the timing of the events within the time slots; and providing, from the second decoder, a signal representing the information expressed in the second time code signal using a second set of discrete digits; and adding the set of discrete digits and the second set of discrete digits in a second token.

Embodiment 31. The method according to any one of embodiments 22 to 30, wherein the events of the time-function code signal have indistinguishable forms.

Embodiment 32. A system to interface between the statistical processing and pattern recognition functions provided by the neural processing component and the digital data processing devices and to decode a time-based code signal, the system comprising : a neural processing component; an input to which the neural processing component is connected and which receives a time-code signal, where: the time-code signal is divided into time intervals, each of the time intervals of the signal The time-code code comprises an event, and the synchronization of the events within the time intervals expresses the information content of the time-code signal; an event listener configured to detect the timing of events within the time intervals of the time-based code signal; a translator configured to translate the synchronization of events within the time intervals of the code function of the time in states of a set of digits; and an output configured to provide a signal comprising the digits.

Embodiment 33. The system according to embodiment 32, wherein the translator comprises a set of comparators that receive the detected timings of the events and compare the detected timings of the events with the time margins within the intervals.

Embodiment 34. The system according to any one of embodiments 32 to 33, wherein the neural processing component is implemented using wet neural components.

Embodiment 35. The system according to any one of embodiments 32 to 34, wherein the translator is configured to translate the events within the time intervals of the time-function code into a binary signal.

Embodiment 36. The system according to any of embodiments 32 to 35, wherein the event detector comprises a pulse detector.

Embodiment 37. The system according to any one of embodiments 32 to 36, further comprising a slot synchronization component, the slot synchronization component demarcating the time slot stage of the time-based code.

Embodiment 38. The system according to embodiment 37, wherein the interval synchronization component comprises a comparator configured to compare a count of time with a reference.

Embodiment 39. The system according to embodiment 38, wherein the reference is constant and the time intervals are all of the same single length.

Embodiment 40. The system according to embodiment 37, further comprising a start detector configured to detect a start of the code signal as a function of time.

Embodiment 41. The system according to any of embodiments 32 to 40, wherein the start detector is coupled to the interval synchronization component and provides a reset signal to the interval synchronization component, resetting the restart signal the demarcation of the stage of time intervals.

Therefore, particular embodiments of the invention have been described. Other embodiments are within the scope of the following claims. In some cases, the actions listed in the claims can be performed in a different order and still achieve desirable results. Furthermore, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or the sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing can be advantageous.

Claims (16)

1. An encoding system implemented in digital electronic circuits or in combinations of computer software and hardware, the encoding system comprising: a time encoder (105) configured to encode information into a set of time-function code signals (135), each of the time-function code signals (135) including time intervals (320, 1420, 2905) and each one of the time intervals (320, 1420, 2905) including an event (325, 1425, 2910), occurrences of the events (325, 1425, 2910) within the time intervals (320, 1420, 2905) that are synchronized to represent information; Y a compressor encoder (2205) comprising a set of converter devices (2305) each connected and configured to receive and weight the amplitudes of the events (325, 1425, 2910) in a respective one of the time-function code signals (135) as a function of the timing of other events (325, 1425, 2910) in the respective time signal time-function code, and providing a signal (2345) that includes the amplitude-weighted events at relative times corresponding to the timing of the unweighted events within the respective time-code signal. The system according to claim 1, wherein the encoder comprises a reset mechanism, said reset mechanism being configured to reset the weighting of the amplitudes of the events (325, 1425, 2910) in the converter devices to a known state. . The system according to any one of claims 1 to 2, wherein the encoder comprises an integrator (2310) connected and configured to integrate amplitude-weighted time-function codes into a signal. The system according to any one of claims 1 to 3, wherein the integrator (2310) is configured to integrate the amplitude-weighted time-function codes into a one-dimensional signal. The system according to any one of claims 1 to 4, wherein the weighting of the converter devices (2305) does not add new information to the time-code signal (135). The system according to any one of claims 1 to 5, wherein the weighting of each event (325, 1425, 2910) is a non-linear function of the occurrence times of the predecessor events (325, 1425, 2910) in the time-function code signal (135). The system according to any of claims 1 to 6, wherein the compressor encoder (2205) comprises: an integrator (2310) connected and configured to receive the signals that include amplitude-weighted sequences of events (325, 1425, 2910) , the integrator (2310) comprising a comparator (260, 3635) connected to receive a signal characterizing the integration, wherein the comparator (260, 3635) is configured to compare the signal characterizing the integration with a dynamic threshold value, and in response to the integration characterizing signal reaching the dynamic threshold value, provide an output event and reestablishing the comparison between the integration characterizing signal and the dynamic threshold value. The system according to claim 7, wherein the integrator (2310) further comprises an event counter configured to count the number of input events (325, 1425, 2910) in the time sequences. The system according to any of claims 7 to 8, wherein the integrator (2310) further comprises a threshold value adjuster connected to receive a count of the input events (325, 1425, 2910) in the time sequences , the threshold value adjuster being connected and configured to adjust the dynamic threshold value in response to counting the number of input events (325, 1425, 2910) in the time sequences. 10. A decoding device (3205, 3700) implemented in digital electronic circuits or in combinations of computer software and hardware, the decoding device comprising: an input (3710) connectable to receive an input time series of events (325, 1425, 2910), with the events (325, 1425, 2910) in the input time series occurring at non-uniform intervals, the timing of the input events (325, 1425, 2910) within the input time series encoding information; a set of weighting converter devices (3310), each configured to uniquely convert the input time series into a set of amplitudes (3340), each amplitude being a function of the timing of multiple input events (325 , 1425, 2910) in the input time series; Y a set of outputs (3335), each included in a respective weighting converter device and connectable to provide the output with a respective series of amplitudes, where the amplitudes vary, but the number of amplitudes is the same as the number of events (325, 1425, 2910) in the input time series, wherein at least some of the amplitudes generated by different weight converting devices differ for each nonzero input time series. The decoder device according to claim 10, further comprising a reset mechanism, the reset mechanism being configured to reset the converter devices (2305) to a known state. The decoding device according to any of claims 10-11, further comprising: a set of data storage devices that store a set of weighting weights; and a set of multipliers, each of the multipliers being connected and configured to multiply one of the sets of amplitudes by a respective weighting weight; Y an adder configured to add the products of the sets of amplitudes and the respective second weighting weights. The decoding device according to any of claims 10 to 12, wherein each of the weighting converter devices comprises a network of signal processors interconnected by one or more processing junctions that dynamically adjust the response intensity according to the time pattern of events (325, 1425, 2910) in the input time series to generate the set of amplitudes. The decoding device according to any one of claims 10 to 13, in combination with a device comprising: an input (3345) connected to receive one of the output series (3470) of amplitudes; a comparator (3635) connected to compare the output series (3470) of amplitudes with a second series of amplitudes and generate a signal indicative of a difference between the output series of amplitudes and the second series of amplitudes; a second converter device configured to convert a time series into the second series of amplitudes, each amplitude in the second series being a function of the synchronization of multiple events (325, 1425, 2910) at the time series input in the converter device ; a permutator (3670) configured to permute the time series input at the converter device; and an output connectable to provide a time series input to the converter device in response to the signal indicative of the difference between the output series of amplitudes and the second series of amplitudes that fall below a threshold value. The decoding device according to claim 14, wherein the second converter device (2305) comprises a network of signal processors interconnected by one or more processing junctions that dynamically adjust the response intensity according to the time pattern of events in the input time series to generate the second series of amplitudes. 16. The decoding device according to any of claims 14 to 15, wherein the comparator comprises a set of comparators each connected to compare a single amplitude of the output series with a single amplitude of the second series of amplitudes, wherein the Decoding device, optionally, comprises one or both of: a buffer (3615, 3625) for storing the series of output amplitudes; Y a second buffer (3615, 3625) for storing the second set of amplitudes.