CN107273322B - Parallel data output method and device - Google Patents
Parallel data output method and device Download PDFInfo
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- CN107273322B CN107273322B CN201710331166.5A CN201710331166A CN107273322B CN 107273322 B CN107273322 B CN 107273322B CN 201710331166 A CN201710331166 A CN 201710331166A CN 107273322 B CN107273322 B CN 107273322B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
- A61B8/56—Details of data transmission or power supply
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
- G06F13/4018—Coupling between buses with data restructuring with data-width conversion
Abstract
The application provides a parallel data output method and a device, wherein the parallel data output method comprises the following steps: receiving serial data and a parallel data identification clock whose frequency varies with a variation in an input frequency of the serial data; converting serial data into parallel output data; and outputting the parallel output data according to the parallel data identification clock. By the parallel data output method and the parallel data output device, the accuracy of data output when the serial data input frequency changes can be improved.
Description
Technical Field
The present application relates to data processing technologies, and in particular, to a parallel data output method and apparatus.
Background
In a medical ultrasonic imaging system, a probe of an ultrasonic system is used for sampling a tissue to be detected, and data processing is performed after sampling data is converted by an Analog-to-Digital Converter (ADC), so that clear imaging of the tissue to be detected is obtained. Most of the current ADC chips use serial output, which requires serial/parallel conversion (serial-to-parallel conversion) of serial data in the data processing process. In the traditional serial-parallel conversion, a system clock source is used in an FPGA (Field Programmable Gate Array) to perform serial-parallel conversion on serial data output by an ADC chip, and since there is no clock to perform real-time synchronization on the converted parallel data, when the input frequency of the serial data changes, the check code needs to be retransmitted, and the output control unit reassembles the converted parallel data according to the check code and outputs the reassembled parallel data. This method is not suitable for the situation that the serial data input frequency changes continuously. Because the probes in the ultrasound system need to work at different frequencies, the data processing system needs to process data at different frequencies, and most of the current ADC chips use serial output, which requires that the serial-to-parallel conversion unit can adapt to serial data at different input frequencies.
The traditional serial-parallel conversion mode needs to send the check code when the frequency changes, so that the check code sending is manually interfered according to the frequency change when error data is output at the moment of frequency change, and the upper computer is also required to send a message to the serial-parallel conversion unit to send the check code when the working frequency of the probe is changed, so that the communication time and the communication complexity are increased, and an unstable risk is brought to a system.
Disclosure of Invention
One aspect of the present application provides a parallel data output method, including: receiving serial data and a parallel data identification clock whose frequency varies with a variation in an input frequency of the serial data; converting the serial data into parallel output data; and outputting the parallel output data according to the parallel data identification clock.
Another aspect of the present application provides a parallel data output apparatus. The parallel data output apparatus includes: the data conversion module is used for receiving serial data and converting the serial data into parallel output data; and the control module is used for receiving a parallel data identification clock with the frequency changing along with the change of the input frequency of the serial data and controlling the data conversion module to output the parallel output data according to the parallel data identification clock.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the invention.
FIG. 1 is a flow chart illustrating a method of parallel data output according to an exemplary embodiment of the present application;
FIG. 2 is a timing diagram illustrating a conversion of serial data to parallel data according to an exemplary embodiment of the present application;
FIG. 3 is a flow diagram for one embodiment of the steps in the method shown in FIG. 1 for outputting parallel output data according to a parallel data clock;
FIG. 4 is a flowchart of one embodiment of the step of outputting parallel output data based on parallel data identification clocks in the method shown in FIG. 1;
FIG. 5 is a block diagram illustrating a parallel data output apparatus according to an exemplary embodiment of the present application;
fig. 6 is a block diagram illustrating another parallel data output apparatus according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the examples of the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the embodiments of the application, as detailed in the appended claims.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the present application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used in the embodiments of the present application to describe various information, the information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information, without departing from the scope of the embodiments of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
FIG. 1 is a flow diagram illustrating a parallel data output method according to one embodiment. The embodiment of the application can be applied to a medical ultrasonic imaging system, sampling data of an ultrasonic system is converted through an ADC (Analog-to-Digital Converter), and converted serial data can be converted into parallel data through the parallel data output method and output. However, the parallel data output method of the present application may also be applied to other systems or fields. The parallel data output method includes steps 11-13. Wherein the content of the first and second substances,
in step 11, a parallel data identification clock is received in which serial data and a frequency varies with a variation in an input frequency of the serial data.
In the embodiment of the present application, the serial data and parallel data identification clock (FC L K) is a standard output signal of the ADC, the input frequency of the serial data and the frequency of FC L K vary with the variation of the sampling frequency of the ADC, e.g., the frequency of FC L K is the same as the sampling frequency of the ADC and the input frequency of the serial data is six times the sampling frequency of the ADC, i.e., the frequency of FC L K and the input frequency of the serial data may be adjusted with respect to the variation of the sampling frequency of the ADC, and thus, the clock frequency of FC L K varies with the variation of the input frequency of the serial data, e.g., the clock frequency of FC L K increases with the increase of the input frequency of the serial data or the clock frequency of FC L K decreases with the decrease of the input frequency of the serial data, as shown in fig. 2, the clock frequency of FC L K decreases with the decrease of the input frequency of the serial data, and thus, the number of bits of the serial data received in each clock cycle of FC L K may remain substantially unchanged, and the serial data may be received in each cycle 3612 bits per FC 3526K as shown in fig. 2.
In step 12, the serial data is converted into parallel output data.
In this embodiment, when the maximum output bit number of the DDR module or the two-pole cascade DDR module is greater than or equal to the bit number of serial Data received in one FC L K cycle, the DDR module or the two-pole cascade DDR module can directly convert the serial Data into parallel output Data.
In another alternative embodiment, the present step 12 comprises a substep 121 and a substep 122, as shown in fig. 3, wherein,
in sub-step 121, the serial data synchronization clock (DC L K) is divided to obtain a divided clock.
In an alternative embodiment, the division of the serial data synchronization clock (DC L K) may be accomplished by a frequency dividerSpecifically, when the maximum output bit number of the DDR module or the two-pole cascade DDR module is less than the bit number of serial data received in one FC L K period, a frequency division coefficient may be determined according to the maximum output bit number of the DDR module or the two-pole cascade DDR module and the bit number of serial data received in one FC L K period, and then the frequency divider or the C L KDIV module may implement fast frequency division according to the set frequency division coefficient to obtain a frequency division clock (SC L K). continuing referring to fig. 2, an example of receiving 12-bit serial data in one FC L K period is described, where the 12-bit serial data is d, respectively0，d1…d11If the maximum output bit number of the DDR module or the two-stage cascade DDR module is 4 bits, the serial data synchronous clock needs to be divided by 3 (that is, the frequency division coefficient is 3), so as to obtain SC L K.
In sub-step 122, serial data is converted into a plurality of sets of intermediate parallel data according to the frequency division clock, and parallel output data is obtained according to the plurality of sets of intermediate parallel data.
In the embodiment of the application, the DDR module or the two-pole cascade DDR module can convert serial data into a plurality of groups of intermediate parallel data according to SC L K. As shown in FIG. 2, when the DDR module or the two-pole cascade DDR module detects a rising edge of SC L K, a group of intermediate parallel data Q is output0{d3,d2,d1,d0When the DDR module or the two-pole cascade DDR module detects the rising edge of another SC L K, a group of middle parallel data Q is output1{d7,d6,d5,d4When the DDR module or the two-pole cascade DDR module detects another rising edge of an SC L K, a group of intermediate parallel data Q is output2{d11,d10,d9,d8Therefore, 3 SCs L K are required to complete the conversion of 12-bit serial data into parallel data for output, each SC L K completes the conversion of 4-bit data, the parallel output data at least includes Q0{d3,d2,d1,d0}、Q1{d7,d6,d5,d4}、Q2{d11,d10,d9,d8Three sets of intermediate parallel data. In this embodiment, the parallel output data is Q0{d3,d2,d1,d0}、Q1{d7,d6,d5,d4}、Q2{d11,d10,d9,d8FIG. 2 is only an example, the number of bits of serial data, the number of bits of parallel output data, the coefficient of frequency division, etc. vary according to practical applications and is not limited to the example shown in FIG. 2. the number of bits of parallel output data is equal to the number of bits of serial data received in one FC L K cycle, for example, the number of bits of serial data received in one FC L K cycle is 12 bits, and the number of bits of parallel output data is 12 bits.
With continued reference to fig. 1, in step 13, parallel output data is output based on the parallel data identification clock.
In the embodiment of the application, the parallel output data can be output by the DDR module or the two-pole cascade DDR module according to the parallel data identification clock (FC L K).
In an alternative embodiment, this step 13 comprises a substep 131 and a substep 132, as shown in fig. 4, wherein,
in sub-step 131, the transition time of the parallel data identification clock (FC L K) is determined.
In an alternative embodiment, the DDR module or the two-pole cascade DDR module may perform serial-parallel conversion on FC L K to obtain clock parallel data, and then determine the time of data transition in the clock parallel data to be the transition time of FC L K, where the transition time may include a rising edge or a falling edge of FC L K, referring to fig. 2, for example, FC L K is illustrated, and the clock parallel data after serial-parallel conversion of FC L K is Q (fclk), which includes Q0{1,1, 1}, Q1{0,0, 1}, and Q2{0,0,0,0}, so that serial-parallel conversion of a plurality of FC L K results in a series-parallel data Q (fclk), and in the series-parallel data Q (fclk), the time of data {0,0,0,0} transitioning to data {1,1, 1} is the rising edge of FC L K, and the time of data transition from {1,1,1, 0} to FC 0, FC L K is the falling edge of FC L K.
With continued reference to FIG. 4, at the transition time, the parallel output data is output in sub-step 132. in the embodiment of the present application, the parallel output data may be output sequentially on the rising edge of the parallel data identification clock, or the parallel output data may be output sequentially on the falling edge of the parallel data identification clock. in an alternative embodiment, with continued reference to FIG. 2, the example of receiving 12-bit serial data in one FC L K cycle is described, where the 12-bit serial data are d-bits each0，d1…d11If the serial data of one FC L K period is converted into serial-parallel data, three groups of intermediate parallel data are output as Q0{d3,d2,d1,d0}、Q1{d7,d6,d5,d4}、Q2{d11,d10,d9,d8}. outputs 12-bit parallel data when detecting the rising edge of FC L K, i.e. outputs Q simultaneously0{d3,d2,d1,d0}、Q1{d7,d6,d5,d4}、Q2{d11,d10,d9,d8And three sets of intermediate parallel data, so that parallel output data is output.
In the embodiment, the frequency of the FC L K changes when the frequency of the serial data input changes, as shown in FIG. 2, the serial data input the second set of data d in the second clock cycle of the FC L K0，d1…d11In accordance with the method described above, upon detection of yet another rising edge of FC L K, Q is simultaneously output0{d3,d2,d1,d0}、Q1{d7,d6,d5,d4}、Q2{d11,d10,d9,d8And the other three groups of intermediate parallel data ensure the correctness of the parallel output data.
In the embodiment of the application, because the relationship between the input frequency of the serial data and the frequency of the parallel data identification clock is unchanged, when the input frequency of the serial data changes, the frequency of the parallel data identification clock also changes, so that the converted parallel data is synchronized in real time, the combination mode of the parallel output data is automatically adjusted, and the correct output of the parallel output data is ensured. In addition, the check code is not needed to be checked during serial-parallel data conversion, so that the problems of parallel data output error and check code interference when the serial data input frequency changes are solved, and the compatibility of the ultrasonic system to frequency change is improved.
Corresponding to the embodiment of the parallel data output method, the application also provides an embodiment of the parallel data output device.
The embodiment of the parallel data output device can be applied to a parallel data output method. The device embodiments may be implemented by software, or by hardware, or by a combination of hardware and software. Taking a software implementation as an example, as a device in a logical sense, the device is formed by reading corresponding computer program instructions in the nonvolatile memory into the memory for operation through the processor of the parallel data output device.
Fig. 5 is a block diagram illustrating a parallel data output apparatus according to an embodiment of the present invention, which may be applied to a medical ultrasound imaging system, and data obtained by converting sampled data of an ultrasound system through an ADC (Analog-to-Digital Converter) is output after being subjected to serial-to-parallel data conversion through the parallel data output apparatus according to the embodiment of the present invention.
In an alternative embodiment, the data conversion module 51 and the control module 52 may be implemented by FPGA (field programmable Gate Array) chips. In another alternative embodiment, the data conversion module 51 may be implemented by a DDR module within an FPGA or a two-pole cascade DDR module, and the control module 52 may be implemented by a controller independent from the FPGA. However, the data conversion module 51 and/or the control module 52 may be implemented by other hardware and/or software.
In the illustrated embodiment, DC L K may be output by the ADC chip to the data conversion module 51 and the control module 52 for adjusting the clock signal of the entire parallel data output device0，…dn(n is the number of bits of data, for example, but not limited to 11) from the ADC chip to the data conversion module 51, and the data conversion module 51 performs serial-to-parallel conversion to output parallel output data, where the parallel output data includes q0，…qn(n is the number of bits of data, for example, but not limited to 11), FC L K may be output by the ADC chip to the control module 52, and the control module 52 controls the data conversion module 51 to output parallel output data according to FC L K.
In an alternative embodiment, the data conversion module 51 performs serial-to-parallel conversion on FC L K to obtain clock parallel data q (fclk), and the control module 52 determines that a data transition time in q (fclk) is a transition time of FC L K, and the control module 52 controls the data conversion module 51 to output parallel output data at the transition time.
Fig. 6 is a block diagram showing a parallel data output apparatus according to another embodiment, the parallel data output apparatus shown in fig. 6 is similar to the parallel data output apparatus shown in fig. 5, and compared with the parallel data output apparatus shown in fig. 5, the parallel data output apparatus shown in fig. 6 further includes a frequency division module 53. in an alternative embodiment, the frequency division module 53 may be implemented by a frequency divider, and in another alternative embodiment, the frequency division module 53 may be implemented by a C L KDIV module of an FPGA internal unit, the ADC chip outputs a serial data synchronous clock (DC L K) to the frequency division module 53, the frequency division module 53 divides the frequency of DC L K to obtain a frequency division clock (SC L K). specifically, the frequency division coefficient may be determined according to the maximum output bit number of the DDR module or the two-pole cascade DDR module and the bit number of serial data received in one FC L K cycle, and then the frequency division module 53 may implement fast frequency division according to the set frequency division coefficient to obtain SC L k.a data conversion module 51 converts multiple sets of intermediate parallel data into the parallel data according to SC L K, and the control module 52 outputs the parallel data including multiple sets of the parallel data output data 51.
The parallel data output apparatus shown in fig. 5 and 6 may be used to perform the parallel data output method described above.
In the embodiment of the present application, because the relationship between the input frequency of the serial data received by the data conversion module 51 and the frequency of the parallel data identification clock received by the control module 52 is not changed, when the input frequency of the serial data changes, the frequency of the parallel data identification clock also changes, real-time synchronization is performed on the converted parallel data, and the control module 52 can adjust the combination mode of the parallel output data output by the data conversion module 51 according to the parallel data identification clock, so as to ensure correct output of the parallel output data. In addition, the data conversion module 51 does not need to check the check code when performing serial-parallel data conversion, thereby avoiding the problems of parallel data output error and check code intervention when the serial data input frequency changes, and improving the compatibility of the ultrasonic system to frequency changes.
The implementation process of the functions and actions of each module in the system is specifically described in the implementation process of the corresponding step in the method, and is not described herein again.
For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (8)
1. A parallel data output method, comprising:
receiving serial data and a parallel data identification clock whose frequency varies with a variation in an input frequency of the serial data;
converting the serial data into parallel output data; and
outputting the parallel output data according to the parallel data identification clock, wherein the bit number of the parallel output data is equal to the bit number of serial data received in one parallel data identification clock period;
wherein said identifying a clock according to said parallel data, outputting said parallel output data, comprises:
determining the jumping time of the parallel data identification clock; and
and outputting the parallel output data at the jump moment.
2. The method of claim 1, wherein the determining that the parallel data identifies transition times of a clock comprises:
performing serial-parallel conversion on the parallel data identification clock to obtain clock parallel data; and
and determining the data jumping time in the clock parallel data as the jumping time of the parallel data identification clock.
3. The method of claim 1, wherein the transition time comprises a rising edge or a falling edge of the parallel data identification clock.
4. The method of claim 1, comprising dividing a serial data synchronization clock to obtain a divided clock;
the converting the serial data into parallel output data includes:
and converting the serial data into a plurality of groups of intermediate parallel data according to the frequency division clock, and obtaining the parallel output data according to the plurality of groups of intermediate parallel data.
5. A parallel data output apparatus, comprising:
the data conversion module is used for receiving serial data and converting the serial data into parallel output data; and
the control module is used for receiving a parallel data identification clock with the frequency changing along with the change of the input frequency of the serial data, and controlling the data conversion module to output the parallel output data according to the parallel data identification clock, wherein the bit number of the parallel output data is equal to the bit number of the serial data received in one parallel data identification clock period;
wherein the control module is used for determining the jump time of the parallel data identification clock, and
and controlling the data conversion module to output the parallel output data at the jump moment.
6. The apparatus of claim 5, wherein the data conversion module is configured to perform serial-to-parallel conversion on the parallel data identification clock to obtain clock parallel data; and the control module is used for determining the data hopping moment in the clock parallel data as the hopping moment of the parallel data identification clock.
7. The apparatus of claim 5, wherein the transition time comprises a rising edge or a falling edge of the parallel data identification clock.
8. The apparatus of claim 5, wherein the apparatus further comprises:
the frequency division module is used for carrying out frequency division on the serial data synchronous clock to obtain a frequency division clock;
the data conversion module is used for converting the serial data into a plurality of groups of intermediate parallel data according to the frequency division clock and obtaining the parallel output data according to the plurality of groups of intermediate parallel data.
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| CN110275851B (en) * | 2019-07-19 | 2020-02-07 | 广州波视信息科技股份有限公司 | Data serial-parallel conversion device, delayer and data processing method |
| CN113258921B (en) * | 2021-06-02 | 2021-10-01 | 牛芯半导体(深圳)有限公司 | Serial-to-parallel conversion circuit, method and serial deserializer |
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