JP2013500539A - 分散型プレディケート予測を実現するための方法、システム、およびコンピュータによってアクセス可能な媒体 - Google Patents

分散型プレディケート予測を実現するための方法、システム、およびコンピュータによってアクセス可能な媒体 Download PDF

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JP2013500539A
JP2013500539A JP2012522834A JP2012522834A JP2013500539A JP 2013500539 A JP2013500539 A JP 2013500539A JP 2012522834 A JP2012522834 A JP 2012522834A JP 2012522834 A JP2012522834 A JP 2012522834A JP 2013500539 A JP2013500539 A JP 2013500539A
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predicate
predictor
computing system
cores
core
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バーガー，ダグ
ケックラー，ステファン，ダブリュー．
エスマエイルザデー，ハーディ
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ボード オブ リージエンツ，ユニバーシテイ オブ テキサス システム
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
    • G06F8/4451—Avoiding pipeline stalls
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
  • Executing Machine-Instructions (AREA)
JP2012522834A 2009-09-09 2010-06-11 分散型プレディケート予測を実現するための方法、システム、およびコンピュータによってアクセス可能な媒体 Pending JP2013500539A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/556,440 US8433885B2 (en) 2009-09-09 2009-09-09 Method, system and computer-accessible medium for providing a distributed predicate prediction
US12/556,440 2009-09-09
PCT/US2010/038350 WO2011031361A1 (en) 2009-09-09 2010-06-11 Method, system and computer-accessible medium for providing a distributed predicate prediction

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JP2014095690A Division JP5747104B2 (ja) 2009-09-09 2014-05-07 分散型プレディケート予測を実現するための方法、システム、およびコンピュータによってアクセス可能な媒体

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JP2014095690A Active JP5747104B2 (ja) 2009-09-09 2014-05-07 分散型プレディケート予測を実現するための方法、システム、およびコンピュータによってアクセス可能な媒体
JP2015096238A Pending JP2015164068A (ja) 2009-09-09 2015-05-11 分散型プレディケート予測を実現するための方法、システム、およびコンピュータによってアクセス可能な媒体

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JP2015096238A Pending JP2015164068A (ja) 2009-09-09 2015-05-11 分散型プレディケート予測を実現するための方法、システム、およびコンピュータによってアクセス可能な媒体

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US (1) US8433885B2 (enExample)
JP (3) JP2013500539A (enExample)
KR (1) KR101364314B1 (enExample)
CN (2) CN102473086B (enExample)
DE (1) DE112010003595B4 (enExample)
WO (1) WO2011031361A1 (enExample)

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US10678544B2 (en) 2015-09-19 2020-06-09 Microsoft Technology Licensing, Llc Initiating instruction block execution using a register access instruction
US10698859B2 (en) 2009-09-18 2020-06-30 The Board Of Regents Of The University Of Texas System Data multicasting with router replication and target instruction identification in a distributed multi-core processing architecture
US10719321B2 (en) 2015-09-19 2020-07-21 Microsoft Technology Licensing, Llc Prefetching instruction blocks
US10768936B2 (en) 2015-09-19 2020-09-08 Microsoft Technology Licensing, Llc Block-based processor including topology and control registers to indicate resource sharing and size of logical processor
US10776115B2 (en) 2015-09-19 2020-09-15 Microsoft Technology Licensing, Llc Debug support for block-based processor
US10871967B2 (en) 2015-09-19 2020-12-22 Microsoft Technology Licensing, Llc Register read/write ordering
US10936316B2 (en) 2015-09-19 2021-03-02 Microsoft Technology Licensing, Llc Dense read encoding for dataflow ISA
US11016770B2 (en) 2015-09-19 2021-05-25 Microsoft Technology Licensing, Llc Distinct system registers for logical processors
US11126433B2 (en) 2015-09-19 2021-09-21 Microsoft Technology Licensing, Llc Block-based processor core composition register
US11681531B2 (en) 2015-09-19 2023-06-20 Microsoft Technology Licensing, Llc Generation and use of memory access instruction order encodings

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US9946549B2 (en) 2015-03-04 2018-04-17 Qualcomm Incorporated Register renaming in block-based instruction set architecture
US9916164B2 (en) * 2015-06-11 2018-03-13 Intel Corporation Methods and apparatus to optimize instructions for execution by a processor
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US9952867B2 (en) 2015-06-26 2018-04-24 Microsoft Technology Licensing, Llc Mapping instruction blocks based on block size
US10175988B2 (en) 2015-06-26 2019-01-08 Microsoft Technology Licensing, Llc Explicit instruction scheduler state information for a processor
US20160378491A1 (en) * 2015-06-26 2016-12-29 Microsoft Technology Licensing, Llc Determination of target location for transfer of processor control
US10409606B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Verifying branch targets
US9946548B2 (en) 2015-06-26 2018-04-17 Microsoft Technology Licensing, Llc Age-based management of instruction blocks in a processor instruction window
US9720693B2 (en) 2015-06-26 2017-08-01 Microsoft Technology Licensing, Llc Bulk allocation of instruction blocks to a processor instruction window
US10409599B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Decoding information about a group of instructions including a size of the group of instructions
US10191747B2 (en) 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US11755484B2 (en) 2015-06-26 2023-09-12 Microsoft Technology Licensing, Llc Instruction block allocation
US10169044B2 (en) 2015-06-26 2019-01-01 Microsoft Technology Licensing, Llc Processing an encoding format field to interpret header information regarding a group of instructions
US9940136B2 (en) 2015-06-26 2018-04-10 Microsoft Technology Licensing, Llc Reuse of decoded instructions
US20170083341A1 (en) * 2015-09-19 2017-03-23 Microsoft Technology Licensing, Llc Segmented instruction block
US10061584B2 (en) 2015-09-19 2018-08-28 Microsoft Technology Licensing, Llc Store nullification in the target field
US20170083319A1 (en) * 2015-09-19 2017-03-23 Microsoft Technology Licensing, Llc Generation and use of block branch metadata
US10031756B2 (en) 2015-09-19 2018-07-24 Microsoft Technology Licensing, Llc Multi-nullification
US10095519B2 (en) 2015-09-19 2018-10-09 Microsoft Technology Licensing, Llc Instruction block address register
US11687345B2 (en) 2016-04-28 2023-06-27 Microsoft Technology Licensing, Llc Out-of-order block-based processors and instruction schedulers using ready state data indexed by instruction position identifiers
US20180081690A1 (en) * 2016-09-21 2018-03-22 Qualcomm Incorporated Performing distributed branch prediction using fused processor cores in processor-based systems
US11531552B2 (en) 2017-02-06 2022-12-20 Microsoft Technology Licensing, Llc Executing multiple programs simultaneously on a processor core
US10963379B2 (en) 2018-01-30 2021-03-30 Microsoft Technology Licensing, Llc Coupling wide memory interface to wide write back paths
US10824429B2 (en) 2018-09-19 2020-11-03 Microsoft Technology Licensing, Llc Commit logic and precise exceptions in explicit dataflow graph execution architectures

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JP2013534004A (ja) * 2010-06-18 2013-08-29 ボード・オブ・リージエンツ，ザ・ユニバーシテイ・オブ・テキサス・システム 統合分岐先・述語予測
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US10678544B2 (en) 2015-09-19 2020-06-09 Microsoft Technology Licensing, Llc Initiating instruction block execution using a register access instruction
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US11977891B2 (en) 2015-09-19 2024-05-07 Microsoft Technology Licensing, Llc Implicit program order

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JP2014142969A (ja) 2014-08-07
JP5747104B2 (ja) 2015-07-08
KR101364314B1 (ko) 2014-02-18
JP2015164068A (ja) 2015-09-10
CN105183449B (zh) 2018-12-18
WO2011031361A1 (en) 2011-03-17
CN102473086B (zh) 2015-08-19
KR20120068855A (ko) 2012-06-27
US20110060889A1 (en) 2011-03-10
CN105183449A (zh) 2015-12-23
CN102473086A (zh) 2012-05-23
DE112010003595B4 (de) 2024-06-06
US8433885B2 (en) 2013-04-30
DE112010003595T5 (de) 2012-11-22

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