JP2013258484A - Dielectric board connection structure - Google Patents

Dielectric board connection structure Download PDF

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JP2013258484A
JP2013258484A JP2012132121A JP2012132121A JP2013258484A JP 2013258484 A JP2013258484 A JP 2013258484A JP 2012132121 A JP2012132121 A JP 2012132121A JP 2012132121 A JP2012132121 A JP 2012132121A JP 2013258484 A JP2013258484 A JP 2013258484A
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dielectric substrate
signal line
connection structure
dielectric
conductor
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Satoshi Takahashi
聡 高橋
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Fujitsu Ltd
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Fujitsu Ltd
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Abstract

PROBLEM TO BE SOLVED: To mount components achieving high package density in a device where the components are installed on a multi-layer dielectric board.SOLUTION: An insulator layer is covered by an inner conductor, and an outer conductor is covered by the insulator layer. Openings are provided at the outer conductor and the insulator layer so as to expose the inner conductor. Signal line paths, such as a microstrip line and a coplanar line, which are formed on a surface of a dielectric board, are electrically connected with the inner conductor through the openings. This structure allows electronic components to be mounted on the dielectric board achieving higher packaging density than a convention structure. Further, the structure realizes higher heat radiation performance than the convention structure.

Description

本発明は、誘電体基板上の信号線路と、同軸線路との接続構造に関する。   The present invention relates to a connection structure between a signal line on a dielectric substrate and a coaxial line.

トランジスタ等の電子部品が誘電体基板上に実装された構造を有する装置において、誘電体基板上のマイクロストリップライン等の信号線路と、同軸線路または同軸コネクタとを電気的に接続する技術が知られている(例えば、特許文献1参照)。   In an apparatus having a structure in which an electronic component such as a transistor is mounted on a dielectric substrate, a technique for electrically connecting a signal line such as a microstrip line on the dielectric substrate and a coaxial line or a coaxial connector is known. (For example, refer to Patent Document 1).

また、誘電体基板上の信号線路と、該誘電体基板に設けられたスルーホールを通る同軸線とを接続することにより、複数の積層したそれぞれの誘電体基板上の信号線路間を接続する技術が知られている(例えば、特許文献2参照)。   Also, a technique for connecting signal lines on each of a plurality of laminated dielectric substrates by connecting a signal line on the dielectric substrate and a coaxial line passing through a through-hole provided in the dielectric substrate. Is known (see, for example, Patent Document 2).

ここで、図10及び図11をもとに、従来技術を用いた誘電体基板の積層構造について説明する。図10は従来技術を用いた誘電体基板の接続構造を示す側面図である。図11は従来の誘電体基板の接続構造における各層の誘電体基板の構造を示す平面図であり、(a)は図10中のA点から実線矢印方向に見た平面図、(b)は図10中のB点から破線矢印方向に見た平面図、(c)は図10中のB点から実線矢印方向に見た平面図、(d)は図10中のC点から破線矢印方向に見た平面図である。   Here, a laminated structure of a dielectric substrate using a conventional technique will be described with reference to FIGS. FIG. 10 is a side view showing a dielectric substrate connection structure using a conventional technique. FIG. 11 is a plan view showing the structure of the dielectric substrate of each layer in the conventional dielectric substrate connection structure, (a) is a plan view seen from the point A in FIG. 10 in the direction of the solid line arrow, and (b) is a plan view. 10 is a plan view seen from the point B in FIG. 10 in the direction of the broken line arrow, (c) is a plan view seen from the point B in FIG. 10 in the direction of the solid line arrow, and (d) is a direction from the point C in FIG. FIG.

図10及び図11において、誘電体基板301の外側の面には信号線路303が形成され、信号線路303上の適所には抵抗、コンデンサ等の電子部品305が実装されている。また、図10及び図11において、誘電体基板302の外側の面には信号線路304が形成され、信号線路304上の適所には電子部品305が実装されている。なお、ここでいう「内側の面」とは、それぞれの誘電体基板において他の誘電体基板と向かい合った面のことを指し、「外側の面」とはその反対側の面のことを指すものとする。   10 and 11, a signal line 303 is formed on the outer surface of the dielectric substrate 301, and electronic components 305 such as resistors and capacitors are mounted at appropriate positions on the signal line 303. 10 and 11, a signal line 304 is formed on the outer surface of the dielectric substrate 302, and an electronic component 305 is mounted at an appropriate position on the signal line 304. As used herein, “inner surface” refers to the surface of each dielectric substrate facing the other dielectric substrate, and “outer surface” refers to the opposite surface. And

誘電体基板301の内側の面と誘電体基板302の内側の面とは同軸線路306によって接続されている。ここで、同軸線路306は中心部に内部導体307が、また外周に外部導体308が同心円状に形成され、内部導体307と外部導体308との間には誘電体309が介在せしめられている。そして、信号線路303と信号線路304とは、内部導体307を介して電気的に接続されている。   The inner surface of the dielectric substrate 301 and the inner surface of the dielectric substrate 302 are connected by a coaxial line 306. Here, the coaxial line 306 has an inner conductor 307 formed at the center and an outer conductor 308 formed concentrically on the outer periphery, and a dielectric 309 is interposed between the inner conductor 307 and the outer conductor 308. The signal line 303 and the signal line 304 are electrically connected via the internal conductor 307.

また、誘電体基板301の内側の面と誘電体基板302の内側の面には導体箔等によって電位の基準面(GND面)が形成されており、外部導体308を介して互いに電気的に接続されている。   In addition, a reference surface (GND surface) of a potential is formed on the inner surface of the dielectric substrate 301 and the inner surface of the dielectric substrate 302 by a conductor foil or the like, and is electrically connected to each other via the external conductor 308. Has been.

図10及び図11において図示したように、従来の実装方法では複数の誘電体基板を積層させてそれぞれの誘電体基板に電子部品を実装する場合、同軸を挟んだ各々の誘電体基板の外側の面に信号線路が形成される。図12は従来の誘電体基板積層構造を筐体300に格納した場合の例を示す側面図である。なお、図10及び図11に示した誘電体基板接続構造の要素と共通するものに関しては、同一の符号を付している。図12に示す構造では、電子部品を両誘電体基板の外側の面に実装しなければならず、両誘電体基板の間に電子部品が実装されない無駄な空間が生じるため、実装密度が低くなってしまう。   As shown in FIGS. 10 and 11, in the conventional mounting method, when a plurality of dielectric substrates are stacked and an electronic component is mounted on each dielectric substrate, the outer side of each dielectric substrate sandwiching the coaxial is sandwiched. A signal line is formed on the surface. FIG. 12 is a side view showing an example in which a conventional dielectric substrate laminated structure is stored in a housing 300. In addition, the same code | symbol is attached | subjected about the thing which is common in the element of the dielectric substrate connection structure shown in FIG.10 and FIG.11. In the structure shown in FIG. 12, the electronic components must be mounted on the outer surfaces of the two dielectric substrates, and a useless space in which the electronic components are not mounted is generated between the two dielectric substrates. End up.

上述の問題を解決するために、スルーホール等を利用して信号線路を誘電体基板の内側の面に導くことで、電子部品の実装面の向きを揃える構造が考えられる。図13は従来の誘電体基板の層状構造において、スルーホール310を用いて実装面を変更した場合の形態を示す側面図、図14(a)は図13中のA点から実線矢印方向に見た平面図、(b)は図13中のB点から破線矢印方向に見た平面図、(c)は図13中のB点から実線矢印方向に見た平面図、(d)は図13中のC点から破線矢印方向に見た平面図である。図13及び図14において、誘電体基板302の内側の面には信号線路311が形成され、その適所には電子部品305が実装されている。また、信号線路311は、スルーホール310を通じて信号線路304と電気的に接続されている。   In order to solve the above-described problem, a structure is considered in which the direction of the mounting surface of the electronic component is aligned by guiding the signal line to the inner surface of the dielectric substrate using a through hole or the like. FIG. 13 is a side view showing a configuration in which a mounting surface is changed using a through hole 310 in a conventional layered structure of a dielectric substrate, and FIG. 14A is a view from the point A in FIG. (B) is a plan view seen from the point B in FIG. 13 in the direction of the broken line arrow, (c) is a plan view seen from the point B in FIG. 13 in the direction of the solid line arrow, and (d) is FIG. It is the top view seen from the C point in the inside in the direction of a dashed-line arrow. 13 and 14, a signal line 311 is formed on the inner surface of the dielectric substrate 302, and an electronic component 305 is mounted at an appropriate position. The signal line 311 is electrically connected to the signal line 304 through the through hole 310.

このような構造を用いることで誘電体基板301と誘電体基板302とで電子部品305の実装面の向きを揃えることが可能となるが、該構造においては電子部品の実装に様々な制約が生じるため、実装密度を大きくする効果は限定的である。   By using such a structure, it is possible to align the mounting direction of the electronic component 305 between the dielectric substrate 301 and the dielectric substrate 302. However, in this structure, various restrictions are imposed on the mounting of the electronic component. Therefore, the effect of increasing the mounting density is limited.

具体的には、誘電体基板302の内側の面において、同軸線路306とスルーホール311との間には信号線路が存在しないため、この領域に電子部品を実装することができない。また、誘電体基板302の外側の面において、同軸線路306とスルーホール311との間に信号線路304が存在するため、この部分を筐体のGND面(電位が0である基準面)に接触させることができない。   Specifically, since no signal line exists between the coaxial line 306 and the through hole 311 on the inner surface of the dielectric substrate 302, an electronic component cannot be mounted in this region. In addition, since the signal line 304 exists between the coaxial line 306 and the through hole 311 on the outer surface of the dielectric substrate 302, this portion is brought into contact with the GND surface (reference surface where the potential is 0) of the housing. I can't let you.

実開平6−73902号公報Japanese Utility Model Publication No. 6-73902 特開2001−189609号公報JP 2001-189609 A

そこで、本発明では、複数層の誘電体基板上に部品が配置された装置において、高い実装密度で部品を実装することが可能な構造を提供することを目的とする。   Therefore, an object of the present invention is to provide a structure in which components can be mounted at a high mounting density in an apparatus in which components are arranged on a plurality of layers of dielectric substrates.

上記の課題を解決するために、本発明にかかる誘電体基板接続構造は、内部導体と、該内部導体を被覆する絶縁体層と、該絶縁体層を被覆する外部導体層と、該内部導体を露出させる開口部とを有する同軸線路と、前記内部導体と電気的に接続された信号線路を表面に有する誘電体基板とを含む。   In order to solve the above problems, a dielectric substrate connection structure according to the present invention includes an inner conductor, an insulator layer covering the inner conductor, an outer conductor layer covering the insulator layer, and the inner conductor. And a dielectric substrate having a signal line electrically connected to the inner conductor on the surface.

複数層の誘電体基板上に部品が配置された装置において、高い実装密度で部品を実装することが可能になる。   In an apparatus in which components are arranged on a multi-layer dielectric substrate, components can be mounted at a high mounting density.

第1の実施の形態にかかる誘電体基板接続構造の斜視図。The perspective view of the dielectric substrate connection structure concerning 1st Embodiment. 第1の実施の形態にかかる誘電体基板接続構造の側面図。The side view of the dielectric substrate connection structure concerning a 1st embodiment. 第1の実施の形態にかかる誘電体基板接続構造の平面図。The top view of the dielectric substrate connection structure concerning 1st Embodiment. 第1の実施の形態にかかる誘電体基板接続構造を筐体100に格納した場合の側面図例。The side view example at the time of storing the dielectric substrate connection structure concerning 1st Embodiment in the housing | casing 100. FIG. 第2の実施の形態にかかる誘電体基板接続構造の側面図。The side view of the dielectric substrate connection structure concerning 2nd Embodiment. 第2の実施の形態にかかる誘電体基板接続構造の平面図。The top view of the dielectric substrate connection structure concerning 2nd Embodiment. 第3の実施の形態にかかる誘電体基板接続構造の側面図。The side view of the dielectric substrate connection structure concerning 3rd Embodiment. 第3の実施の形態にかかる誘電体基板接続構造の平面図。The top view of the dielectric substrate connection structure concerning 3rd Embodiment. 第3の実施の形態にかかる誘電体基板接続構造を筐体200に格納した場合の側面図例。The example of a side view at the time of storing the dielectric substrate connection structure concerning 3rd Embodiment in the housing | casing 200. FIG. 従来技術を用いた誘電体基板の第一の例の接続構造を示す側面図。The side view which shows the connection structure of the 1st example of the dielectric substrate using a prior art. 従来技術を用いた誘電体基板の第一の例の接続構造を示す平面図。The top view which shows the connection structure of the 1st example of the dielectric substrate using a prior art. 従来技術を用いた誘電体基板の第一の例の接続構造を筐体300に格納した場合の側面図例。The side view example at the time of storing the connection structure of the 1st example of the dielectric material board using a prior art in the housing | casing 300. FIG. 従来技術を用いた誘電体基板の第二の例の接続構造を示す側面図。The side view which shows the connection structure of the 2nd example of the dielectric substrate using a prior art. 従来技術を用いた誘電体基板の第二の例の接続構造を示す平面図。The top view which shows the connection structure of the 2nd example of the dielectric substrate using a prior art.

以下に添付図面を参照して、本発明にかかる誘電体基板接続構造の実施の形態について詳細に説明する。なお、この実施の形態は開示の技術を限定するものではない。
[第1の実施の形態]
Exemplary embodiments of a dielectric substrate connecting structure according to the present invention will be explained below in detail with reference to the accompanying drawings. Note that this embodiment does not limit the disclosed technology.
[First Embodiment]

図1は第1の実施の形態にかかる誘電体基板接続構造の斜視図、図2は第1の実施の形態にかかる誘電体基板接続構造の側面図である。また、図3(a)(b)(c)及び(d)はそれぞれ図2中のA点から実線矢印方向に見た平面図(a)、B点から破線矢印方向に見た平面図(b)、B点から実線矢印方向に見た平面図(c)及びC点から破線矢印方向に見た平面図(d)である。   FIG. 1 is a perspective view of the dielectric substrate connection structure according to the first embodiment, and FIG. 2 is a side view of the dielectric substrate connection structure according to the first embodiment. 3 (a), (b), (c) and (d) are respectively a plan view (a) viewed from the point A in FIG. 2 in the direction of the solid line arrow, and a plan view viewed from the point B in the direction of the broken line arrow ( b) A plan view (c) seen from the point B in the direction of the solid line arrow and a plan view (d) seen from the point C in the direction of the broken line arrow.

ここで、本実施の形態にかかる誘電体基板の材質としてはエポキシ、PTFE(ポリテトラフルオロエチレン)、ポリイミド等が用いられることが一般的である。しかし、本実施の形態にかかる誘電体基板接続構造を含む装置の機能が正しく実現可能であれば、どのような誘電体を用いても構わない。これは第2の実施の形態以降についても同様である。   Here, as a material of the dielectric substrate according to the present embodiment, epoxy, PTFE (polytetrafluoroethylene), polyimide, or the like is generally used. However, any dielectric material may be used as long as the function of the device including the dielectric substrate connection structure according to the present embodiment can be correctly realized. The same applies to the second and subsequent embodiments.

図1、図2及び図3において、誘電体基板1の外側の面には信号線路3が形成され、信号線路3上の適所には抵抗、コンデンサ等の電子部品5が実装されている。なお、本実施の形態では引き続き、それぞれの誘電体基板において他の誘電体基板と向かい合った面を「内側の面」、その反対側の面を「外側の面」と呼称することがある。また、以下信号線路としてマイクロストリップラインを用いた場合について説明する。   1, 2, and 3, a signal line 3 is formed on the outer surface of the dielectric substrate 1, and electronic components 5 such as resistors and capacitors are mounted at appropriate positions on the signal line 3. In the present embodiment, the surface of each dielectric substrate that faces the other dielectric substrate may be referred to as an “inner surface” and the opposite surface may be referred to as an “outer surface”. The case where a microstrip line is used as the signal line will be described below.

また、図1、図2及び図3において、誘電体基板2の内側の面には信号線路4が形成され、信号線路4上の適所には電子部品5が実装されている。
誘電体基板1の内側の面と誘電体基板2の内側の面との間には同軸線路6が形成されており、同軸線路6は中心部に内部導体7が、また外周に外部導体8が同心円状に形成され、内部導体7と外部導体8との間には誘電体9が介在せしめられている。また、外部導体8の外側には必要に応じて絶縁体層(図示せず)が形成されていてもよい。そして、信号線路3と信号線路4とは、内部導体7を介して電気的に接続されている。また、各々の同軸線路は、本発明にかかる誘電体基板接続構造を構成する各電子部品及び各信号線路の特性インピーダンスと整合するように配置されているものとする。
1, 2, and 3, a signal line 4 is formed on the inner surface of the dielectric substrate 2, and an electronic component 5 is mounted at an appropriate position on the signal line 4.
A coaxial line 6 is formed between the inner surface of the dielectric substrate 1 and the inner surface of the dielectric substrate 2, and the coaxial line 6 has an inner conductor 7 at the center and an outer conductor 8 at the outer periphery. Concentric circles are formed, and a dielectric 9 is interposed between the inner conductor 7 and the outer conductor 8. Further, an insulator layer (not shown) may be formed outside the outer conductor 8 as necessary. The signal line 3 and the signal line 4 are electrically connected via the internal conductor 7. Each coaxial line is arranged so as to match the characteristic impedance of each electronic component and each signal line constituting the dielectric substrate connection structure according to the present invention.

さらに、同軸線路6には内部導体7を露出させるように切り出し窓10が形成されており、信号線路4は切り出し窓10を通り、外部導体8に接触することなく内部導体7と電気的に接続されている。   Further, a cutout window 10 is formed in the coaxial line 6 so as to expose the inner conductor 7, and the signal line 4 passes through the cutout window 10 and is electrically connected to the inner conductor 7 without contacting the outer conductor 8. Has been.

誘電体基板1の内側の面には導体箔等によってGND面が形成されており、同軸線路6の外部導体8と電気的に接続されている。また、誘電体基板2の外側の面にも導体箔等によってGND面が形成され、スルーホール11を介して外部導体8と電気的に接続されている。   A GND surface is formed on the inner surface of the dielectric substrate 1 by a conductor foil or the like, and is electrically connected to the outer conductor 8 of the coaxial line 6. A GND surface is also formed on the outer surface of the dielectric substrate 2 by a conductor foil or the like, and is electrically connected to the external conductor 8 through the through hole 11.

本実施の形態によれば、誘電体基板1と誘電体基板2とを同軸線路6によって接続した構造において誘電体基板2の内側の面に実装面を設けることが可能である。すなわち、複数層の誘電体基板を接続する構造において、各層の電子部品の実装面の向きを揃えることができる。また、本構造によれば、実装される電子部品の大きさに合わせて同軸線路6の長さを設定することで、容易に誘電体基板間の厚さを変更できる。さらに、本構造によれば、スルーホールを用いて実装面を変更することなく各層の電子部品の実装面を揃えることが可能であるので、従来の誘電体基板接続構造よりも電子部品の実装面を揃えた際に生じる構造上の制約が少ない。したがって、本実施の形態にかかる誘電体基板接続構造は、従来の誘電体基板接続構造と比較して高い実装密度を実現することができる。   According to the present embodiment, it is possible to provide a mounting surface on the inner surface of the dielectric substrate 2 in the structure in which the dielectric substrate 1 and the dielectric substrate 2 are connected by the coaxial line 6. That is, in a structure in which a plurality of layers of dielectric substrates are connected, the orientation of the mounting surface of the electronic component of each layer can be made uniform. Moreover, according to this structure, the thickness between the dielectric substrates can be easily changed by setting the length of the coaxial line 6 according to the size of the electronic component to be mounted. Furthermore, according to this structure, it is possible to align the mounting surface of the electronic component of each layer without changing the mounting surface using a through hole, so that the mounting surface of the electronic component is more than the conventional dielectric substrate connection structure. There are few structural restrictions that arise when aligning. Therefore, the dielectric substrate connection structure according to the present embodiment can achieve a higher mounting density than the conventional dielectric substrate connection structure.

図4は本実施の形態にかかる誘電体基板接続構造を筐体100に格納した場合の例を表す側面図である。なお、図1乃至図3に示した誘電体基板接続構造の要素と共通するものに関しては、同一の符号を付している。図4に示すように、本実施の形態によれば、誘電体基板2の外側の面全体をGND面とすることができるので、誘電体基板2の外側の面を筐体100のGND面と任意に接触させることができる。したがって、本実施の形態にかかる誘電体基板接続構造は、従来の誘電体基板接続構造と比較して放熱性を高くすることができるとともに、GND面を強化することができる。   FIG. 4 is a side view showing an example when the dielectric substrate connection structure according to the present embodiment is stored in the housing 100. In addition, the same code | symbol is attached | subjected about the thing which is common in the element of the dielectric substrate connection structure shown in FIG. 1 thru | or FIG. As shown in FIG. 4, according to the present embodiment, the entire outer surface of dielectric substrate 2 can be the GND surface, so that the outer surface of dielectric substrate 2 is the GND surface of housing 100. It can be contacted arbitrarily. Therefore, the dielectric substrate connection structure according to the present embodiment can increase heat dissipation and strengthen the GND surface as compared with the conventional dielectric substrate connection structure.

なお、図1、図2及び図3において、各誘電体基板上に電子部品5がそれぞれ1個ずつ図示されているが、実際にはそれぞれ複数個実装されていても構わない。また、図1,図2及び図3において、信号線路3及び信号線路4は直線上に図示されているが、実際にはそれぞれ曲線であっても、分岐していても構わない。また、図1、図2及び図3において、信号線路3と信号線路4が平行となるように切り出し窓10の向きが設定されているが、実際には任意の方向に切り出し窓10を形成し、内部導体7と信号線路4とを接続させても構わない。
[第2の実施の形態]
1, 2, and 3, one electronic component 5 is illustrated on each dielectric substrate. However, a plurality of electronic components 5 may be actually mounted. 1, 2 and 3, the signal line 3 and the signal line 4 are illustrated on a straight line, but may actually be curved or branched. 1, 2, and 3, the direction of the cutout window 10 is set so that the signal line 3 and the signal line 4 are parallel to each other, but in practice, the cutout window 10 is formed in an arbitrary direction. The internal conductor 7 and the signal line 4 may be connected.
[Second Embodiment]

次に、第2の実施の形態にかかる誘電体基板接続構造について説明する。第1の実施の形態では、2層の誘電体基板を接続させた構造について説明を行ったが、第2の実施の形態では3層以上の誘電体基板を接続させた構造について説明を行う。   Next, a dielectric substrate connection structure according to the second embodiment will be described. In the first embodiment, a structure in which two layers of dielectric substrates are connected is described. In the second embodiment, a structure in which three or more layers of dielectric substrates are connected is described.

図5は、第2の実施の形態にかかる誘電体基板接続構造の側面図である。図5及び図6において、誘電体基板101の上側の面には信号線路104が、誘電体基板102の上側の面には信号線路105が、誘電体基板103の上側の面には信号線路106がそれぞれ形成され、信号線路104、信号線路105及び信号線路106上の適所にはそれぞれ抵抗、コンデンサ等の電子部品107が実装されている。   FIG. 5 is a side view of the dielectric substrate connection structure according to the second embodiment. 5 and 6, the signal line 104 is provided on the upper surface of the dielectric substrate 101, the signal line 105 is provided on the upper surface of the dielectric substrate 102, and the signal line 106 is provided on the upper surface of the dielectric substrate 103. Are formed, and electronic components 107 such as resistors and capacitors are mounted at appropriate positions on the signal line 104, the signal line 105, and the signal line 106, respectively.

図6は第2の実施の形態にかかる誘電体基板接続構造を示す平面図であり、(a)は誘電体基板101の平面図、(b)は誘電体基板102の平面図、(c)は誘電体基板103の平面図である。誘電体基板101の下側の面と誘電体基板102の上側の面との間には同軸線路108が形成されており、同軸線路108は中心部に内部導体109が、また外周に外部導体110が同心円状に形成され、内部導体109と外部導体110との間には誘電体111が介在せしめられている。また、外部導体110の外側には必要に応じて絶縁体層(図示せず)が形成されていてもよい。そして、信号線路104と信号線路105とは、内部導体109を介して電気的に接続されている。   6A and 6B are plan views showing a dielectric substrate connection structure according to the second embodiment, wherein FIG. 6A is a plan view of the dielectric substrate 101, FIG. 6B is a plan view of the dielectric substrate 102, and FIG. FIG. 3 is a plan view of the dielectric substrate 103. A coaxial line 108 is formed between the lower surface of the dielectric substrate 101 and the upper surface of the dielectric substrate 102. The coaxial line 108 has an inner conductor 109 at the center and an outer conductor 110 at the outer periphery. Are formed concentrically, and a dielectric 111 is interposed between the inner conductor 109 and the outer conductor 110. Further, an insulator layer (not shown) may be formed outside the outer conductor 110 as necessary. The signal line 104 and the signal line 105 are electrically connected via the internal conductor 109.

同様に、誘電体基板102の下側の面と誘電体基板103の上側の面との間にも同軸線路108が形成されており、信号線路105と信号線路106とは、内部導体109を介して電気的に接続されている。また、各々の同軸線路は、本発明にかかる誘電体基板接続構造を構成する各電子部品及び各信号線路の特性インピーダンスと整合するように配置されているものとする。   Similarly, a coaxial line 108 is also formed between the lower surface of the dielectric substrate 102 and the upper surface of the dielectric substrate 103, and the signal line 105 and the signal line 106 are connected via the internal conductor 109. Are electrically connected. Each coaxial line is arranged so as to match the characteristic impedance of each electronic component and each signal line constituting the dielectric substrate connection structure according to the present invention.

さらに、同軸線路108には内部導体109を露出させるように切り出し窓112が形成されており、信号線路105、信号線路106はそれぞれ切り出し窓を通り、外部導体110に接触することなく内部導体109と電気的に接続されている。誘電体基板101,102及び103の下側の面には導体箔等によってGND面が形成されており、それぞれのGND面は、スルーホール113及び外部導体110を介して互いに電気的に接続されている。   Further, a cutout window 112 is formed on the coaxial line 108 so as to expose the internal conductor 109, and the signal line 105 and the signal line 106 pass through the cutout window and contact the internal conductor 109 without contacting the external conductor 110. Electrically connected. A GND surface is formed by a conductive foil or the like on the lower surface of the dielectric substrates 101, 102, and 103, and each GND surface is electrically connected to each other through the through hole 113 and the external conductor 110. Yes.

本実施の形態によれば、各層の電子部品の実装面を揃えることで、3層以上の誘電体基板を接続させた構造をとることができる。
[第3の実施の形態]
According to the present embodiment, it is possible to adopt a structure in which three or more dielectric substrates are connected by aligning the mounting surfaces of the electronic components of the respective layers.
[Third Embodiment]

次に、第3の実施の形態にかかる誘電体基板接続構造について説明する。第1の実施の形態及び第2の実施の形態では2層以上の誘電体基板を接続させた構造において、各層の電子部品の実装面を揃えた構造について説明を行ったが、第3の実施の形態では2層の誘電体基板を接続させた構造において、2つの誘電体基板をつなぐ同軸線路を挟んで向かい合った面に電子部品の実装面が形成された構造について説明を行う。   Next, a dielectric substrate connection structure according to the third embodiment will be described. In the first embodiment and the second embodiment, in the structure in which two or more dielectric substrates are connected, the structure in which the mounting surfaces of the electronic components of each layer are aligned has been described. The third embodiment In the embodiment, a structure in which two layers of dielectric substrates are connected and a mounting surface of an electronic component is formed on a surface facing each other across a coaxial line connecting the two dielectric substrates will be described.

図7は、第3の実施の形態にかかる誘電体基板接続構造の側面図、図8(a)(b)(c)及び(d)はそれぞれ図7中のA点から実線矢印方向に見た平面図(a)、B点から破線矢印方向に見た平面図(b)、B点から実線矢印方向に見た平面図(c)及びC点から破線矢印方向に見た平面図である。   7 is a side view of the dielectric substrate connecting structure according to the third embodiment. FIGS. 8A, 8B, 8C, and 8D are respectively viewed from the point A in FIG. FIG. 4A is a plan view seen from the point B in the direction of the dashed arrow, a plan view seen from the point B in the direction of the solid arrow, and a plan view seen from the point C in the direction of the dashed arrow. .

図7及び図8において、誘電体基板201の内側の面には信号線路203が形成され、信号線路203上の適所には抵抗、コンデンサ等の電子部品205が実装されている。また、図7において、誘電体基板202の内側の面には信号線路204が形成され、信号線路204上の適所には抵抗、コンデンサ等の電子部品205が実装されている。   7 and 8, a signal line 203 is formed on the inner surface of the dielectric substrate 201, and electronic components 205 such as resistors and capacitors are mounted at appropriate positions on the signal line 203. In FIG. 7, a signal line 204 is formed on the inner surface of the dielectric substrate 202, and electronic components 205 such as resistors and capacitors are mounted at appropriate positions on the signal line 204.

誘電体基板201の下側の面と誘電体基板202の上側の面との間には同軸線路206が形成されており、同軸線路206は中心部に内部導体207が、また外周に外部導体208が同心円状に形成され、内部導体207と外部導体208との間には誘電体209が介在せしめられている。また、外部導体208の外側には必要に応じて絶縁体層(図示せず)が形成されていてもよい。そして、信号線路203と信号線路204とは、内部導体207を介して電気的に接続されている。また、各々の同軸線路は、本発明にかかる誘電体基板接続構造を構成する各電子部品及び各信号線路の特性インピーダンスと整合するように配置されているものとする。   A coaxial line 206 is formed between the lower surface of the dielectric substrate 201 and the upper surface of the dielectric substrate 202. The coaxial line 206 has an inner conductor 207 at the center and an outer conductor 208 at the outer periphery. Are formed concentrically, and a dielectric 209 is interposed between the inner conductor 207 and the outer conductor 208. Further, an insulator layer (not shown) may be formed outside the external conductor 208 as necessary. The signal line 203 and the signal line 204 are electrically connected through the internal conductor 207. Each coaxial line is arranged so as to match the characteristic impedance of each electronic component and each signal line constituting the dielectric substrate connection structure according to the present invention.

さらに、同軸線路206には内部導体207を露出させるように切り出し窓210及び切り出し窓211が形成されている。そして、信号線路203は切り出し窓210を、信号線路204は切り出し窓211をそれぞれ通り、外部導体208に接触することなく内部導体207と電気的に接続されている。   Furthermore, a cutout window 210 and a cutout window 211 are formed in the coaxial line 206 so as to expose the internal conductor 207. The signal line 203 passes through the cutout window 210, and the signal line 204 passes through the cutout window 211, and is electrically connected to the internal conductor 207 without contacting the external conductor 208.

誘電体基板201の上側の面には導体箔等によってGND面が形成されており、スルーホール212を介して外部導体208と電気的に接続されている。また、誘電体基板202の下側の面には導体箔等によってGND面が形成されており、スルーホール212を介して外部導体208と電気的に接続されている。   A GND surface is formed on the upper surface of the dielectric substrate 201 with a conductive foil or the like, and is electrically connected to the external conductor 208 through the through hole 212. In addition, a GND surface is formed on the lower surface of the dielectric substrate 202 with a conductive foil or the like, and is electrically connected to the external conductor 208 through the through hole 212.

本実施の形態によれば、誘電体基板201と誘電体基板202とを同軸線路206によって結合した構造において誘電体基板201の下側の面と誘電体基板202の上側の面とに実装面を設けることが可能である。したがって、本実施の形態によれば、第1の実施の形態と比較してさらに高い実装密度を実現することができるとともに、GND面を強化することができる。   According to the present embodiment, the mounting surface is formed on the lower surface of the dielectric substrate 201 and the upper surface of the dielectric substrate 202 in the structure in which the dielectric substrate 201 and the dielectric substrate 202 are coupled by the coaxial line 206. It is possible to provide. Therefore, according to the present embodiment, it is possible to achieve a higher mounting density than that of the first embodiment and to strengthen the GND surface.

図9は本実施の形態にかかる誘電体基板接続構造を筐体200に格納した場合の例を表す側面図である。なお、図7及び図8に示した誘電体基板接続構造の要素と共通するものに関しては、同一の符号を付している。図9に示すように、本実施の形態によれば、誘電体基板201及び誘電体基板202の外側の面を筐体200のGND面と任意に接触させることができる。したがって、本実施の形態にかかる誘電体基板接続構造は、第1の実施の形態と比較してさらに放熱性を高くすることができる。   FIG. 9 is a side view showing an example in which the dielectric substrate connection structure according to the present embodiment is stored in the housing 200. In addition, the same code | symbol is attached | subjected about the thing which is common in the element of the dielectric substrate connection structure shown in FIG.7 and FIG.8. As shown in FIG. 9, according to the present embodiment, the outer surfaces of dielectric substrate 201 and dielectric substrate 202 can be arbitrarily brought into contact with the GND surface of housing 200. Therefore, the dielectric substrate connection structure according to the present embodiment can further improve the heat dissipation as compared with the first embodiment.

なお、ここまで本発明にかかる誘電体基板接続構造における信号線路としてマイクロストリップラインを用いた場合の例について説明を行ってきたが、実際にはコプレーナラインを信号線路として用いてもよい。それと同様に、本発明にかかる誘電体基板接続構造の各構成要素は、必ずしも図示の通りの形態をとる必要はなく、本発明の趣旨を損なわない範囲で種々の形態をとることができる。   Although the example in the case of using the microstrip line as the signal line in the dielectric substrate connection structure according to the present invention has been described so far, a coplanar line may actually be used as the signal line. Similarly, each component of the dielectric substrate connection structure according to the present invention does not necessarily have to take the form shown in the drawing, and can take various forms within a range not impairing the gist of the present invention.

1,2 誘電体基板
3,4 信号線路
5 電子部品
6 同軸線路
7 内部導体
8 外部導体
9 誘電体
10 切り出し窓
11 スルーホール
100 筐体
101〜103 誘電体基板
104〜106 信号線路
107 電子部品
108 同軸線路
109 内部導体
110 外部導体
111 誘電体
112 切り出し窓
113 スルーホール
200 筐体
201,202 誘電体基板
203,204 信号線路
205 電子部品
206 同軸線路
207 内部導体
208 外部導体
209 誘電体
210,211 切り出し窓
212 スルーホール
300 筐体
301,302 誘電体基板
303,304 信号線路
305 電子部品
306 同軸線路
307 内部導体
308 外部導体
309 誘電体
310,311 スルーホール
312 信号線路
DESCRIPTION OF SYMBOLS 1, 2 Dielectric board | substrates 3 and 4 Signal line 5 Electronic component 6 Coaxial line 7 Inner conductor 8 Outer conductor 9 Dielectric 10 Cutting window 11 Through hole 100 Housing | casing 101-103 Dielectric substrates 104-106 Signal line 107 Electronic component 108 Coaxial line 109 Internal conductor 110 External conductor 111 Dielectric 112 Cutting window 113 Through hole 200 Housing 201, 202 Dielectric substrate 203, 204 Signal line 205 Electronic component 206 Coaxial line 207 Internal conductor 208 External conductor 209 Dielectric 210, 211 Cutting Window 212 Through hole 300 Housing 301, 302 Dielectric substrate 303, 304 Signal line 305 Electronic component 306 Coaxial line 307 Internal conductor 308 External conductor 309 Dielectric 310, 311 Through hole 312 Signal line

Claims (7)

内部導体と、該内部導体を被覆する絶縁体層と、該絶縁体層を被覆する外部導体層と、該内部導体を露出させる該絶縁層及び該外部導体層に形成された開口部とを有する同軸線路と、
前記内部導体と電気的に接続し、かつ、前記開口部を通るように形成された信号線路を表面に有する誘電体基板と、
を含むことを特徴とする誘電体基板接続構造。
An inner conductor; an insulator layer covering the inner conductor; an outer conductor layer covering the insulator layer; the insulating layer exposing the inner conductor; and an opening formed in the outer conductor layer. A coaxial line,
A dielectric substrate electrically connected to the inner conductor and having a signal line formed on the surface thereof so as to pass through the opening;
A dielectric substrate connection structure comprising:
前記同軸線路は積層された複数の誘電体基板上の信号線路間を接続し、少なくとも一つの誘電体基板の表面に形成された信号線路が前記開口部を通るように形成されていることを特徴とする請求項2記載の誘電体基板接続構造。   The coaxial line connects signal lines on a plurality of laminated dielectric substrates, and a signal line formed on the surface of at least one dielectric substrate is formed so as to pass through the opening. The dielectric substrate connection structure according to claim 2. 複数の前記誘電体基板上の信号線路は、積層方向で同じ方向の面に形成されていることを特徴とする請求項3記載の誘電体基板接続構造。   4. The dielectric substrate connection structure according to claim 3, wherein the signal lines on the plurality of dielectric substrates are formed on surfaces in the same direction in the stacking direction. 複数の前記誘電体基板上の信号線路は、互いに向かい合う面に形成されていることを特徴とする請求項3記載の誘電体基板接続構造。   4. The dielectric substrate connection structure according to claim 3, wherein the signal lines on the plurality of dielectric substrates are formed on surfaces facing each other. 前記信号線路は、前記誘電体基板の前記信号線路と反対側の面に導体が形成されたマイクロストリップラインを構成する信号線路であることを特徴とする請求項1乃至5のいずれか1項に記載の誘電体基板接続構造。   6. The signal line according to claim 1, wherein the signal line is a signal line constituting a microstrip line in which a conductor is formed on a surface of the dielectric substrate opposite to the signal line. The dielectric substrate connection structure described. 前記信号線路は、前記信号線路を挟むように平行に複数の導体が形成されたコプレーナ線路を構成する信号線路であることを特徴とする請求項1乃至5のいずれか1項に記載の誘電体基板接続構造。   6. The dielectric according to claim 1, wherein the signal line is a signal line constituting a coplanar line in which a plurality of conductors are formed in parallel so as to sandwich the signal line. Board connection structure. 誘電体基板の表面に信号線路を形成し、
内部導体に絶縁体層を被覆させ、
前記絶縁体層に外部導体を被覆させ、
前記外部導体と前記絶縁体層とに前記内部導体を露出させるように開口部を形成し、
前記信号線路を、前記開口部を通るように前記内部導体と電気的に接続する
ことを特徴とする誘電体基板積層方法。
A signal line is formed on the surface of the dielectric substrate,
Cover the inner conductor with an insulator layer,
Coating the insulator layer with an outer conductor;
Forming an opening to expose the inner conductor to the outer conductor and the insulator layer;
The dielectric substrate laminating method, wherein the signal line is electrically connected to the inner conductor so as to pass through the opening.
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