JP5950683B2 - Multilayer substrate, printed circuit board, semiconductor package substrate, semiconductor package, semiconductor chip, semiconductor device, information processing apparatus and communication apparatus - Google Patents

Description

  The present invention relates to a multilayer substrate, a printed circuit board and a semiconductor package substrate using the multilayer substrate, a semiconductor package using the semiconductor package substrate, a semiconductor chip having a rewiring layer, a semiconductor device in which the semiconductor chip is sealed in a package, and a print The present invention relates to an information processing apparatus and a communication apparatus using at least one of a circuit board, a semiconductor chip, and a semiconductor device.

  In a multi-layer substrate constituting a resin printed circuit board, a package substrate, or the like, or a semiconductor chip rewiring layer, a GND (ground) layer or a GND plane in the layer is used as a reference potential, and a signal wiring (hereinafter, referred to as a signal wiring) The transmission line structure is simply provided with “wiring”. Here, when a high-speed signal or high noise resistance is required, a differential signal having a normal phase and a reverse phase is used, and the wiring is also two pair wirings. At this time, the driver outputs a differential signal, and the receiver identifies the logic signal based on whether the differential amplitude (positive phase-negative phase) is positive or negative.

  A differential signal is often used when transmitting a high-speed signal exceeding 1 Gbps, or when transmitting a long distance by a cable or the like. Therefore, it is necessary that the loss of frequency dependence in the transmission line is small in a frequency range from a low frequency to a signal frequency or several times thereof. The frequency-dependent loss includes a dielectric loss due to a dielectric surrounding the signal conductor of the transmission line, and a conductor loss due to the skin effect of the conductor.

  In order to reduce the dielectric loss, it is most effective to use a material having a small dielectric loss tangent (tan δ) which is a physical property value of the dielectric material. However, a material having a low dielectric loss tangent is more expensive than a normal dielectric loss tangent material.

  In order to reduce the conductor loss, it is necessary to use a material having a small conductor resistance or to make the conductor surface smooth (unevenness is several μm or less, preferably 1 μm or less). However, most of the conductive materials for printed circuit boards and package boards are copper, and there is no choice. Moreover, even if the conductor surface is completely smoothed, the increase in resistance due to the skin effect is only the same as the theoretical value, and cannot be reduced below the theoretical value.

  In addition, the differential signal is a signal transmission method in which common noise is inherently small and thus radiation noise is hardly generated. However, common noise may occur due to mode conversion in which a part of the differential amplitude is changed to the common amplitude due to asymmetry in the transmission path design of the printed circuit board or the package substrate or the semiconductor input / output buffer design.

  On the other hand, even if there is common noise in the GND plane, which is the reference potential, the differential amplitude is not affected by the common amplitude. However, for the same reason as described above, a part of the common amplitude is converted into the differential amplitude, May be disturbed.

  Therefore, in order to make full use of the merit of using differential signal transmission, it is important to maintain symmetry throughout the entire signal transmission path such as a semiconductor, a package, a printed circuit board, a connector, and wiring in a semiconductor chip. In Serial-ATA, which is one of various standards for handling high-speed differential signals, a restriction value for mode conversion is provided for each frequency.

  However, in a printed circuit board or a package board, the transmission path is not necessarily symmetrical. For example, between the pair wiring by the normal phase signal wiring and the negative phase signal wiring and the connector, the semiconductor package terminal, and the terminal of the semiconductor chip, the wiring of the positive phase signal and the negative phase signal is separated, and the connector Depending on the arrangement of pins and terminals, there is a difference in the length to the end of the pair wiring.

  Here, in order to adjust the length of the wiring, there is a case where the length of the wiring is adjusted by providing a bypass wiring that is originally unnecessary from the pin on which the wiring is shortened. However, even if the wiring lengths are equal, the shape is not symmetrical. Further, even after the pair wiring is formed, the wiring path is hardly required to be a straight line, and the path is traced while being bent while keeping the pair wiring in the multilayer substrate. Strictly speaking, it cannot be said that the entire transmission line is symmetrical.

  In order to solve such a problem, as a technique for reducing dielectric loss, an inner layer pair wiring is formed between a pair wiring (inner layer pair wiring) for a printed circuit board having a strip line structure with GND planes above and below. An arrangement has been proposed in which a dielectric material having a dielectric constant lower than that of a dielectric layer sandwiching a layer to be included from above and below is disposed (see, for example, Patent Document 1).

JP 2009-141233 A

However, the prior art has the following problems.
In the printed circuit board described in Patent Document 1, a material having a small relative dielectric constant and dielectric loss tangent is disposed only in the left and right or between the inner layer pair wirings and in any direction of the upper and lower GND planes. There is a problem that dielectric loss cannot be reduced. There is also a problem that no countermeasures are taken for common noise generated by mode conversion.

  The present invention has been made to solve the above-described problems, and is a multilayer substrate that can reduce dielectric loss, suppress common noise generated by mode conversion, and suppress an increase in cost. The purpose is to obtain.

Multilayer substrate according to the present invention, a wiring layer including the signal wiring for transmitting the differential signals, viewed contains a full or partial ground plane, disposed above and below with respect to one or more wiring layers And a dielectric layer provided between the wiring layer and the ground layer. The signal wiring for transmitting the operation signal constitutes a pair wiring, and the dielectric layers are wirings having different dielectric loss tangents. A first dielectric layer on the layer side and a second dielectric layer on the ground layer side. The first dielectric layer is provided so as to enclose the left and right sides and the upper and lower sides between the pair wirings. The tangent is smaller than the dielectric tangent of the second dielectric layer.

According to the multilayer substrate of the present invention, the dielectric layer provided between the wiring layer and the ground layer includes the first dielectric layer on the wiring layer side and the second dielectric on the ground layer side having different dielectric tangents. The dielectric loss tangent of the first dielectric layer is smaller than the dielectric loss tangent of the second dielectric layer.
Therefore, it is possible to reduce dielectric loss, suppress common noise generated by mode conversion, and suppress an increase in cost.

(A), (b) is the perspective view and sectional drawing which show a general conventional multilayer substrate. (A), (b) is sectional drawing which shows the multilayer board | substrate which concerns on Embodiment 1 of this invention with an electric force line. (A), (b) is sectional drawing which shows the multilayer board | substrate which concerns on Embodiment 2 of this invention with an electric force line. (A), (b) is sectional drawing which shows the structure of the base material of the multilayer substrate based on Embodiment 3 of this invention. (A)-(d) is sectional drawing which shows the structure of the base material of the multilayer substrate based on Embodiment 4 of this invention. It is explanatory drawing which illustrates the board | substrate wiring in the multilayer substrate based on Embodiment 5 of this invention.

Hereinafter, preferred embodiments of a multilayer substrate according to the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts will be described with the same reference numerals.
This multilayer substrate includes, for example, a printed circuit board and a semiconductor package board that transmit high-frequency signals, a semiconductor package using the semiconductor package board, a semiconductor chip and a semiconductor device having a redistribution layer, and a printed circuit board, a semiconductor chip, and a semiconductor device. It is used for an information processing apparatus and a communication apparatus using at least one.

Embodiment 1 FIG.
FIG. 1 is a perspective view and a cross-sectional view showing a pair wiring often used for a high-speed signal in a general conventional multilayer substrate. FIG. 1A shows a stripline structure, and FIG. 1B shows a microstrip structure. These structures can also be formed in the rewiring layer of the semiconductor chip.

  In FIG. 1, the multilayer substrate includes a dielectric material 1 of the substrate, a GND layer or a GND plane 20 (hereinafter, referred to as “GND plane 20”) provided in the layer, and a wiring layer 30. Has been. The wiring layer 30 includes wirings 301 and 302 that are a positive-phase signal wiring and a negative-phase signal wiring for differential signals. Here, even if the GND plane 20 is a complete plane without a hole, it may have a mesh structure due to restrictions at the time of forming a multilayer structure.

  The stripline structure means a structure in which layers having the GND plane 20 are provided above and below the wiring layer 30 and the space between the layers is filled with the dielectric material of the base material. In addition, the microstrip structure includes a layer having the GND plane 20 on only one of the upper and lower sides of the wiring layer 30, and the space between the layers is filled with the dielectric material of the base material, and is opposite to the wiring layer 30. This means that there is no substrate or GND plane 20 on the side, or there is a substrate with some thickness but no GND plane 20. Moreover, the pair wiring formed with each structure is called a stripline pair wiring and a microstrip pair wiring. In a microstrip structure substrate, a solder resist is often applied to the surface where the GND plane 20 is not provided, but is omitted here.

  Conventionally, in any structure, one kind of substrate material has been used. Therefore, in order to reduce the dielectric loss, increase the wiring length with a high-speed signal exceeding GHz, or increase the signal speed, it is necessary to make the base material a material with a small dielectric loss tangent, and the substrate is expensive. Met. Moreover, if all the base materials are made to have a low dielectric loss tangent, the common noise generated by the mode conversion is difficult to attenuate.

  FIG. 2 is a cross-sectional view showing the rewiring layer of the multilayer substrate or semiconductor chip according to the first embodiment of the present invention together with the lines of electric force. In FIG. 2, the appearance of the electric lines of force 40 is shown superimposed on a cross-sectional view of a plane perpendicular to the strip line pair wiring of the multilayer substrate. FIG. 2A shows the case of the differential mode, and FIG. 2B shows the case of the common mode.

  In FIG. 2, the dielectric material of the base material is composed of a dielectric layer 10 having a small dielectric loss tangent and a dielectric layer 11 having a large dielectric loss tangent. Other configurations are the same as those shown in FIG.

  The differential mode in FIG. 2A shows a case where the logical value of the differential signal is 1, that is, the left wiring 301 is High and the right wiring 302 is Low (both potentials higher than the GND plane 20). Yes. The electric lines of force 40 coming out of the left wiring 301 having a high potential may reach the GND plane 20 of the multilayer substrate and may reach the right wiring 302. Further, the electric lines of force 40 of the right wiring 302 having a low potential may come from the left wiring 301 and may reach the GND plane 20.

  In the common mode of FIG. 2B, the left and right wirings 301 and 302 are both at the same potential as that of the GND plane 20, and the electric lines of force 40 coming from the left and right wirings 301 and 302 are all of the multilayer board. It reaches the GND plane 20.

  In the multilayer substrate shown in FIG. 2, the base material between the two GND planes 20 has a multilayer structure of a portion having a large dielectric loss tangent and a portion having a small dielectric loss tangent, and the dielectric tangent is formed above and below the wiring layer 30. A small substrate is placed.

  By adopting such a structure, in the differential mode, a part of the electric lines of force 40 pass only through the dielectric layer 10 having a small dielectric loss tangent, so the dielectric loss is alleviated. The This effect is more than twice that of the prior art. On the other hand, in the case of the common mode, all the electric lines of force 40 always pass through the dielectric layer 11 having a large dielectric loss, so that the dielectric loss is not reduced much compared to the differential mode.

  As described above, in the stripline pair wiring, the frequency-dependent dielectric loss can be made smaller in the differential mode than in the common mode. Thereby, the high frequency loss with respect to differential amplitude can be made small, On the other hand, the common amplitude which becomes only noise in differential signal transmission can be easily attenuated. Further, in order to improve the transmission characteristics of the differential signal, the substrate cost can be suppressed as compared with the case where the entire substrate is made of a material having a small dielectric loss tangent.

  In the first embodiment, the pair wirings are arranged on the left and right of the same layer. However, the wiring layers may be arranged on the upper and lower sides with two wiring layers. In addition, two types of materials, a material having a relatively large dielectric loss tangent and a material having a relatively small dielectric loss tangent, are used. Alternatively, one or more types of dielectrics having a dielectric loss tangent having an intermediate size may be sandwiched therebetween. Furthermore, a layer having a small dielectric tangent, a layer having a large dielectric tangent, or an intermediate layer may be provided again between the GND plane 20 and the dielectric layer having a large dielectric tangent. These three points are the same in the following embodiments.

As described above, according to the first embodiment, with respect to one or more wiring layers, the multi-layer substrate in which the ground layers are arranged above and below is provided between the wiring layer and the ground layer. The dielectric layer has a first dielectric layer on the wiring layer side and a second dielectric layer on the ground layer side having different dielectric tangents, and the dielectric tangent of the first dielectric layer is the same as that of the second dielectric layer. Less than dielectric loss tangent.
Therefore, it is possible to reduce dielectric loss, suppress common noise generated by mode conversion, and suppress an increase in cost.

Embodiment 2. FIG.
3 is a cross-sectional view showing a rewiring layer of a multilayer substrate or a semiconductor chip according to Embodiment 2 of the present invention together with lines of electric force. In FIG. 3, the external appearance of the electric lines of force 40 is shown superimposed on a cross-sectional view of a plane perpendicular to the microstrip pair wiring of the multilayer substrate. 3A shows the case of the differential mode, and FIG. 3B shows the case of the common mode. Other configurations are the same as those shown in FIG.

  The differential mode of FIG. 3A shows a case where the logical value of the differential signal is 1, that is, the left wiring 301 is High and the right wiring 302 is Low (both potentials higher than the GND plane 20). Yes. The electric lines of force 40 coming out of the left wiring 301 having a high potential reach the GND plane 20 of the multilayer substrate, reach the right wiring 302 through the dielectric of the multilayer substrate, and pass through the sky to the right wiring. There are those that reach 302 and those that extend above in the illustrated range. Also, the electric lines of force 40 of the right wiring 302 having a low potential come from the left wiring 301, reach the GND plane 20, and come from the sky in the illustrated range.

  In the common mode of FIG. 3B, the left and right wirings 301 and 302 are both at the same potential as that of the GND plane 20, and the electric lines of force 40 coming out of the left and right wirings 301 and 302 are connected to the GND of the multilayer substrate. There are those that reach the plane 20 and those that extend upward in the illustrated range.

  In the multilayer substrate shown in FIG. 3, the base material between the two GND planes 20 has a multilayer structure of a portion having a large dielectric loss tangent and a portion having a small dielectric loss tangent, and is a base having a small dielectric loss tangent below the wiring layer 30. The material is arranged.

  With this structure, in the differential mode, a part of the electric force lines 40 passing through the base material passes only through the dielectric layer 10 having a small dielectric loss tangent. Body loss is alleviated. On the other hand, in the common mode, all electric lines of force 40 reaching the GND plane 20 of the substrate always pass through the dielectric layer 11 having a large dielectric loss, so that the dielectric loss is less than that in the differential mode. Not relaxed.

  As described above, in the microstrip pair wiring, the frequency-dependent dielectric loss can be made smaller in the differential mode than in the common mode. Thereby, the high frequency loss with respect to differential amplitude can be made small, On the other hand, the common amplitude which becomes only noise in differential signal transmission can be easily attenuated. Further, in order to improve the transmission characteristics of the differential signal, the substrate cost can be suppressed as compared with the case where the entire substrate is made of a material having a small dielectric loss tangent.

As described above, according to the second embodiment, one or two or more wiring layers are provided between the wiring layer and the ground layer in the multilayer substrate in which the ground layer is arranged on one side. The dielectric layer has a first dielectric layer on the wiring layer side and a second dielectric layer on the ground layer side having different dielectric tangents, and the dielectric tangent of the first dielectric layer is the same as that of the second dielectric layer. Less than dielectric loss tangent.
Therefore, it is possible to reduce dielectric loss, suppress common noise generated by mode conversion, and suppress an increase in cost.

  In a general multilayer substrate, a protective film (eg, a solder resist) having a relatively large dielectric loss tangent may be provided on the substrate surface. In this case, although the effect is slightly weakened, the same effect can be obtained. On the other hand, if the dielectric loss tangent of the protective film is small, the effect reduction is mitigated.

Embodiment 3 FIG.
FIG. 4 is a cross-sectional view showing the configuration of the base material of the multilayer substrate according to Embodiment 3 of the present invention. FIG. 4 shows a part of the laminated structure of the substrate material when the multilayer dielectric is manufactured. FIG. 4A shows the case of a general thick film substrate, and FIG. 4B shows the case of a build-up substrate in which a dielectric layer and a conductor layer can be sequentially stacked.

  Here, as the substrate material, a first resin-containing glass fiber substrate material in which glass and resin are combined, and a second resin-containing glass fiber substrate material in which the combination of glass and resin is different from the first resin-containing glass fiber substrate material. A combination of any two or more of the first substrate material made of resin and the second substrate material made only of resin different from the first substrate material is used.

  In FIG. 4, the multilayer dielectric includes a low dielectric loss tangent material 100 having no copper foil on both sides, a low dielectric loss tangent material 101 having wiring formed on one side, a high dielectric loss tangent material 110 having no copper foil on both sides, and a single side. It is manufactured from a high dielectric loss tangent material 111 having a copper foil.

  In the case of the general thick film substrate of FIG. 4A, the copper foil of the high dielectric loss tangent material 111 with the single-sided copper foil is used as the GND plane 20. In this method, a material having a copper foil only on one side is used from the beginning, or all the copper is removed in an etching process on one side of a material having a copper foil on both sides.

  In addition, the low dielectric loss tangent material 100 having no copper foil on both sides uses a material that does not have a copper foil on both sides from the beginning, or removes all copper from the material having a copper foil on both sides or one side in an etching process. Use.

  In addition, the low dielectric loss tangent material 101 having the wiring formed on one side is used by forming the wiring in the etching process with respect to the material having the copper foil only on one side from the beginning, or the material having the copper foil on both sides. On the other hand, wiring is formed on one side in an etching process, and all copper on the opposite side is removed and used.

  In addition, the dotted line in a figure shows the range which removed copper by etching, and in the general thick film board | substrate shown to Fig.4 (a), when the material which has copper foil on one side is used about all the materials Is shown.

  On the other hand, in the case of the general build-up substrate of FIG. 4B, the high dielectric loss tangent material 110 having no copper foil on both sides is made of a material having no copper foil on both sides, or the copper foil on both sides or one side. For some materials, all copper is removed in the etching process.

  In this build-up substrate, the dielectric layer and the conductor layer are stacked one by one. Here, like the thick film substrate, the copper foil is removed between the high dielectric loss tangent material and the low dielectric loss tangent material. Moreover, although the lowermost single-sided copper foil is a set with a high dielectric loss tangent material (high dielectric loss tangent material 111 with single-sided copper foil), this is a set with a low dielectric loss tangent material. Good.

  As described above, according to the third embodiment, the structure shown in FIG. 2 is configured in the multilayer structure of the substrate by manufacturing one substrate with the configuration including the above-described stacking order. . A similar method can be applied to the structure shown in FIG. Therefore, the structure according to the present invention can be realized with the conventional substrate manufacturing method as it is, and it is possible to realize a substrate that has low loss in the differential mode and attenuates the common mode without increasing the substrate manufacturing cost. it can.

Embodiment 4 FIG.
FIG. 5 is a cross-sectional view showing the structure of the base material of the multilayer substrate according to Embodiment 4 of the present invention. FIG. 5 shows a structure of a multilayer dielectric substrate material made of glass fibers containing a resin and a laminated structure.

  In FIG. 5, the glass fiber 50 is contained in the dielectric layer 10 having a small dielectric loss tangent or the dielectric layer 11 having a large dielectric loss tangent. Other configurations are the same as those shown in FIG. 5A shows a case where the dielectric loss tangent of the resin is smaller than the dielectric loss tangent of the glass fiber, and FIG. 5B shows the case where the dielectric loss tangent of the glass fiber is smaller than the dielectric loss tangent of the resin. Yes.

  In both cases of FIGS. 5A and 5B, all are exemplified by the substrate material containing glass fiber 50 having copper foil on both sides. Further, the portion closer to the wiring layer 30, that is, the resin-only portion in FIG. 5A, and the glass fiber 50 portion containing the resin in FIG. 5B are low dielectric loss tangents.

  With such a structure, even with a conventional material, it is possible to make a thick portion with a large dielectric loss tangent and a small thickness portion with a single material in the substrate material. Thereby, the number of substrate materials and the stacking process can be reduced, and the substrate cost can be reduced.

  FIGS. 5C and 5D show examples in which the thicknesses of the resin on both surfaces of the glass fiber 50 are the same. FIG. 5C shows the dielectric loss tangent of the glass fiber 50. 5D shows the case where the dielectric loss tangent of the glass fiber 50 is smaller than the dielectric loss tangent of the resin.

  In both cases of FIGS. 5C and 5D, all are exemplified by the substrate material containing glass fiber 50 having copper foil on both sides. Further, the portion closer to the wiring layer 30, that is, the resin-only portion in FIG. 5C, and the glass fiber 50 portion containing the resin in FIG. 5D are low dielectric loss tangents.

  Thus, by making the resin thickness the same on both surfaces of the glass fiber 50, the warpage stress in the substrate manufacturing process can be reduced, and the substrate manufacturing cost can be reduced. Further, in the fourth embodiment, since one kind of base material is used, the risk of peeling at the substrate manufacturing process and substrate warpage after manufacturing and at the base material boundary can be reduced, and the reliability is high. A substrate can be obtained.

Embodiment 5 FIG.
FIG. 6 is an explanatory view illustrating substrate wiring in a multilayer substrate according to Embodiment 5 of the present invention. In FIG. 6, the substrate wiring includes a BGA (Ball Grid Array) package pad 60, a connector pin through hole 70 into which a connector pin (not shown) is inserted, a normal phase signal wiring 301 and a reverse phase signal wiring 302. And a pair of pair wirings 81 composed of another normal phase signal wiring 301 and a reverse phase signal wiring 302.

  In the pair wiring 80, a signal is transmitted from another substrate to the BGA package pad 60 through the connector pin and the connector pin through hole 70. On the other hand, in the pair wiring 81, a signal is transmitted from the BGA package pad 60 to another substrate via the connector pin through hole 70 and the connector pin. In any of the pair wirings 80 and 81, the equal length processing is performed only on the reception side and the transmission side is not performed until the pair wirings 80 and 81 are formed from the BGA package pad 60 and the connector pin through hole 70.

  In general, when the lengths of the normal phase signal and the reverse phase signal until the pair wirings 80 and 81 are formed are different, a mode conversion in which a part of the differential amplitude is changed to the common amplitude is generated. When common noise is induced and resonates on the substrate, large radiation noise is generated at the frequency of the common noise.

  For this reason, it is desirable to align the lengths of the wirings (leading lines) of the normal phase signal and the negative phase signal until the pair wirings 80 and 81 are formed. However, for this purpose, it is necessary to bother the individual lead lines and occupy an originally unnecessary wiring area. In addition, when there are a large number of differential signals, it may be difficult to draw out other signals. Furthermore, it takes time to design the substrate, leading to an increase in development cost.

  On the other hand, in the multilayer substrates shown in the first to fourth embodiments, common noise generated by mode conversion on the transmission side is attenuated during propagation, and resonance hardly occurs. This eliminates the need for equal length processing in the transmission line on the transmission side, eliminates the need for an extra wiring area, and further reduces the time required for board design.

  If the receiving-side package substrate or another substrate connected to the receiving-side connector is also the substrate shown in the first to fourth embodiments, equal length processing in the receiving-side lead line is not necessary. Furthermore, design time and development costs can be reduced. Further, this embodiment can obtain the same effect on the rewiring layer in the semiconductor chip.

  DESCRIPTION OF SYMBOLS 1 Dielectric material, 10 Dielectric layer with a small dielectric loss tangent, 11 Dielectric layer with a large dielectric loss tangent, 20 GND plane, 30 Wiring layer, 40 Electric field lines, 50 Glass fiber, 60 BGA package pad, 70 For connector pins Through hole, 80, 81 pair wiring, 100 Low dielectric loss tangent material without copper foil on both sides, 101 Low dielectric loss tangent material with wiring formed on one side, 110 High dielectric loss tangent material without copper foil on both sides, 111 Copper on one side High dielectric loss tangent material with foil, 301 positive phase signal wiring, 302 reverse phase signal wiring.

Claims (15)

A wiring layer including signal wiring for transmitting a differential signal;
Look containing a full or partial ground plane, a ground layer disposed up and down with respect to one or more of the wiring layers,
A dielectric layer provided between the wiring layer and the ground layer,
The signal wiring for transmitting the operation signal constitutes a pair wiring,
The dielectric layer is
A first dielectric layer on the wiring layer side and a second dielectric layer on the ground layer side having different dielectric loss tangents,
The first dielectric layer is provided so as to wrap around the left and right and top and bottom between the pair wirings,
A multilayer substrate, wherein a dielectric loss tangent of the first dielectric layer is smaller than a dielectric loss tangent of the second dielectric layer. It said first dielectric layer and the dielectric layer made of the second dielectric layer, according to claim 1, characterized in that it has a structure obtained by stacking a plurality of different substrate materials to each other of the dielectric loss tangent Multilayer board. The plurality of substrate materials having different dielectric loss tangents are a first resin-containing glass fiber substrate material in which glass and resin are combined, and the first resin-containing glass fiber substrate material is different in a combination of glass and resin. It is a combination of any two or more of a glass fiber substrate material containing material, a first substrate material made of resin only, and a second substrate material made of resin different from the first substrate material. Item 3. The multilayer substrate according to Item 2 . The dielectric layer composed of the first dielectric layer and the second dielectric layer is a resin-containing glass fiber, and is formed by increasing the thickness of only the resin on one or both sides in the thickness direction of the glass fiber. The multilayer substrate according to claim 1, wherein the multilayer substrate has a structure in which one or two or more types of substrate materials are stacked. Before Symbol pair wiring, the both ends of the pair wiring, substantially equal wiring lengths of the previous positive phase and negative phase from pair wiring end of the signal receiving side, a positive phase above the pair wiring terminal of the signal transmitting side and the opposite The multilayer substrate according to any one of claims 1 to 4 , wherein the multilayer substrate has a wiring shape having a difference in wiring length with a phase. Before Symbol pair wiring, the both ends of the pair wiring, substantially equal wiring length is the previous positive phase and negative phase from pair wiring terminal of the signal transmitting side, ahead of the positive phase from the pair wiring end of the signal receiving side and the opposite The multilayer substrate according to any one of claims 1 to 4 , wherein the multilayer substrate has a wiring shape having a difference in wiring length with a phase. Before Symbol pair wiring at each of both ends of the pair wiring, from claim 1, characterized in that the pair wiring end having a wiring shape having a difference in the wiring length between the positive phase and the negative phase to claim 4 The multilayer substrate according to any one of the above. Printed circuit board characterized by using the multilayer substrate according to any one of claims 1 to 7. A semiconductor package substrate using the multilayer substrate according to any one of claims 1 to 7 . A semiconductor package using the semiconductor package substrate according to claim 9 . A wiring layer including signal wiring for transmitting a differential signal;
Look containing a full or partial ground plane, a ground layer disposed up and down with respect to one or more of the wiring layers,
A dielectric layer provided between the wiring layer and the ground layer,
The signal wiring for transmitting the operation signal constitutes a pair wiring,
The dielectric layer is
A first dielectric layer on the wiring layer side and a second dielectric layer on the ground layer side having different dielectric loss tangents,
The first dielectric layer is provided so as to wrap around the left and right and top and bottom between the pair wirings,
A semiconductor chip, wherein a dielectric loss tangent of the first dielectric layer is smaller than a dielectric loss tangent of the second dielectric layer. The dielectric layer made of the first dielectric layer and said second dielectric layer, to claim 11, characterized in that it has a plurality of different dielectric materials have a layered structure of dielectric loss tangent The semiconductor chip described. A semiconductor device using at least one of the semiconductor package substrate according to claim 9 and the semiconductor chip according to claim 11 or 12 . An information processing apparatus using at least one of the printed circuit board according to claim 8 , the semiconductor chip according to claim 11 or claim 12 , and the semiconductor device according to claim 13 . Printed circuit board according to claim 8, the communication device characterized by using at least one of the semiconductor devices according to the semiconductor chip, and claim 13 of claim 11 or claim 12.

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