JP2013257208A - Defect causing stage analyzing device and defect causing stage analyzing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To analyze whether a defect detected through final inspection is caused by a process stage or inspection stage.SOLUTION: A linking part 17 of a defect causing stage analyzing device 16 reads illumination defect information and TFT correction information out of an information management database 9 as to one liquid crystal display panel, and relates both the results (what is called linking). A classification part 18 classifies the illumination defect information by the TFT correction information. An overlap mapping part 19 maps the classified illumination defect information on the same coordinates one over another as to one lot or a plurality of lots of liquid crystal display panels. A map display part 20 displays one or a plurality of overlap maps which are preset or specified by an operator among the plurality of overlap maps which are thus obtained.

Description

  The present invention relates to a defect cause process analysis apparatus and a defect cause process analysis method for supporting estimation of a manufacturing process that causes a defect in a manufacturing process of a liquid crystal display panel or the like.

  “Defect inspection apparatus for flat panel display” disclosed in Japanese Patent Application Laid-Open No. 2009-264865 (Patent Document 1) as a method for inferring a defect cause process by comparing an inspection result for each manufacturing process with a result of a final inspection There is.

  In the defect inspection apparatus for the flat panel display, defect inspection is performed immediately after each step of the TFT (Thin Film Transistor) process, and the inspection result is stored in the defect inspection database of the defect analysis database. Similarly, defect inspection is performed immediately after each step of the color filter process, and the inspection result is stored in the defect inspection database. Next, after assembling, the TFT substrate completed by the TFT process and the color filter substrate completed by the color filter process are bonded together, divided into panel units, injected with liquid crystal, sealed, and then inspected for lighting. The inspection result of this point inspection is stored in the lighting inspection database.

  Then, the lighting inspection results for each panel in the above assembly are aggregated to obtain the lighting inspection results for each substrate, and the defect in the lighting inspection results is verified by comparing with the inspection results in the TFT process and the color filter process. In which process and process are identified.

  However, the defect inspection apparatus for the flat panel display has the following problems.

  That is, it was specified in which step of the TFT process the lighting defect occurred. The cause of the lighting defect was caused by the process in the generation process or the inspection process. There is a problem that it cannot be distinguished whether it is a thing or not.

JP 2009-264865 A

  Accordingly, an object of the present invention is to provide a defect cause process analysis apparatus and a defect cause process analysis method capable of analyzing whether the cause of the defect detected in the final inspection is caused by the process process or the inspection process. There is.

In order to solve the above problems, the defect cause process analysis apparatus of the present invention is:
In the manufacturing process in which the intermediate inspection is performed after the processing is performed on the member, the detected defect is corrected, and then the final inspection is performed, the defect information in the final inspection, its position, and the correction information in the correction And the position thereof, the defect information is mapped onto the coordinates set on the member, and the defect information and the correction information are determined based on the position of the defect information and the position of the correction information. A linking part for linking, and
Based on the result of the association by the association unit, a classification unit that classifies the defect information with the correction information;
Based on the result of the classification by the classification unit, overlay mapping is performed by mapping the defect information related to a preset number of members on the coordinates set on the member for each correction information. And
A map display unit that displays the overlay map generated by the overlay mapping unit is provided.

  Here, the “association between the defect information and the correction information” is “association of the defect information and the correction information”.

  According to the above configuration, the overlay information generated by superimposing and mapping the defect information on the set number of members classified by the correction information on the coordinates set on the member is displayed. can do. Therefore, the operator of the defect cause process analysis apparatus determines that the defect detected in the final inspection is the intermediate result from the pegging classification result obtained from the overlay map for each correction information and the distribution state of the defect information. It is possible to quickly determine visually whether the inspection is caused or the previous processing is caused.

Moreover, in the defect cause process analysis apparatus of one embodiment,
A database for storing defect information and its position in the final inspection and correction information and its position in the correction,
The associating unit obtains the defect information and its position and the correction information and its position from the database.

  According to this embodiment, the associating unit can easily acquire the defect information and its position, and the correction information and its position regarding a large number of the members.

Moreover, in the defect cause process analysis apparatus of one embodiment,
The manufacturing process is as follows:
The member is a glass substrate,
The processing is a processing for manufacturing a TFT substrate by performing film formation, exposure, etching, and alignment film formation on the glass substrate,
The intermediate inspection is an inspection for the TFT substrate,
It is a liquid crystal display panel manufacturing process in which the final inspection is a lighting inspection for a liquid crystal display panel manufactured using the TFT substrate.

  According to this embodiment, after processing a glass substrate to manufacture a TFT substrate, the TFT substrate is inspected, a detected defect is corrected, and the TFT substrate is manufactured. In a liquid crystal display panel manufacturing process for performing a lighting inspection on a liquid crystal display panel, the lighting defect detected by the lighting inspection is caused by the inspection of the TFT substrate or by the processing for manufacturing the TFT substrate before that. It is possible to quickly determine visually whether to do this.

In addition, the defect cause process analysis method of the present invention,
In the manufacturing process in which the intermediate inspection is performed after the processing is performed on the member, the detected defect is corrected, and then the final inspection is performed, the defect information in the final inspection, its position, and The correction information in the correction and its position are acquired, the defect information is mapped onto the coordinates set on the member, and the defect information and the position of the correction information are based on the position of the defect information and the position of the correction information. A linking process for linking with the correction information;
A classification step of classifying the defect information with the correction information based on the result of the association in the association step by the classification unit;
Based on the result of the classification in the classification step, the overlap mapping unit superimposes the defect information on a preset number of members on the coordinates set on the members according to the correction information. A superposition mapping process for mapping together;
The map display unit includes a map display step for displaying the overlay map generated in the overlay mapping step.

  According to the above configuration, the overlay information generated by superimposing and mapping the defect information on the set number of members classified by the correction information on the coordinates set on the member is displayed. can do. Therefore, from the pegging classification result obtained from the overlay map for each correction information and the distribution state of the defect information, the defect detected in the final inspection is caused by the intermediate inspection or the previous one before It is possible to quickly determine visually whether the processing is caused.

  As apparent from the above, according to the present invention, the defect information related to the set number of members classified according to the correction information is generated by being superimposed on the coordinates set on the member. Since the overlay map is displayed, the defect detected in the final inspection is caused by the intermediate inspection from the pegging classification result obtained from the overlay map for each correction information and the distribution state of the defect information. It is possible to quickly determine visually whether or not the previous processing is caused.

  Therefore, feedback to the processing and the intermediate inspection can be performed quickly, and a reduction in the direct rate in the manufacturing process can be prevented.

It is a figure which shows the outline | summary in the defect cause process analysis apparatus of this invention. It is a figure which shows an example of the superimposition map displayed on the map display part in FIG. It is explanatory drawing of mapping of defect information, and the linkage | linking of defect information and correction information. It is explanatory drawing of the classification | category by the correction information of defect information. It is explanatory drawing of the said superimposition map.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 is a diagram showing an outline of the defect cause process analysis apparatus of the present embodiment. In this embodiment, a defect cause process analysis apparatus in manufacturing a liquid crystal display panel as an example of the defect cause process analysis apparatus will be described.

  As shown in FIG. 1, the defect cause process analyzer 16 analyzes the defect cause process based on information obtained in the inspection process and the correction process in the liquid crystal display panel manufacturing process.

  Hereinafter, prior to the description of the defect cause process analyzer 16, a manufacturing process of the liquid crystal display panel will be described.

  The liquid crystal display panel is manufactured through the TFT process 1, the LCD (Liquid Crystal Display) process 2 and the panel process 3. The completed liquid crystal display panel is subjected to a lighting inspection in the lighting inspection process 4, and then has a defect. If there is, the correction is performed by the laser repair process 5, and the liquid crystal display panel having no defect and the corrected liquid crystal display panel are shipped as products.

  In FIG. 1, the TFT process 1 is a process for manufacturing a TFT substrate of a liquid crystal display panel. In this TFT process 1, after a manufacturing process 6 such as film formation, exposure, etching, alignment film formation, etc. on a glass substrate, a TFT layer, a wiring layer, a pixel electrode, etc. are formed on the glass substrate. On the other hand, inspection (TFT inspection) is performed in the TFT inspection step 7, and correction (TFT correction) is performed on the found defect in the TFT correction step 8. Then, the obtained TFT defect information and TFT correction information are stored in the information management database 9.

  In this case, specific examples of the TFT defect information include a defect type, defect coordinates, defect strength, and inspection conditions. Specific examples of the TFT correction information include correction success, no correction (because it is a defect that does not need correction), correction skip (not detected by TFT inspection), correction impossible, defect position unknown, etc. .

  A TFT substrate in which no defect is found in the TFT inspection step 7 through the manufacturing process 6 of the TFT step 1, and a TFT substrate in which a defect is found in the TFT inspection step 7 and corrected in the TFT correction step 8 , Sent to the LCD step 2.

  The LCD process 2 is a process for manufacturing an LCD by performing various processing on the TFT substrate from the TFT process 1. In the LCD process 2, an LCD is formed through processing such as color filter substrate manufacturing 10, bonding of the TFT substrate and the color filter substrate 11, substrate cutting 12 and liquid crystal injection / sealing 13 and the like. The LCD thus formed is sent to the panel process 3.

  The panel process 3 is a process for manufacturing a liquid crystal display panel by performing various processing on the LCD from the LCD process 2. In this panel process 3, a liquid crystal display panel is formed through processing such as backlight manufacturing 14 and module assembly 15. The liquid crystal display panel thus formed is sent to the lighting inspection process 4.

  In the lighting inspection process 4, each pixel in the liquid crystal display panel from the panel process 3 is sequentially lit to inspect whether there is any lighting defect. The liquid crystal display panel having the lighting defect is repaired using a laser in the laser repair process 5. In that case, lighting defect information and repair information obtained in the lighting inspection step 4 are stored in the information management database 9.

  In this case, specific examples of the lighting defect information include a defect type and defect coordinates.

  Here, an identification number is given to the TFT substrate and the liquid crystal display panel so that each of the liquid crystal display panels is manufactured from which TFT substrate. For example, “TFT lot number” and “TFT substrate number” are assigned to the TFT substrate. In addition to the “panel position number”, the “TFT lot number” and “TFT substrate number” of the derived TFT substrate are given to the liquid crystal display panel. Thus, based on the “TFT lot number”, “TFT substrate number” and “panel position number” added to the liquid crystal display panel, it is determined from which position of which TFT substrate the liquid crystal display panel is cut. It has come to understand.

  The TFT defect information and the TFT correction information stored in the information management database 9 are stored in association with “TFT lot number” and “TFT substrate number” which are TFT identification numbers. Further, lighting defect information and repair information are stored in association with “TFT lot number”, “TFT substrate number”, and “panel position number” which are panel identification numbers.

  The identification number may be configured so that the target liquid crystal display panel is a liquid crystal display panel cut from which position on which TFT substrate, and is limited to the above-described configuration. is not.

  Further, the TFT defect information, the TFT correction information, the lighting defect information, and the repair information stored in the information management database 9 are on a coordinate space set in advance on the TFT substrate to indicate the inspection position. Position (coordinates) is given.

  Next, the defect cause process analyzer 16 will be described. The defect cause process analyzer 16 analyzes the process that causes the lighting defect based on the TFT defect information, the TFT correction information, and the lighting defect information stored in the information management database 9. The defect cause process analysis device 16 includes a linking unit 17, a classification unit 18, an overlay mapping unit 19, and a map display unit 20.

  In the above configuration, the associating unit 17 reads the plurality of lighting defect information and the plurality of TFT correction information stored in the information management database 9 for one liquid crystal display panel, Based on the lighting defect coordinates, the information is associated (so-called “linking”). Then, the classification unit 18 classifies the lighting defect information with the TFT correction information based on the association result. Thus, a group of lighting defects successfully corrected in the TFT correction process 8, a group of lighting defects in which the position of the TFT defect detected in the TFT inspection process 7 is unknown, and a lighting in which no defect was detected in the TFT inspection process 7 They are classified into defect groups.

  The overlay mapping unit 19 sets the lighting defect information classified according to the TFT correction information by the associating unit 17 and the classifying unit 18 with respect to one or several lots of the liquid crystal display panels for each TFT substrate. Overlapping and mapping on the same coordinates.

  The map display unit 20 includes one or a plurality of preset overlay maps among the overlay maps one more than the number of types of the TFT correction information obtained by the overlay mapping unit 19 as described above. The map or one or a plurality of overlay maps designated by the operator are displayed as the analysis result of the defect cause process.

  Therefore, as shown in FIG. 2, the operator can estimate the cause process of the lighting defect based on the overlay map displayed by the map display unit 20.

  That is, in the overlay map categorized by the TFT correction information “correction successful” illustrated in FIG. 2A, there are many TFT defects particularly in a specific portion with a broken circle (A) on the TFT substrate 21. There are many lighting defects that occur and are not corrected by TFT correction. In such a case, it can be determined that “it is caused by the device of the manufacturing process of the TFT process 1”.

  In addition, in the overlay map classified by the TFT correction information “defect position unknown” illustrated in FIG. 2B, the TFT defect on the TFT substrate 21 determined as “defect position unknown” by the TFT correction step 8. The coordinates and the coordinates on the TFT substrate 21 of the lighting defect detected in the lighting inspection process 4 are close to each other. In such a case, it can be determined that there is an error in the position detected by the inspection apparatus in the TFT inspection process 7 and that there is a possibility of displacement of the inspection apparatus.

  In addition, in the overlay map classified by the TFT correction information “correction skip (not detected by TFT inspection)” illustrated in FIG. 2C, there are many lighting defects that are not detected in the TFT inspection step 7. In such a case, it can be determined that “the detection rate of the inspection apparatus in the TFT inspection step 7 is low”.

  In addition, in the overlay map classified by the TFT correction information “not corrected (no correction required)”, TFT defects on the TFT substrate detected in the TFT inspection process 7 and not corrected in the TFT correction process 8 are detected. If the coordinates and the coordinates on the TFT substrate of the lighting defect detected in the lighting inspection process 4 are close to each other, “There are many over-detections in the TFT inspection process 7; It can be determined that the TFT has been pressed and the TFT defect has flowed out. That is, it can be determined that “it is caused by the inspection apparatus in the TFT inspection step 7”.

  Further, in the overlay map classified by the TFT correction information “uncorrectable”, the coordinates of the TFT defect determined as “uncorrectable” in the TFT correction step 8 and detected in the lighting inspection step 4 When the coordinates of the lighting defect on the TFT substrate are close to each other, ““ defects on a scale that spans multiple TFTs ”are generated,“ a large number of defects are locally generated by dust, etc. "There is a problem with the device of the manufacturing process of TFT process 1".

  In the above embodiment, a flat liquid crystal display panel is taken as an example of a manufactured product. However, it is not necessarily flat and may be a three-dimensional object. Further, as an inspection in the TFT inspection process 7 and the lighting inspection process 4, an inspection on a two-dimensional plane is taken as an example. However, it does not necessarily have to be a flat surface, and may be a transmission type inspection in which a three-dimensional map is obtained or an appearance inspection in which a surface two-dimensional map is obtained. In short, it is an inspection method for obtaining an inspection result that can be mapped on the coordinates set on the manufactured product, and any product that has a shape that can be inspected by the inspection method may be used. .

As described above, in the above embodiment,
“Processing 1” → “Inspection 1” → “Correction” → (“Processing 2”) → “Inspection 2”
like,
For the product that has undergone “processing 1”, “inspection 1” as the intermediate inspection is performed, and when a defect is found, the defect is “corrected” based on the information on the defect position and the information on the defect state. . Thereafter, in the manufacturing process of performing the “processing 2” on the product in which the defective portion is not found and the corrected product, and performing the “inspection 2” as the final inspection to obtain information on the defect, The information management database 9 stores the correction information and its position in the “correction” process, and the defect information and its position in the “inspection 2” process.

  Here, the “processing 1” corresponds to the manufacturing process 6 of the TFT process 1 in the above embodiment, the “inspection 1” corresponds to the TFT inspection process 7, and the “correction” corresponds to the TFT correction process 8. It corresponds to. The “processing 2” corresponds to the LCD process 2 and the panel process 3 in the above embodiment, and the “inspection 2” corresponds to the lighting inspection process 4. Therefore, the correction information in the “correction” step corresponds to the TFT correction information in the above embodiment, and the defect information in the “inspection 2” step corresponds to lighting defect information.

  However, the “machining process 2” is a machining process that does not create a defect as detected by “inspection 2”. In the present invention, the “processing 2” may be omitted.

  Then, the defect cause process analyzer 16 uses a predetermined number (for example, one lot) of the correction information and defect information in the final inspection stored in the information management database 9 as an example of the database, The following defect cause process is analyzed.

  That is, the defect information and its position, the correction information and the position stored in the information management database 9 for one product are read out by the associating unit 17 of the defect cause process analyzing apparatus 16 and FIG. As shown in (a), the defect information is mapped onto the coordinates set on the product. Further, based on the position of the defect information and the position of the correction information, as shown in FIG. 3 (b), associating the correction result of the defect information with the “correction”, that is, The defect information and the correction information are linked. In FIG. 3B, it is assumed that the correction information is “A” and “B”. The correction information indicates that “C” is a defect that has not been corrected in the “correction” process (that is, not detected in the “inspection 1” process).

  Then, the classification unit 18 classifies the defect information according to the type of the correction information as shown in FIG. 4 based on the association result. FIG. 4A shows the defect information group in the case of the correction information “A”. FIG. 4B shows the defect information group in the case of the correction information “B”. FIG. 4C shows the defect information group in the case of the correction information “C”.

  Further, as shown in FIG. 5, the overlay mapping unit 19 superimposes the defect information for one lot or several lots on the same coordinate for each correction information as shown in FIG. Mapping. FIG. 5A is an overlay map for the correction information “A”. FIG. 5B is an overlay map for the correction information “B”. FIG. 5C is an overlay map for the correction information “C”. Further, in both FIG. 5A and FIG. 5B, the mark ● represents the defect information already overlaid in the process of superimposing the defect information for one lot or several lots. Further, the ◯ mark represents the defect information regarding one product to be overlaid next. However, in FIG. 5C, the correction information “C” is a defect that has not been corrected in the “correction” process (that is, not detected in the “inspection 1” process). Only the defects are mapped.

  As shown in FIG. 5, as a result of the superposition and mapping, the number of types of the correction information (in this example, “A” and “B”) is added to “1”. A map is generated. The number of maps is increased by “1” from the number of types of correction information because defects detected in the “inspection 2” process may not be detected in the “inspection 1” process.

  Then, the map display unit 20 designates one or a plurality of overlay maps for each of the correction information designated in advance among the plurality of overlay maps obtained as described above, or designated by the operator. In addition, one or a plurality of overlay maps for each correction information are displayed as analysis results of the defect cause process.

  Therefore, the operator detects that the defect detected in the final inspection is “inspection 1” from the pegging classification result obtained from one or a plurality of superimposition maps for each correction information and the distribution state of the defect information. It is possible to quickly visually determine whether the process is caused or whether the previous “processing 1” process is caused.

  For example, when there are many defects detected in the “inspection 1” process and the “inspection 2” process at a specific location in the overlay map classified by the correction information “correction success” in the “correction” process, It can be determined that “it is caused by the process device of processing 1”.

  Further, in the overlay map classified by the correction information “defect position unknown” in the “correction” process, the correction coordinates in the “correction” process determined as “defect position unknown” and the “inspection 2” process If the defect coordinates are close to each other, it can be determined that there is an error in the position detected by the inspection apparatus in the “inspection 1” process, and that there is a possibility that the inspection apparatus is misaligned.

  In addition, in the overlay map classified by the correction information “correction skip (not detected by TFT inspection)” in the “correction” process, the defect map in the vicinity of the defect coordinates in the “inspection 2” process If there is no corrected coordinate, it can be determined that “the detection rate of the inspection apparatus in the“ inspection 1 ”process is low”.

  In addition, in the overlay map classified by the correction information “No correction (no correction necessary)” in the “correction” step, the coordinates of the correction information and the defect coordinates in the “inspection 2” step are close to each other. If there is a lot of over-detection in the “Inspection 1” process, it is possible to determine that “the correction in the“ Correction ”process has been pressed and defects in the“ Processing 1 ”process have flowed out”. It can be determined that “it is caused by the inspection apparatus in the first inspection step”.

  Further, in the overlay map classified by the correction information “cannot be corrected” in the “correction” step, the correction coordinates determined as “cannot be corrected” and the defect coordinates in the “inspection 2” step are close to each other. If it is, it can be determined that “a serious problem has occurred in the process device of the processing 1”.

  Therefore, according to the above embodiment, there is provided a defect cause process analysis apparatus and a defect cause process analysis method capable of analyzing whether the cause of the defect detected in the final inspection is caused by the process process or the inspection process. Can be provided.

  As a result, feedback to the process step and the inspection step can be performed quickly, and a reduction in the direct rate in the manufacturing process can be prevented.

DESCRIPTION OF SYMBOLS 1 ... TFT process 2 ... LCD process 3 ... Panel process 4 ... Lighting inspection process 5 ... Laser repair process 6 ... Manufacturing process 7 ... TFT inspection process 8 ... TFT correction process 9 ... Information management database 10 ... Color filter substrate manufacture 11 ... Bonding DESCRIPTION OF SYMBOLS 12 ... Board | substrate cutting | disconnection 13 ... Liquid crystal injection | pouring / sealing 14 ... Backlight manufacture 15 ... Module assembly 16 ... Defect cause process analysis device 17 ... Linking part 18 ... Classification part 19 ... Overlay mapping part 20 ... Map display part 21 ... TFT substrate

Claims (4)

In the manufacturing process in which the intermediate inspection is performed after the processing is performed on the member, the detected defect is corrected, and then the final inspection is performed, the defect information in the final inspection, its position, and the correction information in the correction And the position thereof, the defect information is mapped onto the coordinates set on the member, and the defect information and the correction information are determined based on the position of the defect information and the position of the correction information. A linking part for linking, and
Based on the result of the association by the association unit, a classification unit that classifies the defect information with the correction information;
Based on the result of the classification by the classification unit, overlay mapping is performed by mapping the defect information related to a preset number of members on the coordinates set on the member for each correction information. And
A defect cause process analysis apparatus comprising: a map display unit that displays an overlay map generated by the overlay mapping unit. In the defect cause process analysis apparatus according to claim 1,
A database for storing defect information and its position in the final inspection and correction information and its position in the correction,
The defect causal process analyzer according to claim 1, wherein the associating unit acquires the defect information and its position, and the correction information and its position from the database. In the defect cause process analysis apparatus according to claim 1 or 2,
The manufacturing process is as follows:
The member is a glass substrate,
The processing is a processing for manufacturing a thin film transistor substrate by performing film formation, exposure, etching, alignment film formation on the glass substrate,
The intermediate inspection is an inspection for the thin film transistor substrate,
A defect cause process analysis apparatus, characterized in that the final inspection is a liquid crystal display panel manufacturing process in which a lighting inspection is performed on a liquid crystal display panel manufactured using the thin film transistor substrate. In the manufacturing process in which the intermediate inspection is performed after the processing is performed on the member, the detected defect is corrected, and then the final inspection is performed, the defect information in the final inspection, its position, and The correction information in the correction and its position are acquired, the defect information is mapped onto the coordinates set on the member, and the defect information and the position of the correction information are based on the position of the defect information and the position of the correction information. A linking process for linking with the correction information;
A classification step of classifying the defect information with the correction information based on the result of the association in the association step by the classification unit;
Based on the result of the classification in the classification step, the overlap mapping unit superimposes the defect information on a preset number of members on the coordinates set on the members according to the correction information. A superposition mapping process for mapping together;
A defect cause process analysis method comprising: a map display process for displaying the overlay map generated in the overlay mapping process by the map display unit.

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