JP2013254159A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device that can prevent a reduction in yields while maintaining reliability of liquid crystal sealing by sealant and can suppress occurrence of display unevenness in the vicinity of gate lead-out wiring.SOLUTION: Each pixel of a liquid-crystal display panel has a pixel electrode to which an image signal is supplied via a TFT and a switching element and a common electrode to which a predetermined common potential is supplied. Further, the liquid-crystal display panel has gate wiring for supplying a control signal to the TFT of each pixel and source wiring for supplying the image signal to the TFT. At the time of start-up, supply of the control signal to scan wiring is started after a predetermined period of time has elapsed since supply of the common potential to the common electrode was started.

Description

  The present invention relates to a liquid crystal display device, and more particularly to a technique for improving the display quality of a horizontal electric field type liquid crystal display device.

  In recent years, in place of conventional display devices using cathode ray tubes, display devices using thin and flat display panels using the principles of liquid crystal, electroluminescence, charged fine particles and the like have been widely used. A liquid crystal display device, which is a representative of these new display devices, has not only a feature of being thin and light, but also a feature of being capable of low voltage driving with low power consumption.

  A display panel of a liquid crystal display device is configured by sealing liquid crystal between two substrates. One of the two substrates has a display area in which a plurality of pixels are arranged in a matrix, and is called an “array substrate”. The other substrate is formed with a color filter, a black matrix (light-shielding film) and the like so as to face the display area of the array substrate, and is called “counter substrate”. The array substrate and the counter substrate are bonded together using a sealant that seals the liquid crystal.

  In particular, a thin film transistor (TFT) type liquid crystal display device has a configuration in which each pixel has a TFT for supplying an image signal to the pixel. Therefore, the TFT type liquid crystal display device can hold a voltage for driving each pixel independently and can realize a high-quality image display with little crosstalk. Further, the array substrate is provided with a gate wiring (scanning wiring) connected to the gate electrode of the TFT of each pixel and a source wiring (signal) connected to the source electrode of the TFT of each pixel so as to intersect the gate wiring. Wiring). The gate wiring is used for on / off control of each TFT. The source wiring supplies an image signal applied to the electrode (pixel electrode) of each pixel to the TFT. Usually, the pixel is disposed in each of the regions surrounded by the gate wiring and the source wiring.

  In a general liquid crystal display device, an image signal applied to each pixel electrode is held between the pixel electrode and a counter electrode (common electrode), but a method of driving a liquid crystal using a horizontal electric field ( In an in-plane switching (IPS) type liquid crystal display device known as a lateral electric field method), both a pixel electrode and a counter electrode are disposed on the array substrate side. In the IPS liquid crystal display device, the pixel electrode and the counter electrode are arranged in a slit plate shape or a comb-like shape in the same layer or different layers with gaps alternately in plan view. A horizontal electric field is generated between the pixel electrode and the counter electrode with respect to the substrate surface, and display is controlled by driving the liquid crystal using the horizontal electric field.

  The IPS method is superior in viewing angle characteristics compared to the conventional TN (Twisted Nematic) method, but the liquid crystal positioned immediately above the pixel electrode and the counter electrode hardly contributes to the display. Therefore, there is a drawback that the light transmittance is small.

  As a lateral electric field system that has improved this drawback, for example, there is a fringe field switching (FFS) system disclosed in Patent Documents 1 and 2 (in Patent Documents 1 and 2, the FFS system is also in a broad sense). It is called “IPS system”).

  In the FFS mode liquid crystal display device, both the pixel electrode and the counter electrode are formed on the array substrate side. However, unlike the IPS method, the pixel electrode and the counter electrode are arranged so as to overlap each other with an insulating film interposed therebetween. In the FFS system, both a configuration in which the lower electrode is a pixel electrode and a configuration in which the upper electrode is a pixel electrode are possible.

  In the FFS mode liquid crystal display device, the lower electrode (lower electrode) of the pixel electrode and the counter electrode is usually formed in a plate shape (planar shape), and the upper electrode (upper electrode). Is formed in a plate shape (slit plate shape) having a slit-like opening or a comb-teeth shape. Since the liquid crystal is driven by a fringe electric field generated between the upper electrode and the lower electrode, the liquid crystal directly above the upper electrode can be driven to contribute to display. Therefore, the FFS method has an advantage that the light transmittance is higher than that of the IPS method.

  In a horizontal electric field type liquid crystal display panel such as an IPS method or an FFS method, both the pixel electrode and the counter electrode are disposed on the array substrate side, so that the surface of the counter substrate facing the liquid crystal is a black matrix made of an organic resin. Insulating films such as overcoats and color filters. That is, unlike a counter substrate used in a vertical electric field type display panel such as a TN mode, a transparent conductive film as a counter electrode (common electrode) is not provided on a surface of the counter substrate facing the liquid crystal. For this reason, in the horizontal electric field method, the potential variation of the counter substrate occurs due to the influence of the electric field generated from the gate lead-out wiring (wiring for leading the gate electrode out of the display area) on the array substrate, and the potential of the counter substrate near There is a problem that display unevenness occurs in the display area.

  In Patent Documents 1 and 2, as a countermeasure, a shield electrode (conductive film) for electric field shielding is disposed on the gate lead-out wiring of the array substrate via an insulating film, thereby suppressing display unevenness. .

  In Patent Documents 1 and 2, ITO (Indium Tin Oxide) is used for the conductive film to be the shield electrode. Since the adhesive strength between ITO and the sealant is not reliable, in Patent Documents 1 and 2, the shield electrode (ITO) is always placed below the uppermost insulating film in the sealing material formation area, The reliability of the adhesive force between the counter substrate and the array substrate by the material is ensured. Thereby, the occurrence of display unevenness can be suppressed while maintaining the reliability of sealing the liquid crystal with the sealing material.

JP 2009-265484 A JP 2010-49185 A

  In the liquid crystal display devices disclosed in Patent Documents 1 and 2, since the shield electrode is disposed below the uppermost insulating film, the thickness of the insulating film between the shield electrode and the gate lead-out wiring is the uppermost layer of the shield electrode. It becomes smaller than the case where it arrange | positions on this insulating film. Therefore, compared with the case where the shield electrode is disposed on the uppermost insulating film, there are concerns that the load capacity of the gate wiring increases and the yield decreases due to a short circuit between the shield electrode and the gate wiring. .

  The present invention has been made to solve the above-described problems, and can prevent a decrease in yield while maintaining the reliability of liquid crystal sealing with a sealant, and suppress the occurrence of display unevenness in the vicinity of the gate lead-out wiring. An object of the present invention is to provide a liquid crystal display device that can be used.

  The liquid crystal display device according to the present invention supplies a switching element, a pixel having a pixel electrode to which an image signal is supplied through the switching element, a common electrode to which a predetermined common potential is supplied, and a control signal to the switching element. A liquid crystal display panel having a scanning wiring and a signal wiring for supplying the image signal to the switching element, and at the time of start-up, the supply of the control signal to the scanning wiring is performed by supplying the common potential to the common electrode; It is started after a predetermined time from the start of supply.

  According to the liquid crystal display device of the present invention, at the time of start-up, the common potential is supplied to the common electrode, and the control signal is supplied to the scanning wiring after the potential of the counter substrate has converged to the common potential. Occurrence of potential fluctuation in the counter substrate due to the electric field from the lead-out wiring is suppressed. Therefore, it is possible to prevent display unevenness in the vicinity of the lead-out wiring.

  Thereby, for example, even if the shield electrode is disposed only in the region inside the seal material, display unevenness can be sufficiently suppressed. In that case, even if the shield electrode is disposed on the uppermost layer of the array substrate, the adhesive strength of the sealing material is not affected, so that the reliability of the adhesive strength of the sealing material can be ensured. Further, since the thickness of the insulating film between the shield electrode and the lead line is increased, it is possible to prevent a short circuit between the shield electrode and the lead line, and to prevent a decrease in yield. Furthermore, the effect that the load capacity of the scanning wiring can be reduced is also obtained.

It is a block diagram which shows the structure of the liquid crystal display device which concerns on embodiment of this invention. It is a top view which shows typically the structure of the liquid crystal display device which concerns on embodiment of this invention. It is an enlarged plan view which shows the structure of the pixel of the liquid crystal display device which concerns on embodiment of this invention. It is an expanded sectional view which shows the structure of the pixel of the liquid crystal display device which concerns on embodiment of this invention. FIG. 5 is an enlarged plan view showing a configuration of a region for forming a gate lead-out wiring of the liquid crystal display device according to the embodiment of the present invention. It is an expanded sectional view which shows the structure of the formation area | region of the gate extraction wiring of the liquid crystal display device which concerns on embodiment of this invention. It is a flowchart which shows the operation | movement at the time of starting of the liquid crystal display device which concerns on embodiment of this invention. It is a flowchart which shows the operation | movement at the time of completion | finish of operation | movement of the liquid crystal display device which concerns on embodiment of this invention.

  FIG. 1 is a block diagram showing a configuration of a liquid crystal display device 100 according to an embodiment of the present invention. In the present embodiment, it is assumed that the liquid crystal display device 100 is an FFS system, but the present invention is a lateral electric field system (for example, an IPS system) in which both a pixel electrode and a common electrode (counter electrode) are provided on the same substrate. ) Can be widely applied to liquid crystal display devices.

  As shown in FIG. 1, the liquid crystal display device 100 includes a control unit 101, a display drive unit 102, a backlight drive unit 103, an on / off switch unit 104, a power supply unit 105, a liquid crystal display panel 60, and a backlight 80. It is out.

  The liquid crystal display panel 60 includes a gate line 2, a source line 5, and a common line 9. The gate wiring 2 (scanning wiring) is a wiring for supplying a control signal to the gate electrode of the TFT (switching element) of each pixel to control on / off of each TFT. The source wiring 5 (signal wiring) is a wiring for supplying an image signal applied to the electrode (pixel electrode) of each pixel to the TFT. The common wiring 9 is a wiring for supplying a predetermined potential (common potential) to the common electrode of each pixel. The backlight 80 is a light source that irradiates the liquid crystal display panel 60 with light.

  The on / off switch unit 104 is for a user or the like to switch the liquid crystal display device 100 on and off, for example. The display driving unit 102 has a function of outputting various signals to the gate wiring 2, the source wiring 5, and the common wiring 9 to display an image on the liquid crystal display panel 60. That is, the display driving unit 102 includes a gate wiring driving circuit that scans the gate wiring 2, a source wiring driving circuit that supplies an image signal to the source wiring 5, and a circuit that supplies a common potential to the common wiring 9. Yes. The backlight drive unit 103 supplies power to the backlight 80 to light it. A power source for driving the liquid crystal display panel 60 by the display driving unit 102 and a power source for driving the backlight 80 by the backlight driving unit 103 are supplied from the power source unit 105.

  The control unit 101 is a processing circuit that exchanges signals and information with hardware resources such as the display drive unit 102, the on / off switch unit 104, and the power supply unit 105, and comprehensively controls their operations. The control unit 101 is realized by a central processing unit (CPU) that operates based on a control program stored therein. In addition, the control unit 101 includes a timer unit 106. The timekeeping unit 106 measures the passage of time, and is realized, for example, by a counter that counts the elapsed time from the time when the time measurement was started.

  FIG. 2 is a plan view schematically showing the configuration of the liquid crystal display device of the present embodiment. The liquid crystal display panel 60 provided in the liquid crystal display device 100 is bonded to the array substrate 10 and the counter substrate 20 using a sealing material 40 provided on the outer periphery thereof, and the liquid crystal is sealed between the array substrate 10 and the counter substrate 20. It has a stopped structure. Although not shown, the liquid crystal display panel 60 has a polarizing plate and a phase plate attached to both sides thereof, and is housed in a casing together with the backlight 80 and an external circuit, so that the liquid crystal display device 100 is configured.

  The liquid crystal display panel 60 is divided into a display area 50 in which a plurality of pixels 30 are arranged in a matrix and a frame area 55 outside the display area 50. In the display area 50, a plurality of gate wirings 2 extending in the horizontal direction (left-right direction) and a plurality of source wirings 5 intersecting therewith and extending in the vertical direction (up-down direction) are arranged. A pixel 30 is formed in each region surrounded by 5. Although not shown, each pixel 30 is formed with a TFT connected to the gate line 2 and the source line 5, a pixel electrode for holding an image signal supplied through the TFT, and a common electrode. Further, a common wiring 9 for supplying a common potential to the common electrode of each pixel 30 is disposed on the outer periphery of the display region 50.

  In the horizontal electric field type liquid crystal display panel 60, these elements are all formed on the array substrate 10 side. On the other hand, a color filter, a black matrix, or the like (not shown) is formed on the counter substrate 20 that is disposed to face the array substrate 10 with the liquid crystal interposed therebetween.

  The array substrate 10 uses an insulating substrate such as glass or plastic as a base material, and a gate wiring 2, a source wiring 5, a pixel 30 and the like are formed in the display region 50 thereof. In the frame region 55 of the array substrate 10, a gate wiring driving circuit 70 connected to the gate wiring 2 and a source wiring driving circuit 72 connected to the source wiring 5 are mounted by COG (Chip On Glass) mounting technology. Various signals (clock signal, image signal (image data), driving voltage, etc.) generated by an external circuit (not shown) are supplied to the gate wiring driving circuit 70 and the source wiring driving circuit 72 at the end of the array substrate 10. A plurality of terminals are provided, and the external circuit is connected to these terminals via flexible boards 74 and 76.

  As shown in FIG. 2, one end of each gate line 2 is drawn to the outside of the display area 50 and connected to the gate line drive circuit 70. A portion of the gate line 2 that is led out of the display area 50 is referred to as a “gate lead-out line 2a”. Similarly, one end of each source line 5 is drawn to the outside of the display area 50 and connected to the source line drive circuit 72. A portion of the source line 5 that is led out of the display area 50 is referred to as a “source lead line 5a”.

  On the gate lead-out wiring 2a, a shield electrode 90 (conductive film) that shields an electric field generated from the gate lead-out wiring 2a and suppresses display unevenness is disposed. In the present embodiment, the shield electrode 90 is disposed only in a region inside the sealing material 40.

  Although there are a large number of gate wirings 2, source wirings 5, gate lead-out wirings 2a, source lead-out wirings 5a, etc., only a part of them is shown in FIG. 2 for convenience of illustration. In a small liquid crystal display panel having a relatively small number of wirings, a driving circuit in which the gate wiring driving circuit 70 and the source wiring driving circuit 72 are integrated may be used. In that case, the flexible substrates 74 and 76 may be combined into one sheet.

  FIG. 3 is an enlarged plan view showing the configuration of the pixels 30 formed on the array substrate 10. 4 is an enlarged cross-sectional view of the pixel 30 and corresponds to a cross section taken along the line AA in FIG. Since the liquid crystal display device 100 of the present embodiment is an FFS method, both the pixel electrode and the common electrode of the pixel 30 are formed on the array substrate 10. Here, an example is shown in which the pixel electrode is disposed in the lower layer and the counter electrode is disposed in the upper layer. Hereinafter, the configuration of the pixel 30 will be described with reference to FIGS. 3 and 4.

  As shown in FIG. 3, the pixel 30 is formed in a region surrounded by the gate wiring 2 and the source wiring 5. As shown in FIG. 4, the gate wiring 2 extends on the insulating substrate 1. The insulating substrate 1 is made of glass, plastic or the like, and the gate wiring 2 is made of a metal such as Al, Cr, Mo, Ti, Ta, W, Ni, Cu, Au, Ag, or an alloy or a laminated film thereof. .

  A gate insulating film 3 made of an inorganic film such as an oxide film or a nitride film is formed on the gate wiring 2. The source wiring 5 is disposed on the gate insulating film 3 so as to intersect the gate wiring 2. The source wiring 5 is made of a metal such as Al, Cr, Mo, Ti, Ta, W, Ni, Cu, Au, or Ag, or an alloy or laminated film thereof.

  A part of the gate wiring 2 is used as a gate electrode of a TFT provided in the pixel 30. In the TFT formation region, a stacked structure of a semiconductor film 4 and an ohmic contact film 41 into which impurities are implanted is formed in an island shape above the gate wiring 2 via a gate insulating film 3. A part of the source wiring 5 branches and extends onto the semiconductor film 4 and the ohmic contact film 41 to constitute a source electrode 51 of the TFT. The drain electrode 52 of the TFT is also formed using the same layer as the source wiring 5.

  As shown in FIG. 4, in the region between the source electrode 51 and the drain electrode 52, the ohmic contact film 41 is removed and the semiconductor film 4 is exposed. This portion of the semiconductor film 4 becomes a channel portion of the TFT. Further, the portion of the gate wiring 2 below the channel portion functions as the gate electrode of the TFT.

  The semiconductor film 4 and the ohmic contact film 41 may extend not only in the TFT formation region, but also below the source wiring 5 along the source wiring 5. In this case, even if the semiconductor film 4 and the ohmic contact film 41 under the source wiring 5 are redundant wirings and the source wiring 5 is disconnected, the electrical signal can be prevented from being interrupted. Further, since the disconnection of the source wiring 5 is likely to occur at a step portion intersecting with the gate wiring 2, the semiconductor film 4 and the ohmic contact film 41 as redundant wiring are formed in an island shape at the intersection between the gate insulating film 3 and the source wiring 5. It may be formed.

  A plate-shaped pixel electrode 6 (lower electrode) connected to the drain electrode 52 is formed on the gate insulating film 3. In the transmissive liquid crystal display panel 60, the pixel electrode 6 is formed of a transparent oxide conductive film such as ITO. In the case of the reflection type, the pixel electrode 6 is formed of a conductive film having a high reflectance such as a metal such as Al, Ag, or Pt, an alloy thereof, or a laminated film. In FIG. 4, the connection between the pixel electrode 6 and the drain electrode 52 is achieved by extending a part of the pixel electrode 6 on the drain electrode 52, but conversely, the pixel electrode 6 is connected to the drain electrode 52. A part of the drain electrode 52 may be extended on the pixel electrode 6 as a lower layer.

  An interlayer insulating film 7 is formed on the source wiring 5, the source electrode 51, the drain electrode 52, and the pixel electrode 6. The interlayer insulating film 7 is made of an inorganic film such as an oxide film or a nitride film, an organic resin insulating film, or a laminated film thereof.

  A common electrode 8 (counter electrode) made of a transparent oxide conductive film such as ITO is formed on the interlayer insulating film 7. In the present embodiment, a plate-shaped (slit plate-shaped) common electrode 8 having a slit 82 is used, but the common electrode 8 has a comb-tooth shape (a shape in which one end of the slit 82 is opened), a stripe shape, or the like. But you can. A common potential is applied to the common electrode 8. In each FFS pixel 30, a fringe electric field corresponding to an image signal supplied to the pixel electrode 6 is generated between the pixel electrode 6 and the common electrode 8 through the interlayer insulating film 7 in the slit 82 portion. Thereby, the liquid crystal 15 is driven.

  As shown in FIG. 3, in the present embodiment, connection portions 84 and 86 that connect to the common electrode 8 of the adjacent pixel 30 are provided on the common electrode 8. In other words, the common electrode 8 is connected to the common electrode 8 of the pixel 30 adjacent in the extending direction (vertical direction) of the source wiring 5 through the connection portion 84, and the gate wiring 2 is extended through the connection portion 86. It is connected to the common electrode 8 of the pixel 30 adjacent in the current direction (horizontal direction).

  From the viewpoint of reducing the resistance of the common electrode 8 and shielding the electric field from the gate wiring 2 and the source wiring 5, it is desirable that the connection portions 84 and 86 of the common electrode 8 cover substantially the entire gate wiring 2 and the source wiring 5. . However, from the viewpoint of preventing the TFT characteristics from being affected by the common potential of the common electrode 8, it is desirable that the upper portion of the TFT is not covered with the common electrode 8 (connection portions 84 and 86). Therefore, in this embodiment, an opening 81 is provided above the TFT. As a result, the plurality of pixels 30 are covered with the mesh-shaped common electrode 8.

  Since the opening 81 on the TFT also causes electric field leakage from the gate wiring 2, it is preferable to minimize the size of the opening 81 as long as the influence of the common potential on the TFT is negligible. The TFT may be covered with the common electrode 8 without providing the opening 81. One of the connecting portion 84 extending in the horizontal direction and the connecting portion 86 extending in the vertical direction may be omitted. In this case, the plurality of pixels 30 are covered with the stripe-shaped common electrode 8.

  Further, since the connection portions 84 and 86 prevent the electric field generated from the gate wiring 2 and the source wiring 5 from being applied to the liquid crystal, in the normally black mode liquid crystal display panel 60, the connection portions 84 and 86 ( The liquid crystal on the gate wiring 2 and the source wiring 5) acts as a light shielding film. Therefore, in that case, there is also an advantage that it is not necessary to form a black matrix along the gate line 2 and the source line 5 in the display region 50 of the counter substrate 20.

  Although illustration is omitted, each of the array substrate 10 and the counter substrate 20 is formed by coating and forming an alignment film (not shown) made of an organic resin such as polyimide on the surface and subjected to an alignment process by a method such as rubbing or photo-alignment. The Thereafter, the array substrate 10 and the counter substrate 20 are overlapped so that the alignment films face each other, and a display region 50 is secured while a gap of about several μm is secured by a spacer material (not shown) made of an organic resin or the like. Are bonded together using a sealing material 40 formed so as to surround. Liquid crystal is sealed in a gap inside the sealing material 40 to form a liquid crystal display panel 60.

  A polarizing plate and a phase plate are attached to both surfaces of the liquid crystal display panel 60, and a scanning line driving circuit 70, a signal line driving circuit 72, and flexible substrates 74 and 76 are mounted in the frame region 55. The liquid crystal display device 100 is completed by housing the liquid crystal display panel 60 together with an external circuit for supplying various electric signals to the liquid crystal display panel 60, the backlight 80, and the like.

  FIG. 5 is an enlarged plan view of a formation region of the gate lead-out wiring 2a in the liquid crystal display panel 60, and corresponds to the region S shown in FIG. FIG. 6 is an enlarged cross-sectional view of a region (region S) where the gate lead-out wiring 2a is formed, and corresponds to a cross section taken along the line BB shown in FIG. 5, illustration of the black matrix 22 and the overcoat 23 of the counter substrate 20 shown in FIG. 6 is omitted. Further, the pixel 30 shown in FIG. 3 exists in the right end portion of FIG. 5, but the illustration is omitted. Hereinafter, the structure of the formation region of the gate lead-out wiring 2a will be described with reference to FIGS.

  The gate lead-out wiring 2 a is formed on the insulating substrate 1 of the array substrate 10 using the same layer as the gate wiring 2. A gate insulating film 3 is formed on the gate lead-out wiring 2a. A common line 9 to which a common potential is supplied is formed on the gate insulating film 3 on the outer periphery of the display region 50 using the same layer as the source line 5. An interlayer insulating film 7 is formed on the common wiring 9.

  A shield electrode 90 is formed above the gate lead-out wiring 2 a via the gate insulating film 3 and the interlayer insulating film 7. The shield electrode 90 is formed using the same layer as the common electrode 8 of the pixel 30 and is made of a transparent oxide conductive film such as ITO. The shield electrode 90 is connected to the common wiring 9 through the contact hole 11 provided in the interlayer insulating film 7. That is, a common potential is applied to the shield electrode 90.

  The shield electrode 90 functions to shield the electric field from the gate lead-out wiring 2a. The shield electrode 90 is formed so as to cover the entire formation region of the gate lead-out wiring 2a inside the seal material 40 (that is, the region from the end of the display region 50 to the seal material 40). This is desirable in terms of shielding the electric field from 2a.

  Further, the common electrode 8 of the pixel 30 is connected to the shield electrode 90 through the connection portion 86. That is, the common electrode 8 is also connected to the common wiring 9 through the contact hole 11 shown in FIGS. 5 and 6, whereby a common potential is applied to the common electrode 8. Therefore, the connection portion 86 connected to the shield electrode 90 also functions to shield the electric field from the gate lead-out wiring 2a, as with the shield electrode 90.

  The size, shape, number and position of the contact hole 11 may be arbitrary. For example, in FIG. 5, the contact holes 11 are provided at a pitch twice that of the gate lead-out wiring 2a. That is, the contact hole 11 is formed as a region on the gate lead-out wiring 2a and a region between the gate lead-out wiring 2a.

  The sealing material 40 serves to bond the array substrate 10 and the counter substrate 20 and seal the liquid crystal 15 therebetween. The sealing material 40 needs to be a material that does not dissolve impurities into the liquid crystal 15, and is generally a thermosetting type or a photocurable type made of an epoxy resin or the like.

  As shown in FIG. 6, in this embodiment, the shield electrode 90 is disposed only inside the position of the sealing material 40, and the sealing material 40 is bonded to the lower interlayer insulating film 7. The interlayer insulating film 7 is made of an inorganic film such as an oxide film or a nitride film, or an insulating film of an organic resin, or a laminated film thereof. Generally, these are made of a transparent oxide conductive film such as ITO (Indium Tin Oxide). It has better adhesion to the sealing material 40 than the shield electrode 90. Therefore, with the configuration of FIG. 6, high adhesiveness is obtained between the array substrate 10 and the counter substrate 20, and as a result, the liquid crystal 15 can be sealed with high reliability.

  A gate wiring drive circuit 70 is mounted on the array substrate 10 in the frame region 55 outside the sealing material 40. The gate wiring drive circuit 70 is COG-connected to the connection terminal 16 provided on the array substrate 10. The connection terminal 16 is connected to the gate lead-out wiring 2 a through a contact hole provided in the gate insulating film 3 and the interlayer insulating film 7. Similar to the shield electrode 90, the connection terminal 16 is formed using the same layer as the common electrode 8.

  The counter substrate 20 has a structure in which a black matrix 22 made of a black organic resin, an overcoat 23 made of a transparent organic resin, a color filter, an alignment film (not shown), and the like are formed on an insulating substrate 21 such as glass or plastic. have. Although illustration is omitted, in the display area 50 of the counter substrate 20, usually one of the three primary color filters of red, blue, and green is disposed above each pixel 30. In order to improve color reproducibility, color filters of four primary colors or more may be used.

  In general, the common electrode made of a transparent oxide conductive film such as ITO is not formed on the liquid crystal 15 side of the counter substrate 20 used in the horizontal electric field type liquid crystal display device 100, and only the dielectric insulating film is formed. Yes. For this reason, when the electric field from the gate lead-out wiring 2a reaches the counter substrate 20 without being shielded, the potential variation occurs in the insulating substrate 21, the black matrix 22, the overcoat 23, the color filter and the like of the counter substrate 20, and the gate lead-out. This causes display unevenness in an area near the wiring 2a (around the display area 50).

  In the present embodiment, the shield electrode 90 that shields the electric field from the gate lead-out wiring 2a is provided only in the region inside the seal material 40, and is provided in the region where the seal material 40 is formed and the region outside the seal material 40. Not done. This configuration can increase the adhesion between the array substrate 10 and the counter substrate 20 via the sealing material 40, but the electric field from the gate lead-out wiring 2a that wraps around the region where the sealing material 40 is formed and the region outside thereof is There is a possibility that potential fluctuations may occur in the counter substrate 20 and display unevenness may occur.

  The present inventor has found that this display unevenness occurs in the vicinity of the gate lead-out wiring 2a (the outer periphery of the display area 50) immediately after the liquid crystal display device 100 is started, and then gradually disappears toward the outside of the display area 50. It has been found that it has the characteristics. Furthermore, the present inventor has also confirmed that the display unevenness has a feature that the degree thereof varies depending on the potential of the gate wiring 2.

  From these characteristics, the generation mechanism of display unevenness is considered as follows. First, immediately after activation of the liquid crystal display device 100, when a gate potential is applied to the gate lead-out wiring 2a, the black matrix 22, the color filter, etc. are charged in the region 20a of the counter substrate 20 facing the gate lead-out wiring 2a. Is done. The charged electric charges propagate through the black matrix 22, the color filter, etc., and reach the counter substrate 20 in the display area 50. Then, a vertical electric field is generated between the array substrate 10 and the counter substrate 20 in the display area 50, and display unevenness occurs.

  The counter substrate 20 in the display region 50 is subjected to potential fluctuation due to charge propagation, but eventually the potential fluctuation converges and reaches an equilibrium state. When the equilibrium state is reached, no vertical electric field is generated between the array substrate 10 and the counter substrate 20 in the display area 50, and the display unevenness in the display area 50 disappears. That is, the region where the vertical electric field is generated between the array substrate 10 and the counter substrate 20 due to the influence of the gate potential is reduced to the region where the shield electrode 90 is disposed, and at least in the display region 50, the potential of the counter substrate 20 is reduced. Is considered to have converged to substantially the same potential as the array substrate 10. Here, the potential of the array substrate 10 in the display region 50 is in a state where the common potential is dominant on the time average. Therefore, it is considered effective to converge the counter substrate 20 to a common potential in order to prevent display unevenness.

  In view of the occurrence mechanism of the display unevenness, the inventor has devised a driving method at the time of starting the liquid crystal display device 100 that can suppress the display unevenness. FIG. 7 is a flowchart thereof.

  When the user operates the on / off switch unit 104 to instruct the liquid crystal display device 100 to start operation (S11), the control unit 101 causes the power supply unit 105 to start supplying power to the display drive unit 102. (S12). Then, the control unit 101 starts timing by the timing unit 106 (S13) and also controls the display drive unit 102 to start driving the common wiring 9 of the liquid crystal display panel 60. That is, a common potential is supplied to the common wiring 9 (S14).

  Thereafter, when the elapsed time is detected by the timer 106 (YES in S15), the controller 101 controls the display driver 102 to start driving the source line 5 (S16). That is, the source line drive circuit 72 starts outputting the drive signal (image signal) of the source line 5. Subsequently, driving of the gate wiring 2 is started (S17). That is, the gate wiring driving circuit 70 starts outputting the driving signal for the gate wiring 2.

  Next, the control unit 101 causes the power supply unit 105 to start supplying power to the backlight drive unit 103 (S18). Then, the backlight drive unit 103 is caused to output a drive signal for the backlight 80, and the backlight 80 is turned on (S19).

  Thus, the operation at the time of starting the liquid crystal display device 100 is completed. Thereafter, an image is displayed on the liquid crystal display panel 60 by a general driving method of the liquid crystal display panel 60.

  According to the liquid crystal display device 100 according to the present embodiment, at the time of activation, the driving of the common electrode 8 (application of the common potential) is first started prior to the driving of the gate line 2 and the pixel electrode 6. That is, the common electrode 8 of each pixel 30 of the array substrate 10 and the shield electrode 90 on the gate lead-out wiring 2a have a common potential. As a result, electric charges are charged in the black matrix 22 and the color filter of the counter substrate 20 that oppose the display region 50 and the shield electrode 90. The charged charge propagates through the black matrix 22, the color filter, etc., reaches the counter substrate 20 in the region where the sealant 40 is formed and the region outside the sealant 40, and almost the entire region of the counter substrate 20 converges to a common potential. To do.

  Thereafter, when a predetermined time elapses, driving of the source wiring 5 is started, and then driving of the gate wiring 2 is started. Since the drive signal (image signal) of the source line 5 is close to the common potential in terms of time average, it hardly affects the occurrence of display unevenness. On the other hand, when a drive signal is input to the gate wiring 2, the counter substrate 20 is charged by the electric field from the gate wiring 2 in a region where the shield electrode 90 is not provided. However, at this time, the counter substrate 20 converges to the common potential and is under the influence of the electric field of the common potential. This potential relationship is the same as the above-described equilibrium state. Therefore, the region where the vertical electric field is generated between the counter substrate 20 and the array substrate 10 due to the influence of the electric field from the gate wiring 2 is reduced to the formation region of the shield electrode 90 and does not reach the display region 50. Display unevenness does not occur.

  Finally, the backlight 80 is turned on. When the backlight 80 is turned on last, even if display unevenness occurs slightly when the gate wiring 2 starts to be driven, there is an effect that it is difficult to be visually recognized until the backlight is turned on, and the power consumption of the backlight 80 is reduced. We can expect reduction effect.

  Further, it is desirable that the time measured by the time measuring unit 106, that is, the delay time from the start of driving the common line 9 to the start of driving the source line 5 and the gate line 2 can be adjusted for each liquid crystal display panel 60. . The longer the delay time is, the higher the effect of preventing display unevenness, but the problem is that the time required to start up the liquid crystal display device 100 becomes longer. This is because it is preferable that the startup time can be optimized.

  In the flowchart of FIG. 7, an example is shown in which both the drive start of the source line 5 (S16) and the drive start of the gate line 2 (S17) are delayed for a certain time from the drive start of the common line 9 (S14). As described above, the drive signal of the source line 5 is close to the common potential in terms of time average and hardly affects the occurrence of display unevenness. Therefore, the drive start of the source line 5 does not necessarily have to be delayed. That is, at the time of activation, the driving of the common wiring 9 and the driving of the pixel electrode 6 may be started at the same time, and the driving of the gate wiring 2 may be started after a predetermined time has elapsed.

  In addition, when the operation of the liquid crystal display device 100 ends, the operation stop operation may be performed in the reverse order. FIG. 8 is a flowchart illustrating a driving method when the operation of the liquid crystal display device 100 is stopped.

  When the user operates the on / off switch unit 104 to command the liquid crystal display device 100 to end the operation (S21), the control unit 101 starts measuring time by the time measuring unit 106 (S22), and the backlight driving unit 103. Is controlled to turn off the backlight 80 (S23), and the power supply unit 105 stops the power supply to the backlight drive unit 103 (S24).

  Next, the control unit 101 controls the display driving unit 102 to stop driving the gate wiring 2 of the liquid crystal display panel 60 (S25). That is, the gate wiring driving circuit 70 stops outputting the driving signal for the gate wiring 2. Subsequently, the driving of the source line 5 is also stopped (S26). That is, the source wiring drive circuit 72 stops outputting the drive signal for the source wiring 5.

  Thereafter, when the elapsed time is detected by the time counting unit 106 (YES in S27), the control unit 101 controls the display driving unit 102 to stop driving the common wiring 9. That is, the supply of the common potential to the common wiring 9 is stopped (S28). Then, the control unit 101 causes the power supply unit 105 to stop supplying power to the display driving unit 102 (S29).

  Thus, the operation at the end of the operation of the liquid crystal display device 100 is completed.

  Thus, by stopping the driving of the common wiring 9 at the end of the operation, the potential of the counter substrate 20 can be maintained at the common potential, and the potential fluctuation of the counter substrate 20 can be prevented from occurring at the end of the operation. .

  As described above, according to the liquid crystal display device 100 according to the present embodiment, even when the shield electrode 90 is disposed only inside the sealing material 40 as shown in FIG. Can suppress the potential fluctuation of the counter substrate 20 and can prevent display unevenness.

  Further, by arranging the shield electrode 90 only on the inner side of the seal material 40, even if the shield electrode 90 is provided on the uppermost layer of the array substrate 10, it affects the adhesion between the seal material 40 and the array substrate 10. Never do. Therefore, even if the material of the shield electrode 90 is not relatively high, such as ITO, the adhesion between the array substrate 10 and the counter substrate 20 can be maintained. Therefore, the choice of the material of the shield electrode 90 or the sealing material 40 spreads, and it can be expected to contribute to cost reduction. Further, when the shield electrode 90 is disposed in the uppermost layer of the array substrate 10, a large insulating film thickness between the shield electrode 90 and the gate lead-out wiring 2a can be secured. Therefore, the occurrence of a short circuit between the shield electrode 90 and the gate lead-out wiring 2a can be suppressed, the yield can be prevented from decreasing, and the load capacity of the gate wiring can be reduced.

  In the present invention, the embodiments can be appropriately modified and omitted within the scope of the invention.

  DESCRIPTION OF SYMBOLS 1 Insulating substrate, 2 Gate wiring, 2a Gate extraction wiring, 3 Gate insulating film, 4 Semiconductor film, 5 Source wiring, 5a Source extraction wiring, 6 Pixel electrode, 7 Interlayer insulation film, 8 Common electrode, 9 Common wiring, 10 Array substrate, 11 contact hole, 15 liquid crystal, 16 connection terminal, 20 counter substrate, 21 insulating substrate, 22 black matrix, 23 overcoat, 30 pixels, 40 sealing material, 41 ohmic contact film, 50 display area, 51 source electrode , 52 drain electrode, 55 frame region, 60 liquid crystal display panel, 70 gate wiring drive circuit, 72 source wiring drive circuit, 74 flexible substrate, 76 flexible substrate, 80 backlight, 84 connection portion, 86 connection portion, 90 shield electrode, 82 slit, 100 liquid crystal table Device, 101 control unit, 102 display drive unit, 103 a backlight driving unit, 104 on / off switch unit, 105 power supply unit, 106 timer unit.

Claims (8)

A pixel having a switching element and a pixel electrode to which an image signal is supplied through the switching element, and a common electrode to which a predetermined common potential is supplied;
A scanning wiring for supplying a control signal to the switching element;
A liquid crystal display panel having a signal wiring for supplying the image signal to the switching element;
At the time of start-up, the supply of the control signal to the scanning wiring is started after a predetermined time since the supply of the common potential to the common electrode is started. The liquid crystal display device according to claim 1, wherein at the time of start-up, the supply of the control signal to the scanning line is started after the supply of the image signal to the signal line. 3. The liquid crystal display device according to claim 1, wherein at the end of the operation, the supply of the common potential to the common electrode is stopped after a predetermined period after the supply of the control signal to the scanning wiring is stopped. . A backlight for irradiating the liquid crystal display panel with light;
4. The liquid crystal display device according to claim 1, wherein at the time of start-up, the backlight is turned on a predetermined time after the supply of the common potential to the common electrode is started. The liquid crystal display device according to claim 4, wherein at the time of startup, the backlight is turned on after supply of the control signal to the scanning wiring. 6. The liquid crystal display device according to claim 4, wherein at the end of the operation, the backlight is turned off before the supply of the common potential to the common electrode is stopped. The liquid crystal display device according to claim 1, wherein the predetermined time can be set arbitrarily. The liquid crystal display panel is
A first substrate on which the switching element, the pixel electrode, the common electrode, the scanning wiring, and the signal wiring are formed;
A second substrate disposed opposite the first substrate;
A sealing material that is formed so as to surround a display region in which the pixels are disposed, and that bonds the first substrate and the second substrate;
A liquid crystal sandwiched between the first substrate and the second substrate and sealed with the sealing material;
The first substrate is
A lead-out line for pulling out the scan line to the outside of the display area;
A shield electrode provided on the lead-out wiring via an insulating film and supplied with the common potential;
The liquid crystal display device according to claim 1, wherein the shield electrode is disposed only inside the seal material.

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