JP2013251338A - Semiconductor device for high-voltage power - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for high-voltage power that has reduced useless space, is easy to be formed, and has short working process time.SOLUTION: A semiconductor device for high-voltage power includes: a first first-conductivity-type semiconductor layer (high-resistance Nlayer) 1; a first second-conductivity-type layer (P layer) 2 selectively formed on one surface of the first first-conductivity-type semiconductor layer 1; a second first-conductivity-type layer (Nlayer) 3 formed on the other surface of the first first-conductivity-type semiconductor layer 1; a trench 4 formed in contact with the first second-conductivity-type layer 2; an insulator 5 in the trench 4; a second second-conductivity-type layer (P layer) 6 formed on a side wall and a bottom of the trench 4; and a third first-conductivity-type layer (Nlayer) 7 selectively formed on the bottom of the trench 4. A depletion layer does not spread to a termination portion of the first first-conductivity-type semiconductor layer 1 by the third first-conductivity-type layer 7 and a termination distance becomes shorter, so that the width of the semiconductor device can be reduced by cutting the termination portion of the first-conductivity-type semiconductor layer 1.

Description

  The present invention relates to a semiconductor device for high voltage power such as a power semiconductor used at 600 to 1200 V, for example.

  The bottleneck in miniaturization of power semiconductor devices, particularly high voltage power semiconductor devices for small chips, is the problem of the size of the end region of the chip.

  The power semiconductor has a structure having a high electric field portion inside the silicon chip. FIG. 13 (plan view (a), enlarged sectional view (b) of the termination region, enlarged plan view (c) of the termination region. As shown in FIG. 2, in the vicinity of the end portion (termination portion 22) around the circuit portion 21 in the chip 20, a ring-shaped P-type layer called a guard ring 23 is formed to release a high electric field to the surface of the chip 20. The structure is used (for example, refer nonpatent literature 1). However, since this guard ring structure needs to be provided with a plurality of concentric rings in order to lower the high voltage stepwise, a large space is taken and becomes a barrier to miniaturization of the chip 20. In order to reduce this space, many studies have been made to form a trench at the end of the chip (for example, see Non-Patent Documents 2 to 4).

  As shown in FIG. 13D, the trench termination structure is a high-resistance layer in which a depletion layer spreads at the termination portion of the circuit portion 21 in the chip 20 when voltage is held (off state where no current flows). A trench (groove) 24 having a depth substantially equal to the thickness of is formed.

  In Patent Document 1, a trench is formed in a terminal portion of the power semiconductor so as to substantially penetrate a high resistance layer (low concentration layer) to which a high voltage is applied.

  The power semiconductor disclosed in Patent Document 2 has a structure in which a conductor such as polycrystalline silicon is formed inside a trench formed in a terminal portion, and a sufficient breakdown voltage cannot be obtained at a high voltage.

US Pat. No. 7,855,415 US Pat. No. 6,833,584

M. Adler et al. "Theory and Breakdown Voltage for Planar Devices with a Single Field Limiting Ring", IEEE Transactions on Electron Devices, Vol.24, No.2, pp.107-113, Feb. 1977. R. Kamibaba et al. "Design of trench termination for High Voltage Device", Proc. Of ISPSD 2010, pp. 107-110, 2010. D. Dragomirescu et al. "Novel Concepts High Voltage Junction Termination Techniques Using Very Deep Trenches", Proc. Of Semiconductor Conference 1999, pp.67-70, 1999. W. Hsu et al. "Innovative Designs Enable 300-V TMBS with Ultra-low On-state Voltage and Fast Switching Speed", Proc. Of ISPSD 2011, pp80-83, 2011. T. Drabe et al. "Theoretical Investigation of Planer Junction Termination", Solid-State Electronics, Vol.39, No. 3, pp. 323-328, Mar. 1996.

  In recent power semiconductors, wafers (chips) have been thinned for higher performance (for example, the structure on the front surface of the wafer is 5 to 6 microns, the high resistance layer is 40 to 120 microns, and the number of structures on the back surface is several. μm), especially in IGBTs and PiN diodes of 600 V or higher, the thickness of the high resistance layer has come to occupy most of the thickness of the chip.

When forming such a deep trench, there are the following problems.
(1) When a trench having substantially the same depth as that of the high resistance layer is formed on the wafer, a very thin portion of the wafer is partially formed, and the wafer becomes structurally weak and cracks during the process.

(2) When a deep trench is formed, the processing time is long and the cost of the trench forming process increases.

(3) When the trench is backfilled with an insulator after the trench is formed, if the trench is deep, a portion that is not partially filled is formed. In particular, voids are generated when an organic material is embedded in a trench by a coater (a device that rotates a wafer and applies a liquid organic material before curing to the front surface of the wafer).

(4) A high electric field permeates through the insulator inside the trench and oozes out to the opposite side of the trench, so that the electric field is crushed layer formed in the dicing process on the chip end face (the cut end of the chip after the dicing process) Leakage current is generated by approaching the portion where the crystal structure is destroyed.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a high voltage power semiconductor device that has little wasted space, is easy to form, and has a short processing time.

In order to solve the above problems, a semiconductor device for high voltage power according to the present invention includes:
A first first conductivity type semiconductor layer;
A first second conductivity type layer selectively formed on one surface of the first first conductivity type semiconductor layer;
A second first conductivity type layer formed on the other surface of the first first conductivity type semiconductor layer;
A trench formed in the first first conductivity type semiconductor layer in contact with the first second conductivity type layer;
An insulator filled in the trench;
A second second conductivity type layer formed on the sidewall and bottom of the trench;
And a third first conductivity type layer formed apart from the second second conductivity type layer and substantially in contact with the side wall or bottom of the trench.

  In the present invention, the third first conductivity type layer is formed so as to be separated from the second second conductivity type layer and substantially in contact with the side wall or bottom of the trench. The depletion layer does not extend to the end portion of the first first conductivity type semiconductor layer by the mold layer, and the end distance is shortened. Therefore, the end portion of the first conductivity type semiconductor layer is cut to reduce the width of the semiconductor device. Can do.

  The insulator filled in the trench is preferably an organic substance or a material containing an organic substance.

  The depth of the trench is preferably 0.3 to 0.4 with respect to the thickness of the first first electric semiconductor layer.

  The dielectric constant of the insulator filled in the trench is preferably in the range of 2.65 to 11.7.

  According to the present invention, it is possible to obtain a semiconductor device for high voltage power with little wasted space, easy formation, and short processing time.

1 is a configuration diagram of a semiconductor device for high voltage power according to an embodiment of the present invention. The potential distribution of the semiconductor device for high voltage power and the shape of the depletion layer are compared. (A) is the case of the present embodiment in which the third first conductivity type layer is formed at the bottom of the trench. The case where the 3rd 1st conductivity type layer is not formed is shown. FIG. 4 is a configuration diagram showing an example of an element that takes different voltages on the left and right surfaces of a trench 4. In the embodiment of the present invention, it is a graph showing the relationship between the standardized minimum termination length and standardization trench depth when the length L _i of the first first-conductivity type semiconductor layer as a parameter. In the embodiment of the present invention, it is a graph showing the relationship between the standardized minimum termination length and the standardized trench depth when the relative dielectric constant ε _r of the insulator is used as a parameter. In the embodiment of the present invention, when the trench depth D _T = 55 μm, the relationship between the dose amount (total amount of impurities) of the P ⁻ layer and the breakdown voltage when the distance (termination length) W _T at the bottom of the trench is changed. It is a graph which shows. In the embodiment of the present invention, when the trench depth D _T = 15 μm, it is a graph showing the relationship between the dose amount (total amount of impurities) of the P ⁻ layer and the breakdown voltage when the trench termination length W _T is changed. . In the embodiment of the present invention, it is a graph showing the relationship between the trench termination length W _T and the breakdown voltage when the trench depth _DT is changed. In the embodiment of the present invention, when changing the breakdown voltage is a graph showing the relationship between the depth D _T of the trench minimum termination length and the trench. In the embodiment of the present invention, it is an explanatory view showing the shape of a potential distribution and the depletion layer of the trench end portion when varying the depth D _T and a trench termination length W _T of the trench. In the embodiment of the present invention, it is a graph showing the relationship between the maximum electric field intensity in the trench termination length W _T and the trench. It is explanatory drawing which shows the manufacturing process of the semiconductor device for high voltage electric power which concerns on embodiment of this invention. It is explanatory drawing of a prior art.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a configuration diagram showing an embodiment, and a semiconductor device is described in a diode structure.

In FIG. 1, the semiconductor device for high voltage power according to the embodiment is selectively formed on the first first conductivity type semiconductor layer (high resistance N ⁻ layer in this example) 1 and one surface thereof. The first second conductivity type layer (P layer in this example) 2, the second first conductivity type layer (N ⁺ layer in this example) 3 formed on the other surface, and the first second conductivity type A trench 4 formed in contact with the mold layer 2, an insulator 5 in the trench 4, a second second conductivity type layer (P layer in this example) 6 formed on the side wall and bottom of the trench 4, It has a third first conductivity type layer (N ⁺ layer in this example) 7 selectively formed at the bottom of the trench 4. An anode electrode is formed in contact with the first second conductivity type layer 2, and a cathode electrode is formed in contact with the second first conductivity type layer 3. An SiO ₂ layer is formed on the surface of the insulator 5 as an insulating layer. In addition, the right part of FIG. 1 is a termination | terminus part.

  As a material of the insulator 5, an inorganic material such as silicon oxide, a mixture of silica and resin, an organic material such as polyimide or BCB (benzocyclobutene) resin, or a material mixed with an organic material can be used. The latter organic material or a mixture of organic materials has the advantage that the temperature during application and formation is low, there is no influence on the device structure such as diffusion of impurities, and there is little warping of the wafer after formation due to stress or the like. .

  The first second conductivity type layer (P layer) 2 at the top of FIG. 1 can be changed to an IGBT (Insulated Gate Bipolar Transistor) or MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure depending on the device structure.

FIG. 2 shows the case (a) of the present embodiment in which the third first conductivity type layer (N ⁺ layer) 7 is formed at the bottom of the trench 4 and the third first conductivity type layer (N ⁺ layer). 7 is a comparison of the potential distribution and the shape of the depletion layer. When the third first conductivity type layer (N ⁺ layer) 7 is not formed, the depletion layer spreads toward the terminal end side of the chip as shown in FIG. The distance (distance where the depletion layer spreads from the left end of the trench) is longer. On the other hand, in the structure in which the third first conductivity type layer (N ⁺ layer) 7 is formed, the depletion layer does not spread as shown in FIG. 2A, and the termination distance can be further shortened. .

This structure can also be used for element isolation, and elements that take different voltages on the left and right surfaces of the trench 4 can be arranged. For example, as shown in FIG. 3, with a P / N opposite structure, a p ⁻ epitaxial growth layer 12 and a buried n ⁺ layer 13 are formed on a p ⁺ substrate 11. In the structure in which the n ⁻ layer 15 and the p ⁺ layer 16 that stops the depletion layer are selectively formed at the bottom of the trench 14, the ground voltages are different in the regions A and B on both sides of the trench 14. An IC or the like can be formed. Such a structure is, for example, an IGBT gate drive circuit used for a high voltage inverter, and allows a high side drive IC and a low side drive IC to be formed on the same chip. In this structure, a high voltage can be easily realized as compared with the conventional separation, and since the capacitive coupling component between the separated portions becomes very small, the potential of the two portions changes greatly and instantaneously increases to a high dV / dt. Even if this occurs, there is also a merit that there is little possibility of malfunction. In addition, there is an advantage that the cost is low as compared with the separation technique based on the conventional SOI (Silicon on Insulator) technique.

FIG. 4 shows a structural parameter that can ensure a breakdown voltage of 90% of the ideal breakdown voltage (one-dimensional structure without a termination structure) as a ratio to the length L _i of the high resistance layer (first first conductivity type semiconductor layer 1). Represents. However, it is assumed that the insulator 5 is embedded in the trench 4. The insulator 5 is assumed to be organic and has a relative dielectric constant ε _r of 2.65. This analysis result shows that the relative permittivity ε _r does not change greatly even if it is about 2.5 to 3.5. From this result, even if the length L _{i of} the high resistance layer (first first conductivity type semiconductor layer 1) is different, the ratio of the structure that obtains a breakdown voltage of 90% hardly changes.

High resistance layer (first first conductivity type semiconductor layer 1) to the length L _i, a surface P-type layer ratio D of the (first of the second conductivity type layer 2) the depth D _T of the trenches 4 from the bottom _{When T} / _Li is 0.5, from the surface P layer (second second conductivity type layer 6) side of the trench 4 to the N ⁺ layer (third first conductivity type layer 7) at the bottom of the trench 4 The ratio W _T / L _i between the distance (terminal length) W _T and L _i is 0.3 or more, and when D _T / L _i is 0.32, W _T / L _i is 1.1 or more, D _T / When L _i is 0.15, W _T / L _i is desirably 2.4 or more. By designing the depth D _T and the termination length W _T of the trench 4 in this way, the ideal breakdown voltage can be stably achieved. 90% or more of the breakdown voltage can be obtained.

FIG. 5 shows structural parameters for obtaining an ideal withstand voltage of 90% with respect to the relative dielectric constant ε _r of the insulator 5 filling the trench 4. In this example, a dielectric having ε _r = 11.7 (calculated assuming the same insulator as silicon, but a material obtained by mixing a high dielectric constant inorganic material with a resin) and ε _r = 2. Two cases of 65 dielectrics (eg BCB and silicone) are shown. With each relative dielectric constant ε _r , the standardized trench depth D _T / L _i with respect to the standardized minimum termination length W _T / L _i varies greatly, but D _T / L _i is in the range of 0.3 to 0.4. If so, no change in design is required even if the relative dielectric constant ε _r of the insulator 5 is greatly different. For example, when the material of the buried insulator 4 in the trench 4 is changed or when inorganic particles are introduced into the organic material to improve the insulation performance and long-term reliability of the buried material, the design value in this range is It is reasonable. Further, even if the insulator of the insulator 5 changes over time and the relative dielectric constant changes, the ideal withstand voltage hardly changes.

6 and 7 show the RESURF effect on the breakdown voltage when the trench depths D _T = 55 μm and D _T = 15 μm. Here, the RESURF effect means that by using a specific structure, a withstand voltage higher than the withstand voltage of the PN junction expected in the planar junction can be realized. In these figures, the optimum dose (total amount of impurities) of the P ⁻ layer varies depending on the trench depth D _T and length W _T.

FIG. 8 is a plot of the breakdown voltage of each trench structure for each combination of D _T and W _T shown in Table 1. FIG. 8 also plots the calculation result (Drabe's result: see Non-Patent Document 5) described above.

  The ideal breakdown voltage of a one-dimensional PiN diode structure for an i layer of 110 μm is 1526 V, and the minimum termination length for each trench depth is a length that satisfies a breakdown voltage of 90% or more of the ideal breakdown voltage. It depends on. For shallower trenches, this is an estimate.

  A trade-off curve between the trench depth and the minimum termination length is shown in FIG. This curve shows that the minimum termination length is sufficiently shortened even for shallower trenches. In particular, it can be seen from this figure that even if the trench depth is shortened from 95 μm to 55 μm, the termination length is only a small increase, that is, the termination length is sufficiently shortened even with a trench half as deep as the i layer. I understand that.

The curve of FIG. 5 above is supported for four different trench depths shown in FIGS. 10 (a)-(d). These structures successfully show a breakdown voltage of 90% or more of the ideal breakdown voltage and suppression of attenuation layer expansion to the outside of the trench. Deep trench structures and half-depth structures have successfully achieved a significant reduction in termination length. On the other hand, as shown in FIG. 11, the electric field inside the trench filler (insulator) increases as the minimum termination length decreases.
Thereby, the depth ratio of 0.3 to 0.4 can simultaneously reduce the minimum termination length while also relaxing the electric field in the insulator, and provides a power semiconductor with high reliability and less dead space. be able to.

FIG. 12 shows a process of forming the second second conductivity type layer 6 and the third first conductivity type layer 7 in the present embodiment.
(1) First, the first second conductivity type layer 2 is formed on the upper surface of the first first conductivity type semiconductor layer 1 shown in FIG. 12A, and the second first conductivity type layer 3 is formed on the lower surface. The trench 4 is formed by performing RIE (Reactive Ion Etching) on the formed substrate from the upper surface (see FIG. 12B).
(2) Next, as shown in FIG. 12C, boron implantation (oblique implantation) using a mask is performed to form the second second conductivity type layer 6.
(3) Next, as shown in FIG. 12D, ions (phosphorus) are implanted into the target location of the second second conductivity type layer 6 through the slit 10a using the stencil mask 10, and the third A seed 8 of the first conductivity type layer is formed.
(4) Next, as shown in FIG. 12 (e), the seed 8 is diffused into the first first conductivity type semiconductor layer 1 by thermal diffusion to form a third first conductivity type layer 7.
(5) Finally, as shown in FIG. 12 (f), the insulator 4 is filled in the trench 4 by coating and etching the insulator with a coater.
In this way, the third first conductivity type layer 7 can be formed at the bottom of the trench 4.

In the above embodiments, although the third first-conductivity type layer 7 of an example formed on the terminal end side of the bottom of the trench 4 is not limited to this location, W _T of the left end of the bottom of the trench 4 It may be formed at any location on the bottom (or corner) of the trench 4 as long as it is far away.

  Further, in the present embodiment, the first conductivity type is an N-type semiconductor and the second conductivity type is a P-type semiconductor. Conversely, the first conductivity type is a P-type semiconductor and the second conductivity type is an N-type semiconductor. Also good.

  INDUSTRIAL APPLICABILITY The present invention is suitably used as a high-voltage power semiconductor device with little wasted space, easy formation, and short processing time, such as a drive semiconductor device such as a motor and an air conditioner, and a power source for 240 V power supply type electrical equipment. can do.

DESCRIPTION OF SYMBOLS 1 1st 1st conductivity type semiconductor layer 2 1st 2nd conductivity type layer 3 2nd 1st conductivity type layer 4 Trench 5 Insulator 6 2nd 2nd conductivity type layer 7 3rd 1st conductivity type Layer 10 stencil mask 11 p ⁺ substrate 12 p ^- epitaxial growth layer 13 buried n ⁺ layer 14 trench 15 n ^- layer 16 p ⁺ layer

The depth of the trench is preferably 0.3 to 0.4 with respect to the thickness of the first first conductivity type semiconductor layer.

Claims (4)

A first first conductivity type semiconductor layer;
A first second conductivity type layer selectively formed on one surface of the first first conductivity type semiconductor layer;
A second first conductivity type layer formed on the other surface of the first first conductivity type semiconductor layer;
A trench formed in the first first conductivity type semiconductor layer in contact with the first second conductivity type layer;
An insulator filled in the trench;
A second second conductivity type layer formed on the sidewall and bottom of the trench;
A semiconductor device for high voltage power, comprising: a third first conductivity type layer formed apart from the second second conductivity type layer and substantially in contact with a side wall or bottom of the trench.   The semiconductor device for high voltage power according to claim 1, wherein the insulator filled in the trench is an organic substance or a material containing an organic substance.   3. The high-voltage power semiconductor device according to claim 1, wherein a depth of the trench is 0.3 to 0.4 with respect to a thickness of the first first electric semiconductor layer.   4. The high voltage power semiconductor device according to claim 1, wherein a dielectric constant of an insulator filled in the trench is in a range of a relative dielectric constant of 2.65 to 11.7. 5.