JP2013240262A - Device for controlling three-level inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device for controlling a three-level inverter which suppresses an imbalance in neutral potential irrespective of the power factor of an inverter output current and of whether there is a fundamental, and suppresses an increase in computational load and an increase in the number of components.SOLUTION: A zero-phase voltage calculation section 11 calculates a zero-phase voltage on the basis of a deviation between neutral potentials Vdc1, Vdc2, and adders 15 add the zero-phase voltage to voltage command values Vu, Vv, Vwto calculate corrected voltage command values Vu', Vv', Vw'. A neutral current estimation circuit 2 estimates neutral currents of phases, and a sign determination section 20 determines the sign of the zero-phase voltage added to the voltage command values Vu, Vv, Vwon the basis of the sign of the voltage command value Vu, Vv, Vwand the sign of an inverter output current detection value Iinvu, Iinvv, Iinvw, the values in a phase that has the largest absolute value of the estimated neutral current.

Description

  The present invention relates to balance control of neutral point potential in a three-level inverter.

  In the three-level inverter shown in FIGS. 1 and 2, the neutral point potentials Vdc1 and Vdc2 may be unbalanced depending on conditions such as a load, variation in characteristics of switching elements and DC capacitors, and the like. This unbalance of the neutral point potentials Vdc1 and Vdc2 causes problems such as “the voltage applied to the switching elements T1 to T4 becomes excessive” and “the voltage / current waveform output from the inverter is distorted”.

  As a solution to the unbalance between the neutral point potentials Vdc1 and Vdc2, a method of adding a DC offset to the zero phase of the output voltage when the inverter inputs and outputs active power is conventionally known. Further, when the inverter inputs and outputs reactive power, as described in Patent Document 1, it is only necessary to add the sixth harmonic to the zero phase of the output voltage.

Japanese Patent Application Laid-Open No. 07-079574 JP 09-233840 A JP 2003-169480 A JP 2011-239564 A

  However, Patent Document 1 cannot deal with devices such as active filters whose output current is limited to harmonics.

  Patent Document 2 is an example in which control of the neutral point potential with an active filter is studied. However, in this patent document 2, since an energy storage element and a parallel inverter are installed, and some neutral power is controlled by outputting some effective / reactive power, the cost increases. Further, when the output of reactive power is not required, the operation becomes unnecessary, which may adversely affect the system voltage amplitude.

Patent Document 3 is a control method for estimating an electric current flowing through a neutral point in the following three patterns (1) to (3) and selecting an optimum pattern.
(1) A pattern in which the voltage command value is not corrected.
(2) A pattern in which an offset is added so that the voltage command of the phase that becomes the highest value among the three-phase voltage commands becomes the highest value on the positive side.
(3) A pattern in which an offset is added so that the voltage command of the phase that becomes the lowest value among the three-phase voltage commands becomes the lowest value on the negative side.

  The control method of Patent Document 3 can also control the neutral point potential as long as current flows regardless of active power, reactive power, and harmonics. However, in order to estimate the neutral point currents of all the three patterns, three neutral point current calculation circuits are required as shown in FIG. As a result, a calculation load increases in a digital circuit such as a CPU, and the number of parts increases in an analog circuit.

  Further, Patent Document 3 has a feature that it is determined whether or not the neutral point potential has exceeded a predetermined limit value, and control that suppresses the unbalance of the neutral point potential is started after the limit value is exceeded. . Therefore, there arises a problem that the neutral point potential imbalance increases due to the delay until the start of control.

  Further, Patent Document 4 calculates a zero-phase bias voltage compensation value by using absolute values and signs of voltage command values of all three phases and a load current as a method for determining the sign and magnitude of a zero-phase voltage to be added. Then, how much the neutral point current can be changed (referred to as “neutral point current change amount” in Patent Document 4) is obtained. This Patent Document 4 has the following problems (1) to (3).

  (1) Since all three phase voltage / current signals are used, the computation load increases.

  (2) A division operation is required. Division in an arithmetic processing unit such as a CPU has a high calculation load, and an integrated circuit such as an FPGA requires a large number of logic cells and calculation time. Therefore, it is difficult to implement division and design in digitization is difficult.

  (3) Since there is no steady balance correction function, if there are variations in the characteristics of switching elements, or if an offset is superimposed on the detected voltage / current value, the offset is also superimposed on the estimated current value, resulting in incorrect compensation. And the imbalance expands over time. Element characteristics and detector characteristics may change over time.

  As described above, in the control device of the three-level inverter, the neutral point potential imbalance is suppressed regardless of the power factor of the inverter output current and the presence or absence of the fundamental wave, and the calculation load is increased. Controlling the increase is an issue.

  The present invention has been devised in view of the above-described conventional problems. One aspect of the present invention is connected in series between the DC terminals, and divides the DC voltage between the DC terminals by half. Control of a three-level inverter comprising a plurality of capacitors as neutral points and a plurality of switching elements that convert a three-level DC voltage applied to the plurality of capacitors into an AC voltage based on a correction voltage command value A zero-phase voltage calculator that calculates a zero-phase voltage based on a voltage deviation between each DC terminal and the neutral point; and a correction voltage obtained by adding the zero-phase voltage and a voltage command value An adder for calculating the command value, a neutral point current estimation circuit for estimating the neutral point current of each phase, and a phase having the largest absolute value among the neutral point currents estimated by the neutral point current estimation circuit. Based on the sign of the voltage command value and the sign of the inverter output current detection value. A code decision unit which determines the sign of the zero-phase voltage added to the voltage command value had, characterized by comprising a.

  The zero-phase voltage calculator corrects the zero-phase voltage by adding a value obtained by multiplying a sum of neutral point currents of respective phases by a preset gain to the zero-phase voltage. To do.

  Further, the zero-phase voltage calculation unit includes a filter that extracts at least a high-frequency component of a value obtained by multiplying a sum of neutral point currents of the respective phases by a preset gain, and the high-frequency component is extracted from the zero-phase voltage. The zero phase voltage is corrected by adding to.

  Also, if the result of multiplying the sign of the inverter output current detection value of the phase with the largest absolute value of the estimated neutral point current value by the sign of the zero-phase voltage is +, the upper limit value of the absolute value of the zero-phase voltage is 1 and when the multiplication result is-, a limiter is provided which sets the upper limit value of the absolute value of the zero-phase voltage as the absolute value of the voltage command value of the phase having the largest absolute value among the neutral point currents. To do.

  Further, the neutral point current estimation circuit estimates a value obtained by subtracting a voltage command value of each phase from 1 and an inverter output current detection value as a neutral point current of each phase.

  Further, when the d-axis component of the inverter output current is small, a DC offset is added to the zero-phase voltage.

  Furthermore, the DC offset is characterized in that the sign is switched based on the sign of the d-axis component of the inverter output current.

  According to the present invention, in the control device for a three-level inverter, neutral point potential imbalance is suppressed regardless of the power factor of the inverter output current and the presence or absence of the fundamental wave, and the calculation load and the number of components are increased. It becomes possible to suppress.

It is a block diagram which shows the main circuit of a NPC type | mold 3 level inverter. It is a block diagram which shows the main circuit of an A-NPC type | mold 3 level inverter. FIG. 2 is a configuration diagram illustrating a control device for a three-level inverter in the first embodiment. FIG. 3 is a configuration diagram illustrating a control device for a three-level inverter according to a second embodiment. FIG. 5 is a configuration diagram illustrating a control device for a three-level inverter according to a third embodiment. FIG. 10 is a configuration diagram illustrating a control device for a three-level inverter according to a fourth embodiment. FIG. 10 is a configuration diagram illustrating a control device for a three-level inverter according to a fifth embodiment.

  Hereinafter, the control device of the three-level inverter in the first to third embodiments will be described in detail with reference to the drawings.

[Embodiment 1]
FIG. 1 is a configuration diagram showing a main circuit of an NPC type three-level inverter. As shown in FIG. 1, the main circuit of the NPC type three-level inverter includes capacitors C1 and C2 connected in series between DC terminals P and N, and switching elements T1 to T4. The capacitors C1 and C2 divide the DC voltage between the DC terminals P and N into neutral point potentials Vdc1 and Vdc2, and the connection point between the capacitors C1 and C2 forms a neutral point. The switching elements T1 to T4 are composed of self-extinguishing semiconductor elements (elements having self-extinguishing capability such as transistors, GTOs, and IGBTs) and diodes connected in antiparallel to these individual self-extinguishing semiconductor elements. Is done. A pair of clamp diodes D1 and D2 are connected in parallel to the switching elements T2 and T3.

  FIG. 2 is a configuration diagram showing a main circuit of the A-NPC type three-level inverter. As shown in FIG. 2, the A-NPC type three-level inverter includes capacitors C1 and C2 connected in series between the DC terminals P and N, switching elements T1 and T4 connected in parallel with the capacitors C1 and C2, Bidirectional withstand voltage switch comprising switching elements T2 and T3 interposed between neutral points of capacitors C1 and C2 and neutral points of switching elements T1 and T4 (hereinafter referred to as bidirectional switch) And is composed of. 1 and 2 show only one phase for simplification, but actually, switching elements T1 to T4 (clamp diodes D1 and D2) are provided in three phases.

  Next, a control device 1A for a three-level inverter according to the first embodiment will be described with reference to FIG.

First, the control device 1A for the three-level inverter in the first embodiment estimates the neutral point current in the neutral point current estimation circuit 2. The neutral point current estimation circuit 2 outputs the absolute values of the voltage command values Vu ^* , Vv ^* , Vw ^{* by} the absolute value calculator 3, and subtracts the output of the absolute value calculator 3 from 1 in the subtractor 4. . Finally, the multiplier 5 calculates the product of the output result of the subtracter 4 and the inverter output current detection values Iinvu, Iinvv, Iinvw of the corresponding phase, and calculates the neutral point current estimated value.

  Next, the absolute value calculation circuit 6 calculates the absolute value of the output result (neutral point current estimated value) of the multiplier 5, and the selector 7 outputs the output of the absolute value calculator 6 of each phase (in each phase). From the absolute value of the sex point current estimated value), the phase having the maximum output value of the absolute value calculator 6 is specified.

The switches SW1 and SW2 receive voltage command values Vu ^* , Vv ^* , Vw ^* and inverter output current detection values Iinvu, Iinvv, Iinvw, and switch the output according to a signal from the selector 7. That is, the switches SW1 and SW2 are the voltage command value Vu ^* and the inverter output current detection value Iinvu when the selector 7 selects the U phase, and the voltage command value Vv ^* and the inverter when the selector 7 selects the V phase. When the output current detection value Iinvv and the selector 7 select the W phase, the voltage command value Vw ^* and the inverter output current detection value Iinvw are output.

Next, the zero phase voltage calculator 11 calculates the zero phase voltage. First, Vdc1-Vdc2, which is an unbalance of neutral point potentials, is calculated by the subtracter 8 from the DC voltages Vdc1, Vdc2 detected by the detector (not shown), and then the low-pass filter LPF1 From the output Vdc1-Vdc2, the switching in PWM control and the pulsation of the third harmonic generated at the time of reactive power output are removed. The output of the low-pass filter LPF1 is multiplied by a gain G set in advance by the amplifier 9, and the zero-phase voltage command value superimposed on the voltage command values Vu ^* , Vv ^* , Vw ^* is calculated.

  The sign detector 10A detects the sign of the output of the switch SW1, and outputs 1 when positive and -1 when negative. Similarly, the sign detector 10B detects the sign of the output of the switch SW2, and the sign detector 10C detects the sign of the output result of the amplifier 9. The multiplier 12A calculates the product of the code detection results of the switches SW1 and SW2 (outputs of the code detectors 10A and 10B), and the multiplier 12B calculates the code detection results of the outputs of the switch SW2 and the amplifier 9 (code detectors 10B and 10B, 10C), and the multiplier 12C calculates the product of the multiplier 12A output and the amplifier 9 output. Further, the output result of the switch SW1 is input to the absolute value calculator 13, and the absolute value of the output result of the switch SW1 is calculated.

The switch SW3 inputs 1 and the output of the absolute value calculator 13 and the output of the multiplier 12B. If the output of the multiplier 12B is 1, 1 is output, and if the output of the multiplier 12B is −1. The absolute value of the output result of the switch SW1 (output of the absolute value calculator 13) is output to the limiter 14. The limiter 14 limits the output of the multiplier C by setting the output result of the switch SW3 as the upper limit and the value obtained by inverting the sign in the output result of the switch SW3 as the lower limit. In other words, the output result of the switch SW3 is limited as the upper limit value of the multiplier 12C output. The output of the limiter 14 is output to the adder 15 after abrupt fluctuations are suppressed in the low-pass filter LPF2. The adder 15 adds the output result of the low-pass filter LPF2 and the voltage command values Vu ^* , Vv ^* , Vw ^*, and calculates the corrected voltage command values Vu ^* ′, Vv ^* ′, Vw ^* ′.

A gate signal is generated by PWM modulation based on the corrected voltage command values Vu ^* ′, Vv ^* ′, Vw ^* ′, and the three-level inverter (switching elements T1 to T4) shown in FIG. 1 or FIG. 2 is driven.

  A method for controlling the neutral point potentials Vdc1 and Vdc2 in the first embodiment will be described. The first embodiment is characterized in that a phase that has the greatest influence on the neutral point potentials Vdc1 and Vdc2 is estimated.

First, the neutral point current estimation circuit 2 estimates the neutral point current. Here, the voltage command values Vu ^* , Vv ^* , and Vw ^* are in the range of −1 to 1, and are defined as a lower arm being always ON at −1, a neutral point being ON at 0, and an upper arm being ON at 1. . For example, if Vu ^* = − 0.7, 70% of the PWM carrier cycle is ON for the lower arm and 30% is ON for the neutral point. Therefore, the expected value of the neutral point current can be obtained by the following equation (1).

  The neutral point current in the V phase and the W phase can be similarly obtained.

Next, the phase that has the greatest influence on the neutral point potentials Vdc1 and Vdc2 is estimated. This is determined by selecting the phase having the largest absolute value of the neutral point current simply estimated by the selector 7. The selection result of the selector 7 is input to the switches SW1 and SW2, and thereafter processing is performed using the voltage command values Vu ^* , Vv ^* and Vw ^* of the selected phase and the inverter output current detection values Iinvu, Iinvv and Iinvw. . Finally, for the selected phase, the zero-phase voltage necessary for controlling the neutral point potentials Vdc1 and Vdc2 is obtained. Table 1 shows the relationship between the switching pattern and the zero-phase voltage added to the voltage command values Vu ^* , Vv ^* , Vw ^* .

In the switching pattern of No. 1, both the output voltage and the output current are positive, and the upper arm and the neutral point are turned ON alternately. At this time, a current flows out from the capacitor C2, and a discharging operation is performed. When the capacitor C2 is charged, the current flowing out from the neutral point may be reduced. Therefore, a positive zero-phase voltage is added to move the output voltage away from zero so that a large amount of current flows through the upper arm. Other switching patterns (numbers 2 to 4) are also conceivable. Based on Table 1, the sign of the zero-phase voltage to be added is determined and superimposed on the voltage command values Vu ^* , Vv ^* , and Vw ^* .

The above operation is realized by the control device 1A in the first embodiment shown in FIG. In FIG. 3, the sign of the zero-phase voltage superimposed on the voltage command values Vu ^* , Vv ^* , Vw ^* is determined by the sign determination unit 20 combining the sign detectors 10A, 10B and the multiplier 12A. When collating with Table 1, the output signal of the multiplier 12A is the maximum value of the voltage command values Vu ^* , Vv ^* , Vw ^{* and} the maximum value of the inverter output current detection values Iinvu, Iinvv, Iinvw. , The meanings are as follows.
Positive: Adds zero phase voltage of +.
Negative: Adds a negative zero-phase voltage.

On the other hand, the output signal of the multiplier 12B is multiplied by the sign of the maximum value of the inverter output current detection values Iinvu, Iinvv, Iinvw and the sign of the zero-phase voltage. become.
Positive: Moves the output voltage away from zero.
Negative: Makes the output voltage close to zero.

As an example, the phase selected by the selector 7 is the U phase, the switching pattern of number 2 in Table 1, the output voltage is positive (Vu ^* > 0), the output current is negative, the output of the amplifier 9 is positive, and the capacitor C2 is charged. Think about when you want to. At this time, since the output of the multiplier 12A is negative, the output of the multiplier 12C is also negative, and the negative zero-phase voltage is added to the voltage command values Vu ^* , Vv ^* , Vw ^* . Here, since the output result of the multiplier 12B is also negative, the zero-phase voltage superimposed on the voltage command values Vu ^* , Vv ^* , and Vw ^* is limited by the limiter 14 to Vu ^* to −Vu ^* . Here, since the output of the multiplier 12C is negative, the limiter output is limited to the range of 0 to -Vu ^* .

Therefore, since the correction voltage command value Vu ^* ′ for the selected U phase is limited to the range of Vu ^* −0 ≧ Vu ^* ′ ≧ Vu ^* + (− Vu ^* ), the addition result of the zero phase voltage (correction voltage command The values Vu ^* ′, Vv ^* ′, Vw ^* ′) will not fall below zero. As described above, when the output voltage is desired to approach zero as in the switching pattern of No. 2, the absolute value of the amplifier 9 output (zero phase voltage) based on the neutral point potential unbalance Vdc1-Vdc2 is too large. As a result of adding the zero-phase voltages, it is possible to prevent the output voltages Vu, Vv, Vw from going away from zero.

  As described above, according to the control device for the three-level inverter in the first embodiment, the neutral point potentials Vdc1 and Vdc2 are balanced regardless of the power factor of the inverter output current and the presence or absence of the fundamental wave in the three-level inverter. Can do. As a result, it is possible to solve problems such as an excessive voltage applied to the switching elements T1 to T4 and distortion in the voltage and current waveforms output from the inverter.

  In addition, Patent Document 3 requires three neutral point current calculation circuits. However, since Embodiment 1 only needs to provide one neutral point current estimation circuit 2, the calculation load is larger than that of Patent Document 3. Can be reduced.

[Embodiment 2]
FIG. 4 is a block diagram showing a control device 1B for a three-level inverter in the second embodiment.

 The second embodiment is different from the first embodiment in the following points.

  In the second embodiment, the adder 16 calculates the sum of the output results (neutral point current estimated value) of the multiplier 5 in each phase, and sets the gain Gh preset in the amplifier 17 to the output of the adder 16. Multiply. Then, the output result of the amplifier 17 is added to the output result of the amplifier 9 in the adder 18, and the output of the adder 18 is used as a zero-phase voltage estimated value. Since other configurations are the same as those of the first embodiment, description thereof is omitted here.

  In the second embodiment, as described above, the neutral point current estimated values of all phases are added and input to the amplifier 17, and the output of the amplifier 17 is added to the output result of the amplifier 9. Since the capacitors C1 and C2 differentiate the voltage into a current, adding the output signal of the amplifier 17 based on the sum of the neutral point current estimated values to the output signal of the amplifier 9 is an unbalanced neutral point potential Vdc1. This is equivalent to adding a differential amplifier to the processing of the amplifier 9 based on −Vdc2.

  As described above, according to the control device 1B of the three-level inverter in the second embodiment, the pulsation of the neutral point potentials Vdc1 and Vdc2 can be suppressed. Further, since the neutral point current can be estimated and compensated before the actual unbalance of the neutral point potentials Vdc1 and Vdc2, the unbalance of the neutral point potentials Vdc1 and Vdc2 can be suppressed to be small. It becomes possible. Further, compared to a method of actually adding a differential amplifier, there is a feature that the output of the amplifier 9 does not change abruptly even if there is noise, and the control is less likely to become unstable. Further, since no detector is required compared to the method of actually detecting the neutral point current, the number of parts and the cost can be reduced.

  Further, only the configuration (adder 16, amplifier 17, and adder 18) added in the second embodiment is taken out, and the existing neutral point potential imbalance control (adds a DC zero-phase voltage during active power input / output). It can also be applied in combination.

  Further, since only two adders and one amplifier need be added to the configuration of the first embodiment, the increase in calculation load is also small.

  Furthermore, when determining the compensation amount of the zero-phase voltage, only the voltage command value of one phase and the inverter output current are used instead of all three phases, so that a divider is not required compared to Patent Document 4, and the calculation load is reduced. Few. Further, like the first embodiment, it also has a steady neutral point potential balance function.

[Embodiment 3]
FIG. 5 is a configuration diagram illustrating a control device 1C for a three-level inverter according to the third embodiment.

 In the third embodiment, a filter 21 for extracting a high frequency component is added after the amplifier 17 to the second embodiment, and the high frequency component is added to the output of the amplifier 9 by an adder 18. .

  In the third embodiment, the frequency band is separated by the high-pass filter HPF21. For example, the neutral point imbalance less than 150 Hz is compensated by the voltage detection values Vdc1 and Vdc2, and the neutral point imbalance exceeding 150 Hz is neutral point. Compensation is based on the estimated current value. A pulsation of 150 Hz (a frequency three times that of the fundamental wave) always occurs when the inverter outputs reactive power, and cannot be completely removed. Therefore, by ignoring the 150 Hz pulsation that cannot be removed, unnecessary zero-phase voltage addition can be suppressed, and overmodulation can be prevented.

  Moreover, even if an offset is superimposed on the neutral point current estimated value due to the characteristics of the switching element and the current detector, the offset can be removed by the high-pass filter HPF21, so that the steady neutral point imbalance can be reduced. it can.

[Embodiment 4]
In the control devices of the three-level inverters such as Embodiments 1 to 3 and Patent Document 1, there is a problem that the effect of neutral point potential control is reduced when the output current of the inverter is small. This is because when the output current is small, even if neutral point potential balance control is performed, the current flowing through the neutral point, which is a neutral point potential adjusting means, decreases.

  Therefore, if a disturbance occurs in the neutral point potential when the output current of the inverter is small, it takes time until the potential is balanced. In the meantime, the output voltage distortion of the inverter increases due to fluctuations in the voltage level. In the worst case, a voltage exceeding the rating is applied to the switching element and electrolytic capacitor, which causes deterioration and thermal damage of these elements. cause. As a countermeasure, a method of connecting a voltage dividing resistor is conceivable. However, the higher the effect is, the smaller the value of the resistor is required, and the steady loss of the inverter device increases.

  Therefore, the control device 1D for the three-level inverter according to the fourth embodiment is obtained by adding a DC offset adding unit 26 as shown in FIG.

First, the DC offset adding unit 26 receives the d-axis component (active power component) Id ^* of the inverter output current in the absolute value calculator 22 and outputs the absolute value thereof. The d-axis component Id ^* of the inverter output current may be a command value or a detected value. In addition, Id ^* > 0 indicates that the inverter outputs active power.

  Next, the limiter 23 outputs “1” when the absolute value is close to zero, and outputs “0” when the absolute value is equal to or greater than a predetermined value. The multiplier 24 takes the product of three signals: the output of the limiter 23, the gain K, and the output of the zero-phase voltage calculation unit 11. Here, the gain K usually designates a positive value.

  In the adder 25, the output of the multiplier 24 (DC offset adding unit 26) and the output result of the low-pass filter LPF 2 are added and output to the adder 15. Others are the same as in the first embodiment, and a description thereof is omitted here.

  Usually, a filter including a reactor is connected to the output side of the inverter, and iron loss and copper loss occur in the reactor. Further, if the load is a motor or a transformer, iron loss occurs even when there is no load. Since these losses need to be supplied from the inverter, the inverter always outputs a small amount of active power. The fourth embodiment is based on this idea.

Here, it is assumed that the d-axis component Id ^* of the inverter output current is close to zero and it is desired to charge the capacitor C2 with Vdc1> Vdc2. At this time, the output of the zero-phase voltage calculator 11 becomes a positive value. Further, since the gain K> 0 and the d-axis component Id ^* of the inverter output current becomes 1 by the limiter 23 and is input to the multiplier 24, the output of the multiplier 24 becomes a positive value. 15 is added to the output voltage command values Vu ^* , Vv ^* , Vw ^* . Since the active power is being output a little, a large number of switching patterns 1 and 3 in Table 1 appear, and as a result, charging of the capacitor C2 is prompted.

If the limiter 23 increases the d-axis component Id ^* of the inverter output current to some extent, the output of the DC offset adding unit 26 becomes zero. However, there is a certain amount of output current at this time, and a sufficient neutral point potential control effect can be obtained only by the control block thus far (the control block of the first embodiment).

  As described above, according to the fourth embodiment, in addition to the function and effect of the first embodiment, it is assumed that the inverter always outputs active power, and a DC offset is added to the output voltage command value. Thus, the effect of neutral point potential control at light load can be improved.

  Further, if the load is on the DC side and the main purpose of the inverter is to input active power and convert AC power to DC power, it is necessary to compensate the loss generated on the DC side with the inverter. In such an application, it can be considered that the inverter always receives a little active power. In this case, the same effect can be obtained by specifying a negative value as the gain K.

  In addition, when using the detected value of the inverter current for neutral point potential control, the detection error of the current detector is relatively large at light loads when the current detector is not fully adjusted and there is a deviation in offset or gain. Become. In this state, there is a possibility that the neutral point potential control effect is reduced only by the control blocks so far, or the neutral point potential imbalance is increased. However, since the inverter operating state is estimated by the DC offset adding unit 26 without using current detection, the effect of neutral point potential balance control can be improved.

[Embodiment 5]
FIG. 7 shows the configuration of a control device 1E for a three-level inverter in the fifth embodiment. As shown in FIG. 7, the fifth embodiment is different from the fourth embodiment in the sign detection unit 27 that detects the sign of the d-axis component Id ^* of the inverter output current, and the product of the output of the sign detection unit 27 and the gain K. Is added to the multiplier 28.

In the fifth embodiment, it is assumed that the main application of the inverter is both active power input and output. In such a case, the sign of the gain K cannot be determined in advance. Therefore, the sign detector 27 detects the direction of the d-axis component Id ^* of the inverter output, and when the sign of the d-axis component Id ^* of the inverter output changes, the multiplier 28 changes the sign of the gain K. Thereby, even when the direction of the active power handled by the inverter changes, it is possible to improve the effect of the neutral point potential at light load.

The sign detection unit 27 has hysteresis, and when the d-axis component Id ^* of the inverter output that is an input is close to zero, the output outputs the previous detection result.

  Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

For example, the voltage command values Vu ^* , Vv ^* , and Vw ^* shown in FIG. 3 may be values given by feedforward, and the difference between the detected value of the inverter output current or the inverter output voltage and the command value is the current. It may be the result of amplifier output that is controlled and voltage controlled.

  Further, the inverter output current detection values Iinvu, Iinvv, Iinvw may be added with a low-pass filter LPF in order to remove PWM switching noise. Further, when current control is configured, a command value can be used. If the command value is used, there is no noise, disturbance, detection or filter delay, and the effect of neutral point potential control is enhanced.

  Further, the low-pass filter LPF2 may be replaced with a rate-of-change limiter that outputs an input signal by limiting the signal within a predetermined rate of change.

  Further, the third embodiment is, for example, a bandpass filter in which a lowpass filter is added to the highpass filter HPF21, and a frequency signal higher than 150 Hz and lower than the switching frequency is taken out and used for compensation, or instead of the highpass filter HPF21. Alternatively, a band elimination filter may be applied to process only 150 Hz. Further, the low pass filter LPF1 in the zero phase voltage calculation unit 11 in FIG. 5 is changed to a band elimination filter, or the filters 21 and the filters in the zero phase voltage calculation unit 11 are collectively combined. It can also be moved to the output side.

DESCRIPTION OF SYMBOLS 1A, 1B ... Control apparatus of 3 level inverter 2 ... Neutral point potential estimation circuit 11 ... Zero phase voltage calculation part 14 ... Limiter 15 ... Adder 20 ... Sign determination part C1, C2 ... Capacitor T1-T4 ... Switching element Vdc1, Vdc2: neutral point potential Vu ^* , Vv ^* , Vw ^* ... voltage command value Vu ^* ', Vv ^* ', Vw ^* '... correction voltage command value

Claims (7)

A plurality of capacitors that are connected in series between the DC terminals, divide the DC voltage between the DC terminals by half, and have this voltage dividing point as a neutral point;
A control device for a three-level inverter comprising: a plurality of switching elements that convert a three-level DC voltage applied to the plurality of capacitors into an AC voltage based on a correction voltage command value;
A zero-phase voltage calculator that calculates a zero-phase voltage based on a voltage deviation between each DC terminal and the neutral point;
An adder that calculates the corrected voltage command value by adding the zero-phase voltage and the voltage command value;
A neutral point current estimation circuit for estimating the neutral point current of each phase;
The zero-phase voltage to be added to the voltage command value based on the sign of the voltage command value of the phase having the largest absolute value and the sign of the inverter output current detection value among the neutral point currents estimated by the neutral point current estimation circuit. A control device for a three-level inverter, comprising: a code determination unit that determines a code. The zero-phase voltage calculator is
2. The control of a three-level inverter according to claim 1, wherein the zero-phase voltage is corrected by adding a value obtained by multiplying a sum of neutral point currents of respective phases by a preset gain to the zero-phase voltage. apparatus. The zero-phase voltage calculator is
A filter that extracts at least the high frequency component of the value obtained by multiplying the sum of the neutral point currents of each phase by a preset gain is added, and the zero phase voltage is corrected by adding this high frequency component to the zero phase voltage. 3. The control device for a three-level inverter according to claim 2, wherein:   If the sign of the inverter output current detection value of the phase with the largest absolute value of the estimated neutral point current value and the sign of the zero phase voltage is +, the upper limit value of the absolute value of the zero phase voltage is set to 1. When the multiplication result is-, a limiter is provided that sets the upper limit value of the absolute value of the zero-phase voltage as the absolute value of the voltage command value of the phase having the largest absolute value among the neutral point currents. The control device for a three-level inverter according to any one of Items 1 to 3. The neutral point current estimation circuit includes:
The value obtained by subtracting the voltage command value of each phase from 1 and the inverter output current detection value is estimated as a neutral point current of each phase, according to any one of claims 1 to 4. The three-level inverter control device described. When the d-axis component of the inverter output current is small,
6. The three-level inverter control device according to claim 1, wherein a DC offset is added to the zero-phase voltage. The DC offset is
7. The control apparatus for a three-level inverter according to claim 6, wherein the sign is switched based on the sign of the d-axis component of the inverter output current.

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