JP2013239593A - Solid-state imaging device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of suppressing the occurrence of a blooming phenomenon, and a method of manufacturing the same.SOLUTION: According to an embodiment, the solid-state imaging device is provided. The solid-state imaging device comprises: a first conductivity type well layer; a plurality of photoelectric conversion elements; an element isolation region; and a voltage applying part. Each of the photoelectric conversion elements includes a second conductivity type semiconductor region and a first conductivity type semiconductor region sequentially laminated on the well layer. At least a connection part of the element isolation region with the well layer is formed of an insulator, and the element isolation region electrically isolates adjacent photoelectric conversion elements from each other. The voltage applying part applies, to the well layer, a voltage for making the height of a potential barrier of the well layer lower than the height of a potential barrier of the first conductivity type semiconductor region.

Description

  Embodiments described herein relate generally to a solid-state imaging device and a method for manufacturing the solid-state imaging device.

  Conventionally, a solid-state imaging device includes a plurality of photoelectric conversion elements provided corresponding to each pixel of a captured image. Each photoelectric conversion element is electrically separated by an element isolation region, photoelectrically converts incident light into an amount of charge corresponding to the received light intensity, and accumulates it in the charge accumulation region. And in a solid-state imaging device, it images by reading an electric charge from the electric charge accumulation area | region of each photoelectric conversion element.

  In such a solid-state imaging device, for example, a photoelectric conversion element that selectively receives red incident light, a photoelectric conversion element that selectively receives green incident light, and a photoelectric conversion that selectively receives blue incident light. Elements are adjacently arranged to constitute one pixel of the captured image.

  For this reason, in solid-state imaging devices, when the intensity of incident light of a specific color is extremely strong, the amount of charge photoelectrically converted by a photoelectric conversion element that selectively receives incident light of a specific color exceeds the amount of charge that can be accumulated. In some cases, a blooming phenomenon that leaks to the adjacent photoelectric conversion element may occur.

  In such a case, in the solid-state imaging device, charges exceeding the charge amount corresponding to the received light intensity are excessively accumulated in the photoelectric conversion element adjacent to the photoelectric conversion element from which the charge has leaked, so that the brightness of the captured image is the original There may be a problem that the image quality of the captured image is deteriorated because the luminance is higher than the luminance.

JP 2009-260841 A

  The problem to be solved by the present invention is to provide a solid-state imaging device and a method for manufacturing the solid-state imaging device that can suppress the occurrence of blooming phenomenon.

  According to the embodiment, a solid-state imaging device is provided. The solid-state imaging device includes a first conductivity type well layer, a plurality of photoelectric conversion elements, an element isolation region, and a voltage application unit. The plurality of photoelectric conversion elements include a second conductivity type semiconductor region and a first conductivity type semiconductor region that are sequentially stacked on the well layer. In the element isolation region, at least a connection portion with the well layer is formed of an insulator, and electrically isolates the adjacent photoelectric conversion elements. The voltage application unit applies a voltage that lowers the height of the potential barrier of the well layer to be lower than the height of the potential barrier of the semiconductor region of the first conductivity type.

Explanatory drawing by the planar view which shows the CMOS sensor which concerns on embodiment. Explanatory drawing by planar view which expanded a part of pixel part which concerns on embodiment. The cross-sectional schematic diagram by the AA line shown in FIG. 2 which concerns on embodiment. Explanatory drawing which shows the height of the potential barrier in the depth position of the pixel part which concerns on embodiment. Explanatory drawing which shows operation | movement of the pixel part which concerns on embodiment. Explanatory drawing which shows the manufacturing process of the CMOS sensor which concerns on embodiment. Explanatory drawing by planar view which shows the pixel part which concerns on the modification 1 of embodiment. Explanatory drawing by planar view which shows the pixel part which concerns on the modification 2 of embodiment.

  Hereinafter, a solid-state imaging device and a method for manufacturing the solid-state imaging device according to the embodiments will be described in detail with reference to the accompanying drawings. In addition, this invention is not limited by embodiment shown below.

  In this embodiment, as an example of a solid-state imaging device, a so-called surface-irradiation type CMOS (Complementary Metal Oxide Semiconductor) image sensor in which a wiring layer is formed on a surface on which incident light is incident in a light receiving unit that photoelectrically converts incident light. Will be described as an example.

  In the following description, the case where the front-illuminated CMOS image sensor photoelectrically converts incident light into negative charges will be described. However, the front-illuminated CMOS image sensor according to the embodiment is configured to photoelectrically convert incident light into positive charges. There may be.

  Note that the solid-state imaging device according to the present embodiment is not limited to a front-illuminated CMOS image sensor, and is an arbitrary image sensor such as a back-illuminated CMOS image sensor or a CCD (Charge Coupled Device) image sensor. Also good.

  FIG. 1 is an explanatory diagram in plan view of a front-illuminated CMOS image sensor (hereinafter referred to as “CMOS sensor 1”) according to the embodiment. As shown in FIG. 1, the CMOS sensor 1 includes a pixel unit 2 and a logic unit 3 formed on a semiconductor substrate 100.

  The pixel unit 2 includes a plurality of photoelectric conversion elements provided in a matrix corresponding to each pixel of an image to be captured. Each of the photoelectric conversion elements photoelectrically converts incident light into negative charges having an amount corresponding to the received light intensity, and accumulates them in the charge accumulation region. The configuration of the pixel unit 2 will be described later with reference to FIG.

  The logic unit 3 includes a timing generator 31, a vertical selection circuit 32, a sampling circuit 33, a horizontal selection circuit 34, a gain control circuit 35, an A / D (analog / digital) conversion circuit 36, an amplification circuit 37, and the like.

  The timing generator 31 is a pulse signal that serves as a reference for operation timing for the pixel unit 2, the vertical selection circuit 32, the sampling circuit 33, the horizontal selection circuit 34, the gain control circuit 35, the A / D conversion circuit 36, the amplification circuit 37, and the like. Is a processing unit for outputting.

  The vertical selection circuit 32 is a processing unit that sequentially selects, in units of columns, photoelectric conversion elements that read charges from a plurality of photoelectric conversion elements arranged in a matrix. The horizontal selection circuit 34 is a processing unit that sequentially selects photoelectric conversion elements for reading out charges in units of rows.

  The sampling circuit 33 is a processing unit that reads out charges from the photoelectric conversion elements selected by the vertical selection circuit 32 and the horizontal selection circuit 34 at a timing synchronized with the pulse signal output from the timing generator 31. The sampling circuit 33 outputs a signal corresponding to the read charge to the gain control circuit 35.

  The gain control circuit 35 is a processing unit that adjusts the gain of the signal input from the sampling circuit 33 and outputs the adjusted signal to the A / D conversion circuit 36. The A / D conversion circuit 36 is a processing unit that converts an analog signal input from the gain control circuit 35 into a digital signal and outputs the digital signal to the amplification circuit 37. The amplification circuit 37 is a processing unit that amplifies the digital signal input from the A / D conversion circuit 36 and outputs the amplified signal to a predetermined DSP (Digital Signal Processor (not shown)).

  Next, the configuration of the pixel unit 2 will be described. FIG. 2 is an explanatory diagram in plan view in which a part of the pixel unit 2 according to the embodiment is enlarged. As shown in FIG. 2, the pixel unit 2 includes a photoelectric conversion element 4, a read transistor 5, a reset transistor 6, an amplification transistor 7, a floating diffusion (hereinafter referred to as “FD8”), and the like. The amplification transistor 7 is electrically isolated from other circuit elements in the pixel portion 2.

  The photoelectric conversion element 4 includes a photodiode that photoelectrically converts incident light into an amount of charge corresponding to the received light intensity and accumulates it in the charge accumulation region. Here, four photoelectric conversion elements 4 are illustrated, but a plurality of such photoelectric conversion elements 4 are arranged in a matrix corresponding to each pixel of an image to be captured.

  For example, in the CMOS sensor 1, a photoelectric conversion element 4 that selectively receives red incident light, a photoelectric conversion element 4 that selectively receives green incident light, and a photoelectric that selectively receives blue incident light. One photoelectric conversion element 4, which is adjacent to the conversion element 4, constitutes one pixel.

  In the pixel unit 2, a plurality of sets of these three photoelectric conversion elements 4 are arranged in a matrix at positions corresponding to the pixels to be imaged. The combination of the colors of incident light received by each photoelectric conversion element 4 constituting one pixel and the number of photoelectric conversion elements 4 constituting one pixel are not limited to this.

  In addition, an element isolation region 9 that electrically isolates each photoelectric conversion element 4 is provided between adjacent photoelectric conversion elements 4. As shown in FIG. 2, the element isolation regions 9 are provided in a lattice shape so as to surround the light receiving regions of the photoelectric conversion elements 4 in plan view.

  The read transistor 5 is a transistor that reads charges from the photoelectric conversion element 4 to the FD 8 when a predetermined read voltage is applied to the gate 51. The FD 8 is a temporary storage unit for charges read from the photoelectric conversion element 4.

  The reset transistor 6 is a transistor that removes the charge existing in the FD 8 from the FD 8 before the charge is read from the photoelectric conversion element 4 to the FD 8 by applying a predetermined reset voltage to the gate 61.

  The amplification transistor 7 is a transistor in which the gate 71 is connected to the FD 8, the source is connected to a predetermined power source, and the drain is connected to the sampling circuit 33. The amplification transistor 7 outputs a voltage signal amplified to the sampling circuit 33 according to the gate voltage applied to the gate 71, that is, according to the amount of charge read to the FD 8.

  Thus, in the CMOS sensor 1, an image is obtained by acquiring, as color information of each pixel, a voltage signal corresponding to the amount of charge photoelectrically converted by the plurality of photoelectric conversion elements 4 corresponding to each pixel of the captured image. Image.

  Further, the CMOS sensor 1 has a configuration capable of suppressing the occurrence of blooming even when the intensity of incident light of a certain color (hereinafter referred to as “specific color”) is extremely high. Next, the configuration of the pixel unit 2 that suppresses the occurrence of the blooming phenomenon will be described with reference to FIG. 3 is a schematic cross-sectional view taken along line AA shown in FIG. 2 according to the embodiment.

  Although not shown here, a color filter and a microlens are sequentially stacked on the upper layer side of the photoelectric conversion element 4 shown in FIG. 3 via an interlayer insulating film provided with multilayer wiring.

  As shown in FIG. 3, the pixel portion 2 is formed of a semiconductor of a first conductivity type (hereinafter referred to as “P type”) or a second conductivity type (hereinafter referred to as “N type”). The SUB layer 101 is provided on the semiconductor substrate 100.

  The pixel portion 2 is formed by a PN junction of a P-type well layer 40 provided on the SUB layer 101, an N-type semiconductor region 41 and a P-type semiconductor region 42 sequentially stacked on the well layer 40. The photoelectric conversion element 4 is provided.

  In addition, the pixel unit 2 includes an element isolation region 9 that extends from the upper surface of the P-type semiconductor region 42 to the upper surface of the well layer 40 between adjacent photoelectric conversion elements 4. In the element isolation region 9, at least a connection portion 90 with the well layer 40 is formed of an insulator. Further, the portion 91 other than the coupling portion 90 in the element isolation region 9 is formed of a semiconductor doped with a P-type impurity. The element isolation region 9 electrically isolates the adjacent photoelectric conversion element 4.

  Further, the pixel unit 2 includes a voltage application unit 10 that applies a voltage to the well layer 40. The voltage application unit 10 applies to the well layer 40 a positive voltage that causes the potential barrier height of the well layer 40 to be lower than the potential barrier height of the P-type semiconductor region 42.

  In the CMOS sensor 1, the occurrence of blooming phenomenon is suppressed by applying a predetermined voltage to the well layer 40 by the voltage application unit 10. The operation of the CMOS sensor 1 that suppresses the occurrence of the blooming phenomenon will be described below with reference to FIGS.

  4 is an explanatory diagram showing the height of a potential barrier (hereinafter simply referred to as “barrier”) at the depth position of the pixel unit 2 according to the embodiment, and FIG. 5 is a photoelectric conversion according to the embodiment. FIG. 11 is an explanatory diagram showing an operation of the element 4.

  In FIG. 5, reference numeral 4 </ b> R is attached to the photoelectric conversion element 4 that selectively receives red incident light, and reference numeral 4 </ b> G is attached to the photoelectric conversion element 4 that selectively receives green incident light. The charge accumulation amount in 4G is schematically shown by hatching.

  4, in the CMOS sensor 1, when no voltage is applied to the well layer 40 by the voltage application unit 10, the upper surface of the N-type semiconductor region 41 and the barrier of the well layer 40 are P-type. As high as the barrier of the semiconductor region 42. In such a case, the barrier of the inside of the N type semiconductor region 41 and the barrier of the SUB layer 101 is lower than the barrier of the P type semiconductor region 42.

  Thereby, in the CMOS sensor 1, the interface between the P-type semiconductor region 42 and the N-type semiconductor region 41 and the barrier in the well layer 40 serve as a water divide, and the photoelectrically converted charge is converted into the N-type semiconductor region 41. Accumulated inside. That is, in the photoelectric conversion element 4, the N-type semiconductor region 41 is a charge storage region.

  Here, when incident light of a specific color having an extremely high intensity is incident on the CMOS sensor 1, the photoelectric conversion element 4 that selectively receives the incident light of the specific color can store a charge amount that can be stored by photoelectric conversion. Reach the upper limit (saturation charge).

  In the photoelectric conversion element 4, when the amount of charge to be photoelectrically increased further, the charge exceeds the barrier at the interface between the P-type semiconductor region 42 and the N-type semiconductor region 41, and other adjacent charges are provided. A blooming phenomenon that leaks to the photoelectric conversion element 4 occurs.

  Therefore, in the CMOS sensor 1, a predetermined positive voltage is applied to the well layer 40 by the voltage application unit 10. As a result, the potential energy of the well layer 40 is increased, and the barrier of the well layer 40 is the upper barrier of the N-type semiconductor region 41, that is, the P-type semiconductor region 42, as shown by the solid line graph in FIG. Lower than the barrier.

  As a result, the CMOS sensor 1 operates as shown in FIG. 5 when green incident light with extremely high intensity is incident, for example. Specifically, as shown in the left diagram of FIG. 5, when the green incident light L having extremely high intensity is incident on the position where the photoelectric conversion element 4R and the photoelectric conversion element 4G are adjacent to each other, FIG. As shown in the middle figure, a larger amount of charge e is accumulated in the photoelectric conversion element 4G faster than the photoelectric conversion element 4R.

  When the incident light L further enters the photoelectric conversion element 4R and the photoelectric conversion element 4G, as shown in the right diagram of FIG. 5, in the photoelectric conversion element 4G, the amount of charge that is photoelectrically converted reaches the saturation charge amount.

  Thereafter, in the photoelectric conversion element 4G, when the incident light L continues to be incident, charges exceeding the charge amount that can be accumulated are generated by the photoelectric conversion, but the well layer 40 is applied by voltage application to the well layer 40 by the voltage application unit 10. The barriers are falling.

  For this reason, the charge exceeding the saturation charge amount and excessively photoelectrically converted by the photoelectric conversion element 4G does not leak from the upper surface side of the N-type semiconductor region 41 to the adjacent photoelectric conversion element 4R side, and the SUB layer. It is discharged to the 101 side.

  At this time, in the element isolation region 9, as described above, since the connection portion 90 with the well layer 40 is formed of an insulator (see FIG. 3), the barrier of the portion 91 other than the connection portion 90 is lowered. Absent. Therefore, the CMOS sensor 1 can prevent the charge excessively photoelectrically converted by the photoelectric conversion element 4G from leaking to the adjacent photoelectric conversion element 4R side through the element isolation region 9. That is, according to the CMOS sensor 1, even when incident light of a specific color having extremely high intensity is incident, the blooming phenomenon can be suppressed.

  Next, a method for manufacturing the CMOS sensor 1 will be described with reference to FIG. FIG. 6 is a cross-sectional view illustrating an example of the manufacturing process of the CMOS sensor 1 according to the embodiment. In the following, a manufacturing process for forming the portion of the CMOS sensor 1 shown in FIG. 3 will be mainly described, and the other manufacturing processes will be described briefly.

  When the CMOS sensor 1 is manufactured, as shown in FIG. 6A, a semiconductor substrate 100 provided with a SUB layer 101 doped with P-type or N-type impurities is prepared. Then, a well layer 40 doped with a P-type impurity, an N-type semiconductor region 41, and a P-type semiconductor region 42 are sequentially formed on the SUB layer 101 in the semiconductor substrate 100.

  Specifically, for example, a P-type well layer 40 is formed by ion-implanting a P-type impurity such as boron or boron fluoride into a silicon layer provided on the SUB layer 101. Then, an N-type semiconductor region 41 is formed by ion-implanting an N-type impurity such as phosphorus or arsenic into the silicon layer on the well layer 40.

  Further, by implanting a P-type impurity such as boron or boron fluoride into the silicon layer on the N-type semiconductor region 41 at a higher concentration than the impurity concentration in the well layer 40, the P-type semiconductor region 42 is formed. Note that the silicon layer on the SUB layer 101 may not be formed in advance. In such a case, a silicon layer is formed on the SUB layer 101 by an epitaxial method before ion implantation.

  Subsequently, as shown in FIG. 6B, oxygen O 2 is injected with a predetermined ion implantation energy from the upper surface of the P-type semiconductor region 42 toward the formation position of the element isolation region 9 (see FIG. 3) in the semiconductor substrate 100. Ion implantation. Thereby, an oxygen doped region 92 is formed at the position where the element isolation region 9 is formed on the well layer 40.

  Thereafter, as shown in FIG. 6C, a P-type impurity such as boron or boron fluoride enters the semiconductor substrate 100 from the position where oxygen O 2 is ion-implanted on the upper surface of the P-type semiconductor region 42. P is ion-implanted.

  At this time, the P-type impurity P is ion-implanted with a predetermined ion implantation energy weaker than that when oxygen O 2 is ion-implanted. As a result, a P-type doped region 93 is formed on the oxygen-doped region 92.

  Subsequently, as shown in FIG. 6D, a plurality of ion implantations of the P-type impurity P is performed into the semiconductor substrate 100 from the position where the P-type impurity P is ion-implanted on the upper surface of the P-type semiconductor region 42. Repeat once.

  At this time, the ion implantation of the P-type impurity P is sequentially repeated while gradually decreasing the ion implantation energy. Thereby, a P-type doped region 93 extending from the upper surface of the oxygen-doped region 92 to the upper surface of the P-type semiconductor region 42 is formed.

  Thereafter, annealing is performed to activate oxygen O 2 in the oxygen doped region 92 and P-type impurity P ions in the P-type doped region 93. As a result, as shown in FIG. 3 described above, at least the connection portion 90 with the well layer 40 is formed of silicon oxide as an insulator, and a portion 91 other than the connection portion 90 is doped with a P-type impurity P. An isolation region 9 is formed.

  Although not shown here, after the step shown in FIG. 6D, an interlayer insulating film in which a multilayer wiring is provided is formed on the P-type semiconductor region. At this time, a contact hole that connects the wiring connected to the voltage application unit 10 in the multilayer wiring and the well layer 40 is formed, and a conductive metal such as copper is buried in the contact hole.

  As a result, the voltage application unit 10 and the well layer 40 are connected, and the potential barrier height of the well layer 40 is lowered from the voltage application unit 10 to the well layer 40 to be lower than the potential barrier height of the P-type semiconductor region 42. A configuration for applying a voltage is formed. Finally, the CMOS sensor 1 is manufactured by sequentially laminating a color filter and a microlens on the interlayer insulating film on which the multilayer wiring is formed.

  In addition, the structure which connects the well layer 40 and the voltage application part 10 is not limited to the structure mentioned above. For example, a terminal may be provided on the side surface (end surface) of the well layer 40 and the terminal and the voltage applying unit 10 may be connected by a pattern wiring or the like. Further, the arrangement position of the voltage application unit 10 may be an arbitrary position in the CMOS sensor 1.

  As described above, the CMOS sensor 1 according to the embodiment includes the P-type well layer 40, the plurality of photoelectric conversion elements 4, the element isolation region 9, and the voltage application unit 10. The plurality of photoelectric conversion elements 4 include an N-type semiconductor region 41 and a P-type semiconductor region 42 that are sequentially stacked on the well layer 40.

  In the element isolation region 9, at least the connection portion 90 with the well layer 40 is formed of an insulator, and electrically isolates the adjacent photoelectric conversion elements 4. Further, the voltage application unit 10 applies a voltage to the well layer 40 that lowers the height of the potential barrier of the well layer 40 below the height of the potential barrier of the P-type semiconductor region 42.

  Thereby, when the CMOS sensor 1 receives incident light of a specific color, the charge excessively converted by the photoelectric conversion element 4 can be discharged from the well layer 40 to the SUB layer 101 side.

  Therefore, the CMOS sensor 1 can prevent the charge excessively photoelectrically converted by the photoelectric conversion element 4 from leaking to the adjacent photoelectric conversion element 4. That is, according to the CMOS sensor 1, the occurrence of the blooming phenomenon can be suppressed.

  Further, the connection portion 90 with the well layer 40 in the element isolation region 9 is formed by ion implantation of oxygen O 2 into a predetermined position of the semiconductor layer formed on the well layer 40. Thereby, in the CMOS sensor 1, the element isolation region 9 and the well layer 40 can be easily and reliably insulated.

  As described above, in the CMOS sensor 1, the element isolation region 9 and the well layer 40 are reliably insulated so that the potential of the element isolation region 9 can be obtained when a predetermined voltage is applied to the well layer 40 by the voltage application unit 10. It is possible to prevent the height of the barrier from being lowered. Thereby, in the CMOS sensor 1, when a voltage is applied to the well layer 40, it is possible to prevent the photoelectrically converted charge from leaking to the adjacent photoelectric conversion element 4 through the element isolation region 9. it can.

  Further, the portion 91 other than the connection portion 90 with the well layer 40 in the element isolation region 9 is formed by ion-implanting P-type impurities P into the semiconductor layer on the connection portion 90. Thus, for example, when a manufacturing apparatus for manufacturing a conventional CMOS sensor has a configuration in which an element isolation region is formed by ion-implanting a P-type impurity P into a semiconductor layer, it is simply performed by changing the implanted ions. The CMOS sensor 1 which concerns on a form can be manufactured.

  That is, when the element isolation region is formed by a conventional manufacturing apparatus, oxygen O 2 is ion-implanted in the first ion implantation process, and then the P-type impurity P is sequentially ion-implanted, thereby greatly changing the configuration of the manufacturing apparatus. Even without this, the CMOS sensor 1 according to the embodiment can be manufactured.

  Note that the configuration of the pixel unit 2 in the CMOS sensor 1 according to the above-described embodiment is merely an example, and the configuration is arbitrary as long as the voltage application unit 10 reduces the height of the potential barrier of the well layer 40. Can be changed. Hereinafter, the pixel portion of the CMOS sensor according to the modification of the embodiment will be described with reference to FIGS.

  FIG. 7 is an explanatory diagram in plan view showing a pixel unit 2a according to Modification Example 1 of the embodiment, and FIG. 8 is an explanatory diagram in plan view showing pixel unit 2b according to Modification Example 2 of the embodiment. Note that, among the components of the pixel unit 2a according to Modification Example 1 and the pixel unit 2b according to Modification Example 2, the same components as those illustrated in FIG. 3 are denoted by the same reference numerals as those illustrated in FIG. Thus, the description thereof is omitted.

  As shown in FIG. 7, the pixel portion 2a according to the first modification is different from the pixel portion 2 shown in FIG. 3 in the configuration of the element isolation region 9a. Specifically, the element isolation region 9a in the pixel portion 2a is entirely formed of an insulator.

  When the element isolation region 9a is formed, for example, a trench (groove) is formed at a position where the element isolation region 9a is formed in the semiconductor substrate 100 in which the N-type semiconductor region 41 and the P-type semiconductor region 42 are sequentially stacked on the well layer 40. ).

  At this time, for example, a resist is formed on the upper surface of the P-type semiconductor region 42, and an opening is formed by photolithography at a position where the element isolation region 9a is formed in the resist. Subsequently, by performing dry etching using such a resist as a mask, a trench extending from the upper surface of the P-type semiconductor region 42 to the upper surface of the well layer 40 is formed. Thereafter, the element isolation region 9a is formed by burying silicon oxide in the trench by, for example, CVD (Chemical Vapor Deposition).

  In this way, by providing the element isolation region 9a formed entirely of an insulator and applying a predetermined voltage to the well layer 40 by the voltage application unit 10, the blooming phenomenon is performed as in the pixel unit 2 shown in FIG. Can be suppressed.

  Further, in the pixel portion 2a, since the formation position of the element isolation region 9a can be determined by the position of dry etching for forming a trench, the element isolation region 9a is formed at an accurate position as designed.

  Further, as shown in FIG. 8, the pixel portion 2b according to the modified example 2 is also different from the pixel portion 2 shown in FIG. 3 in the configuration of the element isolation region 9b. Specifically, the element isolation region 9b in the pixel portion 2b includes a connecting portion 90b made of an insulator embedded in a formation position of the element isolation region 9b in the semiconductor substrate 100 and a P-type element isolation region 91b.

  When forming such an element isolation region 9 b, for example, an N-type semiconductor region 41 extending from the upper surface of the semiconductor substrate 100 to the upper surface of the well layer 40 in the depth direction of the semiconductor substrate 100 is formed. Subsequently, a trench extending from the upper surface of the N-type semiconductor region 41 to the upper surface of the well layer 40 is formed by dry etching at the formation position of the element isolation region 9b.

  Thereafter, a connecting portion 90b is formed by forming a silicon oxide film having a predetermined thickness in the trench by, for example, CVD. Subsequently, by forming a P-type semiconductor layer on the entire upper surface of the N-type semiconductor region 41 including the trench by, for example, CVD, a P-type element isolation region 91b is formed inside the trench, and the N-type semiconductor region A P-type semiconductor region 42 is formed on the upper surface of 41.

  At this time, the P-type element isolation region 91b and the P-type semiconductor region 42 may be simultaneously formed by performing CVD using a material gas containing a P-type impurity P. Further, a silicon layer is formed by CVD on the entire upper surface of the N-type semiconductor region 41 including the trench, and P-type impurity P is ion-implanted into the silicon layer, whereby the P-type element isolation region 91b and the P-type semiconductor are formed. The region 42 may be formed at the same time.

  In the case of ion implantation, the thickness of the P-type element isolation region 91b and the P-type semiconductor region 42 (the length in the depth direction of the semiconductor substrate 100) is the thickness shown in FIG. It is necessary to adjust the injection energy.

  The provision of the element isolation region 9b and application of a predetermined voltage to the well layer 40 by the voltage application unit 10 can also suppress the occurrence of blooming phenomenon as in the pixel unit 2 shown in FIG.

  Also in the element isolation region 9b in the pixel portion 2b, since the formation position of the element isolation region 9b is determined by the position of dry etching for forming the trench, the element isolation region 9b is formed at an accurate position as designed.

  In addition, in the pixel portion 2b, the P-type semiconductor region 42 and the P-type element isolation region 91b are simultaneously formed in one process, so that the throughput related to the production efficiency of the CMOS sensor 1 is improved.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 CMOS sensor, 2, 2a, 2b Pixel part, 3 Logic part, 4, 4G, 4R Photoelectric conversion element, 5 Read transistor, 6 Reset transistor, 7 Amplification transistor, 8 FD, 9, 9a, 9b Element isolation area, 10 Voltage application unit, 31 timing generator, 32 vertical selection circuit, 33 sampling circuit, 34 horizontal selection circuit, 35 gain control circuit, 36 A / D conversion circuit, 37 amplification circuit, 40 well layer, 41 N-type semiconductor region, 42 P-type semiconductor region, 51, 61, 71 gate, 90, 90b connecting portion, 91 portions other than connecting portion, 91b P-type element isolation region, 92 oxygen-doped region, 93 P-type doped region, 100 semiconductor substrate, 101 SUB layer, L incident light, O2 Element, P P-type impurity, e charge

Claims (5)

A first conductivity type well layer;
A plurality of photoelectric conversion elements including a second conductivity type semiconductor region and a first conductivity type semiconductor region sequentially stacked on the well layer;
An element isolation region for electrically isolating the photoelectric conversion elements adjacent to each other, wherein at least a connection portion with the well layer is formed of an insulator;
A solid-state imaging device, comprising: a voltage applying unit that applies a voltage to the well layer that lowers a potential barrier height of the well layer to be lower than a potential barrier height of the first conductivity type semiconductor region. The connecting portion is
The solid-state imaging device according to claim 1, wherein oxygen is ion-implanted into a predetermined position of a semiconductor layer formed on the well layer. Sites other than the connecting portion in the element isolation region are:
The solid-state imaging device according to claim 2, wherein an impurity of a first conductivity type is ion-implanted into the semiconductor layer on the connection portion. The element isolation region is
The solid-state imaging device according to claim 1, wherein the whole is formed of an insulator. Forming a first conductivity type well layer;
Forming a plurality of photoelectric conversion elements including a second conductivity type semiconductor region and a first conductivity type semiconductor region sequentially stacked on the well layer;
A step of forming an element isolation region for electrically isolating the photoelectric conversion elements adjacent to each other, wherein at least a connection portion with the well layer is formed of an insulator;
Forming a voltage applying unit that applies a voltage to the well layer to lower a potential barrier height of the well layer than a potential barrier height of the first conductivity type semiconductor region. Manufacturing method of solid-state imaging device.

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