JP2013236410A - Variable gain amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable gain amplifier that suppresses an output impedance fluctuation in the event of a gain change.SOLUTION: The variable gain amplifier includes: a grounded source amplification element 3 connected to an input terminal 1 at a gate-biased gate to amplify an input signal; a ladder resistance circuit 61 having a plurality of parallel resistances 63 to which a drain bias is applied from one end, and having a plurality of series resistances 62 connecting the parallel resistances 63 on the other end; a plurality of grounded gate amplification elements 5-5having gate-biased gates grounded in a high frequency manner, drains connected to the parallel resistances of the ladder resistance circuit 61 on the other end, and sources connected to a drain of the grounded source amplification element 3; an output terminal 12 connected to the drain of any one of the plurality of grounded gate amplification elements; and a gate bias control circuit 64 connected to the gates of the plurality of grounded gate amplification elements to selectively supply a gate bias.

Description

  The present invention relates to a variable gain amplifier having a gain switching function.

A variable gain amplifier is an amplifier whose gain can be varied in order to set a high-frequency signal to an appropriate power level.
The variable gain amplifier is a circuit that changes the output power under the condition that the input level is constant, and it is necessary that the distortion characteristics do not deteriorate even if the gain is changed. As a circuit in which the distortion characteristic does not deteriorate when the gain is changed under a condition where the input level is constant, for example, there is a variable gain amplifier shown in Patent Document 1 below.

This variable gain amplifier is a cascode amplifier in which a source grounded FET and a gate grounded FET are cascode-connected.
Of the three gate-grounded FETs on the output side of the variable gain amplifier, two gate-grounded FETs are connected to the output load circuit and the output terminal, and one gate-grounded FET is connected to the power supply terminal so as to be grounded in terms of high frequency. Grounded.
This variable gain amplifier has the highest gain when the grounded-gate FET connected to the output load circuit and the output terminal is turned on and the grounded-gate FET grounded to the ground is turned off in terms of high frequency.
In addition, this variable gain amplifier has a gain that is small because the size of the grounded-gate FET is equivalently reduced when either one of the output load circuit and the two grounded-gate FETs connected to the output terminal is turned off. To reduce.
Furthermore, this variable gain amplifier turns on a gate grounded FET that is grounded in terms of high frequency, and guides a part of the signal amplified by the grounded source FET to the ground, thereby outputting a signal to the output terminal. As a result, it is possible to reduce the gain.

  This variable gain amplifier is a system that changes the gain mainly by changing the loss on the output side of the grounded-source FET that generates distortion, so the output is changed by changing the gain while the input level is constant. The distortion characteristics are not deteriorated even when the power is changed.

JP 2004-128704 A

Since the conventional variable gain amplifier is configured as described above, the gain can be changed by equivalently changing the size of the grounded-gate FET provided on the output side. However, if the size of the common-gate FET provided on the output side is changed equivalently, the output impedance of the variable gain amplifier changes.
Further, even if the output side is matched with a reactance element such as an inductor or a capacitor, the output impedance of the variable gain amplifier changes, so that there is a problem that the matching is shifted.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a variable gain amplifier that can suppress fluctuations in output impedance even when the gain is changed.

A variable gain amplifier according to the present invention has a gate to which a gate bias is supplied connected to an input terminal, a source connected to a ground, and a common-source amplifier that amplifies a signal input from the input terminal, and one end A ladder resistor circuit having a plurality of series resistors connecting the other ends of the plurality of parallel resistors, and a gate to which the gate bias is supplied are grounded in high frequency with a plurality of parallel resistors to which a drain bias is applied from A drain is connected to the other end of each parallel resistor in the ladder resistor circuit, a source is connected to the drain of the common-source amplifier, and a plurality of common-gate amplifiers that amplify the signal amplified by the common-source amplifier An output terminal connected to one of the drains of the plurality of grounded-gate amplification elements, and the gates of the plurality of grounded-gate amplification elements. Is connected to the bets, in which a selectively supplying gate bias control circuit the gate bias to the gate of the plurality of gate grounded type amplifier element.
In addition, a gate bias circuit that supplies a gate bias to the gate of the common-source amplifier is provided, and the gate bias circuit applies a gate bias corresponding to the reference current supplied from the reference current source to the gate of the common-source amplifier. A gate bias supply transistor to be supplied, a first transistor constituting a current mirror circuit paired with the gate bias supply transistor, a drain connected to the drain of the first transistor, and supplied with a drain bias And a second transistor that supplies a voltage generated at the gate to the gate bias control circuit as a gate bias reference voltage, and includes a first transistor, a second transistor, and a grounded source. Type amplifying element and grounded-gate type amplifying element are of the same type In it is obtained by the as configured.

  According to the present invention, there is an effect that the fluctuation of the output impedance can be suppressed even if the gain is changed.

It is a circuit diagram which shows the variable gain amplifier comprised by FET by Embodiment 1 of this invention. It is a circuit diagram which shows the variable gain amplifier comprised by BJT by Embodiment 1 of this invention. It is a circuit diagram which shows the gate bias control circuit comprised by FET by Embodiment 2 of this invention. It is a circuit diagram which shows the gate bias control circuit comprised by BJT by Embodiment 2 of this invention. It is a circuit diagram which shows the variable gain amplifier comprised by FET by Embodiment 3 of this invention. It is a circuit diagram which shows the variable gain amplifier comprised by BJT by Embodiment 3 of this invention. It is a circuit diagram which shows the variable gain amplifier by Embodiment 4 in this invention. It is a graph which shows the effect of the variable gain amplifier by Embodiment 4 in this invention. FIG. 10 is a circuit diagram showing a variable gain amplifier according to a fifth embodiment of the present invention. It is a circuit diagram which shows the variable gain amplifier by Embodiment 6 in this invention. It is a circuit diagram which shows the variable gain amplifier comprised by FET by Embodiment 7 of this invention. It is a circuit diagram which shows the variable gain amplifier comprised by BJT by Embodiment 7 of this invention. It is a circuit diagram which shows the variable gain amplifier comprised by FET by Embodiment 8 of this invention. It is a circuit diagram which shows the variable gain amplifier comprised by BJT by Embodiment 8 of this invention. It is a circuit diagram which shows the variable gain amplifier comprised by FET by Embodiment 10 of this invention. It is a circuit diagram which shows the variable gain amplifier comprised by BJT by Embodiment 10 of this invention. It is a circuit diagram which shows the variable gain amplifier comprised by FET by Embodiment 11 of this invention. It is a circuit diagram which shows the variable gain amplifier comprised by BJT by Embodiment 11 of this invention. It is a circuit diagram which shows the gate bias control circuit comprised by FET by Embodiment 12 of this invention. It is a circuit diagram which shows the gate bias control circuit comprised by BJT by Embodiment 12 of this invention. It is a circuit diagram which shows the variable gain amplifier comprised by FET by Embodiment 13 of this invention. It is a circuit diagram which shows the variable gain amplifier comprised by BJT by Embodiment 13 of this invention.

Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a variable gain amplifier composed of an FET according to Embodiment 1 of the present invention. In the figure, an input terminal 1 is a terminal for inputting a signal.
The DC cut capacitors 2 _{1 to} 2 _n (n is an arbitrary natural number) are connected to the input terminal 1 and are members for cutting a direct current component included in a signal input from the input terminal 1.
The source grounded FETs 3 _{1 to} 3 _n (n is an arbitrary natural number) have a gate connected to the input terminal 1 via DC cut capacitors 2 ₁ to 2 _n and a source connected to the common ground 4. This is a common source amplifying element that amplifies the signal input from.
The gate grounded FET 5 has a gate connected to the gate terminal 6 and is grounded to the ground 4 via a high-pass capacitor 7 at a high frequency, and a drain connected to the output load circuit (load inductor 10 or load resistor 11) and the output terminal 12. The source is connected to the drains of the common-source FETs 3 _{1 to} 3 _n and is a grounded-gate amplification element that amplifies the signal amplified by the common-source FETs 3 _{1 to} 3 _n and outputs the amplified signal to the output terminal 12.

The gate terminal 6 is a terminal to which a gate bias is supplied.
The high-pass capacitor 7 is a member that is connected between the gate terminal 6 and the ground 4 and absorbs an unnecessary high-frequency signal to the ground 4.
The drain bias terminal 8 is a terminal to which a preset drain bias is supplied.
The high-pass capacitor 9 is a member that is connected between the drain bias terminal 8 and the ground 4 and absorbs an unnecessary high-frequency signal to the ground 4.
A load inductor 10 that is an output load circuit is connected between the drain of the common-gate FET 5 and the drain bias terminal 8.
In the example of FIG. 1, a load inductor 10 is connected between the drain of the common-gate FET 5 and the drain bias terminal 8, but a load resistor 11 that is an output load circuit is connected instead of the load inductor 10. You may make it do.

The output terminal 12 is connected to the drain of the common-gate FET 5 and the load inductor 10 via the DC cut capacitor 13 and outputs a signal amplified by the common-gate FET 5.
The DC cut capacitor 13 is a member that cuts a DC component contained in the signal amplified by the common gate FET 5.
The gate bias control circuit 14 is connected to the connection point between the gates of the common-source FETs 3 _{1 to} 3 _n and the DC cut capacitors 2 ₁ to 2 _n via the gate bias terminals 15 ₁ to 15 _n and the gate bias feed resistors 16 _{1 to} 16 _n. Has been.
When the gate bias control circuit 14 receives the reference current from the reference current input terminal 17, it generates a gate bias from the reference current according to the gain control signal input from the gain control signal input terminal 19, and selectively selects the gate bias. Are supplied to the gates of the common-source FETs 3 _{1 to} 3 _n .
The reference current input terminal 17 is a terminal for inputting a reference current, and the reference current source 18 is a power source that supplies the reference current to the reference current input terminal 17.
The gain control signal input terminal 19 is a terminal for inputting a gain control signal for controlling the gain of the variable gain amplifier.

Next, the operation will be described.
Signals input from the input terminal 1 are input to the source grounded FETs 3 _{1 to} 3 _n via the DC cut capacitors 2 ₁ to 2 _n and amplified by the source grounded FETs 3 _{1 to} 3 _n .
The signals amplified by the common source FETs 3 _{1 to} 3 _n are input to the common gate FET 5 and amplified by the common gate FET 5.
The signal amplified by the common-gate FET 5 is output from the output terminal 12 via the load inductance 10 (or load resistor 11) and the DC cut capacitor 13.

At this time, a drain bias set in advance is supplied to the drain bias terminal 8, and an appropriate gate bias set in advance by the gate bias control circuit 14 is supplied to the gates of the common-source FETs 3 _{1 to} 3 _n. Has been. A gate bias set in advance is supplied to the gate terminal 6 of the grounded-gate FET 5, and the variable gain amplifier operates as a cascode amplifier.
As described above, the variable gain amplifier operates as a cascode amplifier in which the plurality of common-source FETs 3 _{1 to} 3 _n and the common-gate FET 5 are cascode-connected, so that a high gain can be obtained.
Since the drain bias terminal 8 is grounded to the ground 4 via the high-pass capacitor 9 and the gate terminal 6 is grounded to the ground 4 via the high-pass capacitor 7, unnecessary high-frequency signals included in the signal are grounded. 4 is absorbed. As a result, the isolation between the variable gain amplifier and the power source can be increased.

Here, the gate bias control circuit 14 selectively supplies the gate bias to the gates of the common-source FETs 3 _{1 to} 3 _n , so that the common-source FET 3 that is actually operated among the plurality of common-source FETs 3 _{1 to} 3 _n is used. And the gain of the variable gain amplifier is changed.
The operation of the gate bias control circuit 14 will be specifically described below.

The current of the cascode amplifier is determined by the current flowing through the common-source FETs 3 _{1 to} 3 _n . Drain current Id _total flowing through all of the source-grounded FET 3 ₁ to 3 _n, the drain current Id _1, Id ₂ flowing through each source-grounded FET 3 ₁ to 3 _n, · · ·, is expressed by the sum of the Id _n. The output power _Pout is expressed as follows when the load is ZL. However, Id _total ^* is a complex conjugate of Id _total .
P _out = Id _total × Id _total ^* × ZL / 2
The output power P _out is proportional to the square of the drain current Id _total flowing through all the common source FETs 3 _{1 to} 3 _n .
Therefore, by changing the total size of the source-grounded FET 3 ₁ to 3 _n, the drain current Id _total flowing through all of the source-grounded FET 3 ₁ to 3 _n changes, the output power P _out is changed, as a result The gain of the variable gain amplifier can be changed.
For example, _if the total size of the common source FETs 3 _{1 to} 3 _n is halved, the output power P _out becomes ¼ and the gain is reduced by about 6 dB.

Here, for example, consider the case where the gate width Wg _1, Wg ₂ ··· Wg _n is the size of the source-grounded FET 3 ₁ to 3 _n with respect to the total of the gate width Wg _total, is set as follows.
Wg ₁ = Wg _total / 2,
Wg ₂ = Wg _1/2
:
Wg _n = (Wg _n-1 ) / 2
The gain is maximized when an appropriate gate bias is supplied to the gates of all the common source FETs 3 _{1 to} 3 _n .
Relative to the maximum gain, the source-grounded FET 3 ₁ of the gate width Wg _1, the gate width Wg _2, · · ·, to the source grounded FET 3 _n-1 of Wg _n-1, one after the other gate bias OFF (= 0V ), Every time the common source FET is turned off, the drain current decreases by ½, and the gain decreases by about 6 dB. That is, it is possible to realize a 6 dB step variable gain amplifier.
In this example, a case _where the gate width of each of the common source FETs 3 _{1 to} 3 _n is reduced by ½ is shown. However, if the gate width is reduced by 1 / √2, for example, a variable gain amplifier with 3 dB steps is obtained. In other words, in order to obtain a variable gain amplifier with an X dB step, the gate width of the common-source FETs 3 _{1 to} 3 _n should be reduced by every 10 (X / 20) power.

As described above, according to the first embodiment, by the gate bias control circuit 14 is selectively supplied to the gate of the source grounded FET 3 ₁ to 3 _n of the gate bias, a plurality of source-grounded FET 3 ₁ to 3 _n of, by switching the common source FET3 to actually operate, and since so as to change the total size of the source-grounded FET3 ₁ to 3 _n, by changing the current flowing through all of the source-grounded FET3 ₁ to 3 _n The output power _Pout can be changed, and as a result, the gain of the variable gain amplifier can be changed.
When a variable gain amplifier is actually realized, the variable amount of gain may shift due to the influence of parasitic elements. In that case, a variable amount of gain can be set by finely adjusting the gate width of the common-source FETs 3 _{1 to} 3 _n .

In addition, since the output power _Pout is changed by changing the size of the grounded-source FETs 3 _{1 to} 3 _n that mainly generate distortion, the output changes because the gain changes under the condition that the input power is constant. However, the distortion characteristics can be prevented from deteriorating.
Further, since the size of the output-side grounded FET 5 does not change with respect to the change in gain, it is possible to suppress the change in output impedance. Thereby, even when the load inductor 10 is connected as an output load circuit and matching is performed, the matching state can be prevented from changing with respect to the change in gain. Therefore, it is possible to reduce the error of the variable gain width due to the change of the matching state.
Further, when the gain is lowered, part of the common-source FETs 3 _{1 to} 3 _n that determines the current value of the variable gain amplifier is turned off to reduce the total size of the common-source FETs 3 _{1 to} 3 _n. The current consumption can be reduced according to the gain.

In the first embodiment, as shown in FIG. 1, an example in which the common source FETs 3 _{1 to} 3 _n are used as the common source amplification element and the common gate FET 5 is used as the common gate amplification element has been described. As shown in FIG. 2, the grounded source BJTs 3 _{1 to} 3 _n may be used as the grounded source amplifying element, and the grounded base BJT5 may be used as the grounded gate amplifying element. Can play.
However, in the variable gain amplifier configured by the BJT of FIG. 2, the base, emitter, and collector of the common-emitter BJTs 3 _{1 to} 3 _n correspond to the gate, source, and drain of the common-source amplifier, respectively.
The base, emitter, and collector of the common base BJT 5 correspond to the gate, source, and drain of the common-gate amplification element, respectively.

Note that the common-source amplifier is not limited to the common-source FETs 3 _{1 to} 3 _n and the common-emitter BJTs 3 _{1 to} 3 _n , and other transistors may be used as long as they are common-source transistors. .
Further, the grounded gate type amplifying element is not limited to the grounded gate FET 5 and the grounded base BJT 5, and other transistors may be used as long as they are grounded gate type transistors.

  In the first embodiment, the output load circuit is connected to the load inductor 10 or the load resistor 11. However, since the change in the output impedance can be suppressed with respect to the change in the gain, the design can be made. It can be established by applying either of them accordingly. For example, when a high frequency signal is handled or when the output is large, the load inductor 10 is applied with an emphasis on performance (gain, output, efficiency, etc.). The resistor 11 may be applied to reduce the size and cost of the chip.

Embodiment 2. FIG.
FIG. 3 is a circuit diagram showing a gate bias control circuit 14 composed of an FET according to the second embodiment of the present invention. In the figure, the current mirror circuit FET 21 has a drain and a gate connected to the reference current input terminal 17, and FIG. The source is grounded to the ground 4 and is a reference current input transistor for allowing the reference current input from the reference current input terminal 17 to flow to the switching FETs 22 _{1 to} 22 _n .
The switching FETs 22 _{1 to} 22 _n are provided corresponding to the common source FETs 3 _{1 to} 3 _n , and the drain is commonly connected to the gate of the current mirror circuit FET 21 and constitutes a current mirror circuit together with the current mirror circuit FET 21. doing. When the switching FETs 22 _{1 to} 22 _n receive a reference current from the current mirror circuit FET 21, the switching FETs supply a gate bias corresponding to the size ratio with the current mirror circuit FET 21 to the gates of the source grounded FETs 3 _{1 to} 3 _n. It is.
The bypass capacitor 23 is connected between the gate of the current mirror circuit FET 21 and the ground 4 and is a member for absorbing an unnecessary high-frequency signal into the ground 4.

The gain control logic circuit 24 is connected to the gain control signal input terminal 19, converts the gain control signal input from the gain control signal input terminal 19 into a gate control signal of the division number n, and converts the gate control signal to the gate control signal terminal. It outputs to 25 _{1 to} 25 _n . That is, the gain control logic circuit 24 of FET 22 ₁ through 22 _n switch, the process of selecting according to a gain control signal to FET 22 ₁ through 22 _n switch supply gate bias to the gate of the source grounded FET 3 ₁ to 3 _n carry out.
The gate bias feed resistors 26 _{1 to} 26 _n are resistors connected between the gates of the switching FETs 22 _{1 to} 22 _n and the gate control signal terminals 25 _{1 to} 25 _n .
The switching FETs 27 _{1 to} 27 _n are provided corresponding to the source grounded FETs 3 _{1 to} 3 _n , the drains are connected to the sources of the switching FETs 22 _{1 to} 22 _n and the gate bias terminals 15 ₁ to 15 _n, and the sources are grounded. 4 is a transistor that is grounded.
Inverters 28 _{1 to} 28 _n have anodes connected to gate control signal terminals 25 _{1 to} 25 _n and cathodes connected to gates of switching FETs 27 _{1 to} 27 _n via gate control signal feed resistors 29 _{1 to} 29 _n. Yes.

Next, the operation will be described.
The reference current input from the reference current input terminal 17 flows through the current mirror circuit FET 21.
At this time, each of the switching FETs 22 _{1 to} 22 _n constituting the current mirror circuit together with the current mirror circuit FET 21 has a current mirror with respect to the reference current if the switching FETs 22 _{1 to} 22 _n are on. A current corresponding to the size ratio with the circuit FET 21 flows.
The current flowing through the switching FETs 22 _{1 to} 22 _n is supplied as a gate bias to the source grounded FETs 3 _{1 to} 3 _n via the gate bias terminals 15 ₁ to 15 _n and the gate bias feed resistors 16 _{1 to} 16 _n shown in FIG. .
Therefore, an appropriate gate bias can be supplied to the common-source FETs 3 _{1 to} 3 _n by setting the sizes of the switching FETs 22 _{1 to} 22 _n in advance to appropriate sizes.

On the other hand, a gain control signal is input to the gain control logic circuit 24 from the gain control signal input terminal 19, and the gain control logic circuit 24 converts the input gain control signal into a gate control signal of the division number n. The gate control signal is output to the gate control signal terminals 25 _{1 to} 25 _n .
The gate control signal output from these gate control signal terminals 25 _{1 to} 25 _{n determines which} of the gate bias terminals 15 ₁ to 15 _n is supplied with the gate bias.
For example, when the gate control signals output from the gate control signal terminals 25 _{1 to} 25 _n are at “H” level, the gates of the switching FETs 22 _{1 to} 22 _n are set to “H” via the gate bias feed resistors 26 _{1 to} 26 _n. "The level is supplied and the switching FETs 22 _{1 to} 22 _n are turned on.
Further, the “L” level is supplied to the gates of the switching FETs 27 _{1 to} 27 _n via the inverters 28 _{1 to} 28 _n and the gate control signal feed resistors 29 _{1 to} 29 _n , and the switching FETs 27 _{1 to} 27 _n are turned off. To do.
Accordingly, the gate bias is supplied to the gate bias terminal 15 ₁ to 15 _n.

Conversely, when the gate control signals output from the gate control signal terminals 25 _{1 to} 25 _n are at “L” level, the gates of the switching FETs 22 _{1 to} 22 _n are connected to the gates of the switching FETs 22 _{1 to} 22 _n via the gate bias feed resistors 26 _{1 to} 26 _n. The L ″ level is supplied, and the switching FETs 22 _{1 to} 22 _n are turned off.
Further, the “H” level is supplied to the gates of the switching FETs 27 _{1 to} 27 _n via the inverters 28 _{1 to} 28 _n and the gate control signal feed resistors 29 _{1 to} 29 _n , and the switching FETs 27 _{1 to} 27 _n are turned on. To do.
As a result, since the gate bias terminals 15 ₁ to 15 _n are grounded to the ground 4, no gate bias is supplied to the gate bias terminals 15 ₁ to 15 _n .

As described above, according to the second embodiment, the current mirror circuit FET 21 and the plurality of switch FETs 22 _{1 to} 22 _n constitute a current mirror circuit, and the switch FETs 22 _{1 to} 22 _n have a reference current. On the other hand, since the current corresponding to the size ratio with the current mirror circuit FET 21 is allowed to flow, the current flowing through the switching FETs 22 _{1 to} 22 _n can be set discretely with respect to the reference current. Therefore, an optimal gate bias can be supplied to the gates of the common-source FETs 3 _{1 to} 3 _n using these currents and the gate bias feed resistors 16 _{1 to} 16 _n . Further, by using the same type of FET in the FET 22 ₁ through 22 _n for FET21 and a plurality of switches for the current mirror circuit, the temperature characteristic is the same in the FET 22 ₁ through 22 _n for FET21 and a plurality of switches for the current mirror circuit Thus, the relationship of flowing a current corresponding to the size ratio with respect to the reference current can be made constant with respect to the temperature.
Further, since the gain control logic circuit 24 for converting the input gain control signal into the gate control signal supplied to the switching FETs 22 _{1 to} 22 _n is provided, the number of input terminals of the gate bias control circuit 14 is set to the source ground. The number n of the FETs 3 _{1 to} 3 _n can be reduced to the number of input terminals for the gain control signal. For example, if the number n of the source grounded FET 3 ₁ to 3 _n is 4, the number of gain control signal input terminal 19 to the two, if the number n of the source grounded FET 3 ₁ to 3 _n is 8, the gain control signal The number of gain control signal input terminals 19 can be reduced to a logarithm with a base of 2, such as up to three input terminals 19. Furthermore, if a serial-parallel conversion circuit is incorporated, the number of gain control signal input terminals 19 can be reduced to one.

In the second embodiment, the current mirror circuit FET 21 and the plurality of switch FETs 22 _{1 to} 22 _n form a current mirror circuit, and the switch FETs 27 ₁ to 27 _n correspond to the source grounded FETs 3 _{1 to} 3 _n. It has been described as providing a 27 _n, as shown in FIG. 4, with a current mirror circuit in the BJT22 ₁ ~22 _n for BJT21 a plurality of switches for the current mirror circuit, the source-grounded FET 3 ₁ to 3 _n Correspondingly, switch BJTs 27 _{1 to} 27 _n may be provided, and the same effect as the gate bias control circuit 14 of FIG. 3 can be obtained.
However, when the gate bias control circuit 14 is configured by replacing the FET with BJT as shown in FIG. 4, the gate is replaced with the base, the source is replaced with the emitter, and the drain is replaced with the collector.

In the second embodiment, the gain control logic circuit 24 that converts the input gain control signal into the gate control signal of the division number n and outputs the gate control signal to the gate control signal terminals 25 _{1 to} 25 _n is provided. Although provided, the gain control logic circuit 24 may be eliminated, and the gate control signal may be directly input to the gate control signal terminals 25 _{1 to} 25 _n . In this case, the circuit configuration can be simplified by eliminating the gain control logic circuit 24.

Embodiment 3 FIG.
FIG. 5 is a circuit diagram showing a variable gain amplifier composed of an FET according to the third embodiment of the present invention. In the figure, the same reference numerals as those in FIG.
The variable gain amplifier of FIG. 5 constitutes a differential amplifier, and a differential positive phase input terminal 31 on the positive phase side of the differential amplifier is a terminal for inputting a positive phase side signal of the differential signal. The positive phase output terminal 32 is a terminal for outputting a positive phase side signal amplified by the common gate FET 5.
The common-source FETs 3 _{1 to} 3 _n constitute a first common-source amplifier, and the common-gate FET 5 constitutes a first common-gate amplifier.
Further, the load inductor 10 (or load resistor 11) constitutes a first output load circuit.

The differential negative phase input terminal 41 on the negative phase side of the differential amplifier is a terminal for inputting a negative phase side signal of the differential signal.
The DC cut capacitors 42 _{1 to} 42 _n (n is an arbitrary natural number) are connected to the differential negative phase input terminal 41 and cut the direct current component included in the negative phase side signal input from the differential negative phase input terminal 41. It is a member.
The source grounded FETs 43 ₁ to 43 _n (n is an arbitrary natural number) have their gates connected to the differential negative phase input terminal 41 via DC cut capacitors 42 _{1 to} 42 _n and their sources connected to the common ground 4. This is a second source grounding type amplifying element that amplifies the negative phase side signal input from the differential negative phase input terminal 41.
The gate grounded FET 45 has a gate connected to the gate terminal 6 and is grounded to the ground 4 via the high-pass capacitor 7 at a high frequency, and a drain is connected to the second output load circuit (the load inductor 50 or the load resistor 51) and the differential. Connected to the negative-phase output terminal 52, the source is connected to the drains of the common-source FETs 43 ₁ to 43 _n , and the negative-phase side signal amplified by the common-source FETs 43 ₁ to 43 _n is amplified to obtain the differential negative-phase output This is a second grounded-gate amplification element that outputs to the terminal 52.

A load inductor 50 as a second output load circuit is connected between the drain of the common-gate FET 45 and the drain bias terminal 8.
In the example of FIG. 5, the load inductor 50 is connected between the drain of the common-gate FET 45 and the drain bias terminal 8, but instead of the load inductor 50, a load resistor that is a second output load circuit. 51 may be connected.

The differential negative-phase output terminal 52 is connected to the drain of the common-gate FET 45 and the load inductor 50 via the DC cut capacitor 53, and is a terminal for outputting the negative-phase side signal amplified by the common-gate FET 45.
The gate bias control circuit 14 is connected to the connection point between the gates of the common-source FETs 3 _{1 to} 3 _n and the DC cut capacitors 2 ₁ to 2 _n via the gate bias terminals 15 ₁ to 15 _n and the gate bias feed resistors 16 _{1 to} 16 _n. Also, the gates of the common source FETs 43 ₁ to 43 _n and the connection points of the DC cut capacitors 42 _{1 to} 42 _n are connected via the gate bias terminals 15 ₁ to 15 _n and the gate bias feed resistors 56 _{1 to} 56 _n. Has been.
When the gate bias control circuit 14 receives the reference current from the reference current input terminal 17, it generates a gate bias from the reference current according to the gain control signal input from the gain control signal input terminal 19, and selectively selects the gate bias. Are supplied to the gates of the common-source FETs 3 _{1 to} 3 _n and the common-source FETs 43 ₁ to 43 _n .

Next, the operation will be described.
The variable gain amplifier according to the third embodiment is different from the variable gain amplifier according to the first embodiment only in that the configuration of the variable gain amplifier is a differential configuration. Therefore, the operation of the variable gain amplifier according to the third embodiment performs the same operation as the operation of the variable gain amplifier according to the first embodiment on the positive phase side and the negative phase side of the differential amplifier. Therefore, the same effect as in the first embodiment can be obtained.

Further, since the variable gain amplifier according to the third embodiment has a differential configuration, at a location corresponding to each other on the circuit in the differential configuration, when one is positive, the other is always negative, and its amplitude Is ideally the same. Therefore, when the locations corresponding to the differential configuration are connected in common, the midpoint is always 0 potential, that is, a high-frequency virtual ground.
If there is no high-frequency virtual ground, it will be grounded to the actual ground, but to the actual ground, parasitic components (such as the routing line on the chip, the pad on the chip, and the wire to be grounded from the pad) Inductance). When this parasitic component enters between the FETs, the FET gain decreases. When there is a high-frequency virtual ground, the parasitic component is reduced because the ground is closer to the FET than the actual ground, and a decrease in the gain of the FET can be suppressed to a small level. As a result, high frequency operation is possible. Alternatively, a high gain can be obtained.

Furthermore, for example, the other ends of the gate bias feed resistance 56 ₁ ~ 56 _n corresponding gate bias feed resistance 16 ₁ ~ 16 _n are connected to a common connection when the differential configuration, the common connection points Gate bias terminals 15 ₁ to 15 _n for selectively supplying a gate bias are connected, and each connection point is configured as a high frequency virtual ground, or the sources of the common source FETs 43 ₁ to 43 _n are common source FETs 3 _{1 to} 3. It is configured to be grounded to the common ground 4 including the source of _n , or the gate of the common-gate FET 45 is commonly connected to the gate of the common-gate FET 5 and is grounded to the ground 4 through the high-pass capacitor 7. In the layout, the high-frequency ground in the differential configuration is arranged symmetrically around the common connection point. Realizes high frequency operation. Alternatively, a high gain can be obtained.

As described above, according to the third embodiment, the function of the differential amplifier can be provided.
Further, with the configuration of the differential amplifier, a high frequency operation is possible due to the virtual ground between the differentials. Alternatively, a high gain can be obtained.
Further, in the layout, by arranging symmetrically around the virtual ground, a high-frequency ground in a differential configuration is realized, and high-frequency operation is possible. Alternatively, a high gain can be obtained.

In the third embodiment, as shown in FIG. 5, common source FETs 3 _{1 to} 3 _n and common source FETs 43 ₁ to 43 _n are used as the common source amplifying element, and common gate FET 5 and the common gate amplifying element are used. Although the example using the grounded gate FET 45 has been described, as shown in FIG. 6, the grounded emitter BJT 3 _{1 to} 3 _n and the grounded emitter BJT 43 ₁ to 43 _n are used as the grounded source amplifying element, and the grounded base is used as the grounded gate amplifying element. The FET 5 and the common base FET 45 may be used, and the same effect as the variable gain amplifier of FIG. 5 can be obtained.

However, in the variable gain amplifier configured with the BJT of FIG. 6, the base, emitter, and collector of the grounded-emitter BJT 3 _{1 to} 3 _n and grounded-emitter BJT 43 ₁ to 43 _n are the gate, source, and drain of the grounded-source amplification element, respectively. It shall be equivalent to
Further, the base, emitter, and collector of the grounded base BJT 5 and the grounded base FET 45 correspond to the gate, source, and drain of the grounded-gate amplification element, respectively.
As the common-source amplifier element, not limited to the source-grounded _{FET3 1 ~3 n, 43 1 ~43} n and an emitter grounded _{BJT3 1 ~3 n, 43 1 ~43} n, any of the transistor having the common-source For example, other transistors may be used.
The grounded-gate amplification element is not limited to the grounded-gate FETs 5 and 45 and the grounded base BJTs 5 and 45, and other transistors may be used as long as they are grounded-gate transistors.
The gate bias control circuit 14 shown in the second embodiment may be used as the gate bias control circuit 14 in the third embodiment.

Embodiment 4 FIG.
FIG. 7 is a circuit diagram showing a variable gain amplifier according to Embodiment 4 of the present invention. In the figure, the same reference numerals as those in FIG.
The variable gain amplifier according to the fourth embodiment is different from the variable gain amplifier according to the first embodiment in FIG. .

Next, the operation will be described.
Signals input from the input terminal 1 are input to the source grounded FETs 3 _{1 to} 3 _n via the DC cut capacitors 2 ₁ to 2 _n and amplified by the source grounded FETs 3 _{1 to} 3 _n .
The signals amplified by the source grounded FETs 3 _{1 to} 3 _n are input to the foremost gate grounded FET 5 and amplified by the gate grounded FET 5.
The signals amplified by the first-stage common-gate FET 5 are sequentially input to the second-stage common-gate FET 5 and amplified by the second-stage common-gate FET 5.
The signal amplified by the final-stage grounded-gate FET 5 is output from the output terminal 12 via the load inductance 10 (or load resistor 11) and the DC cut capacitor 13.

The variable gain amplifier of FIG. 7 can obtain a high gain by operating as a cascode amplifier in which a plurality of common-source FETs 3 _{1 to} 3 _n and two or more common-gate FETs 5 are cascode-connected.
As described above, the variable gain amplifier of FIG. 7 differs from the variable gain amplifier of FIG. 1 in the first embodiment only in that it has a configuration in which two or more stages of grounded gate FETs 5 are cascode connected. Therefore, the same effect as the variable gain amplifier of FIG. 1 can be obtained.
Also, by arranging a plurality of grounded gate FETs 5 on the output side of the variable gain amplifier, it becomes possible to further suppress the change in output impedance when the gain changes.

FIG. 8 is a graph showing the effect of the variable gain amplifier according to the fourth embodiment of the present invention.
The graph of FIG. 8 shows the change in impedance when the gain of the output impedance of the common source FETs 3 _{1 to} 3 _n , the output impedance of one stage of cascode, and the output impedance of two stages of cascode is variable, in the frequency range of 4.5 GHz to 5.5 GHz. Compare with.
In the figure, A is the calculation result of the source grounded FETs 3 _{1 to} 3 _n , B is the output impedance of one stage of cascode, and C is the output impedance of two stages of cascode.

In the calculation of the output impedance of FIG. 8, for example, an FET having a gate length Lg = 0.13 μm is used as the transistor constituting the variable gain amplifier of FIG.
This is a calculation result of the output impedance when the gain is changed in three stages by switching the gate width of the common-source FETs 3 _{1 to} 3 _n .

As shown in FIG. 8, when the gain attenuation is changed from “High” to “Low” in three steps, the output impedance changes greatly in the common source FETs 3 _{1 to} 3 _n , whereas in one stage of the cascode, As a result, the change in the output impedance is reduced, and it can be seen that the change in the output impedance is almost eliminated by using two stages of cascodes.
This is because the change in impedance is suppressed by the isolation of the common-gate FET 5 arranged downstream of the common-source FETs 3 _{1 to} 3 _n . Further, by providing a plurality of grounded gate FETs 5, the isolation is further increased and the output impedance does not change.
Therefore, the output impedance changes when the gain changes, and the error of the gain variable width and the change of the output saturation characteristic due to the change of the matching state can be reduced.

In the fourth embodiment, as shown in FIG. 7, an example in which the common source FETs 3 _{1 to} 3 _n are used as the common source amplification element and the common gate FET 5 is used as the common gate amplification element has been described. The grounded emitter BJT 3 _{1 to} 3 _n may be used as the amplifying element, and the grounded base BJT 5 may be used as the grounded gate amplifying element, and the same effect as the variable gain amplifier of FIG. 7 can be obtained.
However, in the variable gain amplifier configured by BJT, the base, emitter, and collector of grounded-emitter BJTs 3 _{1 to} 3 _n correspond to the gate, source, and drain of the common-source amplifier, respectively.
The base, emitter, and collector of the common base BJT 5 correspond to the gate, source, and drain of the common-gate amplification element, respectively.

Note that the common-source amplifier is not limited to the common-source FETs 3 _{1 to} 3 _n and the common-emitter BJTs 3 _{1 to} 3 _n , and other transistors may be used as long as they are common-source transistors. .
Further, the grounded gate type amplifying element is not limited to the grounded gate FET 5 and the grounded base BJT 5, and other transistors may be used as long as they are grounded gate type transistors.

Embodiment 5 FIG.
FIG. 9 is a circuit diagram showing a variable gain amplifier according to the fifth embodiment of the present invention. In the figure, the same reference numerals as those in FIG.
The grounded-gate FET 5E is the final-stage grounded-gate amplification element arranged on the most output side.
In the example of FIG. 9, FETs with low breakdown voltage are used for the common gate FET 5 and common source FETs 3 _{1 to} 3 _n, and FETs with high breakdown voltage are used for the common gate FET 5E.

Next, the operation will be described.
Signals input from the input terminal 1 are input to the source grounded FETs 3 _{1 to} 3 _n via the DC cut capacitors 2 ₁ to 2 _n and amplified by the source grounded FETs 3 _{1 to} 3 _n .
The signals amplified by the source grounded FETs 3 _{1 to} 3 _n are input to the foremost gate grounded FET 5 and amplified by the gate grounded FET 5.
The signals amplified by the first-stage common-gate FET 5 are sequentially input to the second-stage common-gate FET 5 and amplified by the second-stage common-gate FET 5.
Finally, the signal amplified by the final-stage grounded-gate FET 5E having a high withstand voltage is output from the output terminal 12 via the load inductance 10 (or the load resistor 11) and the DC cut capacitor 13.

The variable gain amplifier of FIG. 9 operates as a cascode amplifier in which a plurality of common-source FETs 3 _{1 to} 3 _n , one or more common-gate FETs 5, and a final-stage common-gate FET 5 E with high breakdown voltage are connected as cascodes. Gain can be obtained.
The variable gain amplifier of FIG. 9 uses an FET having a high withstand voltage as the final-stage gate-grounded FET 5E arranged on the most output side as compared with the variable gain amplifier of FIG. 7 in the fourth embodiment. Since the difference is only in this point, the same effect as the variable gain amplifier of FIG. 7 can be obtained.

In a variable gain amplifier that is cascode-connected using the common-source FETs 3 _{1 to} 3 _n and two or more stages of common-gate FETs 5 and 5E, low-breakdown-voltage FETs are used as the common-gate FET 5 and common-source FETs 3 _{1 to} 3 _n. By using a high breakdown voltage FET as the final stage grounded FET 5E, the maximum voltage amplitude applied between the drain and source of the final stage grounded FET 5E at the time of saturated output power can be suppressed below the breakdown voltage. As a result, a high-power, high-gain, high-efficiency power amplifier can be realized using an FET whose breakdown voltage is reduced by miniaturization.

In the fifth embodiment, as shown in FIG. 9, an example in which the grounded-gate FET 5E is used as the final-stage grounded-gate amplification element has been described. However, the grounded base BJT 5E is used as the final-stage grounded-gate amplification element. The same effects as those of the variable gain amplifier of FIG. 9 can be obtained.
However, in the variable gain amplifier using the grounded base BJT 5E, the base, the emitter, and the collector of the grounded base BJT 5 correspond to the gate, the source, and the drain of the grounded-gate amplification element, respectively.

Embodiment 6 FIG.
FIG. 10 is a circuit diagram showing a variable gain amplifier composed of an FET according to Embodiment 6 of the present invention. In the figure, the same reference numerals as those in FIGS. Omitted.
In the example of FIG. 10, when the gate-grounded FET 5 having a low breakdown voltage is arranged at the final stage on the output side on the positive phase side of the differential amplifier, the final stage on the output side on the negative phase side of the differential amplifier A gate grounded FET 45 with a low breakdown voltage is disposed.
On the other hand, in the case where the gate grounded FET 5E having a high breakdown voltage is arranged in the final stage on the output side on the positive phase side of the differential amplifier, the gate having a high breakdown voltage is provided on the final stage on the output side on the reverse phase side of the differential amplifier. A ground FET 45E is disposed.

  The variable gain amplifier according to the sixth embodiment is different from the variable gain amplifier of FIGS. 7 and 9 according to the fourth and fifth embodiments only in that the variable gain amplifier has a differential configuration. . Therefore, the operation of the variable gain amplifier according to the sixth embodiment is the same as that of the variable gain amplifier of FIGS. 7 and 9 according to the fourth and fifth embodiments on the positive phase side and the negative phase side of the differential amplifier. Perform the action. Therefore, the same effects as in the fourth and fifth embodiments can be obtained.

Further, since the variable gain amplifier according to the sixth embodiment has a differential configuration, at a location corresponding to each other on the circuit in the differential configuration, when one is positive, the other is always negative, and its amplitude Is ideally the same. Therefore, when the locations corresponding to the differential configuration are connected in common, the midpoint is always 0 potential, that is, a high-frequency virtual ground.
If there is no high-frequency virtual ground, it will be grounded to the actual ground, but to the actual ground, parasitic components (such as the routing line on the chip, the pad on the chip, and the wire to be grounded from the pad) Inductance). When this parasitic component enters between the FETs, the FET gain decreases. When there is a high-frequency virtual ground, the parasitic component is reduced because the ground is closer to the FET than the actual ground, and a decrease in the gain of the FET can be suppressed to a small level. As a result, high frequency operation is possible. Alternatively, a high gain can be obtained.

Furthermore, for example, the other ends of the gate bias feed resistance 56 ₁ ~ 56 _n corresponding gate bias feed resistance 16 ₁ ~ 16 _n are connected to a common connection when the differential configuration, the common connection points Gate bias terminals 15 ₁ to 15 _n for selectively supplying a gate bias are connected, and each connection point is configured as a high frequency virtual ground, or the sources of the common source FETs 43 ₁ to 43 _n are common source FETs 3 _{1 to} 3. It is configured to be grounded to the common ground 4 including the source of _n , or the gate of the common-gate FET 45 is commonly connected to the gate of the common-gate FET 5 and is grounded to the ground 4 through the high-pass capacitor 7. In the layout, the high-frequency ground in the differential configuration is arranged symmetrically around the common connection point. Realizes high frequency operation. Alternatively, a high gain can be obtained.

As described above, according to the sixth embodiment, the function of a differential amplifier can be provided.
Further, with the configuration of the differential amplifier, a high frequency operation is possible due to the virtual ground between the differentials. Alternatively, a high gain can be obtained.
Further, in the layout, by arranging symmetrically around the virtual ground, a high-frequency ground in a differential configuration is realized, and high-frequency operation is possible. Alternatively, a high gain can be obtained.
As the gate bias control circuit 14 of the sixth embodiment, the gate bias control circuit 14 of FIG. 3 in the second embodiment may be used.

Embodiment 7 FIG.
FIG. 11 is a circuit diagram showing a variable gain amplifier composed of an FET according to the seventh embodiment of the present invention. In the figure, the same reference numerals as those in FIG.
The common source FET 3 has a gate connected to the input terminal 1 through the DC cut capacitor 2, a source is grounded to the ground 4, and is a common source amplification element that amplifies a signal input from the input terminal 1.
A gate grounded FET 5 ₁ to 5 _n is connected to the gate bias terminal 65 ₁ to 65 _n gate via the gate bias feed resistance 66 ₁ -66 _n, a common ground via a high-pass capacitor 7 ₁ to _7-n 4 Is connected to the other end of the parallel resistor 63 in the ladder resistor circuit 61, the source is connected to the drain of the common source FET 3, and the grounded gate amplifies the signal amplified by the common source FET 3. Type amplification element.

The ladder resistor circuit 61 includes a plurality of parallel resistors 63 having one end connected to the drain bias terminal 8 and a plurality of series resistors 62 connecting the other ends of the plurality of parallel resistors 63. That is, the plurality of series resistors 62 and the plurality of parallel resistors 63 in the ladder resistor circuit 61 form a ladder-type resistor circuit.
The gate bias control circuit 64 is connected to the gates of the grounded gate FETs 5 _{1 to} 5 _n via the gate bias terminals 65 _{1 to} 65 _n and the gate bias feed resistors 66 _{1 to} 66 _n , and the gate grounded FETs 5 _{1 to} 5 _n . This circuit selectively supplies a gate bias to the gate. That is, the gate bias control circuit 64 generates a gate bias from the gate bias reference voltage input from the gate bias reference voltage input terminal 67, and applies the gate bias according to the gain control signal input from the gain control signal input terminal 68. The gate of any one of the grounded-gate FETs 5 to be supplied is selected, and the gate bias is supplied to the gate of the grounded-gate FET 5.
The gate bias reference voltage input terminal 67 is connected to the drain bias terminal 8, and when the gate bias control circuit 64 generates the gate bias, the gate bias control is performed using the drain bias supplied from the drain bias terminal 8 as the gate bias reference voltage. Output to the circuit 64.
The gain control signal input terminal 68 is a terminal for inputting a gain control signal.

The gate bias circuit 71 is a circuit that generates a gate bias to be supplied to the gate of the common-source FET 3 by using the reference current input from the reference current input terminal 17.
The FET 21 for the current mirror circuit of the gate bias circuit 71 has a gate and a source connected to the reference current input terminal 17, a drain connected to the ground 4, and a constant voltage generated between the gate and the source is a gate bias (reference current source). 18 is a gate bias supply transistor that is supplied to the gate of the common source FET 3 as a gate bias corresponding to a reference current supplied from 18.
The bypass capacitor 23 of the gate bias circuit 71 is connected between the gate of the current mirror circuit FET 21 and the ground 4 and is a member for absorbing an unnecessary high-frequency signal included in the gate bias into the ground 4.

Next, the operation will be described.
A signal input from the input terminal 1 is input to the common source FET 3 via the DC cut capacitor 2 and amplified by the common source FET 3.
Signal amplified by the source grounded FET3 is input to the gate grounded FET 5 ₁ to 5 _n, is amplified by the grounded-gate FET 5 ₁ to 5 _n.
The signals amplified by the common gate FETs 5 _{1 to} 5 _n are output from the output terminal 12 via the ladder resistor circuit 61 and the DC cut capacitor 13.

At this time, the drain bias terminal 8 is supplied with a preset drain bias, and the gate of the common source FET 3 is supplied with an appropriate gate bias preset by the gate bias circuit 71.
Further, the gate of any one of the grounded gate FETs 5 _{1 to} 5 _n is supplied with an appropriate gate bias set in advance (supply of the gate bias in the gate bias control circuit 64). The operation will be described later), and the variable gain amplifier operates as a cascode amplifier.
As described above, the variable gain amplifier operates as a cascode amplifier in which the common-source FET 3 and the plurality of common-gate FETs 5 _{1 to} 5 _n are cascode-connected, so that a high gain can be obtained.
The drain bias terminal 8 is grounded to the ground 4 via the high-pass capacitor 9, and the gates of the gate grounded FETs 5 _{1 to} 5 _n are grounded to the ground 4 via the high-pass capacitors 7 _{1 to} 7 _n. The unnecessary high-frequency signal included is absorbed by the ground 4. As a result, the isolation between the variable gain amplifier and the power source can be increased.

Here, when the gate bias reference voltage is received from the gate bias reference voltage input terminal 67, the gate bias control circuit 64 generates a gate bias from the gate bias reference voltage.
When the gate bias is generated from the gate bias reference voltage, the gate bias control circuit 64 generates a gate bias from the gates of the common-gate FETs 5 _{1 to} 5 _n according to the gain control signal input from the gain control signal input terminal 68. The gate of any one of the grounded-gate FETs 5 that supply a bias is selected, and the gate bias is supplied to the gate of the grounded-gate FET 5.
As described above, the gate bias control circuit 64 selects one gate of the common-gate FET 5 that supplies the gate bias from the gates of the common-gate FETs 5 _{1 to} 5 _n and selectively supplies the gate bias. The gain of the variable gain amplifier can be changed by sequentially switching among the plurality of common-gate FETs 5 _{1 to} 5 _n which is the only common-gate FET 5 that is actually turned on.

In the example of FIG. 11, the output terminal 12 is connected between the drain and the ladder resistor circuit 61 of the gate-grounded FET 5 ₁ via a DC cut capacitor 13.
In this case, among the plurality of the gate-grounded FET 5 ₁ to 5 _n, the common gate FET which only turned on, from the right of the gate grounded FET 5 ₁ to 5 _n to switch sequentially (5 ₁ to 5 _n order) The resistance value of the ladder resistance circuit 61 included in the system of the gate-grounded FET 5 to be switched increases in order.
Therefore, if the gate-grounded FETs 5 _{1 to} 5 _n are switched in order from the right, the resistance value of the ladder resistor circuit 61 increases in order, the output power decreases in order, and the gain decreases in order. This makes it possible to vary the gain of the variable gain amplifier discretely.

As described above, according to the seventh embodiment, the gate bias control circuit 64 selectively supplies the gate bias to the gates of the gate-grounded FETs 5 _{1 to} 5 _n , whereby a plurality of gate grounded FETs 5 _{1 to} 5 _{n are provided.} If the output power is changed by switching the grounded FET 5 to be actually operated and changing the loss due to the ladder resistor circuit 61 between the output terminal 12 and the gain, the gain of the variable gain amplifier is changed as a result. Can be made.
In addition, since the gain is changed on the output side of the common-source FET 3 that is an amplifying element that generates distortion, the gain can be varied without deteriorating the distortion characteristics with the input level fixed.
Further, the output impedance of the variable gain amplifier is dominated by the impedance of the ladder resistor circuit 61 provided between the output terminal 12 and the drain bias terminal 8 grounded in terms of high frequency, and the ladder resistor circuit 61 Since the impedance does not change with respect to the change, the change in the output impedance can be suppressed.
Furthermore, since the variable amount of gain is determined by the resistance values of the series resistor 62 and the parallel resistor 63, it can be set arbitrarily and accurately.

In the seventh embodiment, as shown in FIG. 11, an example is described in which the common-source FET 3 is used as a common-source amplification element and the common-gate FETs 5 _{1 to} 5 _n are used as common-gate amplification elements. 12, the grounded emitter BJT3 may be used as the grounded source type amplifying element, and the grounded base BJTs 5 _{1 to} 5 _n may be used as the grounded gate type amplifying element. Can play.
However, in the variable gain amplifier configured with the BJT of FIG. 12, the base, emitter, and collector of the common-emitter BJT 3 correspond to the gate, source, and drain of the common-source amplifier.
In addition, the base, emitter, and collector of the grounded base BJTs 5 _{1 to} 5 _n correspond to the gate, source, and drain of the grounded-gate amplification element, respectively.

Note that the common-source amplifier is not limited to the common-source FET 3 and common-emitter BJT 3, and other transistors may be used as long as they are common-source transistors.
Further, the grounded gate type amplifying element is not limited to the grounded gate FETs 5 _{1 to} 5 _n and the grounded base BJT 5 _{1 to} 5 _n , and other transistors may be used as long as they are grounded gate type transistors. .

Further, in the seventh embodiment, has been described as connecting the output terminal 12 during the gate-grounded FET 5 ₁ of the drain and the ladder resistor circuit 61, the output terminal 12 is out of the gate-grounded FET 5 ₁ to 5 _n What is necessary is just to connect between any one drain and the ladder resistance circuit 61, and it can select suitably.

Embodiment 8 FIG.
FIG. 13 is a circuit diagram showing a variable gain amplifier composed of an FET according to the eighth embodiment of the present invention. In the figure, the same reference numerals as those in FIG.
The first FET 73 of the gate bias circuit 71 has a gate connected to the gate of the current mirror circuit FET 21 and a source grounded to the ground 4, and forms a current mirror circuit paired with the current mirror circuit FET 21. 1 transistor.
In the second FET 75 of the gate bias circuit 71, the source is connected to the drain of the first FET 73, the drain is connected to the drain bias terminal 8 through the resistor 76, and the gate short-circuited to the drain is the gate bias reference voltage input terminal. 67, and is a second transistor that supplies a voltage generated at the gate to the gate bias control circuit 64 as a gate bias reference voltage.

Next, the operation will be described.
In the seventh embodiment, the drain bias terminal 8 is connected to the gate bias reference voltage input terminal 67 of the gate bias control circuit 64, and the drain bias is applied to the gate bias reference voltage. 8, the connection between the gate bias reference voltage input terminal 67 and the drain bias terminal 8 is eliminated, and instead, the gate bias reference voltage is supplied from the gate bias circuit 71 to the gate bias reference voltage input terminal 67. is there.

That is, when the current bias circuit 71 generates a gate bias according to the reference current supplied from the reference current source 18, the gate bias circuit 71 is a two-stage circuit of FETs composed of the first FET 73 and the second FET 75. Then, a gate bias reference voltage is generated by voltage division by the resistor 76, and the gate bias reference voltage is supplied to the gate bias reference voltage input terminal 67 of the gate bias control circuit 64.
In this way, by generating a gate bias reference voltage by a two-stage circuit of FETs, the temperature characteristics of the variable gain amplifier are obtained by combining the temperature characteristics of the gate grounded FETs 5 _{1 to} 5 _{n and} the temperature characteristics of the gate bias reference voltage. Characteristics can be suppressed.

As described above, according to the eighth embodiment, the gate bias reference voltage is generated by the two-stage circuit composed of the first FET 73 and the second FET 75, so that the first and second gates are generated. If the FETs 73 and 75, the common source FET 3 and the common gate FETs 5 _{1 to} 5 _n are formed of the same type, the temperature characteristics of the common gate FETs 5 _{1 to} 5 _{n and} the temperature characteristics of the source of the gate bias reference voltage are matched. The temperature characteristics of the variable gain amplifier can be suppressed.
Further, by changing the resistance value of the resistor 76, the gate bias of the common-gate FETs 5 _{1 to} 5 _n can be changed. Therefore, if the resistance value of the resistor 76 is set so that the distribution ratio for distributing the drain bias supplied to the variable gain amplifier to the common source FET 3 and the common gate FETs 5 _{1 to} 5 _n is optimized, the variable gain amplifier Output power can be improved.

In the eighth embodiment, as shown in FIG. 13, the common-source FET 3 is used as the common-source amplification element, the common-gate FETs 5 _{1 to} 5 _n are used as the common-gate amplification element, and the gate bias circuit 71 is the FET 21. has been described an example in which using a 73, 75, as shown in FIG. 14, the emitter grounded BJT3 used as a source grounded type amplifier element, using the common base BJT5 ₁ ~5 _n as a gate grounded type amplifier element, the gate The bias circuit 71 may use the BJTs 21, 73, and 75, and the same effect as the variable gain amplifier of FIG. 13 can be obtained.

Embodiment 9 FIG.
In the seventh and eighth embodiments, the ladder resistor circuit 61 in FIGS. 11 to 14 has a plurality of series resistors 62 and a plurality of parallel resistors 63 that form a ladder-type resistor circuit. The resistance values of all the series resistors 62 in the circuit 61 may be set to half of the resistance values of all the parallel resistors 63.

When the resistance value of the series resistor 62 in the ladder resistor circuit 61 is set to a half of the resistance value of the parallel resistor 63, the fluctuation of the output impedance by the ladder resistor circuit 61 when the gate-grounded FETs 5 _{1 to} 5 _n are switched is changed. And the resistance value of the series resistor 62 are set to be equal to each other.
Thereby, as compared with the variable gain amplifiers according to the seventh and eighth embodiments, fluctuations in output impedance when the gain is varied can be further suppressed.

Further, in the ladder resistor circuit 61, if the resistance value of the parallel resistor 63 is set to half the resistance value of the series resistor 62, the loss increases by 6 dB each time the gate-grounded FETs 5 _{1 to} 5 _n are sequentially switched. .
Thereby, in the variable gain amplifier according to the ninth embodiment, a 6 dB step variable gain amplifier can be realized. However, when the variable gain amplifier is realized, there is a possibility that the variable amount of gain may be shifted due to the influence of the parasitic element generated. In that case, the set gain variable amount can be improved with precision by finely adjusting the resistance values of the series resistor 62 and the parallel resistor 63.

As described above, according to the ninth embodiment, in the ladder resistor circuit 61, the resistance value of the series resistor 62 is set to half of the resistance value of the parallel resistor 63, so that the switching between the grounded gate FETs 5 _{1 to} 5 _n Thus, fluctuations in output impedance when the gain of the variable gain amplifier is changed can be suppressed.
In addition, a variable gain amplifier having a step of 6 dB can be realized each time the switching of the gate-grounded FETs 5 _{1 to} 5 _n moves one direction away from the output terminal 12.

Embodiment 10 FIG.
FIG. 15 is a circuit diagram showing a variable gain amplifier composed of an FET according to Embodiment 10 of the present invention. In the figure, the same reference numerals as those in FIG.
In the eighth embodiment, the ladder resistor circuit 61 has a plurality of series resistors 62 and a plurality of parallel resistors 63 that form a ladder-type resistor circuit. However, as shown in FIG. The series resistor 62 in 61 may be divided into two so that each series resistor 62 is composed of a plurality of divided resistors.
In this case, the drains of all the grounded gate FETs 5 _{1 to} 5 _n are not connected to the other end of the parallel resistor 63, but the drains of some of the grounded gate FETs 5 (for example, the drains of the grounded gate FETs 5 ₂ and 5 ₄ ). Is connected to a connection point of two divided resistors constituting the series resistor 62.

Next, the operation will be described.
In the tenth embodiment, as described above, since the series resistor 62 in the ladder resistor circuit 61 is divided into two, the variable amount of gain can be set small.
That is, by dividing the series resistor 62 in the ladder resistor circuit 61 into two, it is possible to set the gain variable width to half that of the variable gain amplifier of FIG. In particular, when the sum of the resistance values of the two divided series resistors 62 is half the resistance value of the parallel resistor 63, in the case of the eighth embodiment, the gain variable amount that was 6 dB steps is changed to 3 dB steps. Can do.

As described above, according to the tenth embodiment, since one series resistor 62 is divided into two in the ladder resistor circuit 61, the gain of the amplifier is changed by switching the gate-grounded FETs 5 _{1 to} 5 _n . Fluctuations in output impedance can be suppressed.
In addition, it is possible to realize a variable gain amplifier that reduces the gain variable amount each time the switching between the grounded gate FETs 5 _{1 to} 5 _n moves one direction away from the output terminal 12.

In the tenth embodiment, as shown in FIG. 15, the common-source FET 3 is used as the common-source amplifier, the common-gate FETs 5 _{1 to} 5 _n are used as the common-gate amplifier, and the gate bias circuit 71 is the FET 21. has been described an example in which using a 73, 75, as shown in FIG. 16, the emitter grounded BJT3 used as a source grounded type amplifier element, using the common base BJT5 ₁ ~5 _n as a gate grounded type amplifier element, the gate The bias circuit 71 may use BJTs 21, 73, and 75, and the same effect as the variable gain amplifier of FIG. 15 can be obtained.
In the tenth embodiment, as shown in FIG. 15, the gate bias reference voltage is applied from the gate bias circuit 71 to the gate bias reference voltage input terminal 67, but as shown in FIG. The bias reference voltage may be directly applied to the gate bias reference voltage input terminal 67 from the drain bias terminal 8.

Embodiment 11 FIG.
FIG. 17 is a circuit diagram showing a variable gain amplifier composed of an FET according to the eleventh embodiment of the present invention. In the figure, the same reference numerals as those in FIG.
In the tenth embodiment, the series resistor 62 in the ladder resistor circuit 61 is divided into two, and each series resistor 62 is composed of a plurality of divided resistors. However, as shown in FIG. The series resistor 62 in the ladder resistor circuit 61 may be divided into six, and the six divided resistors constituting the series resistor 62 may be connected in series between the other ends of the two parallel resistors 63.
In this case, not the drain of all the common gate FET 5 ₁ to 5 _n is connected to the other end of the parallel resistor 63, the drain of a portion of the gate-grounded FET 5 (e.g., the drain of the common gate FET 5 ₂ to 5 ₆₎ Are connected to the connection points of the divided resistors constituting the series resistor 62.

Next, the operation will be described.
In the eleventh embodiment, as described above, since the series resistor 62 in the ladder resistor circuit 61 is divided into six, the variable amount of gain can be set small.
In particular, when the sum of the resistance values of the six divided series resistors 62 is half the resistance value of the parallel resistor 63, in the case of the tenth embodiment, the gain variable amount that was 3 dB steps is changed to 1 dB steps. Can do.

In the tenth and eleventh embodiments, the case where the division number of the series resistor 62 is “2” or “6” has been described. However, a division number other than “2” or “6” may be used. In addition, although the drains of the grounded-gate FETs 5 _{1 to} 5 _n are connected to all connection points between the divided series resistors 62, it is not always necessary to connect to all the connection points. It is possible to realize a variable gain amplifier in which the variable amount of is variable.

As described above, according to Embodiment 11, the ladder resistor circuit 61, since the dividing one series resistor 62 into six, changing the gain of the amplifier by switching the gate-grounded FET 5 ₁ to 5 _n Fluctuations in output impedance can be suppressed.
In addition, it is possible to realize a variable gain amplifier that reduces the gain variable amount each time the switching between the grounded gate FETs 5 _{1 to} 5 _n moves one direction away from the output terminal 12.

In the eleventh embodiment, as shown in FIG. 17, the common-source FET 3 is used as the common-source amplification element, the common-gate FETs 5 _{1 to} 5 _n are used as the common-gate amplification element, and the gate bias circuit 71 is the FET 21. has been described an example in which using a 73, 75, as shown in FIG. 18, the emitter grounded BJT3 used as a source grounded type amplifier element, using the common base BJT5 ₁ ~5 _n as a gate grounded type amplifier element, the gate The bias circuit 71 may use BJTs 21, 73, and 75, and the same effect as the variable gain amplifier of FIG. 17 can be obtained.
In the eleventh embodiment, as shown in FIG. 17, the gate bias reference voltage is supplied from the gate bias circuit 71 to the gate bias reference voltage input terminal 67, but as shown in FIG. The bias reference voltage may be directly applied to the gate bias reference voltage input terminal 67 from the drain bias terminal 8.

Embodiment 12 FIG.
Figure 19 is a circuit diagram showing a gate bias control circuit 64 constituted by FET according to the embodiment 12 of the present invention. In the figure, as FET 82 ₁ to 82 _n switch is corresponding to the gate-grounded FET 5 ₁ to 5 _n And a drain connected to the gate bias reference voltage input terminal 67, a source connected to the gate bias terminals 65 _{1 to} 65 _n, and a switch for supplying the gate bias to the gates of the gate-grounded FETs 5 _{1 to} 5 _n It is a transistor.
The gain control logic circuit 84 is connected to the gain control signal input terminal 68, converts the gain control signal input from the gain control signal input terminal 68 into a gate control signal of the division number n, and gate-controls the gate control signal. Output to signal terminals 85 _{1 to} 85 _n . That is, the gain control logic circuit 84 is a circuit that selects the switching FET 82 that supplies the gate bias to the gates of the common-gate FETs 5 _{1 to} 5 _n among the plurality of switching FETs 82 _{1 to} 82 _n according to the gain control signal.

The gate bias feed resistors 86 _{1 to} 86 _n are resistors connected between the gates of the switching FETs 82 _{1 to} 82 _n and the gate control signal terminals 85 _{1 to} 85 _n .
The switching FETs 87 _{1 to} 87 _n are provided corresponding to the gate grounded FETs 5 _{1 to} 5 _n , the drains are connected to the sources of the switching FETs 82 _{1 to} 82 _n and the gate bias terminals 65 _{1 to} 65 _n, and the sources are ground 4. The transistor is grounded.
Inverters 88 _{1 to} 88 _n have anodes connected to gate control signal terminals 85 _{1 to} 85 _n and cathodes connected to gates of switching FETs 87 _{1 to} 87 _n via gate control signal feed resistors 89 _{1 to} 89 _n. Yes.

Next, the operation will be described.
The gain control logic circuit 84 receives a gain control signal from the gain control signal input terminal 68. The gain control logic circuit 24 converts the input gain control signal into a gate control signal of the division number n, and the gate control The signal is output to the gate control signal terminals 85 _{1 to} 85 _n .
One gate bias terminal 65 for supplying a gate bias is determined from the gate bias terminals 65 _{1 to} 65 _n by the gate control signals output from these gate control signal terminals 85 _{1 to} 85 _n .
For example, when the gate control signal output from the gate control signal terminal 85 ₁ is at “H” level, the “H” level is supplied to the gate of the switching FET 82 ₁ via the gate bias feed resistor 86 _1, thereby The FET 82 ₁ is turned on.
Also, being "L" level is supplied to the gate of the switching FET87 ₁ through the inverter 88 ₁ and a gate control signal feed resistors 89 _1, FET87 ₁ is turned off switch.
Accordingly, the gate bias is supplied to the gate bias terminal 65 _1.

Conversely, when the gate control signal output from the gate control signal terminal 85 ₁ is at “L” level, the “L” level is supplied to the gates of the switching FETs 82 _{1 to} 22 _n via the gate bias feed resistor 86 _1. Thus, the switching FET 82 ₁ is turned off.
Also, being "H" level is supplied to the gate of the switching FET87 ₁ through the inverter 88 ₁ and a gate control signal feed resistors 89 _1, FET87 ₁ is turned on switch.
Thereby, since the gate bias terminal 65 ₁ is grounded to the ground 4, the gate bias is not supplied to the gate bias terminal 65 ₁ .
As described above, the gate bias can be selectively supplied to the gates of the common-gate FETs 5 _{1 to} 5 _n by appropriately controlling the level of the gate control signal.

As described above, according to the twelfth embodiment, the gain control logic circuit 84 that converts the gain control signal input to the gate bias control circuit 64 into the gate control signal supplied to the switching FETs 82 _{1 to} 82 _n is provided. As a result, the number of input terminals of the gate bias control circuit 64 can be reduced from the number of the common gate FETs 5 _{1 to} 5 _{n to} the number of input terminals of the gain control signal.

In the twelfth embodiment, the switching FETs 82 _{1 to} 82 _n and 87 _{1 to} 87 _n are provided corresponding to the gate grounding FETs 5 _{1 to} 5 _n . However, as shown in FIG. Switching BJTs 82 _{1 to} 82 _n and 87 _{1 to} 87 _n may be provided corresponding to the FETs 5 _{1 to} 5 _n , and the same effect as the gate bias control circuit 14 of FIG. 19 can be obtained.
However, when the gate bias control circuit 84 is configured by replacing the FET with BJT as shown in FIG. 20, the gate is replaced with the base, the source is replaced with the emitter, and the drain is replaced with the collector.

In the twelfth embodiment, the gain control logic circuit 84 that converts the input gain control signal into the gate control signal of the division number n and outputs the gate control signal to the gate control signal terminals 85 _{1 to} 85 _n is provided. Although provided, the gain control logic circuit 84 may be eliminated, and the gate control signal may be directly input to the gate control signal terminals 85 _{1 to} 85 _n . In this case, the circuit configuration can be simplified by eliminating the gain control logic circuit 84.

Embodiment 13 FIG.
FIG. 21 is a circuit diagram showing a variable gain amplifier composed of an FET according to the thirteenth embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 5 and FIG.
The variable gain amplifier of FIG. 21 constitutes a differential amplifier, and the common-source FET 3 on the positive phase side of the differential amplifier is a first common-source amplifier, and the source on the negative phase side of the differential amplifier. The ground FET 43 is a second source grounded type amplifying element.
The source grounded FET 43 has a gate connected to the differential negative phase input terminal 41 via the DC cut capacitor 42 and is connected to the gate bias circuit 71 via the gate bias feed resistor 56, and the source is grounded to the ground 4. The signal input from the differential negative phase input terminal 41 is amplified.

The common-gate FETs 5 _{1 to} 5 _n on the positive phase side of the differential amplifier are first gate-grounded amplifying elements, and the common-gate FETs 45 _{1 to} 45 _n on the negative phase side of the differential amplifier are second grounded gates. Type amplification element.
A gate grounded FET 45 ₁ to 45 _n is connected to the gate bias terminal 65 ₁ to 65 _n gate via the gate bias feed resistance 106 ₁ - 106 _n, a common ground via a high-pass capacitor 97 ₁ to 97 _n 4 Is connected to the other end of the parallel resistor 103 in the ladder resistor circuit 101, the source is connected to the drain of the common source FET 43, and the gate is grounded to amplify the signal amplified by the common source FET 43. Type amplification element.

The ladder resistor circuit 61 on the positive phase side of the differential amplifier is a first ladder resistor circuit, and the ladder resistor circuit 101 on the opposite phase side of the differential amplifier is a second ladder resistor circuit.
The ladder resistor circuit 101 has a plurality of parallel resistors 103 having one end connected to the drain bias terminal 8 and a plurality of series resistors 1022 connecting the other ends of the plurality of parallel resistors 103. That is, the plurality of series resistors 102 and the plurality of parallel resistors 103 in the ladder resistor circuit 101 form a ladder shape.

The gate bias control circuit 64 is connected to the gate of the gate-grounded _{FET5 1 ~5 n, 45 1 ~45} n through the gate bias terminal 65 ₁ to 65 _n and the gate bias feed resistance _{66 1 ~66 n, 106 1 ~106} n In this circuit, the gate bias is selectively supplied to the gates of the gate-grounded FETs 5 _{1 to} 5 _n and 45 _{1 to} 45 _n . That is, the gate bias control circuit 64 generates a gate bias from the gate bias reference voltage input from the gate bias reference voltage input terminal 67, and in accordance with the gain control signal input from the gain control signal input terminal 68, the gate grounded FET 5 _{1 to} 5 _n and the gate grounded FETs 45 _{1 to} 45 _n , the gates of any one of the gate grounded FETs 5 and 45 that supply the gate bias are selected, and the gate biases of the gate grounded FETs 5 and 45 are selected. Supply to the gate.

Next, the operation will be described.
The variable gain amplifier according to the thirteenth embodiment is different from the variable gain amplifier according to the eighth embodiment only in that the variable gain amplifier has a differential configuration. Therefore, the operation of the variable gain amplifier according to the thirteenth embodiment performs the same operation as that of the variable gain amplifier according to the eighth embodiment on the positive phase side and the negative phase side of the differential amplifier. Therefore, the same effect as in the eighth embodiment can be obtained.

Further, since the variable gain amplifier according to the thirteenth embodiment has a differential configuration, in a location corresponding to each other on the circuit in the differential configuration, when one is positive, the other is always negative, and its amplitude Is ideally the same. Therefore, when the locations corresponding to the differential configuration are connected in common, the midpoint is always 0 potential, that is, a high-frequency virtual ground.
If there is no high-frequency virtual ground, it will be grounded to the actual ground, but to the actual ground, parasitic components (such as the routing line on the chip, the pad on the chip, and the wire to be grounded from the pad) Inductance). When this parasitic component enters between the FETs, the FET gain decreases. When there is a high-frequency virtual ground, the parasitic component is reduced because the ground is closer to the FET than the actual ground, and a decrease in the gain of the FET can be suppressed to a small level. As a result, high frequency operation is possible. Alternatively, a high gain can be obtained.

Furthermore, for example, the other ends of the gate bias feed resistance 106 ₁ - 106 _n of the corresponding gate bias feed resistance 66 ₁ -66 _n are connected in common when a differential configuration, the common connection points Gate bias terminals 65 _{1 to} 65 _n for selectively supplying a gate bias are connected, and each connection point is configured as a high-frequency virtual ground, or the ground 4 common to the source of the common-source FET 43 is connected to the source of the common-source FET 3. The other end of the gate bias feed resistor 16 and the other end of the gate bias feed resistor 56 are connected in common, and the connection point is configured as a high-frequency virtual ground, or the gate grounded FET 5 with the gates of ₁ to 5 _n is via a high-pass capacitor 7 ₁ to _7-n, the gate grounded FET 45 ₁ to 45 _n each gate of Are connected in common through the high-pass capacitor 97 ₁ to 97 _n, by configured to be grounded 4, and arranged symmetrically about a common connection point also in the layout, when a differential configuration High-frequency ground is realized, and high-frequency operation becomes possible. Alternatively, a high gain can be obtained.

As described above, according to the thirteenth embodiment, the function of a differential amplifier can be provided.
Further, with the configuration of the differential amplifier, a high frequency operation is possible due to the virtual ground between the differentials. Alternatively, a high gain can be obtained.
Further, in the layout, by arranging symmetrically around the virtual ground, a high-frequency ground in a differential configuration is realized, and high-frequency operation is possible. Alternatively, a high gain can be obtained.

In the thirteenth embodiment, as shown in FIG. 21, the common-source FET 3 and the common-source FET 43 are used as the common-source amplifier, and the common-gate FETs 5 _{1 to} 5 _n and the common-gate FET 45 ₁ are used as the common gate amplifier. Having described the example of using a to 45 _n, as shown in FIG. 22, a grounded emitter BJT3 and emitter grounded BJT43 used as a source grounded type amplifier element, the base ground FET 5 ₁ to 5 _n and the base ground as a gate grounded type amplifier element FETs 45 _{1 to} 45 _n may be used, and the same effect as the variable gain amplifier of FIG. 21 can be obtained.

However, in the variable gain amplifier configured with the BJT of FIG. 22, the base, emitter, and collector of the grounded-emitter BJT3 and grounded-emitter BJT43 correspond to the gate, source, and drain of the grounded-source amplifier, respectively.
Further, the base, emitter and collector of the grounded base BJTs 5 _{1 to} 5 _n and the grounded base FETs 45 _{1 to} 45 _n correspond to the gate, source and drain of the grounded-gate amplification element, respectively.
Note that the common-source amplifier is not limited to the common-source FETs 3 and 43 and the common-emitter BJTs 3 and 43, and other transistors may be used as long as they are common-source transistors.
The grounded-gate amplification element is not limited to the grounded-gate FETs 5 _{1 to} 5 _n and 45 _{1 to} 45 _n and the grounded base BJTs 5 _{1 to} 5 _n and 45 _{1 to} 45 _n. For example, other transistors may be used.
In the thirteenth embodiment, the differential configuration is applied to the configuration shown in FIG. 13. However, the differential configuration may be applied to the configurations shown in FIGS. 11, 15, and 17. .

1 input terminal, 2 _{1 to} 2 _n , 13, 42, 42 _{1 to} 42 _n , 53 DC cut capacitor, 3, 3 _{1 to} 3 _n source grounded FET (source grounded type amplifying element, first source grounded type amplifying element) ), 43, 43 ₁ ~ 43 _n source grounded FET (second common-source amplifier element), 4 ground, 5,5 ₁ to 5 _n, 5E grounded gate FET (common-gate amplifier element, a first gate grounded Type amplifying element), 45, 45 _{1 to} 45 _n , 45E Common gate FET (second grounded amplifying element), 6 gate terminal, 7, 9, 23, 97 _{1 to} 97 _n high pass capacitor, 8 drain bias terminal 10 load inductor (output load circuit, first output load circuit), 11 load resistance (output load circuit, first output load circuit), 50 load inductor (second output load circuit), 51 load resistance (first 2 Output load circuit), 12 an output terminal, 14 a gate bias control _{circuit, 15 1 ~15 n, 65 1} ~65 n gate bias _{terminal, 16 1 ~16 n, 26 1} ~26 n, 56 1 ~56 n, 66 1 ˜66 _n , 86 ₁ ˜86 _n , 106 ₁ ˜106 _n gate bias feed resistor, 17 reference current input terminal, 18 reference current source, 19, 68 gain control signal input terminal, 21 FET for current mirror circuit (reference current input Transistor), 22 _{1 to} 22 _n switch FET (switch transistor), 27 _{1 to} 27 _n , 87 _{1 to} 87 _n switch FET, 82 _{1 to} 82 _n switch FET (switch transistor), 24, 84 Gain control logic circuit, 25 _{1 to} 25 _n , 85 _{1 to} 85 _n gate control signal terminal, 28 _{1 to} 28 _n , 88 _{1 to} 88 _n inverter, 29 _{1 to} 29 _n , 89 _{1 to} 89 _n Gate control signal feed resistor, 31 differential positive phase input terminal, 32 differential positive phase output terminal, 41 differential negative phase input terminal, 52 differential negative phase output terminal, 61 ladder resistance circuit (first Ladder resistance circuit), 101 ladder resistance circuit (second ladder resistance circuit), 62, 102 series resistance, 63, 103 parallel resistance, 64 gate bias control circuit, 67 gate bias reference voltage input terminal, 71 gate bias circuit, 73 First FET (first transistor), 75 Second FET (second transistor), 76 resistor.

Claims (5)

A gate to which a gate bias is supplied is connected to an input terminal, a source is connected to the ground, and a common source amplifying element that amplifies a signal input from the input terminal;
A ladder resistor circuit having a plurality of parallel resistors to which a drain bias is applied from one end and having a plurality of series resistors connecting the other ends of the plurality of parallel resistors;
A gate to which a gate bias is supplied is grounded in terms of high frequency, a drain is connected to the other end of each parallel resistor in the ladder resistor circuit, a source is connected to a drain of the source grounded amplifying element, and the source grounded A plurality of grounded-gate amplification elements that amplify signals amplified by the type amplification elements;
An output terminal connected to one of the drains of the plurality of common-gate amplification elements;
A gate bias control circuit connected to the gates of the plurality of grounded-gate amplification elements and selectively supplying a gate bias to the gates of the plurality of grounded-gate amplification elements;
A gate bias circuit for supplying a gate bias to the gate of the common-source amplifier,
The gate bias circuit is paired with a gate bias supply transistor for supplying a gate bias corresponding to a reference current supplied from a reference current source to the gate of the common-source amplifier, and the gate bias supply transistor. The first transistor constituting the current mirror circuit, the source is connected to the drain of the first transistor, the drain to which the drain bias is supplied is short-circuited to the gate, and the voltage generated at the gate is the gate bias. And a second transistor that supplies the gate bias control circuit as a reference voltage,
The variable gain amplifier according to claim 1, wherein the first transistor and the second transistor, and the common-source amplifier and the common-gate amplifier are configured of the same type.   2. The variable gain amplifier according to claim 1, wherein the resistance value of the series resistor in the ladder resistor circuit is set to half of the resistance value of the parallel resistor.   The series resistance in the ladder resistor circuit is divided, and the series resistance is composed of a plurality of divided resistors, and one of the drains of the plurality of common-gate amplifiers is not the other end of the parallel resistor but the plurality of divided resistors. 2. The variable gain amplifier according to claim 1, wherein the variable gain amplifier is connected to a connection point of a resistor. The gate to which the gate bias is supplied is connected to the positive phase input terminal, the source is connected to the ground, and the first source grounding amplifies the positive phase side signal of the differential signal input from the positive phase input terminal. A type amplifying element;
A first ladder resistor circuit having a plurality of parallel resistors to which a drain bias is applied from one end and having a plurality of series resistors connecting the other ends of the plurality of parallel resistors;
A gate to which a gate bias is supplied is grounded at a high frequency, a drain is connected to the other end of each parallel resistor in the first ladder resistor circuit, and a source is connected to a drain of the first source grounded amplification element. A plurality of first grounded-gate amplification elements that amplify the signal amplified by the first common-source amplification element;
A positive-phase output terminal of a differential signal connected to one of the drains of the plurality of first grounded-gate amplification elements;
The gate to which the gate bias is supplied is connected to the negative phase input terminal, the source is connected to the ground, and the second source grounding amplifies the negative phase side signal of the differential signal input from the negative phase input terminal. A type amplifying element;
A second ladder resistor circuit having a plurality of parallel resistors to which a drain bias is applied from one end and having a plurality of series resistors connecting the other ends of the plurality of parallel resistors;
A gate to which a gate bias is supplied is grounded in terms of high frequency, a drain is connected to the other end of each parallel resistor in the second ladder resistor circuit, and a source is connected to a drain of the second source grounded amplification element. A plurality of second grounded-gate amplification elements for amplifying the signal amplified by the second common-source amplification element;
A differential signal negative-phase output terminal connected to the drain of any of the plurality of second gate-grounded amplification elements;
A gate that is connected to the gates of the plurality of first and second grounded-gate amplification elements and selectively supplies a gate bias to the gates of the plurality of first and second common-gate amplification elements. A bias control circuit;
A gate bias circuit for supplying a gate bias to the gates of the first and second common-source amplifiers,
The gate bias circuit includes a gate bias supply transistor that supplies a gate bias corresponding to a reference current supplied from a reference current source to the gates of the first and second common-source amplifiers, and the gate bias supply transistor. A first transistor that forms a current mirror circuit paired with a transistor, a source is connected to the drain of the first transistor, and a drain to which a drain bias is supplied is short-circuited to the gate, and is generated at the gate And a second transistor for supplying the gate bias control circuit with the voltage to be used as a gate bias reference voltage,
The first transistor and the second transistor, the first source grounded amplification device and the first gate grounded amplification device, the second source grounded amplification device and the second gate grounded device. A variable gain amplifier, characterized in that the type amplifying element is of the same type.   The variable gain amplifier according to any one of claims 1 to 4, wherein the common-source amplifier and the common-gate amplifier are FETs or BJTs.

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