JPH08172331A - Agc circuit - Google Patents

Abstract

PURPOSE: To stabilize this AGC circuit by reducing the dispersion of AGC characteristics even when the transistor (TR) DC amplification factor of a cascode amplifier is changed. CONSTITUTION: The cascode amplifier 21 is constituted of respectively connecting 1st and 2nd TRs Q11, Q12 to the input side and the output side. A serial circuit between the collector and emitter of diode-connected 3rd and 4th TRs Q13, Q14 is connected between the base of the 2nd TR Q12 and the ground. A constant current source 23 and the collector of a 5th TR Q15 are connected to the base of the 2nd TR Q12. An AGC signal VAGC is supplied to the base of the 5th TR Q15 to control the amount of a current flowing from the constant current source 23 to the base of the 2nd TR Q12. The gain of the cascode amplifier 21 is controlled by controlling the base current and AGC is stabilized.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to an AGC circuit of a receiver.

[0002]

2. Description of the Related Art A superheterodyne receiver is
For example, it is configured as shown in FIG. That is,
In FIG. 3, a broadcast wave signal from a broadcasting station is supplied from a terminal 1 to a frequency converter 3 through a high frequency amplifier 2 and frequency-converted into an intermediate frequency signal having a predetermined intermediate frequency. Then, the intermediate frequency signal is supplied to the detection circuit 5 through the intermediate frequency amplifier 4 to demodulate the audio signal, and the audio signal is taken out to the terminal 6.

At this time, the detection output of the detection circuit 5 is supplied to the AGC voltage forming circuit 7 and the AGC voltage V whose level changes in accordance with the reception level of the broadcast wave signal at the terminal 1.
AGC is formed. Then, this AGC voltage VAGC is supplied to the high-frequency amplifier 2 and the intermediate-frequency amplifier 4 as a control signal for their gain, and AGC is performed.

FIG. 4 shows a specific example of the high frequency amplifier 2 in which AGC is taken into consideration. The transistors Q11 and Q12 are cascode-connected, and the tuning circuit 22 is connected as the load. A constant current source 23 is connected to the base of the transistor Q12, and diode-connected transistors Q13 and Q are connected between the base and the ground.
14 are connected in series. Further, between the base of the transistor Q12 and the ground, the collector and the emitter of the transistor Q15 are connected for AGC control, and the AGC voltage VAGC is supplied to the base.

Therefore, since the output current of the constant current source 23 flows through the series circuit of the transistors Q13 and Q14,
A voltage drop V13 is generated in this series circuit, and this voltage V13 is supplied to the base of the transistor Q12 as its bias voltage.

Therefore, since the transistors Q11 and Q12 operate as a cascode amplifier, when the broadcast wave signal is supplied to the terminal 1, this is amplified by the transistors Q11 and Q12 and supplied to the frequency converter 3.

Then, in this case, AGC is performed as follows. That is, although the collector current of the transistor Q15 changes depending on the AGC voltage VAGC, IAGC is the collector current of the transistor Q15. That is,
AGC current I12: collector current of transistor Q12 (and Q11) I13: current flowing through transistors Q13 and Q14 I23: output current of constant current source 23 hFE: DC current amplification factor of transistors Q11 to Q14, I23 = I12 / hFE + I13 + IAGC ... (1).

Therefore, by modifying the equation (1), I12 = hFE × (I23-I13-IAGC) (2) or I13 = I23-I12 / hFE-IAGC (3) is there.

The AGC voltage VAGC is small, and
When the C current IAGC is smaller than the predetermined value ITH, that is, when IAGC <ITH, I13> 0 (4) can be set in the equation (3).

In this case, even if the AGC voltage VAGC changes, within the range in which the equation (4) is satisfied, the voltage drop V1
3 is almost constant, and this voltage V13 biases the transistor Q12.

Therefore, as indicated by the solid line in FIG.
If AGC <ITH, then transistor Q12 (and Q1
The collector current I12 of 1) is also almost constant, and as a result,
The gains of the transistors Q11 and Q12 are also substantially constant.

However, the AGC voltage VAGC becomes large,
When IAGC ≧ ITH, the equation (3) is I13 = 0, so the equation (2) is I12 = hFE × (I23-IAGC) (5).

Therefore, as shown by the solid line in FIG.
When AGC ≧ ITH, the transistor Q12 (and Q1
The collector current I12 of 1) decreases as the AGC current IAGC increases, and as a result, the gains of the transistors Q11 and Q12 also decrease as the AGC current IAGC increases.

Therefore, the high frequency amplifier 2 in FIG. 4 operates as an AGC amplifier and can perform AGC. It is also possible to perform a delay AGC in which the value ITH has a threshold level.

[0015]

By the way, the AG of FIG.
In the C circuit, as described above, when IAGC ≧ ITH, the collector current I of the transistor Q12 (and Q11) is
12 is expressed by equation (5).

Therefore, if the DC current amplification factor hFE of the transistors Q11 to Q14 varies, the collector current I12 varies as shown by the broken line in FIG. 5, resulting in variation in AGC characteristics.

In particular, when the delay AGC is used, the value ITH of the AGC current IAGC when I13 = 0 in the equation (3) varies, so that the start level of the delayed AGC operation also varies. If the start level of the delayed AGC operation varies to the low level side, the gain becomes insufficient, so the S / N deteriorates, and if it varies to the high level side, the gain becomes excessive, resulting in distortion.

The present invention is intended to solve the above problems.

[0019]

Therefore, in the present invention, when the reference numerals of the respective parts correspond to the embodiments described later, the first transistor Q11 is the input side and the second transistor Q12 is the output side. The cascode amplifier 21 is configured and is a diode-connected third transistor Q13.
And a series circuit between the collector and the emitter of the fourth transistor Q14 are connected between the base of the second transistor Q12 and the ground, and the constant current source 23 and the first current source 23 are connected to the base of the second transistor Q12. 5 is connected to the collector of the transistor Q15, and the base of the fifth transistor Q15 is A
The magnitude of the current flowing from the constant current source 23 to the base of the second transistor Q12 is controlled by being supplied with the GC signal VAGC, and the cascode amplifier 21 is controlled by controlling this base current.
Is controlled so that AGC is performed.

[0020]

The variation of the collector current I12 of the transistors Q11 and Q12 is suppressed according to the direct current amplification factor hFE.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, transistors Q11 and Q12 constitute a cascode amplifier 21.
The base of 11 is connected to terminal 1 through capacitor C11, its emitter is grounded, and its collector is connected to the emitter of transistor Q12. The base of the transistor Q12 is grounded through the capacitor C12, the tuning circuit 22 is connected between the collector of the transistor Q12 and the power supply terminal 8, and the collector of the transistor Q12 is connected to the frequency converter 3 of the next stage.

The transistor Q11 constitutes the current mirror circuit 24 together with the transistors Q21 and Q22 with the ground being the reference potential point.
The emitter of 21 is grounded, a constant current source 25 is connected between its collector and the power supply terminal 8, and its collector is connected to the base of the transistor Q22. The collector of the transistor Q22 is connected to the terminal 8, and the emitter of the transistor Q22 is connected to the bases of the transistors Q11 and Q21 through the resistors R11 and R13.

Further, a constant current source 23 is connected between the terminal 8 and the base of the transistor Q12, the base of which is connected to the collector of the transistor Q14 through a diode-connected transistor Q13, and the emitter of the transistor Q14 is grounded. It

In this case, the transistor Q14, together with the transistors Q11, Q21 and Q22, together with the current mirror circuit 2
4 of which the base is connected to the emitter of a transistor Q22 through a resistor R12.

Further, three diodes (diode-connected transistors) D11 to D13 are connected in series between the base of the transistor Q12 and the ground, and A
The collector and emitter of the transistor Q15 for controlling GC are connected, and the AGC voltage VAGC is supplied to the base thereof. The junction area between the base and emitter of the transistors Q11, Q12 is the same as that of the other transistors Q13, Q14, Q21,
It is n times (n ≧ 1) that of Q22.

According to this structure, the current mirror circuit 24 supplies the base bias currents of the transistors Q11 and Q14.

When the output current of the constant current source 23 flows through the series circuit of the diodes D11 to D13, a drop voltage V11 is generated in this series circuit, and this voltage V11 is applied to the base of the transistor Q12 as its bias voltage. Supplied.

Therefore, since the transistors Q11 and Q12 operate as the cascode amplifier 21, when the broadcast wave signal is supplied to the terminal 1, the transistors Q11 and Q12 operate.
And is supplied to the frequency converter 3.

Then, in this case, AGC is performed as follows. That is, although the collector current of the transistor Q15 changes depending on the AGC voltage VAGC, IAGC: collector current of the transistor Q15. That is,
AGC current I12: collector current of transistor Q12 (and Q11) I13: current flowing through transistors Q13 and Q14 I23: output current of constant current source 23 I11: current flowing through diodes D11 to D13 hFE: DC current amplification of transistors Q11 to Q22 Assuming that the ratio is I23 = I12 / hFE + I13 + I11 + IAGC ... (11) I12 = n.I13 (12), the equation (12) is substituted into the equation (11) to obtain I23 = I12 / hFE + I12 / n + I11 + IAGC ... (13)

Therefore, by modifying the equation (13), I12 = k × (I23-I11-IAGC) (14) k = nhFE / (n + hFE) or I11 = I23-I12 / k -IAGC ... (15).

When the AGC voltage VAGC is small,
When the C current IAGC is smaller than the predetermined value ITH, that is, when IAGC <ITH, I11> 0 (16) can be set in the equation (15).

In this case, even if the AGC voltage VAGC changes, the voltage drop V
11 is almost constant, and this voltage V11 biases the transistor Q12.

Therefore, as indicated by the solid line in FIG.
If AGC <ITH, then transistor Q12 (and Q1
The collector current I12 of 1) is also almost constant, and as a result,
The gains of the transistors Q11 and Q12 are also substantially constant.

However, the AGC voltage VAGC becomes large,
When IAGC ≧ ITH, the equation (15) becomes I11 = 0, so the equation (14) becomes I12 = k × (I23−IAGC) (17).

Therefore, as indicated by the solid line in FIG.
When AGC ≧ ITH, the transistor Q12 (and Q1
The collector current I12 of 1) decreases as the AGC current IAGC increases, and as a result, the gains of the transistors Q11 and Q12 also decrease as the AGC current IAGC increases.

Therefore, the high frequency amplifier 2 of FIG.
Operates as an AGC amplifier and can perform AGC. It is also possible to perform a delay AGC in which the value ITH has a threshold level.

In this case, in equation (17), the value k
(17) is rewritten as follows: I12 = nhFE / (n + hFE) × (I23-IAGC) (18) Further, when the expression (5) is re-posted, I12 = hFE * (I23-IAGC) (5).

Comparing these equations (18) and (5), the collector current I12 in equation (18) is n / (n + hFE) times the collector current I12 in equation (5). There is. Therefore, even if the DC current amplification factor hFE of the transistors Q11 to Q22 varies, the variation of the collector current I12 of the transistor Q12 is n / (n + hFE) times that of the high frequency amplifier 2 of FIG. ) <1, it is possible to suppress variations in the collector current I12 more than in the case of the high frequency amplifier 2 of FIG.

For example, the direct current amplification factor hFE has a typical value of 10
If it varies in the range of 50 to 200 with respect to 0, in the equation (5), the collector current I12 varies in the range of 1/2 to 2 times, and the range of the variation is the minimum value (= 1/2). 4 times)
Double. However, in the equation (18), when n = 5, the range of variation of the collector current I12 is 0.95 to 1.02.
It is double, and it is only in the range of 1.07 times the minimum value (= 0.95 times). That is, in the equation (5), the range of variation is 400%, whereas in the equation (18), it is only 7%.

Further, as is clear from the equation (18), the value n
The smaller the value of, the more the variation of the collector current I12 can be suppressed.

Thus, the AGC of the high frequency amplifier 2 of FIG.
According to the circuit, the direct current amplification factor hFE of the transistor Q12
Even if there is a variation, the variation in the collector current I12 can be suppressed, and thus the variation in the AGC characteristic can be suppressed. Further, for the same reason, it is possible to suppress the fluctuation of the AGC characteristic due to the temperature change.

Further, even when the delay AGC is used, it is possible to suppress variations in the start level of the delay AGC operation, and therefore it is possible to prevent deterioration of S / N and occurrence of distortion. It is also suitable for IC.

In the example shown in FIG. 2, when the current I11 when IAGC <ITH is used effectively,
Indicates a constant voltage circuit. And from this constant voltage circuit 9
Constant voltage of about 1.3V, that is, twice the forward drop voltage between the base and emitter of the transistor (diode D1
2. A constant voltage V9 having a value of (D13 drop voltage) is taken out, and this voltage V9 is supplied to each circuit as an operating voltage or a reference voltage although not shown.

Then, instead of connecting the diodes D11 to D13 in FIG. 1, the base of the transistor Q12 is connected to the output terminal of the constant voltage circuit 9 through the diode-connected transistor Q19.

Further, by the transistors Q15 and Q16,
The current mirror circuit 26 is configured with the ground as a reference potential point, the AGC voltage VAGC from the AGC voltage forming circuit 7 is supplied to the transistor Q16, and the transistors Q15 to A
The GC current IAGC is taken out.

According to such a configuration, when IAGC <ITH, the current I11 flows through the transistor Q15 and a drop voltage is generated in the transistor Q19.
The sum of the output voltage V9 of the constant voltage circuit 9 becomes the bias voltage V11 and is supplied to the base of the transistor Q12.

In this case, the current I11 flows to the load (not shown) of the constant voltage circuit 9 through the transistor Q19, that is, a part of the output current of the constant voltage circuit 9 is supplemented, so The output current of the voltage circuit 9 becomes small. Therefore, the current I11 is effectively used and power saving is performed.

As described above, the smaller the value n is, the smaller the variation of the collector current I12 can be. However, the smaller the value n is, the larger the currents I23 and I11 are. The circuit is more efficient.

[0049]

According to the present invention, even if the DC current amplification factor hFE of the transistor Q12 varies, it is possible to suppress the variation of the collector current I12 of the transistor Q12.
It is possible to suppress variations in C characteristics. Further, it is possible to suppress the fluctuation of the AGC characteristic due to the temperature change.

Further, even when the delay AGC is used, it is possible to suppress variations in the start level of the delay AGC operation, and therefore it is possible to prevent deterioration of S / N and occurrence of distortion. It is also suitable for IC. Moreover, it is possible to save power.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an example of the present invention.

FIG. 2 is a connection diagram showing another example of the present invention.

FIG. 3 is a system diagram showing an example of a reception system.

FIG. 4 is a connection diagram for explaining the present invention.

FIG. 5 is a characteristic diagram showing AGC characteristics.

[Explanation of symbols]

 1 Input Terminal 2 High Frequency Amplifier 3 Frequency Converter 7 AGC Voltage Forming Circuit 21 Cascode Amplifier 24 Current Mirror Circuit

Claims (4)

[Claims] 1. A cascode amplifier is configured with a first transistor as an input side and a second transistor as an output side, and a diode-connected third transistor and a collector-emitter series connection of a fourth transistor are connected in series. A circuit is connected between the base of the second transistor and the ground, and a constant current source and a fifth current source are connected to the base of the second transistor.
Is connected to the collector of the transistor, and the AGC signal is supplied to the base of the fifth transistor to control the magnitude of the current flowing from the constant current source to the base of the second transistor. An AGC circuit in which the gain of the cascode amplifier is controlled by the AGC circuit. 2. The AGC circuit according to claim 1, wherein the junction area between the base and the emitter of the first and second transistors is n times that of the third and fourth transistors (n ≧ 1). ) The AGC circuit. 3. The AGC according to claim 1 or claim 2.
In the circuit, an AGC circuit in which three elements having diode characteristics are connected in series between the base of the second transistor and the ground. 4. The AGC according to claim 1 or 2.
In the circuit, an AGC circuit in which the base of the second transistor is connected to the output terminal of the constant voltage circuit through an element having a diode characteristic.