JP2013231991A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device which prevents breakage of a circuit due to electrostatic discharge, in an etching process.SOLUTION: The display device includes a first conductive layer in which a first signal line that extends within a frame area and a display area and a second signal line that is adjacent to the first signal line and extends within the frame area are formed; an insulating layer which is disposed on the first conductive layer; a second conductive layer which is disposed on the insulating layer and in which a ground wire crossing the first signal line and the second signal line in a plan view is formed; a semiconductor layer which is disposed between the insulating layer and the second conductive layer and in which a first semiconductor film and a second semiconductor film are formed separated from each other; and a protection diode. The first semiconductor film overlaps, in a plan view, a region where the first signal line crosses the ground wire; and the second semiconductor film overlaps, in a plan view, a region where the second signal line intersects the ground wire.

Description

  The present invention relates to a display device.

  For example, in a display device such as a liquid crystal display device, a circuit on an array substrate constituting the display device may be destroyed due to static electricity generated during manufacturing. In order to cope with this problem, it is a common practice to form a ground wire by patterning a metal film on an array substrate to release static electricity generated in the circuit.

  Furthermore, since a high-voltage current may flow through the ground wire, it is possible to improve the withstand voltage characteristics between the wiring below the ground wire and intersecting the ground wire in a planar manner (to alleviate the influence of the potential difference). desirable. In order to improve this withstand voltage characteristic, there is also a display device in which a semiconductor film extending so as to overlap the ground line is formed below the ground line.

  Patent Document 1 is a document related to the present invention, and discloses a configuration in which a ground wire is formed to release static electricity generated in the wiring.

JP 2007-42775 A

  In a display device in which a semiconductor film extending so as to overlap with the ground line is formed below the ground line, when the wiring configuration intersecting with the ground line is changed in order to improve the circuit configuration, the circuit configuration and In some cases, the circuit is destroyed by electrostatic discharge due to the relationship with the semiconductor film. Hereinafter, the situation where the problem occurs will be described with reference to FIGS. 5 to 8 by taking an IPS (In-Plane-Switching) liquid crystal display device as an example.

  FIG. 5 is a partial plan view of an array substrate for explaining the problem of the present invention, and is an example of a configuration in the case where the aforementioned electrostatic discharge problem occurs. This figure is an enlarged view of a peripheral circuit including the ground line PE on the left side of the display area of the liquid crystal display device, and shows a circuit corresponding to two rows of the pixel array. In the figure, the video signal line IL extending in the vertical direction near the right end indicates the left end of the display area, and the right side from the video signal line IL is the display area of the array substrate of the liquid crystal display device, and a plurality of pixel circuits are arranged. Has been. The left side of the video signal line IL is an area (frame area) surrounding the display area. Gate signal lines GL extend in the left-right direction at the center and the top in the drawing. The gate signal line GL intersects with the video signal line IL from the frame area and further extends in the display area from the right end in the figure. The common connection line CCL extends from the left to the right in the frame area adjacent to the upper side of each gate signal line GL in the drawing, and is connected to the common connection electrode CCE before the video signal line IL. The common connection electrode CCE is provided corresponding to the common connection line CCL, and extends from the point of connection with the common connection line CCL along with the video signal line IL toward the upper side of the upper gate signal line GL in the drawing. The gate signal line GL, the common connection line CCL, and the common connection electrode CCE are formed in the same layer (first conductive layer) on the insulating substrate SUB constituting the array substrate.

  A ground wire PE extends vertically in the center in the figure. The video signal line IL and the ground line PE are formed in a layer (second conductive layer) further above the gate insulating film GI formed in the upper layer of the first conductive layer. Here, the inter-wiring semiconductor film SP extends in the same direction as the ground line PE below the ground line PE. The inter-wiring semiconductor film SP and the ground line PE are planarly overlapped, and are wider than the ground line PE at a portion intersecting the gate signal line GL and the common connection line CCL, and are wider than the ground line PE at other portions. Is formed narrowly.

  In this figure, the common connection electrode CCE is connected to the common electrode CT through a contact hole, and the common electrode CT extends in the display area beyond the video signal line IL. The gate signal line GL is electrically connected to the ground line PE by protective diodes PD1 and PD2.

  FIG. 6 is a cross-sectional view taken along the line AA in FIG. 5 and shows a cross-sectional structure of the ground wire portion. There is a first conductive layer on which the common connection line CCL and the gate signal line GL are formed on the insulating substrate SUB, and a gate insulating film GI layer and a semiconductor film SLE are formed on the first conductive layer. The layers are formed in this order: a layer in which the impurity-added semiconductor film DLE is formed, a second conductive layer in which the ground line PE is formed, and an interlayer insulating film MI. Here, the semiconductor film SLE and the doped semiconductor film DLE constitute an inter-wiring semiconductor film SP.

  Here, in the circuit having the configuration shown in FIGS. 5 and 6, static electricity may be accumulated in the wiring or the like by a manufacturing process such as etching performed on the upper layer of the first conductive layer. In particular, when the semiconductor film is etched using plasma ions, since the array substrate is irradiated with ions, static electricity tends to accumulate in the wiring.

  FIG. 7 is a view for explaining an etching process in the array substrate in the subject of the present invention. FIG. 7 shows a state during the manufacture of the circuit shown in FIG. In this figure, after a metal film layer is stacked on the insulating substrate SUB and the gate signal line GL and the common connection line CCL are patterned, the layer of the gate insulating film GI, the layer on which the semiconductor film SLE and the like are formed, and the addition of impurities A layer in which the semiconductor film DLE and the like are formed is stacked, and the impurity-added semiconductor film DLE and the semiconductor film SLE and the like are patterned by etching. As can be seen from this figure, when the semiconductor film is subjected to plasma etching, static electricity is accumulated in the lower layer in the gate signal line GL and the common connection line CCL. Here, the gate signal line GL is a wiring extending from the frame region to the opposite end of the display region, and the common connection line CCL is a wiring that extends in the frame region but is not formed in the display region. Therefore, as can be seen from FIG. 7, the wiring length of the gate signal line GL is significantly longer (at least 10 times or more) than the wiring length of the common connection line CCL. Therefore, the gate signal line GL having a long wiring length is more likely to accumulate static electricity due to the influence of plasma ions in etching.

  When the amount of charge accumulated due to static electricity is different, a potential difference is generated. In the case of FIG. 5, a potential difference is generated between the gate signal line GL and the common connection line, and electrostatic discharge occurs between the common connection line CCL and the gate signal line GL in FIG. The route of electrostatic discharge does not extend the gate insulating film GI in the lateral direction at the shortest distance but via the semiconductor film SLE and the impurity-added semiconductor film DLE above the gate insulating film GI.

  On the other hand, FIG. 8 is a diagram for explaining an etching process in a conventional array substrate. This figure shows a state in the process of manufacturing a circuit of a conventional IPS type or TN type liquid crystal display device, and particularly shows an enlarged vicinity of the ground wire PE. As in FIG. 7, after the gate signal line GL and the common connection line CCL are patterned, a layer of the gate insulating film GI, a layer in which the semiconductor film SLE is formed, a layer in which the impurity-added semiconductor film DLE and the like are formed, and the like are stacked. It shows a state of being etched using plasma ions. Unlike FIG. 7, FIG. 8 differs from FIG. 7 in that the metal wiring ML corresponding to the common connection line in FIG. 7 extends from the frame area to the opposite end of the display area. Therefore, the wiring lengths of the gate signal line GL and the metal wiring ML are substantially the same. In this case, even if charges are accumulated in the gate signal line GL and the metal wiring ML, they are accumulated in substantially the same manner, so that the difference in the amount of charge accumulated in the gate signal line GL and the metal wiring ML is limited, and electrostatic discharge is Does not occur. Note that the metal wiring ML corresponds to a common signal line in the case of an IPS liquid crystal display device, and corresponds to a storage line in the case of a TN liquid crystal display device.

  That is, in the configuration as shown in FIG. 7, the wiring length between the common connection line CCL and the gate signal line GL adjacent to the common connection line CCL is significantly different. A semiconductor film that tends to accumulate unevenly so as to increase and extends below the ground line so as to overlap the ground line is formed so as to connect between the common connection line CCL and the gate signal line GL adjacent thereto. There is a problem that electrostatic discharge occurs before the ground wire is formed and the circuit is destroyed.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a display device that prevents a circuit from being destroyed by electrostatic discharge in an etching process before forming a ground wire.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  (1) A first conductive layer in which a first signal line and a second signal line adjacent to the first signal line are formed on an insulating substrate; and provided in an upper layer of the first conductive layer. A second conductive layer formed on the first insulating layer and an upper layer of the first insulating layer, wherein a ground line that intersects the first signal line and the second signal line in a plane is formed. A first semiconductor film and a second semiconductor film, which are provided between the first insulating layer and the second conductive layer, and are formed so as to overlap the ground wire in a plane and are spaced apart from each other. A wiring length of the first signal line and a wiring length of the second signal line differ by at least 10 times, and the first semiconductor film has the above-mentioned structure in plan view. The second semiconductor film overlaps a portion where the first signal line and the ground line intersect, and the second semiconductor film has the second signal in plan view. Display a line and said ground line overlaps with the intersection, it is characterized.

  (2) The display device according to (1), wherein the first semiconductor film and the second semiconductor film include a semiconductor film to which an impurity is added.

  (3) In (1) or (2), the insulating substrate includes a display region in which a plurality of pixel circuits corresponding to pixels are arranged, and a frame region surrounding the display region, and the first signal line Extends in both the frame area and the display area, and the second signal line extends in the frame area and is not formed in the display area.

  (4) In the display device according to (3), the second signal line is connected to a transparent electrode that is formed above the second conductive layer and extends from the frame region to the display region. .

  (5) In any one of (1) to (4), the first semiconductor film is flat with respect to the wiring in the first conductive layer other than the ground line and the first signal line. The display is characterized in that the second semiconductor film does not overlap with the wiring in the first conductive layer other than the ground line and the second signal line in a plane. apparatus.

  According to the present invention, circuit breakdown due to electrostatic discharge can be prevented in an etching process of a semiconductor film or the like.

It is a figure which shows the equivalent circuit of the display area of the array substrate which concerns on embodiment of this invention, and its peripheral region. It is a fragmentary top view which shows the earth line PE vicinity of the array substrate which concerns on this embodiment. It is sectional drawing in the AA cutting line of FIG. It is a figure for demonstrating the manufacturing process of the array substrate which concerns on this embodiment. It is a figure for demonstrating the manufacturing process of the array substrate which concerns on this embodiment. It is a figure for demonstrating the manufacturing process of the array substrate which concerns on this embodiment. It is a partial top view of the array substrate for demonstrating the subject of this invention. It is sectional drawing in the AA cutting line of FIG. It is a figure explaining the etching process in the array substrate in the subject of this invention. It is a figure explaining the etching process in the conventional array substrate.

  Hereinafter, examples of embodiments of the present invention will be described in detail with reference to the drawings. The display device according to the present embodiment is an IPS (In-Plane-Switching) type liquid crystal display device, and is an array substrate and a filter substrate (also referred to as a counter substrate) provided with a color filter facing the array substrate. ), A liquid crystal material sealed in a region sandwiched between both substrates, and a driver IC attached to the array substrate. The array substrate and the filter substrate are both glass substrates.

  FIG. 1 is a diagram showing an equivalent circuit of the display area DA and its peripheral area of the array substrate according to the present embodiment. In the display area DA of the array substrate, a large number of gate signal lines GL are arranged side by side and extend in the horizontal direction, and are connected to the gate signal line drive circuit YDV outside the display area DA on the right side in the drawing. A large number of video signal lines IL also extend in the vertical direction along with each other, and are connected to the video signal line drive circuit XDV outside the display area DA. The display area DA is partitioned in a matrix by the gate signal lines GL and the video signal lines IL, and each section is a pixel area. A pixel circuit is formed in each pixel region. Further, the common signal line CL extends in the horizontal direction corresponding to each gate signal line GL. The common signal line CL is connected to one common collection line CGL extending in the vertical direction outside the display area on the left side in the drawing. The common set line CGL is connected to the gate signal line drive circuit YDV outside the display area DA.

  A pixel switch SW is disposed in each pixel circuit corresponding to a location where the gate signal line GL and the video signal line IL intersect. The pixel switch SW is a so-called thin film transistor. The gate electrode of the pixel switch SW is connected to the gate signal line GL, and the drain electrode of the pixel switch SW is connected to the video signal line IL. Each pixel circuit is formed with a pair of a pixel electrode PX and a common electrode CT, the pixel electrode PX is connected to the source electrode of the pixel switch SW, and the common electrode CT is connected to the common signal line CL. Yes. Note that the source electrode and the drain electrode of the pixel switch SW are determined by the polarity of the input signal, but the liquid crystal display device can take either polarity. For this reason, the above description is used for convenience. Further, the common electrode CT and the common signal line CL may be integrally formed. Furthermore, the common signal line CL that also serves as the common electrode CT may be formed for each row, or may be integrally formed over a plurality of rows.

  The ground line PE extends in the vertical direction in the figure outside the display area DA on the left side in the figure and on the right side from the common collection line CGL, and is connected to the ground terminal PAD in the lower part in the figure. Each gate signal line GL is connected via protective diodes PD1 and PD2. Here, the protection diode is specifically a diode-connected thin film transistor. The thin film transistor is formed so that the threshold voltage is higher than that of the thin film transistor used in the pixel circuit, and is not turned on by the voltage of the signal current flowing through the gate signal line GL. Further, the protection diode PD1 and the protection diode PD2 have different polarities. In the protective diode PD1, a current flows from the gate signal line GL to the ground line PE, and in the protective diode PD2, a current flows from the ground line PE to the gate signal line GL.

  In the above circuit configuration, a reference voltage is applied to the common electrode CT of each pixel via the common signal line CL. Further, a pixel row is selected by applying a gate voltage to the gate signal line GL. At the selection timing, the video signal is supplied to each video signal line IL, whereby the voltage of the video signal is applied to the pixel electrode PX of each pixel. As a result, a horizontal electric field having an intensity corresponding to the voltage of the video signal is generated between the pixel electrode PX and the common electrode CT, and the orientation of the liquid crystal molecules is determined according to the intensity of the horizontal electric field.

  Note that the potential difference between the gate signal line GL and the ground line PE is kept in a certain range by the protective diodes PD1 and PD2. If a constant potential is supplied from the ground terminal PAD at the time of manufacture or use, the potential of the gate signal line GL is also maintained within a certain range, thereby preventing the circuit from being destroyed after the protection diode is formed.

  In FIG. 1, only 2 × 2 pixel circuits are shown for ease of explanation, but in actuality, the number of pixels (number of pixels arranged in a matrix in the display area) × 3 A pixel circuit is present. Here, the reason for the triple is that three pixel circuits of RGB are required for each pixel.

  FIG. 2 is a plan view showing the vicinity of the ground line PE of the array substrate according to the present embodiment, and is an enlarged view of the left portion of the display area DA in the frame area that is an area surrounding the display area DA. In the drawing, circuits corresponding to two rows in the pixel circuit array are shown. In the figure, the video signal line IL extending in the vertical direction near the right end indicates the left end of the display area DA, and the right side from the video signal line IL is the display area DA of the array substrate of the liquid crystal display device. Is arranged. On the left side of the video signal line IL is a frame area. Gate signal lines GL extend in the left-right direction at the center and the top in the drawing. The common connection line CCL also extends in the left-right direction adjacent to the upper side of each gate signal line GL in the drawing. Here, the gate signal line GL, the common connection line CCL, and the common connection electrode CCE are formed in the same layer (first conductive layer) on the insulating substrate SUB constituting the array substrate.

  A ground wire PE extends vertically in the center in the figure. The video signal line IL and the ground line PE are formed in a layer (second conductive layer) further above the gate insulating film GI formed in the upper layer of the first conductive layer.

  The common connection line CCL will be specifically described below. In FIG. 2, an image is displayed below the gate signal line GL (corresponding to the upper pixel circuit) extending in the left-right direction in the upper part of the drawing and at the right end of the frame area toward the gate signal line GL extending in the left-right direction in the center of the figure. There is a common connection electrode CCE extending in parallel with the signal line IL. The common connection electrode CCE extends to the front of the gate signal line GL extending left and right in the center in the figure, and is connected to the common connection line CCL there. The common connection line CCL extends in the left direction in the drawing from the portion connected to the common connection electrode CCE, and after extending a little in the lower left direction in the drawing and extending toward the left in the drawing. The common connection line CCL intersects the ground line PE in the lower layer, extends toward the left side in the figure, and is connected to a common collection line CGL (not shown) at the left end of the frame area.

  The common connection line CCL and the ground line PE intersect each other in plan view. An inter-wiring semiconductor film SPC (second semiconductor film) is formed so as to overlap with the intersecting portion in a layer between the common connection line CCL (exactly, the gate insulating film GI above) and the ground line PE. Is formed.

  Here, the common connection electrode CCE is connected to the common electrode CT (common signal line CL) located above the ground line PE and the video signal line IL through the contact hole CHC, and the common electrode CT exceeds the video signal line IL in the display region. Is extended. The common electrode CT is a transparent electrode. The common electrode CT is provided so as to cross the pixel regions arranged in the horizontal direction in the horizontal direction, and is also a part of the common signal line CL shown in FIG. Further, the common connection line CCL is a part of the common signal line CL although the layer formed is different from the common electrode CT.

  Further, the gate signal line GL intersects with the video signal line IL from the frame area, and further extends in the display area DA from the right end in the drawing. The wiring structure in the frame area of the gate signal line GL will be specifically described below starting from the display area DA side. The gate signal line GL crosses the video signal line IL in the lower layer from the display area DA on the right side in the drawing and enters the frame area. The video signal line IL and the gate signal line GL intersect each other. Furthermore, after entering the frame area, the gate signal line GL is adjacent to the common connection line CCL and extends toward the left side in the figure. Extends to the left. The gate signal line GL is separated from the common connection line CCL before the ground line PE, and extends downward in the drawing. A contact hole CHG2 is formed above the gate signal line GL. The bottom of the contact hole CHG2 reaches the gate signal line GL. The gate signal line GL faces the left side in the figure from the position where the contact hole CHG2 is formed, and intersects the ground line PE in the lower layer. The gate signal line GL and the ground line PE are orthogonal to each other in plan view. A contact hole CHG3 is formed above the gate signal line GL that intersects the ground line PE, and the bottom of the contact hole CHG3 reaches the gate signal line GL. The gate signal line is divided into upper and lower portions where the contact hole CHG3 is formed, the upper side extends upward in the figure to the front of the common connection line CCL, the lower side extends downward in the figure, and beyond that in the figure Bending leftward, the bent portion is the gate electrode GT1 of the protective diode PD1.

  The gate signal line GL and the ground line PE are orthogonal to each other in plan view. An inter-wiring semiconductor film SPG (first semiconductor film) is formed in a layer between the gate signal line GL (exactly, the upper-layer gate insulating film GI) and the ground line PE so as to overlap the orthogonal portion in plan view. Is formed.

  The gate signal line GL is electrically connected to the ground line PE by protective diodes PD1 and PD2. Specifically, the protection diode PD1 includes a channel semiconductor film SLD1, a drain electrode DT1, a source electrode ST1, and the above-described gate electrode GT1. The channel semiconductor film SLD1 is formed above the gate electrode GT1. The drain electrode DT1 is connected to the upper surface of the right end of the channel semiconductor film SLD1, extends to the right side, and is connected to the ground line PE. The source electrode ST1 is connected to the upper surface of the left end of the channel semiconductor film SLD1, extends to the left and then bends upward, and further bends toward the contact hole CHG3 to form a contact hole CHD3 on the bent point. Has been. The bottom of the contact hole CHD3 reaches the source electrode ST1. The source electrode ST1 and the gate signal line GL are connected by a transparent electrode TW3 provided so as to cover both the contact hole CHD3 and the contact hole CHG3. This structure is a diode-connected thin film transistor in which the gate electrode GT1 and the source electrode ST1 are both connected to the gate signal line GL.

  The protection diode PD2 includes a channel semiconductor film SLD2, a drain electrode DT2, a source electrode ST2, and a gate electrode GT2. The drain electrode DT2 is a wiring of the same layer as the ground line PE, extends from the contact hole CHD2 formed on the right side of the contact hole CHG2 to the right in the figure, and further bends downward in the figure. Further, it is bent toward the left side in the figure. The contact hole CHD2 reaches the drain electrode DT2. The drain electrode DT2 is connected to the upper surface of the right end of the channel semiconductor film SLD2 at the lower surface of the drain electrode DT2. The channel semiconductor film SLD2 extends from the portion connected to the drain electrode DT2 toward the ground line PE in the left direction in the drawing, and is connected to the source electrode ST2 extending from the ground line PE in the right direction in the drawing on the upper surface of the left end. Yes. The gate electrode GT2 is in the same layer as the gate electrode GT1, overlaps the channel semiconductor film SLD2 in a plan view, further extends downward from the right end portion thereof, and a contact hole CHG1 is formed above the tip. Yes. The contact hole CHG1 reaches the gate electrode GT2. On the left side of the contact hole CHG1, there is a branch extending in the left direction in the figure from the ground wire PE, and the contact hole CHD1 is formed above the tip. Contact hole CHD1 reaches ground wire PE. The gate signal line GL and the drain electrode DT2 are connected by a transparent electrode TW2 that covers the contact hole CHG2 and the contact hole CHD2, and the gate electrode GT2 and the ground line PE are connected by a transparent electrode TW1 that covers the contact hole CHD1 and the contact hole CHG1. It is connected. This structure is a diode-connected thin film transistor in which the gate electrode GT2 and the source electrode ST2 are both connected to the ground line PE.

  FIG. 3 is a cross-sectional view taken along the line AA in FIG. 2 and shows a cross-sectional structure of the ground wire portion. There is a first conductive layer on which the common connection line CCL and the gate signal line GL are formed on the insulating substrate SUB. The upper layer of the first conductive layer is planar with the layer of the gate insulating film GI and the common connection line CCL. A layer in which a semiconductor film SLC overlapping with the gate signal line GL and a semiconductor film SLG overlapping in plane are formed; an impurity-added semiconductor film DLC in contact with the upper surface of the semiconductor film SLC; and an impurity-added semiconductor in contact with the upper surface of the semiconductor film SLG A layer in which the film DLG is formed, a second conductive layer in which the ground line PE is formed, and a layer of the interlayer insulating film MI are sequentially stacked. Here, the semiconductor film SLC and the impurity-added semiconductor film DLC constitute an inter-wiring semiconductor film SPC, and the semiconductor film SLG and the impurity-added semiconductor film DLG constitute an inter-wiring semiconductor film SPG.

  Next, a method for manufacturing the array substrate according to the present embodiment will be described. 4A to 4C are diagrams for explaining a manufacturing process of the array substrate according to the present embodiment. First, the gate signal line GL and the common connection line CCL are formed on the array substrate SUB. Here, the array substrate SUB is a transparent substrate such as a glass substrate. In this step, a metal that becomes the gate signal line GL or the like, for example, a refractory metal such as molybdenum, tungsten, or tantalum or an alloy thereof is formed and patterned by photolithography and etching to form the shape of the gate signal line GL or the like. (FIG. 4A).

  Next, a gate insulating film GI is formed so as to cover the gate electrode film. The gate insulating film GI is, for example, silicon dioxide or silicon nitride, and is formed by a CVD method or the like. Then, a semiconductor layer SL containing amorphous silicon (a-Si) is continuously formed. Thereafter, in order to form the impurity-added semiconductor layer DL (n + layer), for example, amorphous silicon in which high-concentration phosphorus is diffused is formed (FIG. 4B).

  Next, the impurity-added semiconductor layer DL and the semiconductor layer SL are patterned by photolithography and etching to form an inter-wiring semiconductor film SPC and an inter-wiring semiconductor film SPG (FIG. 4C). Here, plasma ions using a fluorocarbon-based gas or the like are used as an etching method.

  Next, for example, a metal such as aluminum or an alloy thereof is formed by sputtering to form a metal film. At that time, in order to prevent diffusion of the aluminum film and to reduce contact resistance, layers of high melting point metals such as titanium and molybdenum or alloys thereof (barrier metal layers) may be formed above and below the aluminum layer. Thereafter, the ground wire PE and the like are formed by photolithography and etching. Next, as the interlayer insulating film MI, for example, silicon nitride is formed by a CVD method (see FIG. 3). Then, after forming a planarizing film and forming contact holes CHC and the like, a common electrode CT is formed and patterned, and an insulating film is formed thereon to form contact holes and the like. Thereafter, by forming the pixel electrode PX, an IPS pixel circuit or a frame region circuit is formed.

  With the above structure, the inter-wiring semiconductor film SPC formed on the common connection line CCL and the inter-wiring semiconductor film SPG formed above the gate signal line GL are separated as shown in FIG. It will be provided in an island shape. When plasma etching is performed as described above in the manufacturing process, charges are easily accumulated in the gate signal line GL and the common connection line CCL as in the configuration shown in FIGS. Due to the difference (for example, a difference of 10 times or more), a potential difference similar to that in FIG. 7 is also generated. However, since the semiconductor films serving as the discharge route are formed apart from each other in the structure of FIG. 7, the resistance between the common connection line CCL and the gate signal line GL increases, and electrostatic discharge is suppressed. The reason why the resistance is increased and the electrostatic discharge is suppressed will be further described below.

  One of the reasons described above is that the impurity-added semiconductor layer DL whose conductivity is increased by the addition of impurities is an upper layer, so that the impurity-added semiconductor film DLC and the impurities are added at a relatively early stage of etching. It is to be separated into the semiconductor film DLG. When the semiconductor layer SL is separated into the impurity-added semiconductor film DLC and the impurity-added semiconductor film DLG, the semiconductor layer SL is a semiconductor layer to which no impurity is added, so that the resistance value becomes larger than in the case of FIGS. This is one reason why electrostatic discharge can be suppressed. Another reason is that the inter-wiring semiconductor film SPC and the inter-wiring semiconductor film SPG are separated in an island shape. In the etching process, the array substrate is exposed to plasma ions for a while after the inter-wiring semiconductor film SPC and the inter-wiring semiconductor film SPG are separated, and the charge amount of the gate signal lines GL and the like may increase during that time. However, it is considered that the electrostatic discharge can be suppressed because the inter-wiring semiconductor film SPC and the inter-wiring semiconductor film SPG are insulated if they are separated in an island shape.

  The present invention is not limited to a liquid crystal display device having a structure as shown in FIG. For example, in an organic EL display device or the like, electrodes and wiring are formed on upper and lower layers sandwiching an organic EL element, and the upper wiring is formed in the same area as the lower layer through a contact hole in a frame region. This is because the wiring lengths of adjacent wirings in the same layer may differ significantly when they are connected to other wirings.

  IL video signal line, GL gate signal line, CL common signal line, CGL common aggregate line, XDV video signal line drive circuit, YDV gate signal line drive circuit, DA display area, CT common electrode, CCE common connection electrode, PX pixel electrode , SW pixel switch, CCL common connection line, PE ground line, PAD ground terminal, SLD1, SLD2 semiconductor film, SPC, SPG, SP Inter-wiring semiconductor film, DLC, DLG, DLE Impurity doped semiconductor film, SLC, SLG, SLE semiconductor Film, SLD1, SLD2 channel semiconductor film, GT1, GT2 gate electrode, ST1, ST2 source electrode, DT1, DT2 drain electrode, DL impurity doped semiconductor layer, SL semiconductor layer, TW1, TW2, TW3 transparent electrode wiring, CHG1, CHG2, CHG3, CHD1, C D2, CHD3, CHC contact hole, SUB insulating substrate, GI gate insulating film, MI interlayer insulating film.

Claims (3)

A first conductive layer in which a first signal line, a second signal line adjacent to the first signal line, a first gate electrode, and a second gate electrode are formed on an insulating substrate. When,
A first insulating layer provided on an upper layer of the first conductive layer;
A second conductive layer provided on an upper layer of the first insulating layer and formed with a ground wire that intersects the first signal line and the second signal line in a plane;
A first semiconductor film and a second semiconductor film, which are provided between the first insulating layer and the second conductive layer and which are planarly overlapped and spaced apart from each other; A semiconductor layer in which a third semiconductor film provided so as to overlap with one gate electrode and a fourth semiconductor film provided so as to overlap with the second gate electrode are formed; Including,
The insulating substrate has a display area in which a plurality of pixel circuits corresponding to pixels are arranged, and a frame area surrounding the display area,
The first signal line is a gate signal line extending in both the frame region and the display region and connected to the gate electrode of the thin film transistor,
The second signal line extends in the frame area and is formed in the display area.
The second signal line is connected to a common electrode, which is a transparent electrode that is formed above the second conductive layer and extends from the frame region to the display region,
One end of the third semiconductor film and the first gate electrode and the gate signal line are electrically connected, and the other end of the third semiconductor film is electrically connected to the ground line,
One end of the fourth semiconductor film and the second gate electrode and the ground line are electrically connected, and the other end of the fourth semiconductor film is electrically connected to the gate signal line,
The first semiconductor film overlaps with a portion where the first signal line and the ground line intersect in plan view,
The second semiconductor film overlaps with a portion where the second signal line and the ground line intersect in plan view,
A display device characterized by that.   2. The semiconductor device according to claim 1, wherein the first semiconductor film, the second semiconductor film, the third semiconductor film, and the fourth semiconductor film include a semiconductor film to which an impurity is added. Display device. The first semiconductor film does not overlap with the wiring in the first conductive layer other than the ground line and the first signal line in a plane,
3. The second semiconductor film according to claim 1, wherein the second semiconductor film does not overlap with the wiring in the first conductive layer other than the ground line and the second signal line in a planar manner. Display device.

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