JP2007042775A - Protection diode, method of manufacturing same, and electro-optical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a protection diode which can control breakdown of a switching element due to static electricity during the manufacture of an electro-optical device, and also to provide a method of manufacturing the protection diode and an electro-optical device. <P>SOLUTION: The protection diodes 81, 83 are provided with elements TR1, TR2 formed of a source electrode 85S/drain electrode 85D, a semiconductor layer 85C including a channel region, and a gate electrode 85G arranged facing the semiconductor layer 85C through a gate insulating film 85I. This protection diode includes a capacitance Cp formed with a part of the source electrode 85S/drain electrode 85D and the gate electrode 85G laminated through the gate insulating film 85I. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a protection diode, a method for manufacturing the protection diode, and an electro-optical device.

Currently, electro-optical devices such as liquid crystal display devices are widely used in electronic devices such as mobile phones and portable information terminals. In such an electro-optical device, a TFT (thin film transistor) provided for each pixel in the display area is driven to display various information about electronic devices such as characters, numbers, graphics, and the like. Yes.
Here, as the switching element, for example, a MOS transistor is employed, but this has a drawback that it is easily destroyed by static electricity. Therefore, it is known that a protective diode is formed on a glass substrate as a means for preventing the switching element from being destroyed by static electricity (see, for example, Patent Document 1).
Japanese Patent No. 3261699

By the way, in the above-mentioned patent document, a protective diode is formed by forming a transparent conductive film such as ITO (Indium Tin Oxide) in the uppermost layer, but in a process preceding the process of forming the transparent conductive film. There is a disadvantage that destruction due to the generated static electricity cannot be prevented.
On the other hand, the switching element is generally formed on a substrate such as a glass substrate by using a known semiconductor manufacturing process, and in such a manufacturing process, various manufacturing processes using a plasma atmosphere, Static electricity is generated on the glass substrate due to contact between the transfer arm and the glass substrate during transfer. Furthermore, since the glass substrate has the property of being easily charged with static electricity, it is difficult to suppress the generation of static electricity.
Therefore, there is a problem that the switching element is destroyed during the manufacturing process due to these reasons. Moreover, even if the protection diode is finally formed as in the above-mentioned patent document, there is a problem that the switching element cannot be protected from static electricity in the process before the protection diode is formed.
The present invention has been made in view of the above-described problems, and includes a protection diode, a protection diode manufacturing method, and an electro-optical device that can suppress the destruction of a switching element due to static electricity during the manufacturing process of the electro-optical device. The purpose is to provide.

In order to solve the above problems, the present inventor has conceived the present invention having the following means.
That is, the protection diode of the present invention is a protection diode comprising an element comprising a source / drain electrode, a semiconductor layer having a channel region, and a gate electrode disposed opposite to the semiconductor layer via a gate insulating film. A part of the source / drain electrode and the gate electrode have a capacitance portion formed by overlapping with the gate insulating film interposed therebetween.
In this way, the element can be operated by using the parasitic coupling caused by the structure of the element and the capacitive coupling by the capacitor portion. In addition, since the capacitively coupled protection diode is formed, the electrostatic protection function is provided from an early step (the stage where the source / drain electrodes are formed) without forming the transparent conductive film in the uppermost layer.
Therefore, the switching element can be prevented from being destroyed during the manufacturing process, and the switching element can be protected from static electricity.

  In the protection diode of the present invention, the capacitance ratio of the capacitance portion to the parasitic capacitance in the element is preferably greater than 1, and more preferably greater than 5. In this way, switching characteristics having steep current-voltage characteristics can be obtained.

The protection diode manufacturing method of the present invention includes an element including a source / drain electrode, a semiconductor layer having a channel region, and a gate electrode disposed to face the semiconductor layer via a gate insulating film. A method of manufacturing a protection diode, wherein a capacitance part is formed by overlapping at least one part of the source / drain electrode with the gate electrode through the gate insulating film. It is characterized by that.
In this way, since the protection diode is manufactured, a protection diode having an element that operates by capacitive coupling can be realized. Further, without forming the transparent conductive film as the uppermost layer, it has an electrostatic protection function from an early process (stage where the source / drain electrodes are formed).
Therefore, the switching element can be prevented from being destroyed during the manufacturing process, and the switching element can be protected from static electricity.

The electro-optical device according to the invention includes an element including a source / drain electrode, a semiconductor layer having a channel region, and a gate electrode disposed to face the semiconductor layer via a gate insulating film. A device comprising the protective diode described above.
In this way, the same effect as the above protection diode can be obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In the present embodiment, a liquid crystal device which is one form of an electro-optical device will be described.
In each drawing used for the following description, the scale of each member is appropriately changed to make each member a recognizable size.
In the present specification, the liquid crystal layer side of each component of the liquid crystal device is referred to as an inner side, and the opposite side is referred to as an outer side. “When a non-selection voltage is applied” and “when a selection voltage is applied” are respectively “when the applied voltage to the liquid crystal layer is close to the threshold voltage of the liquid crystal” and “the applied voltage to the liquid crystal layer is It means “when sufficiently high compared to the threshold voltage”.

  First, a liquid crystal device according to an embodiment of the present invention will be described with reference to FIGS. The liquid crystal device according to this embodiment includes a liquid crystal panel in which a liquid crystal layer is sandwiched between a pair of substrates, and polarizing plates respectively disposed on the outside of the liquid crystal panel. In the present embodiment, an active matrix transmissive liquid crystal panel using a thin film transistor (hereinafter referred to as TFT) element as a switching element will be described as an example.

(Circuit diagram of the liquid crystal panel)
FIG. 1 is a circuit diagram of a liquid crystal panel.
Pixel electrodes 9 are formed on a plurality of dots arranged in a matrix so as to form an image display region 60A of the transmissive liquid crystal panel 60. Further, a TFT element 30 which is a switching element for performing energization control to the pixel electrode 9 is formed on the side of the pixel electrode 9. A data line 6 a is electrically connected to the source region of the TFT element 30. The data line 6a is connected to the data line driving circuit 71.

  The scanning line 3 a is electrically connected to the gate of the TFT element 30. Further, the scanning line 3 a is connected to the gate line driving circuit 72. When the gate line driving circuit 72 is driven, scanning signals G1, G2,..., Gm are supplied to the scanning line 3a in pulses at a predetermined timing. Note that the scanning signals G1, G2,..., Gm are applied sequentially to each scanning line 3a in this order.

  Further, the pixel electrode 9 is electrically connected to the drain region of the TFT element 30. When the TFT elements 30 serving as switching elements are turned on for a certain period by the scanning signals G1, G2,..., Gm supplied from the scanning line 3a, the image signals S1, S2,. , Sn are written to the liquid crystal of each pixel at a predetermined timing.

Image signals S1, S2,..., Sn written at a predetermined level in the liquid crystal are held for a certain period by a liquid crystal capacitance formed between the pixel electrode 9 and the common electrode.
Further, a storage capacitor 17 is disposed between the pixel electrode 9 and the capacitor line 3b in parallel with the liquid crystal capacitor so as to prevent leakage of the image signals S1, S2,..., Sn held by the liquid crystal capacitor. It has become.
Thus, when a voltage signal is applied to the liquid crystal, the alignment state of the liquid crystal molecules changes depending on the applied voltage level. As a result, the light incident on the liquid crystal is modulated to enable gradation display.

The liquid crystal panel 60 includes protective diodes 81, 82, and 83 on the outer periphery of the plurality of pixel electrodes 9 arranged in a matrix.
Each of the protection diodes 81 is connected to the data line 6a on one side (an input side described later), and connected to the first common wiring 101 on the other side (an output side described later).
Each of the protection diodes 82 is connected to the scanning line 3a on one side (an input side described later) and connected to the second common wiring 102 on the other side (an output side described later).
Each of the protection diodes 83 is connected to the first common wiring 101 or the second common wiring 102 on one side (input side to be described later), and is connected to the first outer peripheral wiring 103 on the other side (output side to be described later). ing. Further, the first outer peripheral wiring 103 is electrically connected to the second outer peripheral wiring 105 having the silver point 104.
The protective diodes 81 and 83, the first and second common wirings 101 and 102, and the first outer peripheral wiring 103 are formed of the same material as a source wiring and a source electrode described later.
With such a configuration, the circuit configuration of the liquid crystal panel 60 is surrounded by the protection diode 83 and is electrically protected by the protection diode 83.

  In the liquid crystal panel of this embodiment, a rectangular pixel electrode 9 made of a transparent conductive material such as indium tin oxide (hereinafter referred to as ITO) on the TFT array substrate (the outline is indicated by a broken line 9a). Are arranged in a matrix. A data line 6 a, a scanning line 3 a, and a capacitor line 3 b are provided along the vertical and horizontal boundaries of the pixel electrode 9. In the present embodiment, the region in which each pixel electrode 9 is formed is a dot, and the display can be performed for each dot arranged in a matrix.

The TFT element 30 is formed around a semiconductor layer made of an amorphous silicon film. The TFT element 30 is driven by signals input from the data line 6a and the scanning line 3a, and the driving state is determined by the potential of the capacitor line 3b. Retained.
Further, the TFT element 30 is formed in the same configuration as the process of forming the protection diodes 81, 82, 83 described later.

  A common electrode (not shown) is formed so as to face the pixel electrode 9. The common electrode is a so-called solid film formed on the entire surface of the image display region 60A. A liquid crystal layer made of nematic liquid crystal is sandwiched between the pixel electrode 9 and the common electrode. The nematic liquid crystal molecules exhibit positive dielectric anisotropy, and are aligned horizontally when a non-selection voltage is applied and vertically aligned when a selection voltage is applied. Nematic liquid crystal molecules exhibit positive refractive index anisotropy, and the product (retardation) Δnd of the birefringence and the liquid crystal layer thickness is, for example, about 0.40 μm (60 ° C.).

  In the transmissive liquid crystal panel 60 of the present embodiment, the alignment regulation direction by the alignment film of the TFT array substrate on which the pixel electrode 9 is formed and the alignment regulation direction by the alignment film on the counter substrate on which the common electrode is formed are , About 90 ° twisted. Thereby, the liquid crystal panel 60 of the present embodiment is configured to operate in a twisted nematic mode.

  In the present embodiment, nematic liquid crystal is used as the liquid crystal layer, but a liquid crystal material having negative dielectric anisotropy, that is, vertical alignment liquid crystal may be used instead. In this case, the alignment film is preferably formed of an inorganic material such as a silicon oxide film. Further, it is preferable that the alignment film is formed by, for example, oblique vapor deposition to give a pretilt to the vertically aligned liquid crystal.

A polarizing plate (not shown) is disposed outside the TFT array substrate and the counter substrate in the liquid crystal panel 60. In other words, polarizing plates are arranged on the light incident side and the light emitting side of the liquid crystal panel 60.
The polarizing plate has a function of absorbing linearly polarized light in the absorption axis direction and transmitting linearly polarized light in the transmission axis direction. The polarizing plates respectively disposed on both surfaces of the liquid crystal panel 60 are disposed so that the respective absorption axes and transmission axes are orthogonal to each other.
Note that a support substrate made of a light-transmitting material having high thermal conductivity such as sapphire glass or crystal may be disposed between the liquid crystal panel 60 and the polarizing plate. Further, an optical compensation plate such as a retardation plate may be disposed between the polarizing plate and the liquid crystal panel 60.

(First Embodiment of Protection Diode)
Next, the protection diodes 81, 82, and 83 will be described with reference to FIGS.
FIG. 2A is an equivalent circuit diagram of the protection diodes 81 and 83, and FIG. 2B is an equivalent circuit diagram of the protection diode 82. FIG. 3 is a diagram illustrating current-voltage characteristics of the protection diode.

First, the protection diodes 81 and 83 will be described with reference to FIG.
In the case of the protection diode 81, the “input side” means the side connected to the data line 6a in FIG. 1, and the “output side” means the side connected to the first common wiring 101 in FIG. Means. In the case of the protection diode 83, “input side” means the side connected to the first common wiring 101 or the second common wiring 102 in FIG. 1, and “output side” in FIG. The side connected to the first outer peripheral wiring 103 is meant.
Here, the protection diodes 81 and 83 are configured by transistors (elements) TR1 and TR2 provided in parallel. Furthermore, a built-in capacitor Cp (capacitor section, which will be described later) is connected between the gate G of the transistor TR1 and the input side and between the gate G and the output side of the transistor TR2. In addition, a parasitic capacitance Cgd (described later) is generated between the gate G and the input side of the transistor TR2 and between the gate G and the output side of the transistor TR1. The parasitic capacitance Cgd is a capacitance that occurs due to the configuration of a transistor including a stacked layer of a silicon layer, source / drain electrodes, and a gate electrode.

Next, the protection diode 82 will be described with reference to FIG.
As shown in FIG. 2B, the “input side” means the side connected to the scanning line 3a in FIG. 1, and the “output side” is connected to the second common wiring 102 in FIG. Means the other side.
Here, the protection diode 82 includes transistors TR3 and TR4 provided in parallel. Further, the gate G and the input side of the transistor TR3 are connected to the gate G and the output side of the transistor TR4, respectively. Further, parasitic capacitance Cgd (described later) is generated between the gate G of the transistor TR4 and the input side and between the gate G of the transistor TR3 and the output side.
As described above, the protection diodes 81 and 83 have the built-in capacitance Cp, while the protection diode 82 has no configuration.

  As shown in the current-voltage characteristics of FIG. 3, the protection diodes 81, 82, and 83 operate when the input side is applied with a voltage equal to or higher than Vth with respect to the output side. It is like that.

Next, the parasitic capacitance Cgd generated in the transistors TR1, TR2, TR3, TR4 will be described with reference to FIG.
FIG. 4A is an enlarged plan view in which a portion where the parasitic capacitance Cgd is generated in the transistor TR1 is enlarged, and FIG. 4B is a cross-sectional view of FIG. Hereinafter, only the transistor TR1 will be described, and the configurations of the transistors TR2, TR3, and TR4 are the same.
As shown in FIG. 4B, the transistor TR1 includes a gate electrode 85G, a gate insulating film 85I, a channel silicon film (semiconductor layer) 85C, an N + silicon film (semiconductor layer) 85N, a source electrode 85S, and a substrate body 10A. The drain electrode 85D and the protective film 85P are stacked.
Thus, since the gate insulating film 85I and the channel silicon film 85C are interposed between the source electrode 85S and the drain electrode 85D and the gate electrode 85G, a parasitic capacitance Cgd is generated in the transistor TR1. The parasitic capacitance Cgd is a capacitance between the gate electrode 85G and the source electrode 85S / drain electrode 85D, and about half of the total parasitic capacitance when the transistor TR1 is turned on is distributed to Cgd and Cgs.
Specifically, referring to FIG. 4A, since the channel silicon film 85C is also made into a conductor, the area of the total parasitic capacitance is (L + ΔL × 2) × (W + ΔW × 2), and its film thickness. Is the thickness of the gate insulating film 85I. This half value is the parasitic capacitance Cgd.

Next, the built-in capacitors formed in the transistors TR1 and TR2 will be described with reference to FIG.
FIG. 5A is an enlarged plan view of the transistors TR1 and TR2, and FIG. 5B is a cross-sectional view taken along line BB ′ of FIG.
As shown in FIG. 5A, the source line (source electrode) 85S branches at the branch portion 87S, one of which extends so as to overlap the channel silicon film 85C of the transistor TR2, and the other is the bent portion 86S. Is bent so as to overlap with the channel silicon film 85C of the transistor TR1.

  Further, the drain line (drain electrode) 85D is branched at the branch portion 87D, one of which extends so as to overlap the channel silicon film 85C of the transistor TR1, and the other is bent by the bent portion 86D to be the channel of the transistor TR2. It extends so as to overlap the silicon film 85C.

The gate line (gate electrode) 85G of the transistor TR1 has a bent portion 86G, one of which extends so as to overlap the channel silicon film 85C of the transistor TR1, and the other overlaps the drain line 85D of the transistor TR2. ing.
The gate line 85G of the transistor TR2 has a bent portion 86G, one of which extends so as to overlap the channel silicon film 85C of the transistor TR2, and the other overlaps the source line 85S of the transistor TR1.

As shown in FIG. 5B, the stacked structure in the vicinity of the transistors TR1 and TR2 is the same as that in FIG. A contact hole CS is formed in the protective film 85P, and a contact hole CG is formed in the protective film 85P and the gate insulating film 85I. A transparent conductive film 88 is formed so as to cover the contact holes CS and CG, and the gate line 85G and the source line 85S are conducted through the transparent conductive film 88.
The contact hole CD is formed in the protective film 85P (see FIG. 5A) by the same process of forming the contact hole CS in the protective film 85P (see FIG. 5A), and the gate line 85G and the drain line 85D are formed through the transparent conductive film 88. Is conducting.

Then, as shown in FIG. 5, the built-in capacitance Cp shown in FIG. 2 is formed by overlapping the gate line 85G and the drain line 85D and the gate line 85G and the source line 85S. Here, the built-in capacitance Cp is configured by sandwiching the gate insulating film 85I between the gate line 85G and the source line 85S (drain line 85D) in the region (capacitor portion) AR indicated by oblique lines in FIG. The
In the present embodiment, by adjusting the line widths of the gate line 85G, the drain line 85D, and the source line 85S in the region AR, the capacitance ratio k of the built-in capacitance Cp to the parasitic capacitance Cgd is set to about 5. ing. The parasitic capacitance Cgd referred to below means a case where L / W = 14/7 in FIG.

Next, the relationship between the capacitance ratio k of the transistor TR1 (TR2) of this embodiment and the current-voltage characteristics (IV characteristics) will be described with reference to FIG.
In FIG. 6, the horizontal axis represents the voltage value, and the vertical axis represents the current value.
Moreover, the code | symbol E shows the IV characteristic when the transparent conductive film 88 of FIG. 5 is not formed, and the code | symbol F has shown the IV characteristic when the transparent conductive film 88 is formed.
In addition, in the symbol E, the IV characteristic when the capacitance ratio k is changed from 1 to 21 is measured.

As shown in FIG. 6, a steep IV characteristic is obtained as the capacitance ratio k increases. In this embodiment, since the capacitance ratio is 5 or more, sufficiently steep IV characteristics can be obtained. Further, it can be seen that the IV characteristics hardly change as compared with the case where the transparent conductive film 88 of the symbol E is not formed. That is, even if the transparent conductive film 88 is not formed, steep IV characteristics can be obtained by capacitive coupling between the parasitic capacitance Cgd and the built-in capacitance Cp.
This is because the voltage applied between Cgd and Cp is V (Cgd) = (Cp / (Cp + Cgd)) × V, where V is the voltage applied between the input and output in FIG.
V (Cp) = (Cgd / (Cp + Cgd)) × V
V (Cgd)> V (Cp)
Thus, it is experimentally interpreted that when the capacity ratio k is 5 or more, it approaches the IV characteristic of the code F.

  As described above, the transistors TR1 and TR2 operate by using the capacitive coupling of the parasitic capacitance Cgd and the built-in capacitance Cp of the transistors TR1 and TR2. At this time, since the gate electrode 85G, the source electrode 85S, and the drain electrode 85D are not connected, all the wiring through which current flows from input to output is formed of the same material as the source wiring. In order to operate the protection diode efficiently, the capacity ratio k = Cp / Cgd is preferably larger than 1, and more preferably 5 or more. Further, it is more preferable that the capacity ratio k is 11 or more.

  Next, a manufacturing method of the protection diodes 81 and 83 having the transistor TR1 will be described. FIG. 7 is a process diagram for explaining a method of manufacturing the transistor TR1, and shows a cross-sectional view taken along the line B-B ′ of FIG.

As a method for forming the transistor TR1 in the present embodiment, a general 5-photo process is used.
First, as shown in FIG. 7A, a gate electrode 85G made of a Mo / Al stack is formed on the substrate body 10A.
Next, as shown in FIG. 7B, a gate insulating film 85I made of a silicon nitride film is formed, and a channel silicon film 85C and an N + silicon film 85N are continuously formed. Thereafter, a channel silicon film 85C and an N + silicon film 85N are formed in an island shape.
Next, as shown in FIG. 7C, a source electrode 85S and a drain electrode 85D made of a Mo / Al stack are formed.
Next, as shown in FIG. 7D, the N + silicon film 85N is etched to perform source / drain separation. At this point, the transistor TR1 is basically operable.
Next, a protective layer 85P made of a silicon nitride film is formed, and contact holes CS and CG are formed (FIG. 7E). Further, a pixel electrode (transparent conductive film) 88 made of ITO is formed (FIG. 7F).
The plan view of the transistor TR1 is as shown in FIG.

As described above, according to the present embodiment, the built-in capacitor Cp can be formed in the protection diodes 81 and 83 by forming the source electrode 85S / drain electrode 85D. On the other hand, in the past, since the source electrode 85S / drain electrode 85D were connected by the transparent conductive film 88, the protective diode operated only after the last manufacturing.
In this embodiment, since it operates by capacitive coupling, it operates immediately after the source electrode / drain electrode separation of FIG. 7D, so electrostatic protection can be performed from an early stage of the process. It is possible to reduce defects caused by static electricity, static electricity defects, and Vth shift of TFTs.

(Second Embodiment of Protection Diode)
Next, a liquid crystal device according to a second embodiment of the invention will be described with reference to FIG.
Since only the structure of the protection diodes 81 and 83 is different between the present embodiment and the first embodiment, only the different portions will be described in this embodiment, and the same components will be denoted by the same reference numerals and described. Omitted.

As shown in FIG. 8, the protection diodes 81 and 83 of the present embodiment are different from the first embodiment in that an overcoat film 89 made of an acrylic resin is formed on the protection film 85P.
Next, a manufacturing method will be described with reference to FIG. Note that the process up to the separation of the source electrode / drain electrode up to FIG. 7D is the same as in the first embodiment.

Therefore, after the source / drain electrode separation shown in FIG. 7D, the protective film 85P is formed and the contact holes CS and CG are formed as shown in FIG. 9A.
Next, as shown in FIG. 9B, after the overcoat film 89 is formed, the contact holes CS and CG buried by the overcoat film 89 are formed again.
Next, as shown in FIG. 9C, a pixel electrode (transparent conductive film) 88 is formed.
As described above, also in this embodiment, the same effect as in the first embodiment can be obtained.

(Third embodiment of protection diode)
Next, a liquid crystal device according to a third embodiment of the invention will be described with reference to FIG.
Since only the structure of the protection diodes 81 and 83 is different between the present embodiment and the first embodiment, only the different portions will be described in this embodiment, and the same components will be denoted by the same reference numerals and described. Omitted.

Since the liquid crystal device of the present embodiment is a transflective type, the protection diodes 81 and 83 include a reflective region H and a transmissive region T. Accordingly, as shown in FIG. 10, the point that an overcoat film 89 is formed on the protective film 85P at a position corresponding to the reflective region H is different from the first embodiment.
In the reflective region H, a reflective metal such as Al is formed on the overcoat film 89.

Next, a manufacturing method will be described with reference to FIG. The formation of the protective film 85P up to FIG. 7E and the formation of the contact holes CS and CG are the same as those in the first embodiment.
Therefore, after forming the contact holes CS and CG of FIG. 7E, a pattern is formed on the contact holes CS and CG with the pixel electrode 88 made of ITO as shown in FIG. 11A.
Next, as shown in FIG. 11B, an overcoat film 89 made of an acrylic resin is formed. Next, the reflective electrode 90 is formed only in the reflective region H.
As described above, in this embodiment, the same effects as those of the first embodiment can be obtained, and a transflective liquid crystal device can be realized.

FIG. 3 is a circuit diagram of a liquid crystal panel of a liquid crystal display device according to an electro-optical device of the invention. The circuit diagram of the protection diode concerning a 1st embodiment of the present invention. The figure which shows the current-voltage characteristic of the protection diode which concerns on 1st Embodiment of this invention. The figure for demonstrating the parasitic capacitance of the protection diode which concerns on 1st Embodiment of this invention. The figure which shows the structure of the protection diode which concerns on 1st Embodiment of this invention. The figure which shows the current-voltage characteristic of the protection diode which concerns on 1st Embodiment of this invention. Process drawing explaining the manufacturing method of the protection diode which concerns on 1st Embodiment of this invention. The figure which shows the structure of the protection diode which concerns on 2nd Embodiment of this invention. Process drawing explaining the manufacturing method of the protection diode which concerns on 2nd Embodiment of this invention. The figure which shows the structure of the protection diode which concerns on 3rd Embodiment of this invention. Process drawing explaining the manufacturing method of the protection diode which concerns on 3rd Embodiment of this invention.

Explanation of symbols

60 liquid crystal panel (electro-optical device), 85S source electrode, 85D drain electrode, 85N N + silicon film (semiconductor layer), 85C channel silicon film (semiconductor layer), 85I gate insulating film, 85G gate electrode, 81, 83 protection diode, TR1, TR2 transistors (elements), Cp built-in capacitors (capacitors).

Claims (5)

A protective diode comprising an element comprising a source / drain electrode, a semiconductor layer having a channel region, and a gate electrode disposed opposite to the semiconductor layer via a gate insulating film,
A portion of the source / drain electrode and the gate electrode have a capacitance portion formed by overlapping with the gate insulating film;
Protection diode characterized by. The capacitance ratio of the capacitance portion to the parasitic capacitance in the element is greater than 1.
The protective diode according to claim 1. The capacitance ratio of the capacitance portion to the parasitic capacitance in the element is greater than 5,
The protective diode according to claim 1. A method for manufacturing a protection diode comprising an element comprising a source / drain electrode, a semiconductor layer having a channel region, and a gate electrode disposed opposite to the semiconductor layer via a gate insulating film,
Forming a capacitive part by overlapping at least one part of the source / drain electrodes with the gate electrode through the gate insulating film;
The manufacturing method of the protection diode characterized by these. An electro-optical device comprising an element comprising a source / drain electrode, a semiconductor layer having a channel region, and a gate electrode disposed opposite to the semiconductor layer via a gate insulating film,
Comprising the protection diode according to any one of claims 1 to 3,
An electro-optical device.

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