JP2006276582A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device allowing suppression of reduction in the numerical aperture of a pixel even when a visual characteristic is improved by pixel division. <P>SOLUTION: In each of a plurality of pixels P in the liquid crystal display device, an auxiliary capacitor C is divided into two sub-auxiliary capacitors C1, C2 connected in series and a liquid crystal capacitor L is divided into two sub liquid crystal capacitors L1, L2 to which capacity-divided voltages are applied by the two sub-auxiliary capacitors C1, C2. Thereby the pixel P is divided into two sub-pixels P1, P2 respectively corresponding to the two sub liquid crystal capacitors L1, L2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device in which a pixel having a thin film transistor for pixel switching (hereinafter referred to as TFT (Thin Film Transistor)) and a pixel electrode is divided into a plurality of subpixels.

In a liquid crystal display device, one pixel is divided into a plurality of sub-pixels, and by changing the voltage applied to the liquid crystal layer of each sub-pixel, good multi-gradation display is achieved with a wide viewing angle, improving the viewing angle characteristics This technique is well known as a conventional technique called a pixel division method. Such a pixel division method is realized, for example, by forming a control capacitor separately from the auxiliary capacitor in each pixel in a liquid crystal display device using TFTs as pixel switching elements (see, for example, Patent Document 1). .
JP 7-325322 A

  However, in the case where a control capacitor is formed in each pixel separately from the auxiliary capacitor as in the technique described in the above-mentioned patent document, a region where display light is emitted in the pixel by the amount of the control capacitor added in the pixel. Ratio (pixel aperture ratio) decreases, and there is a problem that bright display cannot be performed.

  In view of the above problems, an object of the present invention is to provide a liquid crystal display device capable of suppressing a decrease in pixel aperture ratio even when viewing angle characteristics are improved by pixel division.

  In order to solve the above-described problem, the present invention includes a plurality of pixels provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines, and the pixels are arranged through the thin film transistor for pixel switching. In a liquid crystal display device including a liquid crystal capacitor electrically connected to a data line and an auxiliary capacitor electrically connected in parallel to the liquid crystal capacitor, the auxiliary capacitor includes a plurality of sub auxiliary capacitors connected in series. The liquid crystal capacitor is divided into a plurality of sub liquid crystal capacitors to which a voltage divided by the plurality of sub auxiliary capacitors is applied, and the pixel corresponds to each of the plurality of sub auxiliary capacitors. It is characterized by being divided into sub-pixels.

  In the present invention, in order to improve the viewing angle characteristics by dividing a pixel into a plurality of sub-pixels, an auxiliary capacitor electrically connected in parallel to the liquid crystal capacitor is divided into a plurality of sub-auxiliary capacitors, and the plurality of auxiliary capacitors are used. The divided voltage is applied to a plurality of sub liquid crystal capacitors. For this reason, it is not necessary to add a control capacity in addition to the auxiliary capacity. Therefore, even when the viewing angle characteristic is improved by pixel division, it is possible to suppress a decrease in the pixel aperture ratio.

  In the present invention, the device substrate includes an element substrate and a counter substrate which are arranged to face each other with a liquid crystal layer interposed therebetween. The element substrate includes the scanning line, the data line, the TFT, the plurality of sub-auxiliary capacitors, and the plurality of sub-capacitors. A plurality of subpixel electrodes corresponding to the subpixels are formed, and a counter electrode constituting the plurality of sub liquid crystal capacitors is formed between each of the plurality of subpixel electrodes on the counter substrate. That is, the present invention can be applied to a liquid crystal display device using various liquid crystals other than the IPS mode (In-Plane Switching).

  Further, when a lateral electric field such as IPS mode is used, the scanning substrate, the data line, the TFT, And forming a plurality of sub-auxiliary capacitors, a plurality of sub-pixel electrodes corresponding to the plurality of sub-liquid crystal capacitors, and a common electrode constituting the plurality of sub-liquid crystal capacitors between each of the plurality of sub-pixel electrodes. Good.

  In the present invention, a plurality of insulating layers are stacked on the element substrate, and a conductive layer is formed in each of a lower layer, an interlayer, and an upper layer of the plurality of insulating layers. The lower conductive sub-capacitor formed on the lower layer side of the plurality of sub-auxiliary capacitors is configured such that two conductive layers facing each other across the insulating layer among the plurality of conductive layers are configured as a lower electrode and an upper electrode. The upper electrode and the lower electrode of the upper sub-capacitor formed above the lower sub-capacitor are preferably made of a common conductive layer. With this configuration, the number of conductive layers for forming a plurality of sub-auxiliary capacitors can be reduced, so that two sub-auxiliary capacitors can be formed only by a conductive layer formed simultaneously with a plurality of conductive layers constituting a TFT or the like. Even when a larger number of auxiliary storage capacitors are formed, the number of conductive layers to be added can be reduced. In addition, since the lower side sub-auxiliary capacitor and the upper layer side auxiliary auxiliary capacitor can be formed in a region overlapping in a planar manner, even when the viewing angle characteristic is improved by pixel division, it is possible to suppress a decrease in the pixel aperture ratio.

  In the present invention, the plurality of conductive layers constituting the plurality of auxiliary storage capacitors include a conductive layer formed at the same layer position as the gate electrode of the TFT and a conductive layer formed at the same layer position as the source electrode of the TFT. Preferably, the layer and all of the plurality of subpixel electrodes are included. With such a configuration, two sub-auxiliary capacitors can be formed by these conductive layers. Therefore, when the pixel is divided into two, no new conductive layer is required.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing to be referred to, the scale may be different for each layer or each member in order to make the size recognizable on the drawing.

[Embodiment 1]
(Basic configuration of liquid crystal display device)
FIG. 1 is a block diagram showing a basic electrical configuration of a liquid crystal display device using TFTs as pixel switching elements.

  A liquid crystal display device 1 shown in FIG. 1 is an active matrix liquid crystal display device using TFTs as pixel switching elements, and includes pixels P at respective positions corresponding to intersections of data lines 6a and scanning lines 3a. . Each of these pixels P is formed with a pixel switching TFT 30 for controlling the pixel electrode 9, and a data line 6 a for supplying an image signal is electrically connected to the source of the TFT 30. An image signal to be written to the data line 6 a is supplied from the data line driving circuit 102. The scanning line 3a is electrically connected to the gate of the TFT 30, and a scanning signal is supplied from the scanning line driving circuit 103 to the scanning line 3a in a pulsed manner at a predetermined timing. The pixel electrode 9 is electrically connected to the drain of the TFT 30, and by turning on the TFT 30 as a switching element for a certain period, an image signal supplied from the data line 6a is given to each pixel at a predetermined timing. Write in. Here, the pixel electrode 9 forms a liquid crystal capacitance L between the pixel electrode 9 and a counter electrode described later, and an image signal of a predetermined level written in the liquid crystal capacitance L via the pixel electrode 9 is held for a certain period. . In addition, an auxiliary capacitor C may be added in parallel with the liquid crystal capacitor L for the purpose of preventing the retained image signal from leaking. By this auxiliary capacitance C, the voltage of the pixel electrode 9 is held for a time that is three orders of magnitude longer than the time when the source voltage is applied, for example. As a result, the charge retention characteristics of the liquid crystal capacitor L are improved, and an electro-optical device capable of performing display with a high contrast ratio can be realized. As a method of forming the auxiliary capacitor C, in addition to using the capacitor line 3b, an extended portion from the preceding scanning line 3a can be used. In the following description, a configuration using the capacitor line 3b is used. Will be explained.

(Pixel configuration)
2, 3 and 4 are equivalent circuit diagrams of one pixel of the liquid crystal display device according to the first embodiment of the present invention, a cross-sectional view of one pixel of the liquid crystal display device, and a pixel of the element substrate. It is a top view for one. 3 corresponds to a cross-sectional view taken along line A1-B1 of FIG. Also, in FIG. 4, a conductive film formed simultaneously with the data line is given a slanting line rising to the right, and a conductive film formed simultaneously with the scanning line is given a slanting line descending to the right. The pixel electrode is indicated by a one-dot chain line.

  As shown in FIG. 2, in this embodiment, the auxiliary capacitor C is divided into two auxiliary auxiliary capacitors C1 and C2 connected in series, and the liquid crystal capacitor L is divided by two auxiliary auxiliary capacitors C1 and C2. The sub-liquid crystal capacitors L1 and L2 to which a voltage is applied are divided. Accordingly, the pixel P is divided into two sub-pixels P1 and P2 corresponding to the two sub-liquid crystal capacitors L1 and L2, respectively. Of the two sub liquid crystal capacitors L1 and L2, the first sub liquid crystal capacitor L1 is electrically connected in parallel to the auxiliary capacitor C including the two sub auxiliary capacitors C1 and C2, and the second sub liquid crystal capacitor L2 is Of the two auxiliary auxiliary capacitors C1, C2, the second auxiliary auxiliary capacitor C2 is electrically connected in parallel.

  In the liquid crystal display device 1 configured as described above, when the TFT 30 is turned on, the potential of the data line 6a is divided by the first sub auxiliary capacitor C1 and the second sub auxiliary capacitor C2, and the second sub auxiliary capacitor C2. The second sub liquid crystal capacitor L2 is applied with a lower potential than the first sub auxiliary capacitor C1 and the first sub liquid crystal capacitor L2 formed in the same pixel P. Therefore, the viewing angle characteristics of the first sub-pixel P1 corresponding to the first sub-liquid crystal capacitor L1 and the viewing-angle characteristics of the second sub-pixel P2 corresponding to the second sub-liquid crystal capacitor L2 complement each other. The characteristics are improved.

  In configuring the liquid crystal display device 1 of the present embodiment, as shown in FIG. 3, the element substrate 10 and the counter substrate 20 are arranged to face each other, and the liquid crystal layer 2 is held between these substrates. In this embodiment, all liquid crystals other than the IPS mode described later, for example, TN liquid crystal, ECB mode liquid crystal, guest host type liquid crystal, and vertically aligned liquid crystal are used for the liquid crystal layer 2. A counter electrode 21 made of an ITO layer and an alignment film 22 are formed in this order.

  The planar configuration of the element substrate 10 in such a liquid crystal display device 1 is expressed as shown in FIG. 4. The scanning line 3 a is formed in a direction intersecting with the data line 6 a, and the capacitance is formed in parallel with the scanning line 3 a. A line 3b is formed. The data line 6a is formed integrally with the source electrode 6b of the TFT 30, and the scanning line 3a is formed integrally with the gate electrode 3c of the TFT 30.

  A control electrode 6c is formed in a region overlapping the capacitor line 3b in a plan view, and a second auxiliary storage capacitor C2 is formed between the control electrode 6 and the capacitor line 3b.

  A first subpixel electrode 91 for forming the first subpixel P1 (first subliquid crystal capacitor L1) is electrically connected to the drain region of the TFT 30 via the drain electrode 6d. A part of the sub-pixel electrode 91 overlaps the control electrode 6c in plan view to form a first sub-auxiliary capacitor C1. Further, a second subpixel electrode 92 for forming the second subpixel P2 (second subliquid crystal capacitor L2) is formed in the pixel P, and the second subpixel electrode 92 is connected to the control electrode 6c. Are connected to each other through a contact hole 42b.

  As shown in FIG. 3, the cross-sectional configuration of the element substrate 20 configured in this way is as follows. From the lower layer side to the upper layer side of the element substrate 10, the gate electrode 3c of the TFT 30, a silicon nitride film having a thickness of about 300 nm, and the like. A gate insulating film 41, a semiconductor film 5 made of a silicon film having a thickness of about 150 nm, a source electrode 6 b, an interlayer insulating film 42 made of a silicon nitride film having a thickness of about 180 nm, the pixel electrode 9, and an alignment film 19. It has a laminated structure. Capacitor lines 3b are formed at the same layer position as the gate electrode 3c (under the gate insulating film 41). Each of these conductive layers is, for example, an aluminum layer having a thickness of about 250 nm and a thickness of about 250 nm. It is comprised as a laminated body with a molybdenum layer. Further, a drain electrode 6d and a control electrode 6c are formed at the same layer position as the source electrode 6b (between the gate insulating film 41 and the interlayer insulating film 42). The laminate is composed of a 250 nm aluminum layer and a molybdenum layer having a thickness of about 250 nm. Further, a first subpixel electrode 91 and a second subpixel electrode 92 are formed as the pixel electrode 9 on the upper layer side of the interlayer insulating film 42, and both of these conductive layers have a thickness of, for example, about It is made of 50 nm ITO.

  The first subpixel electrode 91 is electrically connected to the drain electrode 6d through the contact hole 42a in the interlayer insulating film 42, and the second subpixel electrode 92 is connected through the contact hole 42b in the interlayer insulating film 42. It is electrically connected to the control electrode 6c. In the region of the semiconductor film 5 in contact with the source electrode 6b and the region in contact with the drain region, high-concentration n-type semiconductor layers 51 and 52 having a thickness of about 50 nm are formed. .

  In the liquid crystal display device 1 configured as described above, the capacitor line 3b, the gate insulating film 41, the control electrode 6c, the interlayer insulating film 42, and the first subpixel electrode 91 are stacked in a region overlapping in a plane. Therefore, the storage capacitor C is formed between the capacitor line 3b and the first subpixel electrode 91, and the storage capacitor C is divided into the first sub storage capacitor C1 and the second sub storage capacitor C2. Has been. Here, the second sub-auxiliary capacitor C2 has the capacitor line 3b as a lower electrode, the gate insulating film 41 as a dielectric layer, and the control electrode 6c as an upper electrode, and the first sub-auxiliary capacitor C1 has a control electrode. 6c is a lower electrode, the interlayer insulating film 42 is a dielectric layer, and the first subpixel electrode 91 is an upper electrode.

  Therefore, when the second sub-auxiliary capacitor C2 is a lower-layer side sub-auxiliary capacitor and the first sub-auxiliary capacitor C1 is regarded as an upper-layer side sub-auxiliary capacitor, The upper electrode and the lower electrode of the upper sub-capacitor (first sub-auxiliary capacitor C1) are configured by a common conductive layer (control electrode 6c).

  Further, in the liquid crystal display device 1 of the present embodiment, the first sub liquid crystal capacitor L1 is configured between the first sub pixel electrode 91 and the counter electrode 21, and the second sub pixel electrode 92 and the counter electrode 21 are A second sub liquid crystal capacitor L2 is formed therebetween. Here, since the capacitor line 3b is held at the same potential as the counter electrode 21, the electrical connection between the sub liquid crystal capacitors 91 and 92 and the sub auxiliary capacitors C1 and C2 will be described with reference to FIG. As you did.

(Production method)
In manufacturing such a liquid crystal display device 1, the element substrate 10 generally includes the following processes: a process for forming a gate electrode 3 c and a capacitor line 3 b, a process for forming a gate insulating film 41, a process for forming a semiconductor film 5, a high concentration n-type semiconductor layer 51, 52 formation process Source electrode 6b, control electrode 6c, drain electrode 6c formation process Interlayer insulating film 42 formation process Contact hole 42a, 42b formation process Subpixel electrodes 91, 92 can be formed by the formation process. As in the case where no division is performed, five photolithography steps are sufficient. That is, the liquid crystal display device 1 employing pixel division can be manufactured by only partially changing the mask pattern used in the photolithography process.

(Effect of this embodiment)
As described above, in the present embodiment, when performing pixel division, the auxiliary capacitor C electrically connected in parallel to the liquid crystal capacitor L is divided into a plurality of sub auxiliary capacitors C1 and C2, and a plurality of sub auxiliary capacitors C1. , The voltage divided by C2 is applied to the plurality of sub liquid crystal capacitors L1 and L2, so that it is not necessary to add a control capacitor in addition to the auxiliary capacitor C. Therefore, even when the viewing angle characteristic is improved by pixel division, it is possible to suppress a decrease in the pixel aperture ratio.

  In addition, each of the two sub auxiliary capacitors C1 and C2 includes two conductive layers opposed to each other with the insulating layer interposed therebetween as a lower electrode and an upper electrode, and the lower sub auxiliary capacitor (second sub auxiliary capacitor C2). The upper electrode and the lower electrode of the upper sub-capacitor (first sub-auxiliary capacitor C1) are configured by a common conductive layer (control electrode 6c). Therefore, the number of conductive layers for forming the two auxiliary auxiliary capacitors C1 and C2 can be reduced. Therefore, the two auxiliary auxiliary capacitors C1 and C2 are formed only by the conductive layer formed simultaneously with the plurality of conductive layers forming the TFT 30 and the like. Can be configured. Further, since the lower layer side auxiliary auxiliary capacitor (second auxiliary auxiliary capacitor C2) and the upper layer side auxiliary auxiliary capacitor (first auxiliary auxiliary capacitor C1) can be formed in a planarly overlapping region, the viewing angle characteristics can be improved by pixel division. Even in the case of improvement, a decrease in pixel aperture ratio can be suppressed.

[Embodiment 2]
5, 6 and 7 are equivalent circuit diagrams of one pixel of the liquid crystal display device according to the second embodiment of the present invention, a sectional view of one pixel of the liquid crystal display device, and a pixel of the element substrate. It is a top view for one. 6 corresponds to a cross-sectional view taken along line A2-B2 of FIG. Further, in FIG. 7, a conductive film formed simultaneously with the data line is given a slanting line rising to the right, and a conductive film formed simultaneously with the scanning line is given a slanting line descending to the right. The pixel electrode is indicated by a one-dot chain line. Since the basic structure of the liquid crystal display device of this embodiment is the same as that of Embodiment Mode 1, portions having common functions are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 5, the liquid crystal display device 1 of this embodiment includes a liquid crystal capacitor L and an auxiliary capacitor C in each of a plurality of pixels P, and the auxiliary capacitor C includes three sub auxiliary capacitors connected in series. The liquid crystal capacitor L is divided into three sub liquid crystal capacitors L1, L2, and L3 to which voltages divided by the three sub auxiliary capacitors C1, C2, and C3 are applied. Accordingly, the pixel P is divided into three sub-pixels P1, P2, and P3 corresponding to the three sub-liquid crystal capacitors L1, L2, and L3, respectively. Of the three sub-liquid crystal capacitors L1, L2, and L3, the first sub-liquid crystal capacitor L1 is electrically connected in parallel to a capacitor that is a combination of the three sub-auxiliary capacitors C1, C2, and C3. The capacitor L2 is electrically connected in parallel to the combined capacitor of the two auxiliary auxiliary capacitors C2 and C3, and the third auxiliary liquid crystal capacitor L3 is electrically connected in parallel to the third auxiliary auxiliary capacitor C3. Is in a state of being.

In the liquid crystal display device 1 configured as described above, when the TFT 30 is turned on, the potential of the data line 6a is divided by the three sub auxiliary capacitors C1, C2, and C3. C3 and the third sub liquid crystal capacitance L3
<Second sub-auxiliary capacitor C2 and second sub-liquid crystal capacitor L2
<First Sub-Auxiliary Capacitor C1 and First Sub-Liquid Crystal Capacitor L1
Will be applied.

  As described above, in this embodiment, when performing pixel division, the auxiliary capacitor C electrically connected in parallel to the liquid crystal capacitor L is divided into a plurality of sub auxiliary capacitors C1, C2, and C3, and a plurality of sub auxiliary capacitors C1, Since the voltage divided by C2 and C3 is applied to the plurality of sub liquid crystal capacitors L1, L2, and L3, it is not necessary to add a control capacitor in addition to the auxiliary capacitor C. Therefore, even when the viewing angle characteristic is improved by pixel division, it is possible to suppress a decrease in the pixel aperture ratio.

  In configuring the liquid crystal display device 1 of the present embodiment, as shown in FIG. 6, the element substrate 10 and the counter substrate 20 are arranged to face each other, and the liquid crystal layer 2 is held between these substrates. In this embodiment, since all liquid crystals other than the IPS mode described later are used for the liquid crystal layer 2, the counter substrate 20 is formed with the counter electrode 21 made of an ITO layer and the alignment film 29 in this order.

  The planar configuration of the element substrate 10 in the liquid crystal display device 1 is expressed as shown in FIG. The configuration of the data line 6a, the scanning line 3a, the TFT 30 and the like is the same as that of the first embodiment, and thus the description thereof is omitted. However, the first control electrode 6c is formed in a region overlapping the capacitor line 3b in plan view. Thus, a third auxiliary storage capacitor C3 is formed. A second control electrode 7c is formed in a region overlapping the first control electrode 6c in a plan view, and a second auxiliary storage capacitor C2 is formed.

  Here, a first subpixel electrode 91 is electrically connected to the pixel P in order to form a first subpixel P1 (first subliquid crystal capacitor L1). A part of the second control electrode 7c overlaps with the second control electrode 7c to form a first sub-auxiliary capacitor C1. In addition, the pixel P is provided with a second subpixel electrode 92 for forming the second subpixel P2 (second subliquid crystal capacitor L2), and the second subpixel electrode 92 includes the second subpixel electrode 92. The control electrode 4c is connected via a contact hole 43b. Further, a third subpixel electrode 93 for forming the third subpixel P3 (third subliquid crystal capacitor L3) is formed in the pixel P, and the third subpixel electrode 92 includes the first subpixel electrode 92. The control electrode 6c is connected via a contact hole 43c.

  As shown in FIG. 7, the cross-sectional configuration of the element substrate 20 configured as described above includes a gate electrode 3c of the TFT 30 and a silicon nitride film having a thickness of about 300 nm from the lower layer side to the upper layer side of the element substrate 10. A gate insulating film 41, a semiconductor film 5 made of a silicon film having a thickness of about 150 nm, a source electrode 6b, a first interlayer insulating film 42 made of a silicon nitride film having a thickness of about 180 nm, and a second control electrode. 7c, a second interlayer insulating film 43 made of a silicon nitride film having a thickness of about 180 nm, the pixel electrode 9, and the alignment film 19 are laminated.

  Here, at the same layer position as the gate electrode 3c (under the gate insulating film 41), the capacitor line 3b is formed. Each of these conductive layers has, for example, an aluminum layer having a thickness of about 250 nm, Is configured as a laminate with a molybdenum layer of about 250 nm. In addition, a drain electrode 6d and a first control electrode 6c are formed at the same layer position as the source electrode 6b (between the gate insulating film 41 and the interlayer insulating film 42). The laminate is composed of an aluminum layer having a thickness of about 250 nm and a molybdenum layer having a thickness of about 250 nm. Further, on the upper layer side of the interlayer insulating film 42, a first subpixel electrode 91, a second subpixel electrode 92, and a third subpixel electrode 93 are formed as the pixel electrode 9, and these conductive layers are Both are made of, for example, ITO having a thickness of about 50 nm. The second control electrode 7c is also configured, for example, as a laminate of an aluminum layer having a thickness of about 250 nm and a molybdenum layer having a thickness of about 250 nm.

  The first subpixel electrode 91 is electrically connected to the drain electrode 6 d through the contact hole 43 a of the interlayer insulating films 42 and 43, and the second subpixel electrode 92 is a contact with the second interlayer insulating film 43. The third subpixel electrode 93 is electrically connected to the first control electrode 6c through the contact hole 43c of the interlayer insulating films 42 and 43, and is electrically connected to the second control electrode 7c through the hole 43b. Connected.

  In the liquid crystal display device 1 configured as described above, the capacitor line 3b, the gate insulating film 41, the first control electrode 6c, the first interlayer insulating film 42, the second control electrode 7c, the second interlayer insulating film 43, The first subpixel electrodes 91 are stacked in a region overlapping in a plane. Accordingly, a storage capacitor C is formed between the capacitor line 3b and the first subpixel electrode 91, and the storage capacitor C is divided into three sub auxiliary capacitors C1, C2, and C3. Here, the third auxiliary storage capacitor C3 has the capacitor line 3b as a lower electrode, the gate insulating film 41 as a dielectric layer, the first control electrode 6c as an upper electrode, and the second auxiliary storage capacitor C1. The first control electrode 6c is a lower electrode, the interlayer insulating film 42 is a dielectric layer, the second control electrode 7c is an upper electrode, and the first sub-auxiliary capacitor C1 has the second control electrode 7c as a second electrode. The lower electrode, the second interlayer insulating film 43 is a dielectric layer, and the first subpixel electrode 91 is an upper electrode. Accordingly, since the auxiliary auxiliary capacitance located on the lower layer side and the auxiliary auxiliary capacitance located on the upper layer side share the electrode, even when the three auxiliary auxiliary capacitances C1, C2, and C3 are formed, the conductive layer is Less is enough. In addition, since the three auxiliary storage capacitors C1, C2, and C3 can be formed in a region that overlaps in a planar manner, even when the viewing angle characteristics are improved by pixel division, it is possible to suppress a decrease in the pixel aperture ratio.

[Embodiment 3]
FIG. 8 is a plan view of the liquid crystal display device according to the third embodiment of the present invention. The conductive film formed simultaneously with the data lines is shown with a diagonal line rising to the right and formed simultaneously with the scanning lines. The conductive film is shown with a slanting line to the right and the pixel electrode is shown with a one-dot chain line.

  In the liquid crystal display device 1 of the present embodiment, as described with reference to FIG. 2 in the first embodiment, the auxiliary capacitor C is divided into two sub auxiliary capacitors C1 and C2 connected in series, and the liquid crystal capacitor L Is divided into two sub liquid crystal capacitors L1 and L2 to which a voltage divided by two sub auxiliary capacitors C1 and C2 is applied. Accordingly, the pixel P is divided into two sub-pixels P1 and P2 corresponding to the two sub-liquid crystal capacitors L1 and L2, respectively.

  In configuring the liquid crystal display device 1 of the present embodiment, the element substrate and the counter substrate are arranged to face each other, and a liquid crystal layer is held between these substrates. In this embodiment, since an IPS (In-Plane Switching) mode liquid crystal is used for the liquid crystal layer, a counter electrode made of an ITO layer is formed on the counter substrate, but no alignment film is formed. .

  In such a liquid crystal display device 1, the cross-sectional configuration for configuring the auxiliary storage capacitors C1 and C2 on the element substrate 10 is substantially the same as in the first embodiment, but in the IPS mode, a horizontal electric field is applied to the liquid crystal. In order to apply, it is necessary to also form the common electrode facing the subpixel electrodes 91 and 92 constituting the sub liquid crystal capacitors L1 and L2 (subpixels P1 and P2) on the element substrate 20. Therefore, in the liquid crystal display device 1 of this embodiment, the element substrate 10 has a planar configuration shown in FIG.

  In FIG. 8, a scanning line 3a is formed in a direction crossing the data line 6a, and a capacitor line 3b is formed in parallel with the scanning line 3a. The data line 6a is formed integrally with the source electrode 6b of the TFT 30, and the scanning line 3a is formed integrally with the gate electrode 3c of the TFT 30. A control electrode 6c is formed in a region overlapping the capacitor line 3b in a plan view, and a second sub-auxiliary capacitor C2 is formed between the control electrode 6 and the capacitor line 3b. A first subpixel electrode 91 for forming the first subpixel P1 (first subliquid crystal capacitor L1) is electrically connected to the drain region of the TFT 30 via the drain electrode 6d. A part of the sub-pixel electrode 91 overlaps the control electrode 6c in plan view to form a first sub-auxiliary capacitor C1. Further, a second subpixel electrode 92 for forming the second subpixel P2 (second subliquid crystal capacitor L2) is formed in the pixel P, and the second subpixel electrode 92 is connected to the control electrode 6c. Are connected to each other through a contact hole 42b.

  In this embodiment, a part of the capacitor line 3b is formed in a comb-like shape, and a comb-like common electrode 3f is formed. Further, the first subpixel electrode 91 and the second subpixel electrode 92 are comb-shaped toward the comb-shaped common electrode 3f so as to face the comb-shaped common electrode 3f in the lateral direction. Is formed. Accordingly, the first sub-liquid crystal capacitor L1 (first sub-pixel P2) is formed between the first sub-pixel electrode 91 and the common electrode 3f, and between the second sub-pixel electrode 92 and the common electrode 3f. The second sub liquid crystal capacitor L2 (first sub pixel P2) is formed. In the present embodiment, the first sub-pixel electrode 91 is formed with a rectangular portion at the tip of the comb-tooth portion so as to overlap the control electrode 6c in a plan view to form the first sub-auxiliary capacitor C1. .

  Even in the IPS mode liquid crystal display device 1 configured as described above, when performing pixel division, the auxiliary capacitor C that is electrically connected in parallel to the liquid crystal capacitor L is divided into a plurality of sub auxiliary capacitors C1 and C2. Since the voltage divided by the auxiliary auxiliary capacitors C1 and C2 is applied to the plurality of auxiliary liquid crystal capacitors L1 and L2, there is no need to add a control capacitor in addition to the auxiliary capacitor C. Therefore, even when the viewing angle characteristic is improved by pixel division, the same effects as those of the first embodiment can be obtained, such as the reduction in the pixel aperture ratio can be suppressed.

  In this embodiment, the IPS mode is used. However, the present invention is not limited to this, and FFS (Fringe Field Switching) using a horizontal electric field can be used in the same manner.

[Example of mounting on electronic devices]
The electro-optical device to which the present invention is applied includes a personal computer (PC), an engineering work station (EWS), a pager, a word processor, a television, a viewfinder type or a monitor in addition to a mobile phone or a mobile personal computer. In addition to being applicable to electronic devices such as direct-view video tape recorders, electronic notebooks, electronic desk calculators, car navigation devices, POS terminals, touch panels, etc., they are used to construct electronic devices with large screens exceeding 30 inches. You can also.

It is a block diagram which shows the basic electrical constitution of the liquid crystal display device using TFT as a pixel switching element. FIG. 2 is an equivalent circuit diagram for one pixel of the liquid crystal display device according to the first embodiment of the present invention. It is sectional drawing for one pixel of the liquid crystal display device which concerns on Embodiment 1 of this invention. FIG. 3 is a plan view for one pixel of the liquid crystal display device according to Embodiment 1 of the present invention. It is an equivalent circuit diagram for one pixel of the liquid crystal display device according to the second embodiment of the present invention. It is sectional drawing for one pixel of the liquid crystal display device which concerns on Embodiment 2 of this invention. It is a top view for one pixel of the liquid crystal display device which concerns on Embodiment 2 of this invention. It is a top view for 1 pixel of the liquid crystal display device which concerns on Embodiment 3 of this invention.

Explanation of symbols

1 .... Liquid crystal display device 2 .... Liquid crystal layer 3a ... Scanning line 3b ... Capacitor line 3c ... Gate electrode 3f ... Comb-like common electrode 5 .... Semiconductor film 6a ... Data line, 6b ... Source electrode, 6c, 7c ... Control electrode, 6d ... Drain electrode, 9 ... Pixel electrode, 10 ... Element substrate, 20 counter substrate, 21 counter electrode, 30 ... TFT, 41 ... Gate insulating film 42, 43 Interlayer insulating film 91, 92, 93 Subpixel electrode C, auxiliary capacitance C1, C2, C3 sub auxiliary capacitance L liquid crystal capacitance L1, L2, L3, sub liquid crystal capacitance, P, pixel, P1, P2, P3, sub pixel

Claims (5)

A plurality of pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines, the pixels including a liquid crystal capacitor electrically connected to the data lines via a pixel switching thin film transistor; In a liquid crystal display device comprising an auxiliary capacitor electrically connected in parallel to the liquid crystal capacitor,
The auxiliary capacity is divided into a plurality of sub auxiliary capacity connected in series,
The liquid crystal capacitor is divided into a plurality of sub liquid crystal capacitors to which a voltage divided by the plurality of sub auxiliary capacitors is applied,
The liquid crystal display device, wherein the pixel is divided into a plurality of sub-pixels corresponding to each of the plurality of sub-auxiliary capacitors. It has an element substrate and a counter substrate that are arranged to face each other with a liquid crystal layer interposed therebetween,
A plurality of subpixel electrodes corresponding to the scanning lines, the data lines, the thin film transistors, the plurality of sub-auxiliary capacitors, and the plurality of subpixels are formed on the element substrate,
2. The liquid crystal display device according to claim 1, wherein a counter electrode constituting the plurality of sub-liquid crystal capacitors is formed between the counter substrate and each of the plurality of sub-pixel electrodes. It has an element substrate and a counter substrate that are arranged to face each other with a liquid crystal layer interposed therebetween,
The element substrate includes the scanning line, the data line, the thin film transistor, the plurality of sub-auxiliary capacitors, a plurality of sub-pixel electrodes corresponding to the plurality of sub-pixels, and each of the plurality of sub-pixel electrodes. The liquid crystal display device according to claim 1, wherein a common electrode constituting the plurality of sub liquid crystal capacitors is formed on the liquid crystal display device. A plurality of insulating layers are laminated on the element substrate, and a conductive layer is formed in each of the lower layer, the interlayer and the upper layer of the plurality of insulating layers,
Each of the plurality of sub-auxiliary capacitors is configured with two conductive layers facing each other across an insulating layer among the plurality of conductive layers as a lower electrode and an upper electrode,
Of the plurality of sub-auxiliary capacitors, an upper electrode of a lower layer side auxiliary auxiliary capacitor formed on the lower layer side and a lower electrode of the upper layer side auxiliary auxiliary capacitor formed on the upper layer of the lower layer side sub auxiliary capacitor are common. The liquid crystal display device according to claim 2, comprising a conductive layer.   The plurality of conductive layers constituting the plurality of auxiliary storage capacitors include a conductive layer formed in the same layer position as the gate electrode of the thin film transistor, a conductive layer formed in the same layer position as the source electrode of the thin film transistor, and the The liquid crystal display device according to claim 4, wherein all of the plurality of subpixel electrodes are included.

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