JP2013223204A - Analog signal reproduction device and analog signal reproduction method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid an unexpected signal output by the storage of frequency errors concerning analog signal reproduction.SOLUTION: A demodulation unit 2 demodulates sound data from sampling data input from an A/D conversion unit 5, and inputs the data to a sound reproduction unit 7. The demodulation unit 2 extracts a symbol clock from sampling data generated in the A/D conversion unit 5, and inputs a symbol clock to a reproduction clock generation unit 6. The reproduction clock generation unit 6 generates a reproduction clock for reproducing digital sound in synchronization with the timing of a symbol clock, and supplies the reproduction clock to the sound reproduction unit 7. The sound reproduction unit 7 reproduces a sound signal (analog) from sound data (digital) at the timing of a reproduction clock input from the reproduction clock generation unit, and outputs the signal.

Description

  The present invention relates to an analog signal reproduction device and an analog signal reproduction method for reproducing an analog signal from a digital signal obtained by demodulating a received digital modulation signal.

  In a digital radio, an audio signal is sampled at a predetermined frequency, converted into a digital value, and transmitted after being digitally modulated (amplitude shift modulation, frequency shift modulation or phase shift modulation). On the receiving side, the demodulated digital value is DA-converted at the same frequency as that on the transmitting side to reproduce sound.

  In digital modulation / demodulation, the symbol value may not be correctly reproduced due to the jitter of the symbol clock. In view of this, an error from the transmission side is corrected while shifting the timing of the symbol clock in the symbol reproduction unit on the reception side (see, for example, cited document 1).

JP 2010-41139 A

  However, the operation rate of D / A conversion for outputting analog audio on the reception side is not synchronized with the clock for generating the sampling rate on the transmission side, and the sampling rates on the transmission side and the reception side do not exactly match. . When voice communication is performed in real time with a digital radio, an error occurs between the input data rate from the symbol reproduction unit (or decoding unit) (transmission side rate) and the output data rate of DA conversion, and the accumulated error May cause noise and overflow.

  When analog signals are transmitted digitally, encoding input / decoding output is performed at the respective reference frequencies on the encoding side and decoding side, so that errors are accumulated and the buffer overflows on the receiving side or output in reverse. In such a case, the buffer is already empty or data is excessive or insufficient, and an unexpected signal may be output at that time.

  The present invention has been made in view of the above circumstances, and an object thereof is to avoid an unexpected signal output due to accumulation of frequency errors in analog signal reproduction.

In order to achieve the above object, an analog signal reproducing device according to the first aspect of the present invention provides:
A symbol that defines the sampling timing when a demodulated signal having an amplitude corresponding to a frequency or phase shift in the modulated wave is sampled at a predetermined symbol point and demodulated data is generated from the amplitude value of the obtained symbol data A clock recovery unit for recovering the clock;
A demodulator for demodulating the symbol data at the timing of the symbol clock recovered by the clock recovery unit to generate demodulated data;
A clock generation unit for generating a recovered clock for converting the demodulated data into an analog signal in synchronization with the timing of the symbol clock;
A signal reproducing unit for reproducing an analog signal from the demodulated data at a timing of a reproduction clock generated by the clock generation unit;
It is characterized by providing.

  Preferably, the clock generation unit starts counting the reproduction clock using the symbol clock as a trigger, and is required for processing from inputting the demodulated data from the demodulation unit to reproducing an analog signal by the signal reproduction unit. The reproduction clock is generated by delaying time.

Preferably, the clock reproduction unit is
A timer for generating the symbol clock;
An oversampling unit that oversamples the demodulated signal at a frequency higher than the symbol clock;
Among the sampling data obtained by the oversampling, the predetermined symbol point and the sampling data of the predetermined symbol point and the symbol point to be obtained for the sampling data of a total of three points including the two points before and after the symbol point. An arithmetic unit for calculating a deviation between the sampling level of the predetermined symbol point and the sampling data of the two preceding and following points,
A selection unit that selects a correction direction of the symbol clock based on the deviation and the difference;
A timing correction unit that moves the sampling timing of symbol points in the correction direction selected by the selection unit to the timer;
It is characterized by providing.

  Preferably, the timing correction unit causes the timer to sample the symbol point at a time corresponding to the deviation in proportion to an average slope of sampling data at the scheduled symbol point calculated from the difference. It is characterized by moving.

  Preferably, the timer is reset at the detection timing of the symbol clock from the synchronous word pattern detector.

Preferably, the synchronous word pattern detector detects a DC offset caused by a transmission / reception frequency shift by detecting the symbol clock,
A subtractor for correcting the DC offset from the demodulated signal input to the computing means;
It is characterized by that.

An analog signal reproduction method according to a second aspect of the present invention is:
An analog signal reproduction method performed by an analog signal reproduction device that reproduces an analog signal from demodulated data obtained by demodulating a received modulated wave,
The demodulated signal having an amplitude corresponding to the frequency or phase shift in the modulated wave is sampled at a predetermined symbol point, and when generating demodulated data from the amplitude value of the obtained symbol data, the sampling timing is defined. A clock recovery step for recovering the symbol clock;
A demodulation step of demodulating the symbol data at the timing of the symbol clock recovered in the clock recovery step to generate demodulated data;
A clock generation step of generating a recovered clock for converting the demodulated data into an analog signal in synchronization with the timing of the symbol clock;
A signal reproduction step of reproducing an analog signal from the demodulated data at the timing of the reproduction clock generated in the clock generation step;
It is characterized by providing.

  According to the present invention, the difference between the input data rate and the output data rate for DA conversion can be eliminated, and unexpected signal output due to accumulation of frequency errors can be avoided.

It is a block diagram which shows the structural example of the analog signal reproducing | regenerating apparatus which concerns on embodiment of this invention. It is a figure explaining the noise generation of the audio | voice output by a frequency error. It is a block diagram which shows the structural example of the demodulation part which concerns on embodiment. It is a block diagram which shows the structural example of the synchronous word detection part which concerns on embodiment. It is a block diagram which shows the structural example of the symbol reproducing part which concerns on embodiment. It is a figure explaining the correction | amendment of the symbol clock which concerns on embodiment. It is a block diagram which shows the structural example of the audio | voice reproduction | regeneration part and reproduction | regeneration clock generation part which concern on embodiment. It is a figure explaining the production | generation of the analog signal reproduction clock which concerns on embodiment. It is a flowchart which shows an example of the operation | movement of the analog signal reproduction | regeneration which concerns on embodiment.

  FIG. 1 is a block diagram showing a configuration example of an analog signal reproducing device according to an embodiment of the present invention. The analog signal reproduction device 1 includes an antenna 3, a frequency conversion / amplification unit 4, an A / D conversion unit 5, a demodulation unit 2, a reproduction clock generation unit 6, and an audio reproduction unit 7. A signal received by the antenna 3 is converted into an intermediate frequency signal by the frequency conversion / amplification unit 4 and amplified, and then input to the AD conversion unit 5. In the A-D converter 5, the input signal is converted into a digital value with a rate of 96 ksps (sample per second), for example, and input to the demodulator 2.

  The demodulator 2 is composed of a DSP (digital signal processor) or the like, demodulates the audio data from the sampling data input from the AD converter 5 and inputs the demodulated data to the audio reproducer 7. Further, the demodulator 2 extracts a symbol clock from the sampling data, and inputs the symbol clock to the regenerated clock generator 6. The reproduction clock generation unit 6 generates a reproduction clock for reproducing digital audio in synchronization with the timing of the symbol clock and supplies the reproduction clock to the audio reproduction unit 7. The audio reproduction unit 7 reproduces and outputs an audio signal (analog) from the audio data (digital) at the timing of the reproduction clock input from the reproduction clock generation unit 6.

  In general, in a digital wireless device, sound, which is an analog signal, is converted into digital data, and a carrier wave is modulated using the data as a modulation signal and transmitted. Then, the receiver demodulates the received signal, extracts (decodes) a digital signal from the demodulated waveform, and further performs DA conversion to reproduce the sound.

  The accuracy of the sampling rate when the analog signal is digitized depends on the accuracy of the clock that is supplied to the IC that mainly processes (A-D conversion) the DSP. The accuracy of the clock varies slightly depending on the individual device. That is, when a digital signal having a certain sampling rate is generated, a sampling rate error Δx is included.

  The analog signal is encoded every certain sampling period Ts. The encoding unit generates digital data in accordance with the sampling clock period. At this time, processing is performed assuming that the clock has a specified period Ts. Conversely, in decoding, a specific number of data is decoded at a specific time interval.

  This sampling rate depends on the supply clock to the DSP on the transmission side and has an error of the supply clock. In order to reproduce an analog signal from a digital signal, a clock having the same cycle as the sampling rate for generating the digital signal is required. However, since the reproduced sound is output from a DA converter that depends on the clock supplied to the DSP on the receiving side, it is reproduced at a different period from the AD conversion clock on the transmitting side. . The error is gradually accumulated due to the difference in accuracy between the AD conversion clock and the DA conversion clock.

  FIG. 2 is a diagram for explaining generation of noise in audio output due to frequency error. For example, when the clock of the DA converter is slightly faster than the time (sampling rate) determined by the decoding unit (transmission side), the data input to the DA converter gradually disappears. Eventually nothing can be output. In this case, if there is no data, the same value as previously output or the same difference value as the previous difference, or random data or silence data may be output, and it may sound like noise has occurred. is there. Conversely, when the operation of the DA converter is slower, data accumulates in the buffer, causing overflow. Since the overflowed data is lost, even in this case, it may sound like noise has occurred due to data discontinuity due to data loss.

  This problem occurs because there is an error between the clock that is the reference of the audio output and the symbol clock, although the symbol reproduction is correct. Therefore, in the present embodiment, the reference clock for the output of the DA converter is synchronized with the symbol clock of the demodulator 2 that can normally reproduce the symbol, so that the decoder and the DA converter are synchronized. Make no error. On the transmission side, the analog signal is converted into a digital signal in synchronization with the symbol clock of the modulated wave to be transmitted. Therefore, the DA conversion is performed by synchronizing the DA conversion clock on the reception side with the symbol clock. The difference between the input data rate and the output data rate can be eliminated. As a result, unexpected signal output due to accumulation of frequency errors can be avoided. Hereinafter, the demodulation unit 2, the reproduction clock generation unit 6, and the audio reproduction unit 7 of the analog signal reproduction device 1 will be described in detail.

  FIG. 3 is a block diagram illustrating a configuration example of the demodulation unit according to the embodiment. The signal from the A-D conversion unit 5 is input to the orthogonal transformation unit 21 and orthogonally transformed to become, for example, 48 ksps I component and Q component signals, respectively. In the orthogonal transform unit 21, for example, the input signal is divided into two and mixed with an oscillation signal from a local oscillation circuit (not shown). One signal is mixed after the oscillation signal from the local oscillation circuit is shifted in phase by 90 °. As a result, orthogonally transformed signals of I component and Q component are obtained. The I component and Q component signals are input to the detector 22.

  The detector 22 obtains a demodulated signal by obtaining the phase and frequency deviation amount of the signal from the I and Q component signals. For example, from the I and Q components, assuming that I = cos θ and Q = sin θ, the calculation of θ = tan−1 (Q / I) is performed to obtain the signal phase. The obtained phase is subtracted from the delayed one sample previous phase, and the amount of frequency deviation which is the differential amount of the phase is obtained. The detection unit 22 inputs the demodulated signal to the symbol reproduction unit 23 and the synchronization word detection unit 24.

  In the symbol reproduction unit 23, for example, quaternary FSK symbol data is demodulated from the amplitude value (frequency deviation) of the demodulated signal. Prior to that, the synchronization word detection unit 24 detects the synchronization word from the demodulated signal, determines the frame structure of the received signal, and establishes communication (call).

  FIG. 4 is a block diagram illustrating a configuration example of the synchronization word detection unit according to the embodiment. The synchronization word detector 24 includes a memory 41, an average value calculator 42, a register 43, a subtractor 44, a subtractor 45, a memory 46, a correlation calculator 47, a register 48, a comparator 49, and a symbol comparator 40. Is provided.

  The memory 41 stores oversampled values for a predetermined number of received word patterns (demodulated signals), for example, 10 symbol periods. The memory 41 is sequentially updated each time an oversample value is input, and is stored for the latest 10 symbol periods. The average value calculation unit 42 calculates a moving average value of oversampled values stored in the memory 41. The register 43 stores an average value for a predetermined number of predetermined synchronization word patterns as an ideal average value. The subtractor 44 obtains a DC offset from the difference between the ideal average value stored in the register 43 and the moving average value obtained by the average value calculation unit 42. The subtractor 45 subtracts the DC offset from each oversampled value of the received word pattern. The memory 46 stores a synchronization word pattern.

  The correlation calculator 47 performs a correlation calculation between the received word pattern after the DC offset correction in the subtractor 45 and the synchronization word pattern stored in the memory 46. The register 48 stores a predetermined threshold value to be compared with the correlation value. The comparator 49 compares the correlation value obtained by the correlation calculator 47 with the threshold value stored in the register 48, and recognizes it as a synchronization word candidate if it is larger than the threshold value. When the synchronization word candidate is recognized by the comparator 49, the symbol comparator 40 compares each symbol value of the received word pattern after the DC offset correction and the synchronization word pattern. Then, when the errors of all symbols are within a certain range, it is determined that the synchronization word pattern has been detected.

The symbol comparator 40 stores the symbol values P11 ′ to P20 ′ after correcting the DC offset Δf for a predetermined period, for example, symbol values P11 to P20 for 10 symbol periods, in the memory 46. A comparison is made with the corresponding symbol values in the sync word pattern, and if all the symbol errors are within a certain range, it is finally determined that the sync word pattern has been detected. For example, when the symbol value of the synchronous word pattern is Ak and the symbol value of the received word pattern is Bk (where k is the number of samples and k = 1, 2,..., 10), the error Err is
Err = Σ | Ak− (Bk−Δf) |
It can be expressed as The symbol comparator 40 makes a final synchronization determination when the error Err is within a predetermined range.

  The symbol comparator 40 gives a reset signal to the symbol reproducing unit 23 at the detection timing of the synchronization word, and adjusts the timing of the internal symbol clock. Further, the symbol comparator 40 sets the provisional DC offset Δf used for the determination as described above as a true value, and supplies the corresponding value to the symbol reproducing unit 23 as frequency deviation information.

  Furthermore, when the symbol comparator 40 detects the synchronization word, the symbol reproduction unit 23 and the frame generation unit 25 have detected the synchronization word, that is, the reception is performed normally (whether or not the synchronization word is detected). To be notified. By “synchronization word detection”, symbol reproduction in the symbol reproduction unit 23 and frame configuration in the frame generation unit 25, that is, audio output is permitted. When the correlation value is equal to or less than the threshold value in the comparator 49 and when the synchronization word pattern is not detected in the symbol comparator 40, such control output is not performed.

  With this configuration, since the DC offset Δf is removed in the subtractor 44 before the correlation calculation (convolution) in the correlation calculator 47, the threshold value for determining the synchronization word detection in the symbol comparator 40 is set. Can be tough. Moreover, instead of determining the synchronization word detection based on the correlation calculation (convolution) result, the final detection condition is that the error is within a certain range for all the symbol points. Establishment can be performed promptly and with high accuracy.

  FIG. 5 is a block diagram illustrating a configuration example of the symbol reproduction unit according to the embodiment. The symbol reproduction unit 23 determines the symbol from the demodulated signal, demodulates the data, and corrects the symbol clock. In the symbol reproduction unit 23, for example, the demodulated signal oversampled at a sampling rate 10 times the symbol rate is input to the subtractor 30, and the synchronization word pattern is detected by the symbol comparator 40 of the synchronization word detection unit 24. The frequency deviation information corresponding to the DC offset Δf obtained in step S is subtracted and input to the shift register 311. Two stages of shift registers 312 and 313 are cascade-connected to the shift register 311. When new sample data is input, the shift register 311 is sequentially shifted. Accordingly, in the oversampling period, the newest data is held in the shift register 311 and the old data is held in the shift register 313 for three samples.

  The subtraction of the frequency deviation information in the subtracter 30 is limited to the case where the synchronization word pattern is detected by the synchronization word detection unit 24, that is, the frame is received and the reception is normally performed. When a synchronization word is detected, the symbol comparator 40 outputs this DC offset Δf, and Δf = 0 while it is not detected. Thus, when the synchronization word pattern is detected by the synchronization word detection unit 24, the correction by the DC offset Δf detected at that time is prioritized, and the DC offset Δf can be compensated quickly.

  The communication (call) in which the synchronization word pattern is detected uses the frequency deviation information (DC offset) obtained in the first synchronization word, and the frequency deviation information (DC) until the communication (call) is completed. Continue to use (DC offset). When the synchronization word detection unit 24 detects the synchronization word, the synchronization word detection unit 24 can subsequently detect the synchronization word by normal symbol reproduction in the symbol reproduction unit 23. Therefore, the synchronization word detection unit 24 is synchronized until the communication (call) is completed. Does not perform word pattern detection processing. Since the symbol reproduction unit 23 performs reception while having a frequency deviation and detects a synchronization word pattern, the symbol reproduction unit 23 receives a signal of a level that can be demodulated normally and reproduces the reproduced symbol. There is no error in the data and there is no problem.

  Returning to FIG. 5, the stored contents of the shift registers 311 to 3 are respectively taken into the shift registers 341 to 343 at the timing of the symbol clock generated by the timer 33 by the gate circuit 32. Therefore, in each shift register 342, 341, 343, sampling values at the sampling point E scheduled by the symbol clock near the ideal symbol point C and the sampling points F and R before and after that are stored. . Then, the sampling value at the sample point E is input to the symbol determination unit 35. In the symbol determination unit 35, for example, any one of “00”, “01”, “10”, and “11” is most likely as the symbol value of the actual symbol point P estimated from the sampling value at the sample point E. The determination result is output to the frame generation unit 25 as a 2-bit, 2.4 ksps signal.

  The symbol determination unit 35 outputs an ideal amplitude level corresponding to the symbol value of the determination result, and is subtracted from the stored contents of the shift register 342 in the subtractor 362. In the subtractor 361, a difference between the shift register 341 (sample point R) and the shift register 342 (sample point E) is calculated. In the subtractor 363, the difference between the shift register 342 (sample point E) and the shift register 343 (sample point F) is calculated. The subtraction results, that is, the deviation dE from the ideal amplitude level of the sampling data at the scheduled symbol point E and the differences d1 and d2 between the sampling data at the scheduled symbol point E and the preceding and following sampling data are sent to the selector 37. Entered.

  The selector 37 selects the correction direction of the symbol clock based on the deviation dE and the differences d1 and d2. Then, it is input to the timing correction unit 38. The timing correction unit 38 moves the sampling timing of the symbol point in the correction direction selected by the selection unit.

  FIG. 6 is a diagram for explaining the correction of the symbol clock according to the embodiment. In FIG. 6, the deviation dE between the scheduled symbol point E and the ideal symbol point C is negative. Further, the case where both the differences d1 and d2 are positive is depicted. The ideal interval between symbol points C is a reference symbol clock period T.

For example, the selector 37 selects the correction direction based on the sign of the deviation dE and the inclination of the sample points F, E, and R. From the difference d1 and the difference d2, the average slope α of the sample points F, E, and R is t (the sampling (oversampling) period).
α = (d1 + d2) / 2t
Given in. Therefore, if the correction direction is (1) dE> 0, α> 0, the direction to shorten the symbol clock cycle (2) dE> 0, if α <0, the direction to increase the symbol clock cycle (3) dE <0, If α> 0, the direction of increasing the symbol clock period (4) If dE <0, α <0, the direction of decreasing the symbol clock period. When dE = 0 or α = 0, the symbol clock period need not be changed. Since the oversampling period t is always a positive constant, the operation of dividing by 2t can be omitted.

  For example, the timing correction unit 38 corrects the symbol clock period by the oversampling period t in the correction direction (moves the sampling timing of the symbol point). Alternatively, the timing at which an ideal symbol point level is obtained from the inclination α and the deviation dE may be calculated by first-order approximation, and the symbol point sampling timing may be moved to that timing.

  The timing correction unit 38 combines the count value corresponding to the correction amount data with a sign as correction direction data, and outputs the combined result as a timing control signal to the timer 33.

  The timer 33 is composed of a self-propelled counter such as a digital VCO, and its oscillation frequency is set to a symbol frequency. When the symbol period (symbol timing) is reached, an overflow is removed and reset. To resume counting. The symbol timing is the timing when the phase of the digital VCO passes through 0 °. For example, when 0 to 360 ° (one symbol period) of the phase of the VCO is made to correspond to the count value of 0 to 30000 of the counter, the timer 33 adds 3000 for each oversample point T, A symbol clock capable of sampling a symbol value of a symbol rate of 2.4 ksps can be reproduced from oversampled data of 24 ksps.

  In the case of FIG. 6, the timer 33 advances the next symbol clock by 500 counts, for example, in the direction of the sample point R as the correction direction, that is, the advance direction, corresponding to the deviation dE at the sample point E as the correction amount. The count value when the phase of the digital VCO is 0 ° is initially set to 500. Then, the symbol timing is advanced only during the 500 counts, and the next sample point E approaches the ideal symbol point C.

  For example, when the count value of 500 is corrected during the repetition of the count operation, the timer 33 overflows at 30500, and is reset at this time, and the current correction value 500 is added to 500 excluding the overflow. The count operation is restarted, and then overflows at 31000. Thus, when the sum of the correction values reaches 3000, the sampling timing is accelerated by one sample.

  Increasing the maximum value of the timer 33 increases the resolution, and increasing the oversample sampling rate improves the correction accuracy. When the deviation dE at the sample point E is smaller than a predetermined value, stability can be improved by providing a dead zone that does not perform timing correction as described above. The timer 33 is forcibly reset to 0 at the detection timing of the synchronization word pattern by the reset signal from the symbol comparator 40 of the synchronization word detection unit 24 and restarts the count operation.

  The subtracters 361 to 363 may calculate the difference (error) between the values of the registers 341 to 343 and the ideal symbol point level, respectively. In this case, for example, the magnitude of the error of the sampling values at the shift registers 341 and 343, that is, the sampling points R and F is input to the selector 37, and it is determined which error is larger. Then, the sample point R is output to the timing correction unit 38 as data (index) in the direction in which the sample point E is to be moved in FIG. On the other hand, the error (deviation dE) in the subtractor 362 is input to the timing correction unit 38 as correction amount data. In this case, the timing correction unit 38 sets the count value corresponding to the correction amount data to the count value. The codes are combined as correction direction data and output to the timer 33 as a timing control signal.

  The symbol determination unit 35 takes in the amplitude value (frequency deviation), for example, at the timing of the symbol clock of 2.4 kHz and performs map determination, so that the amplitude value (frequency deviation) is “00” or “00” in the 4-level FSK. It is determined which symbol value corresponds to “01”, “10”, or “11”, and symbol data is reproduced. A reset signal is input to the timer 33 of the symbol reproduction unit 23 from the synchronization word detection unit 24 at the detection timing of the synchronization word, and the timing of the internal symbol clock is adjusted.

  The symbol data demodulated by the symbol reproduction unit 23 is output to the frame generation unit 25 as a signal having a symbol rate of 2.4 ksps, for example, with 2 bits per 4 values. In the frame generation unit 25, when the synchronization word detection unit 24 detects the synchronization word, that is, when reception is performed normally, the symbol data is formed into a predetermined frame and output to the audio reproduction 7. In addition, the timer 33 of the symbol reproduction unit 23 outputs the corrected symbol clock to the reproduction clock generation unit 6.

  FIG. 7 is a block diagram illustrating a configuration example of the audio reproduction unit and the reproduction clock generation unit according to the embodiment. The reproduction clock generation unit 6 includes a rate conversion unit 61 and a delay unit 62. The symbol clock input from the timer 33 of the symbol reproduction unit 23 is converted by the rate conversion unit 61 into the frequency of the reproduction clock used by the audio reproduction unit 7. Further, the delay unit 62 delays by the same time as the time (processing time) required for the processing of the audio reproduction unit 7. The audio reproduction unit 7 includes a decoding unit 71, a DA conversion unit 72, an amplification unit 73, and a speaker 74.

  FIG. 8 is a diagram for explaining generation of an analog signal reproduction clock according to the embodiment. In the example of FIG. 8, the input from the symbol reproduction unit 23 to the rate conversion unit is multiplied to 5 times the frequency. And it delays by the same time as the time (processing time) required for the process of the audio | voice reproduction | regeneration part 7. FIG.

  In the audio reproduction unit 7, the demodulated data obtained is decompressed in the decoding unit 71 from, for example, quaternary data having a sampling frequency of 2.4 kHz using a predetermined audio codec circuit. , 8 kHz, 16-bit PCM audio signal. The PCM audio signal is oversampled at, for example, 6 times the frequency (48 kHz), passes through a low-pass filter, and is then input to the DA converter 72. The DA converter 72 converts the PCM signal into an analog audio signal at the reproduction clock frequency 75. The converted audio signal is amplified by the amplifying unit 73 and output from the speaker 74.

  FIG. 9 is a flowchart showing an example of the analog signal reproduction operation according to the embodiment. The modulated wave received by the antenna 3 is frequency-converted / amplified and then oversampled by the A / D converter 5 (step S1). The demodulator 2 regenerates the symbol clock from the oversampled sampling data (step S2). Further, demodulated data is generated in parallel with the reproduction of the symbol clock (step S3).

  The regenerated symbol clock is sent to the regenerated clock generator 6, which generates a regenerated clock for regenerating the analog signal in synchronization with the symbol clock (step S4). On the other hand, the audio reproduction unit 7 decodes the demodulated data (step S5). The audio reproduction unit 7 reproduces an analog signal from the decoded data using the reproduction clock generated by the reproduction clock generation unit 6 (step S6). And while receiving the modulated wave with the antenna 3, the operation | movement of step S1-step S6 is repeated.

  As described above, in the analog signal reproduction device 1 according to the present embodiment, the symbol clock used for symbol reproduction is input to the reproduction clock generation unit 6. The reproduction clock generation unit 6 converts the rate from the symbol clock for sound reproduction (multiplication or frequency division), and delays the same amount as the delay generated by the sound reproduction unit 7 as a reference for the output rate of the DA converter. And Since this reference signal is also generated by the symbol reproducing unit 23, no error occurs between the symbol reproducing unit 23 and the DA converter. That is, the data is reproduced as an analog signal without excess or deficiency. As a result, unexpected signal generation such as noise can be prevented. By using this method, the problem caused by the error between the decoding unit and the DA converter is eliminated.

  In addition, the configuration of the embodiment is an example, and the present invention is not limited to the embodiment. For example, as long as a symbol clock that can normally generate demodulated data from a received signal can be extracted, the demodulator configuration as shown in FIG. 5 is not necessary. For example, as described above, the smaller sampling value error at the sample points R and F may be selected as the data (index) in the direction to be moved.

1 Analog signal playback device
2 Demodulator
3 Antenna
4 Frequency conversion / amplification unit
5 A-D converter
6 Regenerated clock generator
7 Audio playback unit
21 Orthogonal transformation unit
22 detector
23 Symbol playback unit
24 Sync word detector
25 Frame generator
30 Subtractor
32 Gate circuit
33 Timer
35 Symbol determination unit
37 selector
38 Timing corrector
40 symbol comparator
41 memory
42 Average value calculator
43 registers
44, 45 subtractor
46 memory
47 Correlation calculator
48 registers
49 Comparator
61 Rate converter
62 Delay part
71 Decoding unit
72 DA converter
73 Amplifier
74 Speaker 311, 312, 313 Shift register 341, 342, 343 Shift register 361, 362, 363 Subtractor

Claims (7)

A symbol that defines the sampling timing when a demodulated signal having an amplitude corresponding to a frequency or phase shift in the modulated wave is sampled at a predetermined symbol point and demodulated data is generated from the amplitude value of the obtained symbol data A clock recovery unit for recovering the clock;
A demodulator for demodulating the symbol data at the timing of the symbol clock recovered by the clock recovery unit to generate demodulated data;
A clock generation unit for generating a recovered clock for converting the demodulated data into an analog signal in synchronization with the timing of the symbol clock;
A signal reproducing unit for reproducing an analog signal from the demodulated data at a timing of a reproduction clock generated by the clock generation unit;
An analog signal reproducing apparatus comprising:   The clock generation unit starts counting the reproduction clock using the symbol clock as a trigger, and delays the time required for processing from the input of the demodulated data from the demodulation unit to the reproduction of an analog signal by the signal reproduction unit The analog signal reproduction device according to claim 1, wherein the reproduction clock is generated. The clock recovery unit
A timer for generating the symbol clock;
An oversampling unit that oversamples the demodulated signal at a frequency higher than the symbol clock;
Among the sampling data obtained by the oversampling, the predetermined symbol point and the sampling data of the predetermined symbol point and the symbol point to be obtained for the sampling data of a total of three points including the two points before and after the symbol point. An arithmetic unit for calculating a deviation between the sampling level of the predetermined symbol point and the sampling data of the two preceding and following points,
A selection unit that selects a correction direction of the symbol clock based on the deviation and the difference;
A timing correction unit that moves the sampling timing of symbol points in the correction direction selected by the selection unit to the timer;
The analog signal reproducing device according to claim 1, further comprising:   The timing correction unit moves the sampling timing of the symbol point by a time corresponding to the deviation in proportion to an average inclination of sampling data at the scheduled symbol point calculated from the difference. The analog signal reproducing device according to claim 3.   5. The analog signal reproducing apparatus according to claim 3, wherein the timer is reset at a detection timing of a symbol clock from a synchronous word pattern detector. The synchronous word pattern detector detects a DC offset due to a transmission / reception frequency shift by detecting the symbol clock,
A subtractor for correcting the DC offset from the demodulated signal input to the computing means;
6. The analog signal reproducing apparatus according to claim 5, wherein An analog signal reproduction method performed by an analog signal reproduction device that reproduces an analog signal from demodulated data obtained by demodulating a received modulated wave,
The demodulated signal having an amplitude corresponding to the frequency or phase shift in the modulated wave is sampled at a predetermined symbol point, and when generating demodulated data from the amplitude value of the obtained symbol data, the sampling timing is defined. A clock recovery step for recovering the symbol clock;
A demodulation step of demodulating the symbol data at the timing of the symbol clock recovered in the clock recovery step to generate demodulated data;
A clock generation step of generating a recovered clock for converting the demodulated data into an analog signal in synchronization with the timing of the symbol clock;
A signal reproduction step of reproducing an analog signal from the demodulated data at the timing of the reproduction clock generated in the clock generation step;
An analog signal reproduction method comprising:

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